Verification of Multi Bit Cells in Conformal

Verification of Multibit Registers in
Conformal
Product Version Conformal LEC 15.2
August 25, 2016
Copyright Statement
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Verification of Multibit Registers in Conformal
Contents
Purpose ....................................................................................................................... 4
Audience...................................................................................................................... 4
Terms .......................................................................................................................... 4
Understanding Multibit Library Cell Structure .............................................................. 5
Challenges in Multibit Register Mapping...................................................................... 9
Using the Mapping Guide File for Multibit Cell Mapping ............................................ 10
Impact on Checkpoint ............................................................................................ 15
Interaction with Renaming Rules............................................................................ 15
Impact of Multibit Instance Mapping on Hierarchical Comparison .......................... 15
Using Fixed Pattern for Multibit Cell Mapping ............................................................ 15
Using Renaming Rules for Multibit Register Mapping................................................ 21
Summary ................................................................................................................... 22
References ................................................................................................................ 23
Support ...................................................................................................................... 23
Feedback ................................................................................................................... 23

Purpose
Synthesis and physical implementation tools can map and replace multiple register bits
into a single multibit register cell to achieve reduced power, area, and clock skew.
Synthesis tools target the register bits belonging to the same bus or heterogeneous
register bits identified by you for implementation using a multibit register cell.
Physical implementation tools target the single-bit register cells that are physically
placed close to each other for replacement with multibit register cells, provided they are
compatible for grouping into a single multibit cell. This method is able to map
functionally unrelated registers, as well as bused registers, to multibit register cells.
The verification of multibit register cells is challenging because Conformal LEC needs to
correctly infer the single-bit registers from the multibit register cell and map them to the
corresponding single-bit register instances in the other design.
This document explains multiple strategies to ensure correct mapping of individual

registers to the sequential members of the multibit register cell.
Audience
This document is intended for Design or CAD engineers who want to perform
verification of multibit register cells against a golden RTL or a netlist with single-bit
register cells.
Terms
MBIT cell Multibit cell
LEC Logical Equivalence Checker
JSON Java Script Object Notation

Understanding Multibit Library Cell Structure

Multibit synthesis and physical implementation flows require the single-bit as well as the
multibit register cells to be properly defined in the Liberty .lib logical library.
In the Liberty syntax, the ff_bank or latch_bank group describes a multibit cell
consisting of a collection of parallel, single-bit sequential components. Each sequential
component shares control signals with the other parts and performs the same function
as the other parts.
You can use either the bus or bundle Liberty syntax to model these multibit signal pins
in the library.
The general Liberty syntax for a multibit flip-flop using the bus pin-group is as follows:
cell (cell_name) {
...
pin (pin_name) {
...
}
bus (bus_name) {
...
}
ff_bank (variable1, variable2, bits) {
clocked_on : "Boolean_expression" ;
next_state : "Boolean_expression" ;
clear : "Boolean_expression" ;
preset : "Boolean_expression" ;
clear_preset_var1 : value ;
clocked_on_also : "Boolean_expression" ;
}
}
The general Liberty syntax for a multibit flip-flop using the bundle pin-group is as
follows:
cell (cell_name) {
...
pin (pin_name) {
...
}
bundle (bus_name) {
members(pin_list);

...
}
ff_bank (variable1, variable2, bits) {
clocked_on : "Boolean_expression" ;
next_state : "Boolean_expression" ;
clear : "Boolean_expression" ;
preset : "Boolean_expression" ;
clocked_on_also : "Boolean_expression" ;
}
}
The members attribute of a bundle group lists the pins that form the multibit bus. The
pin mapping of individual sequential elements follow the order in which the pins are
listed in the members attribute.
The following snippet shows the Liberty definition of a multibit DFF cell that consists of
four pins each for input and output, and is grouped into a bundle group.
cell (DFF4B) {
area : 1 ;
pin (CLK) {
...
}
bundle (D) {
members(D1, D2, D3, D4);
...
}
pin (CLR) {
...
}
pin (PRE) {
...
}
ff_bank (IQ, IQN, 4) { /* consists of 4 bits */
next_state : "D" ;
clocked_on : "CLK" ;
clear : "CLR’" ;
preset : "PRE’" ;
clear_preset_var1 : L ;
clear_preset_var2 : L ;
}
bundle (Q) {
members(Q1, Q2, Q3, Q4);

direction : output;
function : “IQ”;
...
}
bundle (QN) {
members(Q1N, Q2N, Q3N, Q4N);
direction : output;
function : "IQN" ;
...
}
} /* end of cell DFF4B */
Note that the bundle group defines multibit member pins for the pins D, Q, and QN.

The cell schematic of the above cell will look like the following, when represented in
terms of individual four single-bit register component:
Figure 1: Schematic of the DFF4B multibit register cell
To learn more about the syntax of ff_bank, latch_bank, bundle, and bus, refer to
the Liberty User Guide.

Challenges in Multibit Register Mapping

There is no reliable configuration in synthesis to generate a multibit instance name.
Synthesis tools usually use several naming styles to generate the instance name. In
addition, both synthesis and implementation tools give freedom to the user to choose
any arbitrary strings for the multibit instance name.
Mapping of the multibit instance name involves two main steps:
1) Identifying from the multibit library cell definition the correspondence of a pin and
a particular register bit
2) Partitioning the multibit instance name into individual single-bit register names
and use the name-based mapping method to map them
The first step is automatic in LEC. Conformal automatically identifies the single-bit
register components from the multibit cell definition given in Liberty .lib and generates
single-bit register key points, named after the original multibit instance name.
However, successful partitioning in the multibit instance name can be sometimes

extremely challenging, even impossible, in LEC. Renaming rules no longer suffices to
address such situations.
Here are some examples of intricate multibit instance names, which will help you
understand the difficulty involved in partitioning:
foo_index_08_r_reg_4_AND_2_0
a_eop_r_reg_0__1_0__AND__AND_b_eop_r_reg_1__1_0
fifo_status_r_reg_7_6_AND_3_AND_1
fifo_status_r_reg_5_0
The expected partitioning can be highly non-intuitive.
These multibit instance names have different naming styles, different range
specification styles, and also have multi-dimensional array specifications. It is difficult to
partition these names correctly to the individual register names. No renaming rules can
work for all these scenarios.
For example, the first two multibit instance names might imply partitioning as follows:
foo_index_08_r_reg_4_AND_2_0 ->
foo_index_08_r_reg_4

a_eop_r_reg_0__1_0__AND__AND_b_eop_r_reg_1__1_0 ->
a_eop_r_reg_0__1
a_eop_r_reg_0__0
b_eop_r_reg_1__1
b_eop_r_reg_1__0
To handle the mapping of all kinds of multibit instance names, Conformal recommends
a universal solution called “attribute flow”.
To learn more about “attribute flow”, refer to the section “Using the Mapping Guide File
for Multibit Cell Mapping”.
Using the Mapping Guide File for Multibit Cell Mapping

Implementation tools can generate non-conventional instance names for multibit cells,
making it hard to partition them to individual register names using renaming rules.
To enable partitioning of multibit instance names into individual register names,

Conformal LEC recommends using a universal solution known as “attribute flow”.
The “attribute flow” relies on a mapping-guide file in JSON (Java Script Object Notation)
format, which describes how to partition the multibit instance name into corresponding
single-bit register names. This is not a direct mapping file. It provides a guidance on
name partitioning. There are slight chances that the name mapping can still fail.
Mapping can fail in case of the following scenarios:
1) The multibit cell is not read as a library cell in LEC.
2) The object names provided in the mapping-guide file have no correspondence in

the RTL or the netlist due to name changes or inaccurate information in the guide
file.
3) LEC cannot figure out the corresponding pins of the multibit library cell due to
complex hierarchy or logic inside the cell.
The basic components of the JSON syntax are as follows:
JSON Syntax Component Definition
“key” : “value” Defines a key and the associated value,

separated by a colon and enclosed within quotes

{ “key1” : “value1”, “key2” : “value2”, …} Defines an object as a list of comma-separated

<key>/<value> pairs, enclosed within curly
braces
[ { “key1” : “value1”, … } , Defines an array containing multiple objects,

{ “key2” : “value2”, … } , separated by commas and enclosed within square
… brackets
]
The mapping-guide file used in the “attribute flow” packs information about multibit cell
mapping as a list of <key>/<value> pairs, where <key> represents a predefined field
name in LEC and <value> stores the information associated with the field.
LEC uses the following <key> identifiers and the associated <value> fields in case of
multibit instance mapping:
<key> <value>
“attribute” “multibit”
“context” “<design_name>”
“objects” [
[“multibit_instance1”, “register1”, “register2”, ..]
[“multibit_instance2”, “register1”, “register2”, ..]
……
]
Sample mapping-guide file for multibit mapping:
[
{ "attribute":"multibit",
"context":"top",
"objects":[ ["a_reg_0_AND_a_reg_1", "a_reg_0", "a_reg_1"],
["b_reg_0_AND_b_reg_1", "b_reg_0", "b_reg_1",
In"<UNUSED>",
the above example, the a_reg_0_AND_a_reg_1 multibit instance is partitioned to
the a_reg_0 and a_reg_1 "<UNUSED>"] single-bit]register names. Similarly, the
}
©]2016 Cadence Design Systems, Inc. All rights reserved worldwide. Page 11
b_reg_0_AND_b_reg_1 multibit register instance is partitioned to b_reg_0 and

b_reg_1.
After this mapping-guide file is created, pass the file to Conformal LEC as follows in
SETUP mode:
SETUP> read setup information –type CONFORMAL <mapping-guide file>
LEC will import the partitioning information from this guide file to generate multiple
register name entries in place of the multibit register cell. After partitioning, the individual
registers will be looked up in the RTL and the netlist and will be mapped by name-
match.
Note:
- An attribute file enables mapping of a multibit cell with an arbitrary multibit

instance name.
- The order of individual instance names follows the pin declaration order of the
multibit library cell. In the above example, if the output pin declaration order of
the library cell is {Q1, Q0}, a_reg_0 will be associated with Q1 and a_reg_1
with Q0.
- If some members of the multibit cell are not used for mapping, use the
“<UNUSED>” string in place of those members.
In the above example, b_reg_0_AND_b_reg_1 is a 4-bit multibit library cell with

two of its members unused. “<UNUSED>” indicates the position of the unmapped
members in the bundle.
- The Conformal attribute file needs to be created by the user. LEC can also
facilitate you to write out an attribute file in JSON syntax using the –
extract_info_to_file option of the read setup information command
while parsing the synthesis guide file as follows:
SETUP> read setup information –type VSDC <VSDC file> \

-extract_info_to_file <JSON file name>
Duplicate and conflicting information is discarded with the following warning messages:

Figure 2: Messages for discarding attribute information
To report the summary of attribute information recorded and to find out how many of
them are accepted by LEC, use the “report setup information” command as
follows:
Figure 3: Reporting usage of attribute information

To display the verbose report, add the –verbose switch as follows:
Figure 4: Verbose report for attribute information usage
The multibit register mapping flow with the mapping-guide file is as follows:
Read .lib for MBIT cells Replaces the MBIT cell with
Read designs, constraints etc. generated single-bit register entries
Import JSON mapping-guide file

(read setup info –type conformal <JSON file>)
Maps the generated register entry with

Compare the mapped registers the corresponding single-bit register
Figure 5: Multibit cell mapping flow with JSON mapping-guide file

Impact on Checkpoint
If you are using a checkpoint file to restore a session, the attribute information (from the
JSON file) needs to be read again as follows. It is not saved into the checkpoint
database.
SETUP> read setup information -reset

SETUP> read setup information attr.json //re-reading attribute
information
SETUP> set system mode lec // if restart in LEC mode
Interaction with Renaming Rules

All the renaming rules should be added before “read setup information”. The
generated individual register names are altered as per the renaming rules, before
mapping.
Impact of Multibit Instance Mapping on Hierarchical Comparison

There is no impact of the user-provided multibit instance mapping information on the
HRC database. The information is used only during mapping. So, if you write a design
or write out the mapping file, the name will still be the multibit instance name.
Using Fixed Pattern for Multibit Cell Mapping

If the multibit cell instance name has the following general format, you can use the SET
MULTIBIT OPTION command from LEC to split the multibit instance name into
individual register instance names.
<prepend_string><prefix_string><multibit_name>
where,
• <prepend_string> is the common string that should appear in each individual

instance name.
• <prefix_string> is the string to separate <prepend_string> and

<multibit_name>.
• <multibit_name> is the multibit instance name.
For SET MULTIBIT OPTION to work, the following assumptions must hold true:

1. All individual instance names appear in the multibit instance name, and they are
concatenated with a delimiter string.
2. If individual instances are from the same bus, they can be in the range format.
For example, indexes 0, 1, 2, and 3 can be expressed as 0_3. However, the
indexes must be consecutive; no individual bit can be skipped. For example,
indexes 0, 1, 3, and 4 cannot be expressed as 0_4.
3. The order of individual names in the concatenated multibit instance name should
be consistent with the pin declaration order in the multibit library cell. For
example, if the pin declaration order of library cells is {D1, D0} and 'a_reg' is
associated with 'D0' and 'b_reg' with 'D1', the multibit instance name should be
'CDN_MBIT_b_reg_MB_a_reg'.
The set multibit option command has the following syntax:
SETUP> set multibit option

[-Delimiter <string>]
[-GROUP <string>]
[-PREFIX <string>]
[-PREPEND <string>]
[-RANGE_PATTERN]
[-RANGE_TOKEN <string>]
[-SEPARATOR_TOKEN <string>]
[-TEST <string>]
[-GOLden | -REVised]
This command can handle prefix, delimiter, range pattern, group, prepend strings, range
token, and separator token, embedded in the multibit cell instance name.
All <string> arguments are Perl regular expressions that can include Perl operators.
The general format of multibit instance name recognized by this command is:
<prepend_string><prefix_string><multibit_name>
Therefore, the steps involved to extract individual register name are:
1) Recognize <prepend_string><prefix_string>.
2) Split <multibit_name>.

Step 1:
To extract prepend and prefix strings, use the following commands:
SETUP> set multibit option -prepend <prepend_pattern>

SETUP> set multibit option -prefix <prefix_pattern>
The <prepend_pattern> must be in the format of ^(<prepend_pattern>). Note

that the parenthesis is mandatory to extract the matched string as the prepend string.
LEC concatenates the two patterns (as shown below) and uses it to match the multibit
instance name to extract the prepend string:
“^(<prepend_pattern>)<prefix_pattern>”
The default <prefix_pattern> assumed by this command is CDN_MBIT_.
Step 2:
<multibit_name> should have the following general format:
<reg_1><delimiter><reg_2><delimiter>...<reg_n>[delimiter]
LEC uses the following pattern to (iteratively) match the name and extract individual
names:
<group_pattern><delimiter_pattern>
The default value assumed for <delimiter_pattern> is “_MB_”.
If the delimiter is some other unique string that is not part of the generated register
names, setting the <delimiter_pattern> alone is good enough for LEC to split the
name. However, if the delimiter is a commonly used string (for example, _), you need to
set the group pattern also as follows:
SETUP> set multibit option -group <group_pattern>
<group_pattern> must be in the format of ^(<group_pattern>).
Note that the parenthesis is mandatory to extract the matched string as individual
names.
If the <multibit_name> is in range format, set the range pattern as follows:
SETUP> set multibit option -range_pattern <range_pattern>

The <range_pattern> must be specified in the following format:
(<pattern>)(\d+)<string>(\d+)(<pattern>)
For example, if the range portion in the multibit instance is '3_0', the pattern will be
specified as:
SETUP> set multibit option -range_pattern (.*)(\d+)_(\d+)(.*?)
To report the current setting of this command, use the following command:
SETUP/LEC> set multibit option
Figure 6: Displaying the current setting of the “set multibit option” command
To preview how the inferred register names will be created, you can use the “-test”
option with this command as follows:
SETUP> set multibit option –test <multibit instance name> [-

golden|-revised]

The following example shows how this command will split the multibit instance name to
infer the individual register names:
Figure 7: Testing how the split register names will look like
The individual single-bit register components are then mapped by name to the
corresponding single-bit registers in the Golden design.
The following image illustrates the multibit cell mapping flow using pattern-based name
mapping:
Read .lib for MBIT cells
Replaces the MBIT cell with

Read designs, constraints etc. generated single-bit register entries
Define the MBIT naming rule (set multibit option)
Maps the generated register entry with

the corresponding single-bit register
Compare the mapped registers
Figure 8: Multibit cell mapping flow with set multibit option
Consider, for example, the following multibit cell with instance name:
MBINST_SPI_INST_dout_reg[0]_MBIT_SPI_INST_dout_reg[1]

To infer the individual registers back in Conformal, use the following command:
SETUP> set multibit option –delimiter “_MBIT_” –prefix “MBINST_”

–revised
With this command, Conformal will automatically generate two register entries, one for
each of the two sequential components, and replace the key point for the multibit
instance with them as follows:
MBINST_SPI_INST_dout_reg[0]_MBIT_SPI_INST_dout_reg[1]/sttb_$U1/u
dp1/U$1
dp1/U$1
After the generation of two unique register instances, they are mapped by Conformal
and staged for comparison:
SPI_INST_dout_reg[0] mapped to
dp1/U$1
SPI_INST_dout_reg[1] mapped to
dp1/U$1
Note that /sttb_$U1/udp1/U$1 and /sttb_$U2/udp1/U$1 are identifiers added by

Conformal to make the instance pathnames unique.
The following table exemplifies how this command will generate register instances
against a multibit register instance.

Multibit instance name Set multibit options Decomposed

instance
names
MBIT_a_reg_b_reg set multibit option a_reg
-prefix "MBIT_" - b_reg
delimiter "_" -group
"(.*?_reg")
MBIT_c_reg_1__d_reg_0_ set multibit option c_reg_1
-prefix "MBIT_" - d_reg_0
delimiter "__" -
group
"((.*?(_reg)+(_\d+))
)"
reg_0__2_1_ set multibit option reg_0__2_
-range_pattern reg_0__1_
'(.*)(\d+)_(\d+)(.*_
)'
a_reg_b_reg_0 set multibit option a_reg
-group "(a_reg)" - b_reg_0
delimiter "_"
CDN_MBIT_a_reg_0A_AND__AND_a_reg_1A_MB set multibit option - a_reg_0A

_a_reg_2A_AND__AND_a_reg_3A a_reg_1A
prefix (?:CDN_MBIT_|)
a_reg_2A
a_reg_3A
set multibit option -
delimiter
(?:_MB_|_AND__AND_)
q_reg[0]_MB_[1]_MB_[2]_MB_[3] set multibit option - q_reg[0]

delimiter "_MB_" -
q_reg[1]
prefix "" -
prepend_string q_reg[2]
"^(.*?_reg)" -revised q_reg[3]
Using Renaming Rules for Multibit Register Mapping

This is not a recommended approach. However, you can manually examine the inferred
corresponding register names by Conformal based on the mulitibit cell definition and
write renaming rules to map them to individual registers in the other design.
The difficulty in this approach is that it requires precise identification of the

distinguishing parts of inferred instance names to correlate, because the initial parts will
be common for all.

For example, if the name of a 2-bit multibit cell instance is mbit_flop_inst,

Conformal identifies two key points with names as follows:
mbit_flop_inst/U$1
mbit_flop_inst/U$2
If mbit_flop_inst/U$1 corresponds to ff0 and mbit_flop_inst/U$2

corresponds to ff1 instance in the other design, the renaming rule can be written as
follows:
SETUP> add renaming rule R1 ff%d/U\$1 mbit_flop/U\$@1 –gold
Caveat:
U$1, U$2, and so on in instance names come from the library logic and this might vary
from library to library and also between LEC versions. Therefore, the use of renaming
rules is not a robust solution.
Prefer “attribute flow” for multibit instance mapping.
Summary
The three methods of multibit cell mapping are alternative ways to capture the mapping
intent and use it as a guidance for actual mapping.
Out of them, use of JSON file is the recommended approach for mapping a multibit cell
to single-bit registers, because it is unambiguous and is able to cover all situations. The
other two approaches can be used when the naming style is simple to break down into
individual instance names.
In any case, it is recommended to cross-check the final mapping of the multibit cell to
ensure that it conforms to the mapping intention.

References
Liberty User Guide Version 2009.06
Conformal Equivalence Checker Command Reference Manual
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Verification of Multibit Registers in

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This document explains multiple strategies to ensure correct mapping of individual

LEC Logical Equivalence Checker

JSON Java Script Object Notation

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Understanding Multibit Library Cell Structure

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members(Q1, Q2, Q3, Q4);

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Figure 1: Schematic of the DFF4B multibit register cell

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Challenges in Multibit Register Mapping

Mapping of the multibit instance name involves two main steps:

However, successful partitioning in the multibit instance name can be sometimes

The expected partitioning can be highly non-intuitive.

Learn more at Cadence Online Support - http://support.cadence.com

Using the Mapping Guide File for Multibit Cell Mapping

To enable partitioning of multibit instance names into individual register names,

Mapping can fail in case of the following scenarios:

1) The multibit cell is not read as a library cell in LEC.

2) The object names provided in the mapping-guide file have no correspondence in

The basic components of the JSON syntax are as follows:

JSON Syntax Component Definition

“key” : “value” Defines a key and the associated value,

Learn more at Cadence Online Support - http://support.cadence.com

{ “key1” : “value1”, “key2” : “value2”, …} Defines an object as a list of comma-separated

[ { “key1” : “value1”, … } , Defines an array containing multiple objects,

Sample mapping-guide file for multibit mapping:

b_reg_0_AND_b_reg_1 multibit register instance is partitioned to b_reg_0 and

SETUP> read setup information –type CONFORMAL <mapping-guide file>

- An attribute file enables mapping of a multibit cell with an arbitrary multibit

In the above example, b_reg_0_AND_b_reg_1 is a 4-bit multibit library cell with

SETUP> read setup information –type VSDC <VSDC file> \

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Figure 2: Messages for discarding attribute information

Figure 3: Reporting usage of attribute information

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To display the verbose report, add the –verbose switch as follows:

Figure 4: Verbose report for attribute information usage

Import JSON mapping-guide file

Maps the generated register entry with

Figure 5: Multibit cell mapping flow with JSON mapping-guide file

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SETUP> read setup information -reset

Interaction with Renaming Rules

Impact of Multibit Instance Mapping on Hierarchical Comparison

Using Fixed Pattern for Multibit Cell Mapping

• <prepend_string> is the common string that should appear in each individual

• <prefix_string> is the string to separate <prepend_string> and

• <multibit_name> is the multibit instance name.

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The set multibit option command has the following syntax:

SETUP> set multibit option

Therefore, the steps involved to extract individual register name are:

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To extract prepend and prefix strings, use the following commands:

SETUP> set multibit option -prepend <prepend_pattern>

The <prepend_pattern> must be in the format of ^(<prepend_pattern>). Note

The default <prefix_pattern> assumed by this command is CDN_MBIT_.

<multibit_name> should have the following general format:

The default value assumed for <delimiter_pattern> is “_MB_”.

SETUP> set multibit option -group <group_pattern>

SETUP> set multibit option -range_pattern (.)(\d+)_(\d+)(.?)