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  • Computer Architecture Lab (Day Wise Tasks) For Group-2

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    Suvojit Modak
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    The document outlines the tasks to be completed over 8 days by a computer architecture lab group. On days 1-4, the group will model basic logic gates and multiplexers using dataflow and behavioral modeling. On days 5-6, more complex circuits like adders, flip flops, and counters will be modeled structurally and behaviorally. Day 7 covers additional behavioral models like an ALU, decoder and comparator. Day 8 focuses on structural models of a shift register and data conversion circuits.

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    CA Daywise Tasks

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    The document outlines the tasks to be completed over 8 days by a computer architecture lab group. On days 1-4, the group will model basic logic gates and multiplexers using dataflow and behavioral modeling. On days 5-6, more complex circuits like adders, flip flops, and counters will be modeled structurally and behaviorally. Day 7 covers additional behavioral models like an ALU, decoder and comparator. Day 8 focuses on structural models of a shift register and data conversion circuits.

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    © All Rights Reserved
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    14 views2 pages

    Computer Architecture Lab (Day Wise Tasks) For Group-2

    Uploaded by

    Suvojit Modak
    The document outlines the tasks to be completed over 8 days by a computer architecture lab group. On days 1-4, the group will model basic logic gates and multiplexers using dataflow and behavioral modeling. On days 5-6, more complex circuits like adders, flip flops, and counters will be modeled structurally and behaviorally. Day 7 covers additional behavioral models like an ALU, decoder and comparator. Day 8 focuses on structural models of a shift register and data conversion circuits.

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    © All Rights Reserved
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    Computer Architecture Lab (Day wise Tasks) for Group-2

    Day-1:
    1. AND Gate (Dataflow)
    2. OR Gate (Dataflow)
    3. NOT Gate (Dataflow)
    4. NAND Gate (Dataflow)
    5. NOR Gate (Dataflow)
    6. XOR Gate (Dataflow)
    7. XNOR Gate (Dataflow)
    8. AND using NAND Gate (Dataflow)
    9. OR using NAND Gate (Dataflow)
    10.NOT using NAND Gate (Dataflow)
    11.XOR using NAND Gate (Dataflow)

    Day-2:
    1. 2x1 MUX(Dataflow)

    Day-3:
    1. Half Adder(Dataflow)
    2. Full Adder(Dataflow)
    3. 4x1 MUX(Dataflow)

    Day-4:
    1. AND Gate (Behavioral)
    2. OR Gate (Behavioral)
    3. NOT Gate (Behavioral)
    4. NAND Gate (Behavioral)
    5. NOR Gate (Behavioral)
    6. XOR Gate (Behavioral)
    7. XNOR Gate (Behavioral)
    8. Half Adder(Behavioral)
    9. Full Adder(Behavioral)
    10.2x1 MUX (Behavioral)
    11.4x1 MUX(Behavioral)
    Day-5:
    1. Ripple Carry Adder (Structural)
    2. Full Adder (Structural) using Half Adder dataflow and OR dataflow
    3. 4-bit Adder-Subtractor composite circuit (Structural) using Full Adder dataflow
    4. 8x1 MUX (Structural) with 4x1 MUX dataflow and 2x1 Mux dataflow

    Day-6:
    1. D flip flop (Behavioral)
    2. T flip flop (Behavioral)
    3. JK flip flop (Behavioral)
    4. RS flip flop (Behavioral)

    Day-7:

    1. 4-bit Up Counter (Behavioral)


    2. 4 bit ALU (Behavioral)
    3. 3x8 Decoder (Behavioral)
    4. 8-bit Parity Checker (Behavioral)
    5. 4-bit Comparator (Dataflow)

    Day-8:
    1. 4 bit Serial Shift Register (Structural) using D flip flop behavioural model
    2. Gray to Binary (Dataflow)
    3. Binary to Gray (Dataflow)
    4. 2’s Compliment (Dataflow)

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