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Computer Architecture Lab (Day Wise Tasks) For Group-2
Computer Architecture Lab (Day Wise Tasks) For Group-2
Day-1:
1. AND Gate (Dataflow)
2. OR Gate (Dataflow)
3. NOT Gate (Dataflow)
4. NAND Gate (Dataflow)
5. NOR Gate (Dataflow)
6. XOR Gate (Dataflow)
7. XNOR Gate (Dataflow)
8. AND using NAND Gate (Dataflow)
9. OR using NAND Gate (Dataflow)
10.NOT using NAND Gate (Dataflow)
11.XOR using NAND Gate (Dataflow)
Day-2:
1. 2x1 MUX(Dataflow)
Day-3:
1. Half Adder(Dataflow)
2. Full Adder(Dataflow)
3. 4x1 MUX(Dataflow)
Day-4:
1. AND Gate (Behavioral)
2. OR Gate (Behavioral)
3. NOT Gate (Behavioral)
4. NAND Gate (Behavioral)
5. NOR Gate (Behavioral)
6. XOR Gate (Behavioral)
7. XNOR Gate (Behavioral)
8. Half Adder(Behavioral)
9. Full Adder(Behavioral)
10.2x1 MUX (Behavioral)
11.4x1 MUX(Behavioral)
Day-5:
1. Ripple Carry Adder (Structural)
2. Full Adder (Structural) using Half Adder dataflow and OR dataflow
3. 4-bit Adder-Subtractor composite circuit (Structural) using Full Adder dataflow
4. 8x1 MUX (Structural) with 4x1 MUX dataflow and 2x1 Mux dataflow
Day-6:
1. D flip flop (Behavioral)
2. T flip flop (Behavioral)
3. JK flip flop (Behavioral)
4. RS flip flop (Behavioral)
Day-7:
Day-8:
1. 4 bit Serial Shift Register (Structural) using D flip flop behavioural model
2. Gray to Binary (Dataflow)
3. Binary to Gray (Dataflow)
4. 2’s Compliment (Dataflow)