Chapter 4 Differential Amplifiers The differential amplifier is among the most important circuit inventions, dating back to the vacuum tube era. Offering many useful properties, differential operation has become the dominant choice in today's high-performance analog and mixed-signal circuits. This chapter deals with the analysis and design of CMOS differential amplifiers. Follow- ing a review of single-ended and differential operation, we describe the basic differential pair, and analyze both the large-signal and the small-signal behavior. Next, we introduce the concept of common-mode fejection and formulate it for differential amplifiers. We then study differential pairs with diode-connected and current-source loads as well as differential cascode stages. Finally, we describe the Gibert cell. 4.1 Single-Ended and Differential Operation 100 ‘A single-ended signal is defined as one that is measured with respect to a fixed potential, usually the ground. A differential signals defined as one thatis measured between two nodes that have equal and opposite signal excursions around a fixed potential In the strict sens, the two nodes must also exhibit equal impedances to that potential. Fig. 4.1 illustrate the two types of signals conceptually. The “center” potential in differential signaling is called the “common-mode” (CM) level. @ © Figure 4.1 (a) Single-ended and (b) differential signals.00.4.1 Single-Ended and Differential Operation 101 An important advantage of differential operation over single-ended signaling is higher immunity to “environmental” noise. Consider the example depicted in Fig. 4.2, where two adjacent lines in a circuit carry a small, sensitive signal and a large clock waveform. Due to capacitive coupling between the lines, transitions on line Lp corrupt the signal on line Ly ‘Now suppose, as shown in Fig. 4.2(b), the sensitive signal is distributed as two equal and. ‘opposite phases. Ifthe clock line is placed midway between the two, the transitions disturb the differential phases by equal amounts, leaving the difference intact. Since the common- ‘mode level of the two phases is disturbed but the differential output is not corrupted, we say this arrangement “rejects” common-mode noise. ox Clock Line Vi, diem, Dy signa Line Line-to-Line Capacitance @ © Figure 4.2 (a) Corruption of a signal due to coupling, (b) reduction of coupling by differential operation. Another example of common-mode rejection occurs with noisy supply voltages. In Fig. 4.3(a), if Vpp varies by AV, then Vox: changes by approximately the same amount, ice, the output is quite susceptible to noise on Vpp. Now consider the circuit in Fig. 4.3(b) Here, if the circuit is symmetric, noise on Von affects Vx and Vy but not Vir — Vr = Vou. ‘Thus, the circuit of Fig. 4.3(b) is much more robust to supply noise.102 Chap. 4 Differential Amplifiers @ o Figure 4.3 Effect of supply noise on (a) a single-ended circuit, (b) a differential circuit ‘Thus far, we have seen the importance of employing differential paths for sensitive signals. Its also beneficial to employ differential distribution for noisy lines. For example, suppose the clock signal of Fig. 4.2 is distributed in differential form on two lines (Fig. 4.4), ‘Then, with perfect symmetry, the components coupled from CK and CX to the signal line cancel each other. Figure 4.4 Reduction of coupled noise by differential operation. ‘Another useful property of differential signaling is the increase in maximum achievable voltage swings. In the circuit of Fig. 4.3, for example, the maximum output swing at X or ¥ is equal to Vow — (Vos — Vr), whereas for Vx — Vy, the peak-to-peak swing is equal 10 2lVop ~ Ves ~ Vra)h Other advantages of differential circuits over single-ended counterparts include simpler biasing and higher linearity (Chapter 13). While it may seem that differential circuits occupy twice as much area as single-ended alternatives, in practice this is a minor drawback. Also, the suppression of nonideal effects by differential operation often results ina smaller area than that ofa brute-force single-ended design. Furthermore, the numerous advantages of differential operation by far outweigh the possible increase in the area.Sec. 4.2 4.2 Basic Differential Pai Basic Differential Pair 103 How do we amplify a differential signal? As suggested by the observations in the previous section, we may incorporate two identical single-ended signal paths to process the two phases (Fig. 4.5(a)]. Such a circuit indeed offers some of the advantages of differential © © Figure 4.5 (a) Simple differential circuit, (b) illustration of sensi- tivity to the input common-mode level signaling: high rejection of supply noise, higher output swings, etc. But what happens if Viqu and Vigo experience a large common-mode disturbance or simply do not have a well- defined common-mode de level? As the input CM level, Via,car, changes, so do the bias currents of My and Mz, thus varying both the transconductance of the devices and the output CM level. The variation of the transconductance in turn leads to a change inthe small-signal sain while the departure of the output CM level from its ideal value lowers the maximum allowable output swings. For example, as shown in Fig. 4.5(b), ifthe input CM level is excessively low, the minimum values of Vini and Vin2 may in fact turn off My and M2, leading to severe clipping at the output. Thus, itis important that the bias currents of the devices have minimal dependence on the input CM level. A simple modification can resolve the above issue. Shown in Fig. 4.6, the “differential pair" employs a current source Iss to make Ip; + Ip2 independent of Vin.cw. Thus, if Vint = Vinas the bias current of each transistor equals /ss/2 and the output common-mode "Alto called a source-coupled pair or (nthe British literature) along ale pai108 Chap. 4 Differential Amplifiers Figure 4.6 Basic differential pair. level is Vop — Rp Iss/2. Itis instructive to study the large-signal behavior of the cireuit for both differential and common-mode input variations. 4.2.1 Qualitative Analysis Let us assume that in Fig. 4.6, Vini ~ Vina Varies from —00 to -+oo. If Viq1 is much more negative than Visa, My is off, Ma is on, and Ip: = Iss. Thus, Vout = Voo and Vour2 = Vop ~ Rplss. As Vint is brought closer to Vira, My gradually turns on, drawing a fraction of Iss from Rp and hence lowering Vay. Since Ip) + Ip2 = Iss. the drain current of Mz decreases and Vou rises. As shown in Fig. 4.7(a), for Vie = Vina- We have Vourt = Vour2 = Voo — Rolss/2. As Vin, becomes more positive than Vin2, Mj carries a areater current than does My and Vay drops below Vaya. For sufficient large Vin ~ Vinx ‘M, “bogs” all of Iss, turning M3 off. As a result, Vourr = Vop — Rolss and Vou2 = Vo. Fig. 4.7 also plots Voxei ~ Voua Versus Vint — Vino Voutt~Vous + Roles. Yoo —Yeutt Vpo- Folss Vinr~ Vina Vous ~Apl Yins~Ying mss ® ® Figure 4.7 Input-output characteristics of a differential pair. ‘The foregoing analysis reveals two important attributes of the differential pair. First, the maximum and minimum levels atthe output are well-defined (Vpp and Vo — Ross. respectively) and independent of the input CM level. Second, the small-signal gain (the slope Of Vout — Vou2 versus Vini ~ Vina) is maximum for Vigi = Vina» gradu- ally falling t0 zero as |Vini — Vinal increases. In other words, the circuit becomes more nonlinear as the input voltage swing increases. For Vin = Vina. We Say the circuit is in equilibrium.Sec. 4.2 tovloa, Vinow Basic Differential Pair 105 Now let us consider the common-mode behavior of the circuit. As mentioned earlier, the role of the tail current source is to suppress the effect of input CM level variations on the operation of Mf and Mz and the output level. Does this mean that Vi,,cxy can assume arbitrarily low or high values? To answer this question, we Set Vii = Vina = Vincw and vary Vin.cut from 0 to Vpp. Fig, 48(a) shows the circuit with Iss implemented by an NFET. Note that the symmetry of the pair requires that Vou Yoo Vous Voutz e Vp Vinow vm Yincm © Figure 4.8 (a) Differential pair sensing an input common-mode change, (b) equivalent circuit if My operates in deep ‘rode region, (c) common-mode input-output characteristics. What happens if Vin.cw = 0? Since the gate potential of M, and Mz is not more Positive than their source potential, both devices are off, yielding J; = 0. This indicates that Ms is in deep triode region because Vs is high enough to create an inversion layer in the transistor. With Ip, = Ip2 = 0, the circuit is incapable of signal amplification, and Vout = Vour2 = Vo: "Now suppose Vin,cxy becomes more positive. Modeling My by aresistor as in Fig. 4.8(b), ‘wenote that Mj and Mz turn on f Vip,cxr > Vir. Beyond this point, Ip) and /p2 continue to increase and Vp also rises (Fig. 4.8(C)]. Ina sense, M, and Mz constitute a source follower, forcing Vp to track Vin.cu. For a sufficiently high Vi.,cy, the drain-source voltage of Mz exceeds Voss ~ Vria, allowing the device to operate in saturation. The total current through M; and Mz then remains constant, We conclude that for proper operation, Vin.cw > Vast + (Vass — Vrs) ‘What happens if Vg.cus rises further? Since Vout and Vows ate relatively constant, we expect that M; and Mz enter the triode region if Vig.cu > Vouri-+ Vr = Voo—Rolss/2+ Vru. This sets an upper limit on the input CM level. In summary, the allowable value of108 Chap. 4 Differential Amplifiers Vin,ca is bounded as follows: Iss Vosi + (Voss ~ Vrus) $ Vin.cw $ min | Vop ~ Ro + Vray Vow 4) Example 4.1 ‘Sketch the small-signal differential gain of a differential pair as a functioa of the input CM level Solution ‘As shown in Fig. 4.9, the gain begins to increase as Vi,cy exceeds Vr. After the til current source lav Vm Ve Vine Figure 4.9 ‘enters saturation (Vin,car = Vi) the gain remains relatively constant. Finally if Via,ca is so high that the input transistors enter the triode region (Vin,ca = V2), the gain begin to fall With our understanding of differential and common-mode behavior of the differential pair, we can now answer another important question: How large can the output voltage ‘swings of a differential pair be? As illustrated in Fig. 4.10, for My and Mz to be saturated, each output can go as high as Vop but as low as approximately Vip,cw — Vri. In other Figure 4.10 Maximumallowableout- put swings in a differential pai words, the higher the input CM level, the smaller the allowable output swings. For this reason, it is desirable to choose a relatively low Vin.cw, but the preceding stage may not provide such a level easily. ‘An interesting trade-off exists in the circuit of Fig. 4.10 between the maximum value of Vis,car and the differential gain. Similar to a simple common-source stage (Chapter 3),Sec. 4.2 Basic Differential Pair 107 the gain of a differential pair is a function of the de drop across the load resistors. Thus, if Rplss/2is large, Vis,cw must remain close to ground potential. 4.2.2 Quantitative Analysis ‘We now quantify the behavior of aMOS differential pair as a function of the input differential voltage. We begin with large-signal analysis to arrive at an expression for the plots shown. in Fig. 4.7. Figure 4.11. Differential pir For the differential pairin Fig. 4.11, we have Vout = Von — Roi 1 and Veur2 = Voo— Roalr, its Vount ~ Your = Roalo2 — Roi = Ro(n2 ~ Ip1) if Roy = Ro2 = Ri Thus, we simply calculate Zp; and Zp in terms of Viqi and Vina, assuming the circuit is symmetric, My and Mp are saturated, and 2 = 0. Since the voltage at node P is equal to Vint ~ Vast and Vina = Vases Vint ~ Vin2 = Vest ~ Vaso (42) For a square-law device, we have: (os ~ Vea? = 7— 43) and, therefore, (44) It follows from (4.2) and (4.4) that Zon To Vint — Vina = aa 45) HrCort | HaCor108 Chap. 4 Differential Ampitiers Our objective is to calculate the differential output current, Ip; ~ Ip2- Squaring the two sides of (4.5) and recognizing that Ip; + Ipz = Iss, we obtain (Wnt = Va? = —* gp iss ~ 2V ToT) 46 HaCoe Thats, FoaCor Vin Viz)’ — Iss = ~2VTorlor. an Squaring the two sides again and noting that 4fp3.[p2 = (Ip1 + Ip2)? — (pr ~ loa)? = Bis ~ (pi ~ Ix), we amtive at 2 pi ~ Im = -5 ( Cou) (Vina = Vira)® + IsstixCox Vit —VinF. (4.8) Ww 4; Bor ~ toa = 5eCoxF- (Vint = Viz) | 55 — Vint = Vina. (4.9) MaCone ‘As expected, Io: ~ Ipz isan odd function of Vins ~ Viz falling t0 zero for Vint = Via. AS |Vini ~ Vinal increases from zero, pi ~ Ipa| also increases because the factor preceding the square root rises more rapidly than the argument in the square root drops.? Before examining (4.9) further, itis instructive to calculate the slope of the characteristic, the equivalent Gwe of My and M3. Denoting Ip, ~ lop and Viet ~ Viz by Alp and Vins respectively, the reader can show that Alss Alo 1) 6 W paCaW/E°A¥in 4.1 DAV, — BMC is ay? waCoxw7e °V For AVin = 0,Gm = VinConW]D)Ig5. Moreover, since Vous) — Vow = RpAl = RoGmAViny We can write the small-signal differential voltage gain of the circuit in the equilibrium condition as W Mn Cox IssRo- (4.11) itis itresting to note that, even though I, and oz are even functions of ther respective gate-source voltages oi ~ 1p2 isan odd funtion of Vi ~ Viga- This effect ie studied in Chapter 13. [AuSec.42 Basic Differential Pair 109 Equation (4.10) also suggests that Gy falls to 2er0 for AVig = JIgsGinCasW7D). ‘As we will see below, this value of Vig plays an important role in the operation of the circuit. Let us now examine Eq. (4.9) more closely. It appears thatthe argument in the square root drops to zero for AVig = V/AIss/(iinCos W/L), implying that Ap crosses zero at ‘wo different values of A Vin. This was not predicted in our qualitative analysis in Fig. 4.7. ‘This conclusion, however, is incorrect. To understand why, recall that (4.9) was derived with the assumption that both My and Mz are on. In reality, as A Vi, exceeds a limit, ‘one transistor carries the entire /ss, turning off the other.* Denoting this value by Aina, we have Ip) = Iss and AVin) = Vosi — Vrw because Mz is nearly off. It follows that Diss Vin = |_— Sp (4.12) Hao For AVin > AViniy Mz is off and (4.9) does not hold. As mentioned above, Gy. falls to zer0 for AViq = AVin1- Figure 4.12 plots the behavior. Gm ~ Aint +AVint Vig, ~ Vint +AVint Vin ® © Figure 4.12 Variation of drain curents and overall transconductance ofa differen- tial pair versus input voltage. Example 4.2 lot the input-output characteristic ofa differential par a the device width and the tail curent vary. Solution Consider the characteristic shown in Fig. 4.13(@). As W/L increases, & Vin decreases, narrowing the input range across which both devices are on [Fig.4.13(b)]. As Iss increases, both the input range and the output current swing increase [Fig 4.13(¢)].Intukively, we expect the circuit to become more linear as Iss increases or W/L. decreases. a ‘The value of Vina given by (4.12) in essence represents the maximum differential input that the circuit can “handle.” It is possible to relate AViqi to the overdrive voltage We neglect subthreshold conduction here.110 Chap. 4 Differential Amplifiers © Figure 4.13 of M, and Mz in equilibrium. For a zero differential input, Zp, = Ip = Iss/2, and hence Tss (Wes — Vruia= | “ay 4.13) \| HaCon ‘Thus, the equilibrium overdrive is equal to A Vin /-V2. The point is that increasing A Viqi to make the circuit more linear inevitably increases the overdrive voltage of My and Ms. For a given Iss, this is accomplished only by reducing W/L and hence the transconductance of the transistors. ‘We now study the small-signal behavior of differential pairs. As depicted in Fig. 4.14, wwe apply small signals Vigi and Vigo and assume M; and Mz are saturated. What isthe dif- ferential voltage gain, Vour/(Vini ~ Vina)? Recall from Eq, (4.11) that this quantity equals ViinCoTssW7ERo. Since in the vicinity of equilibrium, each transistor carries approxi- mately Z55/2, this expression reduces to gm Rp, where gm denotes the transconductance of ‘My and Mz. To arrive atthe same result by small-signal analysis, we employ two different ‘methods, each providing insight into the circuit's operation. We assume Ro = Roz = Ro.Sec.42 Basie Differential Pair 1 Figure 4.14 Dilferential pair with small-signal inputs. © © Figure 4.15 (a) Differential par sensing one input signal, (b) circuit of (4) viewed as a CS stage degenerated by Mo, (c) equivalent circuit of (b). Method! The circuit of Fig. 4.14is driven by two independent signals. Thus, the output can be computed by superposition. Letus set Via to zero and find the effect of Vins at X and ¥ (Fig. 4.15(a). To obtain Vi, we note that My forms a common-source stage with a degeneration resistance equal tothe impedance seen looking into the source of Mz (Fig. 4.15(b)]. Neglecting channel-length12 Chap. 4 Differential Amplifiers Yoo Poa’ ¥ $2 Vouta J @ o Figure 4.16 Replacing My by a Thevenin equivalent. ‘modulation and body effect, we have Rs = 1/gna (Fig. 4.15(c)] and Vx. =o Vat 4.14) + Bri | Bm To calculate Vy, we note that M; drives Mz as.a source follower and replace Vins and M by a Thevenin equivalent (Fig. 4.16): the Thevenin voltage Vr = Vigi and the resistance Rr = 1/8mi- Here, Mz operates as a common-gate stage, exhibiting a gain equal to Vy Ro wre (4.15) Sma Bei It follows from (4.14) and (4.15) that the overall voltage gain for Vint is =2Rp (Vie = Vode vint Vint» 4.16) Sei Bn which, for gmt = Sa2 = Bm reduces to (Vie ~ Vr)loue wo vint = ~8orRo Vint 4.17) By virtue of symmetry, the effect of Ving at X and ¥ is identical to that of Vin except for a change in the polarities: (Wx — Vo)ioue w vind = Be RoVin2- 18) ‘Adding the two sides of (4.17) and (4.18) to perform superposition, we have (Wx = Vr roe =) 4.19) Vn = Vig = eR: 4.19)Sec.42 Basic Differential Pair 113 ‘Comparison of (4.17), (4.18), and (4.19) indicates that the magnitude of the differential gain is equal to gm Rp regardless of how the inputs are applied: in Figs. 4.15 and 4.16, the input is applied to only one side whereas in Fig. 4.14 the input is the difference between two sources. It is also important to recognize that if the output is single-ended, ic, it is sensed between X or Y and ground, the gain is halved. Example 4.3 Inthe circuit of Fig. 4.17, Ma is twice as wide as My. Calculate the small-signal gain if the bias values (of Vint and Ving are equal. Figure 4.17 Solution Ifthe gates of Mj and Mz are atthe same de potential, then Vos1 = Vos2 and Ipa = 2Ip1 = 2ss/3 Thus, Smt = V2nCor(WILMG573 and sn2 = /2inCoxCOW]LIIGS7S = 28m. Following the same procedure as above, the reader can show that 2Rp lay) = 782 (420) + Got” 2am 4 = FemiRo. 20 Note that, for a given Zss, this value is lower than the gain of a symmetric differential pair (with 2W/L for each device) [Eq. (4.19)] because gy is smaller How does the gain of a differential pair compare with that of a common-source stage? For a given toral bias current, the value of gm in (4.19) is 1/./2 times that of a single transistor biased at /s¢ with the same dimensions. Thus, the total gain is proportionally less. Equivalently, for given device dimensions and load impedance, a differential pair achieves the same gain as a CS stage at the cost of twice the bias current, Method I Ifa fully-symmetric differential pair senses differential inputs (i.e. the two inputs change by equal and opposite amounts from the equilibrium condition), then the concept of “half circuit” can be applied. We fist prove a lemma,14 Chap. 4 Differential Amplifiers Lemma. Consider the symmetric circuit shown in Fig.4.18(a), where D, and D, represent @ © © Figure 4.18 Ilustration of why node P is a virtual ground. any three-terminal active device. Suppose Vini changes from Vo t0 Vo+ 4 Vig and Via from Vo to Vo — AVi, [Fig. 4.18(b)]. Then, if the circuit remains linear, Vp does not change. Assume A = 0, Proof. Let us assume that Vi and V; have an equilibrium value of V, and change by AV; ‘and AV2, respectively [Fig. 4.18(0)]. The output currents therefore change by £m AV; and Bn AVa. Since Ih + Ia = Ir, We have gm AV: + Bm AV2 = 0, ie, AV; = —AV2, We also know Vini ~Vi = Vina—Va,and hence Vo+ AVin ~(Wa+ AV) = Vo AVin ~Wat AV2) Consequently, 2Vin = AV; — AV2 = 2AVj. In other words, if Vin1 and Vina change by +AVj, and—AV;,,fespectively, then V; and V2 change by the same values, i.e, differential change in the inputs is simply “absorbed” by Vi and V2. In fact, since Vp = Viqj ~ Vi, and since V; exhibits the same change as Vin1, Vp does not change. a The proof of the foregoing lemma can also be invoked from symmetry. As long as the operation remains linear so that the difference between the bias currents of D; and D2 is negligible, the circuit is symmetric, Thus, Vp cannot “favor” the change at one input and “ignore” the other. ‘From yet another point of view, the effect of D; and Dz at node P can be represented by Thevenin equivalents (Fig. 4.19). If Vry and V2 change by equal and opposite amounts and Rri and Rr2 are equal, then Vp remains constant. We emphasize that this is valid if the changes are small such that we can assume Rr) = Rr2 The above lemma greatly simplifies the small-signal analysis of differential amplifiers. AAs shown in Fig. 4.20, since Vp experiences no change, node P can be considered "ac ground” and the circuit can be decomposed into two separate halves, hence the term “half-cireuit concept” [1]. We can write Vx/ Vint = —&mRp and Vy /(—Vin) = ~8mRos where Vini and —Viqi denote the voltage change on each side, Thus, (Vix — Vy) /(2Vini) = ~enRo “itis also posible to derive an expression forthe large-signal behavior of Vp and prove that for small ~ Vga, Vp remains constant, We defer this calculation to Chapter 1,Sec. 4.2 Basic Differential Pair 115 Figure 4.19 Replacing each half of differential pair by a Thevenin equivalent. © Figure 4.20 Application of the half-circut concept. Example 44 Calculate the differential gain of the circuit of Fig. 420(a) if #0. Solution Applying the half-circuit concept as illustrated in Fig. 4.21, we have Vx/Vist = —&m(Rpllro1) and Vy/(—Vint) = ~8m(Roliro2), thus arriving at (Vx ~ Vv)/@Vin1) = —8m(Rolro). where ro = ro: = ron. Note that Method I would require lengthy caleulations here, Figure 4.21 ‘The half-circuit concept provides a powerful technique for analyzing symmetric differ ential pairs with fully differential inputs. But what happens ifthe two inputs are not fully116 Chap.4 Differential Ampiiiers © @ Figure 4.22 Conversion of arbitrary inputs to differential and common-mode components. differential [Fig. 4.22(a)]? As depicted in Figs. 4.22(b) and (c), the two inputs Viqy and Ving can be viewed as Vint = Vin2 Vin fin Vian m= Viet Vira 4, Vion Vian 422) z Vina = Mina = Vint Vins + Vea aa Since the second term is common to both inputs, we obtain the equivalent circuit in Fig. 4.22(d), recognizing that the circuit senses a combination of a differential input and a common-mode variation. Therefore, as illustrated in Fig. 4.23, the effect of each type of input can be computed by superposition, with the half-circuit concept applied to the differential-mode operation. Example 4,5 Inthe cireuit of Fig. 4.20(a), calculate Vy and Vy if Visa # —Vina and & # 0.‘Sec.4.2 Basic Ditferential Pair 17 @ o Figure 4.23 Superposition for differential and common-mode signals. Solution For differential-mode operation, we have from Fig. 4.24(a) Vint = Vin ~an(Rolroi) Ve = = 42H Wy = ~fn(Rotro2 ae Met, 428) That is, Vi ~ Vr = ~am(Ro ro} Vint ~ Vina) 426) Which isto be expected, Oo) © Figure 4.24 For common-mode operation, the circuit reduces to that in Fig. 4.24(b). How much do Vix and Vy change as Vie,car changes? Ifthe circuit is fully symmetric and Iss an ideal current source, the118 Chap. 4 Differential Ampitirs ceurrent drawn by My and Ms from Rp} and Rp2 is exactly equal to [55/2 and independent of Vi,cx ‘Thus, Vx and Vy experience no change as Vip,cxs Varies. Interestingly, the circuit simply amplifies the difference between Vini and Vin2 while eliminating the effect of Vin,cu 4.3 Common-Mode Response ‘An important attribute of differential amplifiers is their ability to suppress the effect of ‘common-mode perturbations. Example 4.5 portrays an idealized case of common-mode response. In reality, neither isthe circuit fully symmetric nor does the current source exhibit an infinite output impedance. As a result a fraction of the input CM variation appears at the output We first assume the circuit is symmetric but the current source has a finite output impedance, Rss (Fig. 4.25(a)]. As Vinca changes, so does Vp, thereby increasing the drain currents of M; and Mz and lowering both Vy and Vy. Owing to symmetry, Vy re- ‘mains equal to Vy and, as depicted in Fig. 4.25(b), the two nodes can be shorted together. Since My and Mz are now “in parallel” ic., they share al oftheir respective terminals, the Vout Vincu hs M+ Me © © Figure 4.25 (a) Differential pair sensing CM input, (b) simplified version of (a), (c) equivalent circuit of ()%.43 Common-Mode Response 119 circuit can be reduced to that in Fig. 4.25(c). Note that the compound device, My + Ms, hhas twice the width and the bias current of each of Mj and Mz and, therefore, twice their ‘transconductance. The CM gain of the circuit is thus equal to 4.27 Ro/2 1/Q28m) + Rss’ where gq denotes the transconductance of each of M; and My and A= y = 0. ‘What is the significance of this calculation? In a symmetric circuit, input CM variations disturb the bias points, altering the small-signal gain and possibly limiting the output voltage swings. This can be illustrated by an example. (4.28) Example 4.6 The circuit of Fig, 4.26 uses a resistor rather than a current source to define a tail current of I mA. Figure 4.26 Assume (W/L)1,2 = 25/0.5, un Cox = 50 WAIV?, Vr = 0.6 V,2= y = 0,and Vp =3 V. (a) What is the required input CM for which Rss sustains 0.5 V? () Calculate Rp for a differential gain of 5 (©) What happens atthe output ifthe input CM level is 50 mV higher than the value calculated in ow 0.5 mA, weave erm Yost = Vos Pl + Ven (429) bnCox = 133. 430) Thus, Vino = Voi +05 V= 1.73 V. Note that Rgs = $00 9. () The transconductance of each device is gm = J ThinCox(W7T)[oi = 1/(632 2), requiring Rp = 3.16k8 fora gain of 5. ‘Note thatthe output bias level is equal to Vop — Ipi Rp = 1.42 V. Since Vin,cw = 1.73 V and (0.6 V, the transistors are 290 mV away from the trode region, Vn120 Chap.4 Differential Ampitiers (©)If Vi,ca increases by 50 mY, the equivalent circuit of Fig. 4.25(c) suggests that Vy and Vy drop by op [AV rl = AVin cw go> aan (Ava! = AVincM Re 1m) am 50 mV x 194 ax) = 968 mv 39 Now, My and Mz are only 143 mV away from the trode region because the input CM level has increased by 50 mV and the output CM level has decreased by 96.8 mV. —————————— ‘The foregoing discussion indicates thatthe finite output impedance of the tail current source results in some common-mode gain in a symmetric differential pair. Nonetheless, this is usually a minor concern, More troublesome isthe variation of the differential output as a result of a change in Vjp,cy, an effect that occurs because in reality the circuit is not fully symmetric, ic. the two sides suffer from slight mismatches during manufacturing. For example, in Fig. 4.25(a), Roi may not be exactly equal to Rp2. We now study the effect of input common-mode variation if the circuit is asymmetric and the tail current source suffers from a finite output impedance. Suppose, as shown in Fig. 4.27, Rp1 = Rp and Ror = Rp + ARp, where ARp denotes a small mismatch and Yoo Ro Ag+ Ay Yours ° Vouta Vs,cu Figure 4.27 Common-mode response inthe presence of resistor mismatch, the circuit is otherwise symmetric. What happens to Vx and Vy as Vie,cu increases? Since ‘M, and Mz are identical, Zp; and Ip increase by [8m /(1 + 28m Rss)1A Vie,ca, but Vx and Vy change by different amounts: Vx = ~AVincm ee a Rake (434) Bn AVy = —AVincew Rp + ARp). 4.35) MTF gags “0 * ARO) ae) ‘Thus, common-mode change at the input introduces a differential component atthe output. We say the circuit exhibits common-mode to differential conversion, This is a critical problem because if the input of a differential pair includes both a differential signal andSec. 4.3 ‘Common-Mode Respons 121 common-mode noise, the circuit corrupts the amplified differential signal by the input CM change. The effect is illustrated in Fig. 4.28. Yoo Figure 4.29 CM response with finite tail capacitance. Jn summary, the common-mode response of differential pairs depends on the output impedance of the tail current source and asymmetries in the circuit, manifesting itself through two effects: variation of the output CM level (in the absence of mismatches) and conversion of input common-mode variations to differential components at the output. In analog circuits, the latter effect is much more severe than the former. For this reason, the ‘common-mode response should usually be studied with mismatches taken into account. How significant is common-mode to differential conversion? We make two observations. First, asthe frequency of the CM disturbance increases, the total capacitance shunting the tail current source introduces larger tail current variations. Thus, even if the output resistance of the current source is high, common-mode to differential conversion becomes significant at hhigh frequencies. Shown in Fig. 4.29, this capacitance arises from the parasitic ofthe current source itself as well as the source-bulk junctions of M; and M2. Second, the asymmetry in the circuit stems from both the load resistors and the input transistors, te latter contributing a typically much greater mismatch. Let us now study the asymmetry resulting from mismatches between My and Mp in Fig. 4.30(a). Owing to dimension and threshold voltage mismatches, the two transistors122 Chap. 4 Differential Amplifiers @ © Figure 4.30 (2) Differential par sensing CM input, (b) equivalent circuit of (@), carry slightly different currents and exhibit unequal transconductances. To calculate the gain from Via,cu to X and Y, we use the equivalent circuit in Fig. 4.30(b), writing Ip; = Bmi(Vin.cw — Ve) and Ipa = Bma(Vin.cw — Vp). That is, (amt + 8n2XVin.cu — Vo)Rss = Vey 436) and Vp = Sart emdRss yo (437) Gm + &na)R55-+ 1 ‘We now obiain the output voltages as Ve = —8miVincw — Ve) 438) =Bmi 5 RoVincm 4.39) Gm F Gna) R55 41 ee and Vy = ~8na(Vincw ~ Ve)Ro (440) 802 Ry Vin.cn. aan Gm ¥ Bad Rss +1 ‘The differential component atthe output is therefore given by Smt ~ Bn Vy — Vy = ———Snt—fr2_ (mt + Gad Rss +1 Vinca 442) In other words, the circuit converts input CM variations to a differential error by a factorSec.43 Common-Mode Response 123 ‘equal to Abn Ro Acu-pw = -——8n8o___, MOMS Gus + BuadRs +1 where Acn-pw denotes common-mode to Smt — Bm Example 4.7 ‘Two differential pairs are cascaded as shown in Fig. 4.31. Transistors Ms and MG suffer from a gm Figure 4.31 mismatch of Agm, the total parasitic capacitance at node P is represented by Cp, and the circuit is ‘otherwise symmetric. What fraction of the supply noise appears as a differential component at the ‘output? Assume 2 7 Solution "Neglecting the capacitance at nodes A and B, we note thatthe supply noise appears at these nodes ‘with no attenuation. Substituting 1/(Cps) for Rss in (4.43) and taking the magnitude, we have Aen \Ac-pul aay 1 J1+ (m3 + Sma) YF Gas +emeF| 25} ‘The key points thatthe effect becomes more noticeable asthe supply noise frequency, increases. For meaningful comparison of differential circuits, the undesirable differential com- ponent produced by CM variations must be normalized to the wanted differential output resulting from amplification. We define the “common-mode rejection ratio” (CMRR) as, CMRR (4s) Apu ‘Acu-pu124 Chap. 4 Differential Amplifiers only gq mismatch is considered, the reader can show from the analysis of Fig. 4.15 tat Ro &mi + 82 + 4Gmi8m2 R55 Abul = 446) ow = TT mi Fema Rss “eo her itis assumed Vin) = —Vigas and hence Corn p a Smit 8n2 + Mamba Rss as 76m fu x B14 2gaRss), . FEO + 260859, (4.48) where gm denotes the mean value, ic., gm = (m1 + &m2)/2. In practice, all mismatches ‘must be taken into account. 4.4 Differential Pair with MOS Loads ‘The load of a differential pair need not be implemented by linear resistors, As with the common-source stages studied in Chapter 3, differential pairs can employ diode-connected or current-source loads (Fig. 4.32). The small-signal differential gain can be derived using Yoo Yoo 5 ve “a! Diss Olss ® ® Figure 4.32 Disferenal per with (a) diode-connected and (b)curent- source loads, the half-cireuit concept. For Fig. 4.32(a), Av = —8nw (Snplrowlror) 449) Sat | (4.50) Bn where subscripts 1” and P denote NMOS and PMOS, respectively. Expressing gm and Smp in terms of device dimensions, we have wn(W/L we Ay — aspSec.4.4 Differential Pair with MOS Loads 125 For Fig. 4.32(b), we have Sma (ronlror): (4.52) In the circuit of Fig. 4,32(a), the diode-connected loads consume voltage headroom, thus creating a trade-off between the output voltage swings, the voltage gain, and the input CM. range. Recall from Eq, (3.35) that, for given bias current and input device dimensions, the circuit's gain and the PMOS overdrive voltage scale together. To achieve a higher gain, (W/L)p must decrease, thereby increasing |Vesp — Vrip| and lowering the CM level at nodes X and ¥. In order to alleviate the above difficulty, part of the bias currents of the input transistors can be provided by PMOS current sources. Illustrated in Fig. 4.33, the idea is to lower the 8m of the load devices by reducing their current rather than their aspect ratio. For example, Figure 4.33 Addition of current sources to increase the voltage gain if Ms and Mg carry 80% of the drain current of M; and Mp, the current through M; and My is reduced by a factor of five. For a given |Vesp — Vrrrl this translates toa factor of five reduction in the transconductance of Ms and Mg because the aspect ratio of the devices can be lowered by the same factor. Thus, the differential gain is now approximately five times that of the case with no PMOS current sources. The small-signal gain ofthe differential pair with current source loads is relatively low — in the range of 10 t0 20 in submicron technologies. How do we increase the voltage gain? Borrowing ideas from the amplifies in Chapter 3, we increase the output impedance of both PMOS and NMOS devices by cascoding, in essence creating a differential version of the cascode stage introduced in Chapter 3. The result is depicted in Fig. 4.34(a). To calculate the gain, we construct the half circuit of Fig. 4.34(b), which is similar to the cascode stage of Fig. 3.60. Thus, lel © &millGmarosrouIIl(Gnsrosro7)] (4.53) Cascoding therefore increases the differential gain substantially but atthe cost of consuming, more voltage headroom, As a final note, we should mention that high-gain fully differential amplifiers require a ‘means of defining the output common-mode level. For example, in Fig. 4.32(b), the output126 Chap. 4 Differential Amplifiers Vege tt My Yeas If Ms Vor ts Ms Vines My © Figure 4.34 (2) Cascode differential pair, (b) half circuit of (2) ‘common-mode level is not well-defined whereas in Fig. 4.32(a), diode-connected transistors define the output CM level as Vp — Vasp. We return to this issue in Chapter 9. 4.5 Gilbert Cell ur study of differential pairs reveals two important aspects of their operation: (1) the small-signal gain of the circuit is a function of the tail current and (2) the two transistors ina differential pair provide a simple means of steering the tail current o one of two destinations. By combining these two properties, we can develop a versatile building block. Suppose we wish to construct a differential pair whose gain is varied by a control voltage. ‘This can be accomplished as depicted in Fig. 4.35(a), where the control voltage defines the © Figure 4:35. (a) Simple VGA, (b) two stages providing variable gainSec.4.5 Gilbert Cell ae tail current and hence the gain. In this topology, Ay = Vou:/ Vin aries from zer0 (if Ips = 0) toa maximum value given by voltage headroom limitations and device dimensions. This circuit is a simple example of a “variable-gain amplifier” (VGA), VGAs find application in systems where the signal amplitude may experience large variations and hence requires inverse changes in the gain, Now suppose we seek an amplifier whose gain can be continuously varied froma negative value to a positive value. Consider two differential pairs that amplify the input by opposite gains (Fig. 4.35(b)]. We now have Voyca/ Vin = ~8m Rp and Vour2/ Vix = +8mRo, Where 4m denotes the transconductance of each transistor in equilibrium, If [and 2 vary in ‘opposite directions, so do |Vouei/ Vinl and |Vaue2/ Vin. But how should Vous; and Voy2 be combined into a single output? As illustrated in Fig, 4.36(a), the two voltages can be summed, producing Vous = Vout + Veur2 = At Vin-+A2Viny Figure 4.36 (a) Summation of the output voltages of two amplifiers, (b) summation in the current domain, (c) use of Ms-Mg to control the gain, (4) Gilbert cell.128 Chap. 4 Differential Amplifiers where A; and Azare controlled by Veon and Veon2Tespectively. The actual implementation is in fact quite simple: since Vounr = RoZp1 ~ Rplp2 and Vourr = Rope ~ Roly We hhave Vou + Voua = Ro(p1+ !ps)— Ro(p2+ Ips). Thus, rather than add Vout and Vowas ‘we simply short the corresponding drain terminals to sum the currents and subsequently generate the output voltage (Fig. 4.36(b)]. Note that iffy = 0, then Vous = +8mRVin and if fz = 0, then Vous = ~8mRDVin. Fot 1y = Ja, the gain drops to zero. In the circuit of Fig. 4.36(b), Veoeri and Vegu2 must vary [1 and 1; in opposite directions such thatthe gain ofthe amplifier changes monotonically. What circuit can vary two currents in opposite directions? A differential pair provides such a characteristic, leading to the topology of Fig. 4.36(c). Note that for a large |Veonsi ~ Veonals all of the tail current is steered to one ofthe top differential pairs and the gain from Vi, to Vag is atts most positive ‘or most negative value. For Veonri = Vion the gai is zero. For simplicity, we redraw the circuit as shown in Fig. 4.36(4). Called the “Gilbert cell” [2], this circuit is widely used in ‘many analog and communication systems. In atypical design, My-Ma are identical and so are Ms and Me. Example 4.8 [Explain why the Gilbert cell can operate as an analog voltage multiplier. Solution ‘Since the gain of the circuit i a function of Veone = Veont — Veont2, We have Vous = Vin f(Veon) Expanding f(Veon) in a Taylor series and retaining only the first-order term, Vion, We have Vous = Vin Veon- Thus, the circuit can multiply voltages. This property accompanies any voltage-controlled vvariable-gain amplifc ‘As with a cascode structure, the Gilbert cell consumes a greater voltage headroom than simple differential pair does. This is because the two differential pairs My-Mz and Ms-Mx are “stacked” on top of the control differential pair. To understand this point, suppose the differential input, Vin, in Fig. 4.36(d) has a common-mode level Veuin- Then, Va = Vew.in= Vast. where My-Ms are assumed identical, For Ms and Mg to operate in saturation, the CM level of Vous Veucoms must be such that Vexcon < Vcsein — Vast + Vrs Since Vesi — Vrus.is roughly equal to one overdrive voltage, we conclude thatthe control CM level must be Tower than the input CM level by atleast this value, In arriving at the Gilbert cell topology, we opted to vary the gain of each differential pair through its tail current, thereby applying the control voltage to the bottom pair and the ‘input signal to the top pairs. Interestingly, the order can be exchanged while still obtaining a VGA. Ilustrated in Fig. 4.37(a), the idea is to convert the input voltage to current by means of Ms and Mg and route the current through My-Mg to the output nodes. If, as shown in Fig. 4.37(b), Veo is very positive, then only My and Mz are on and Vou = ns.6Rp Vin. Similarly if Veou is very negative (Fig. 4.37(0)] then only Ms and Ms are on and Vou = —8ns.6RoVie. If the differential control voltage is zero, then Voy, = 0. The input differential pair may incorporate degeneration to provide a linear voltage-to-currentProblems 129 Figure 4.37 (a) Gilbert cell sensing the input voltage by the bottom differential pair, (b) signal path for very positive Vogts () signal path for very negative Voon Problems Unless otherwise stated, in the following problems, use the device data shown in Table 2.1 andassume Vop = 3 V where necessary. All device dimensions are effective values and in microns. 4.1, Suppose the total capacitance between adjacent lines in Fig. 42 is 10 fF and the capacitance from the drains of My and Mz to ground is 100 FF. (a) What is the amplitude of the glitches in the analog output in Fig. 4.2(a) fora clock swing of V7 (b) Ifin Fig. 4.2(b), the capacitance between L and Lis 1096 less than that between Ly and La, what isthe amplitude ofthe glitches in he differential analog output for a clock swing of3V? 4.2, Sketch the small-signal differential voltage gan ofthe circuit shown in Fig. 4.8(a)if Vp vaties from 0 t03 V. Assume (W/L) = 50/05, Vin.cu Construct the plots of Fig. 4.8(c) fora differential pair using PMOS transistors In the citeuit of Fig. 4.10, (W/L),2 = 50/0.5 and Iss (a) What isthe maximum allowable output voltage swi (b) What is the voltage gain under this condition’ 45. A differential pair uses input NMOS devices with W/Z = 50/0.5 and a til current of I mA. (a) What is the equilibrium overdrive voltage ofeach transistor? (b) How isthe tail current shared between the wo sides if Vin — Vinz (c), What is the equivalent Gy, under tis condition? (@) For what value of Vint ~ Vina does the Gy drop by 109%? By 905? 4.6. Repeat Problem 4.5 with W/L 4.7. Repeat Problem 4.5 with a tail curtent of 2 mA and compare the results 48. Sketch Zp and /p2 in Fig. 4.17 versus Vin ~ Vina. For what value of Vint ~ Vie are the two ‘currents equal? ge Oma? 5/0.5 and compare the results,