Feature

Exploiting the Body

of MOS Devices for
High Performance
Analog Design
Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti,
and Alessandro Trifiletti

Abstract
With the progressive reduction of MOS transistors mini-
mum dimension and their associated supply voltages, the body
terminal—considered in the past as an exclusive source of unwant-
ed second order effects—has been advantageously exploited by
digital designers and is also becoming an attractive opportunity
for the implementation of high-performance analog integrated
circuits. In this paper, we will discuss some techniques that
can be applied to many conventional analog building blocks in
order to improve their performance (such as gain and linear-
ity) and/or decreasing their supply demand. Experimental
prototypes have been implemented and tested, showing
that the proposed techniques are promising candidates
for enhanced analog IC design in nanoscale technologies.

Index Terms—Body Effect, Low Voltage Amplifi-

ers, Transimpedance Amplifiers, Current Mirrors,
Transconductors, Gain Boosting.

1. Introduction

T
he body (or bulk) terminal of CMOS transistors was once known princi-
pally for the adverse consequences of the so called body effect that is a
change of the transistor threshold voltage, VT, due to a nonzero source-
bulk voltage which, for an n-channel MOS transistor, is expressed by

VT 5 VT 0 1 g A "2fF 2 vBS 2 "2fF B , (1)

Digital Object Identifier 10.1109/MCAS.2011.942751

Date of publication: 22 November 2011

8 IEEE CIRCUITS AND SYSTEMS MAGAZINE 1531-636X/11/$26.00©2011 IEEE FOURTH QUARTER 2011
 where VT 0 is the zero-bias thresh-
old, fF is the Fermi potential and g
is the body effect parameter.
In the last years however, the
foregoing effect has been favorably
exploited, mainly by digital designers,
to counteract the limitations incurred
by deep submicron and nanoscale CMOS
devices. For instance, reverse body bias,
which increases the threshold voltage of
transistors, was applied to reduce the sub-
threshold leakage during active burn-in and
stand-by operation [1]–[6] and to compen-
sate for intradie and interdie parameter varia-
tions [7]–[8]. Besides, forward body bias was
used in [9] to design a 1-GHz communication
router operating at 1.1-V supply, whereas adap-
tive body bias and dynamic voltage scaling were
adopted to decrease the power consumption in
microprocessors [10]–[11]. Finally, body bias was
exploited for yield optimization of digital CMOS cir-
cuits [12].
The bulk terminal has also been utilized by ana-
log designers to face the progressive supply voltage
reduction. Threshold voltage lowering was adopted
to design 1-V amplifiers in a 0.5-mm process using the
current driven bulk technique [13]–[14]. But the main us-
age of the bulk terminal is represented by the well-known
body driven technique in which the body is the main input
terminal [15]–[19]. To enable body driving, the gate must
be biased to form a conduction channel inversion layer and
the drain current can be modulated by varying the bulk
voltage through the body effect (1). The bulk-driven transis-
tor is hence a depletion-type device which can work under
negative, zero, or even slightly positive source-bulk voltages.
Compared to conventional gate-driven circuits, the body-driven
ones are characterized by a lower achievable voltage gain and/
or bandwidth as well as increased noise, caused by the limited
transconductance value (the body transconductance, gmb, is only
about 10–20% of the gate transconductance gm). Moreover, body-
driven techniques require a triple-well technology to allow the inde-
pendent control of the body of n- and p-channel MOS devices. Nev-
ertheless, several body-driven implementations have been proposed
[15]–[19] for low-frequency low-gain applications. Gain boosting tech-
N

niques have also been discussed as a possible remedy to the above

ISIO
V
ITAL
© DIG

P. Monsurrò, G. Scotti, and A. Trifiletti are with the DIE (Dipartimento di Ingegneria Elettronica),
University of Rome “Sapienza”, Italy. (e-mail: {scotti,trifiletti}@mail.die.uniroma1.it).
S. Pennisi is with the DIEEI (Dipartimento di Ingegneria Elettrica Elettronica e Informatica),
University of Catania, Italy. (e-mail: salvatore.pennisi@dieei.unict.it).

FOURTH QUARTER 2011 IEEE CIRCUITS AND SYSTEMS MAGAZINE 9

 We will discuss in this paper some additional techniques that exploit the MOS bulk
terminal to improve the performance of widely employed analog building blocks in
terms of achievable gain and linearity and/or to decrease the supply demand.
limitations [18]. In addition, as the switched-capacitor
approach cannot take advantage of pure body-driven
circuits due to the bulk finite input resistance and leak-
age currents, source-follower transistors were added
to shield the bulk input terminal [19].
To further expand this scenario, we will discuss in
this paper some additional techniques that exploit the
MOS bulk terminal to improve the performance of wide-
ly employed analog building blocks in terms of achiev-
able gain and linearity and/or to decrease the supply
demand. The paper reviews in a unified manner several
techniques already proposed by the authors and intro-
duces also a new approach amenable for transimped-
ance amplifiers. More specifically, a body-biasing tech-
nique, able to accurately set the quiescent current of a
MOS transistor through its body terminal is discussed
in sec. II. The body-driven gain boosting technique
is dealt with in sec. III and the dual loop technique is
proposed in Sec. IV. Then, a linearization technique for
VDD
M3 M4
VIN– VIN+ CC
M1 M2
Vbias
M7
VSS
(a)
VDD
M3r NIB
+ –
A With the proposed body-biasing technique, we ex-
IB
M5r
VSS
(b)
Figure 1. (a) Simplified schematic of the basic class AB
OTA and (b) simplified schematic of the biasing circuit
generating Vb .
10 IEEE CIRCUITS AND SYSTEMS MAGAZINE
source-coupled pairs is treated in Sec. V. Some authors’
conclusions are finally summarized in sec. VI.
II. Body Replica Biasing
The first technique we discuss here is a replica biasing
approach that allows the quiescent current of a MOS de-
vice to be accurately set through its body terminal. It
can be applied for example to set the standby current
in a class AB output stage [20] or in a minimum-supply
differential pair while improving its common-mode re-
jection ratio [21].
A. Class AB Output Stage with
Quiescent Current Control
Let us consider the well-known two-stage Miller op-
erational amplifier in Fig. 1(a). It is made up of an input
source-coupled pair (M1-M2) with mirror load (M3 -M4) and
a second stage (M5 and M6). The gates of M5 -M6 are tied
together and directly connected to the output of the first
stage Miller compensation through capacitor Cc across the
second stage is also shown. This solution enables class
AB operation at the output, since the maximum achiev-
able output current in the positive and negative transition
is independent of the quiescent current of M5 and M6 but
M6 is determined by the minimum and maximum voltage at
the output of the first stage and by the chosen aspect ra-
Vout
tio of M5 -M6. Among all the possible alternatives, this out-
put stage topology is the simplest one and for this reason
Vb
it maximizes the output swing. The main drawback of this
solution, that prevents its use in practical applications, is
M5
related to the ill definition of the quiescent current in the
output branch (M5 -M6). Its value cannot be set accurately,
since it strongly depends on the matching properties of
M5 and M6 (that have different channel type), on the qui-
escent output voltage of the first stage and on the supply
voltages. This means that parameters related to this cur-
rent (like output transconductance and dc power dissipa-
tion) are subject to large variations.
ploit the bulk terminal of M5 to control the quiescent
current of the output branch. The body voltage is set
Vb
through a suitable feedback control section based on a
replica bias. The operating principle can be easily ex-
plained by analyzing Fig. 1(b). Transistors M3r and M5r
form a replica of M3 and M5 in the first and second stage
of the OTA and current IB is equal to half that in M7. If we
want to reduce the power consumption of the auxiliary
FOURTH QUARTER 2011
biasing network, we can adopt a scaled replica version
in which currents and aspect ratios in the biasing circuit
are a scaled version of the corresponding parameters in
the main circuit. However, it should be observed that
one biasing network can serve several amplifiers. We as-
sume that the desired quiescent current of M5 -M6 is N
times the quiescent current of M3 (and M4). Therefore,
the aspect ratio of M6 is N times that of M3 -M4 in order
to equalize the VDS voltage of M3 -M4 (and M1-M2) and,
consequently, to avoid systematic offset due to bias in-
equalities of the source-coupled pair.
As a result, the VGS of M5 and that of its replica M5r
are nominally the same. Considering the bias circuit, we
note that the error amplifier A forces the current of M5r
to equal N IB. Since the negative input of A is connected
to the analog ground (VDD1VSS )/2, the negative feedback
sets also the drain of M5r to analog ground by modifying
its body voltage Vb.
The same voltage is used to control the body termi-
nal of M5, which has the same quiescent current of M5r.
The scheme in Fig. 1(b) could require a voltage Vb
spanning below VSS to ensure proper operation. Such a
voltage can be provided either by a separate continu-
ous-time section powered at a higher supply voltage or
by a switched-capacitor section which implements the
error amplifier sensing the drain current of M5r (and
powered at the same supply VDD of the main amplifier).
Fig. 2(a) shows a possible schematic of the bias control
circuit. M15 and M16 constitute a 1:N current mirror that
sets the desired bias current for the replica transistor
M5r. Transistors M7-M10 implement the error amplifier A,
the Miller capacitor, CC, between gate and drain of M7
performs frequency compensation. Transistors M11-M14
together with capacitors C1 and C2 form a switched-ca-
pacitor level shifter, that shifts the output signal from
the analog ground, (VDD 1 VSS )/2, to VSS. The size of
switches and capacitors has to be chosen to minimize
the phase shift around the loop, and a clock frequency
(with non-overlapped phases f 1 and f2 ) much higher than
the maximum signal frequency has to be used.
A drawback of this particular implementation is that
the quiescent drain current of transistors M9 -M10 is ill
defined. This can impact current consumption (if a val-
ue higher than the nominal one is actually obtained) or
the time interval to reach a stable dc current starting
from power on (this time interval increases for lower
currents). However, due to the low supply voltages ad-
opted, the current variation is limited and it only mar-
ginally affects the performance parameters of the main
amplifier. Nevertheless, this problem can be avoided by
configuring M10 as a constant current source. This solu-
tion is illustrated in Fig. 2(b). In this case, due to the

VDD
f1 f2
M10 Vb
M3r M15 M8
M16 M11 M13
CC C1 C2
M14
IB IB
Vb f1
M9 M12 f2
M5r M7
VSS
VSS
(a)
VDD
f1 f2
Vb1 Vb
M3r M15 M8 M10
M16 M11 M13
C1 C2
CC2 CC1
M14
IB IB
Vb f1
M9 M12 f2
M5r M7
VSS
VSS
(b)

Figure 2. Detailed schematics of the switched-capacitor biasing circuit (a) alternative solution with better quiescent cur-
rent definition but (b) requiring nested Miller frequency compensation.

FOURTH QUARTER 2011 IEEE CIRCUITS AND SYSTEMS MAGAZINE 11

 In order to reduce the supply demand of the standard long-tailed pair to its
lower limit, we can remove the tail current generator and obtain
the circuit shown in Fig. 3(a).

additional high-impedance output node that is created,
we now need a nested-Miller frequency compensation
scheme for the loop stability [22]–[25] implemented by
capacitors CC1 and CC2.
B. Minimum Supply Differential Stage
The source-coupled differential stage is one of the most
ubiquitous analog CMOS cells. In order to reduce the
supply demand of the standard long-tailed pair to its
lower limit, we can remove the tail current generator
and obtain the circuit shown in Fig. 3(a). Resistors RCM
provide output common-mode voltage control, as M2a-b
are diode-connected for common-mode input signals.
Let us initially assume that voltage Vb at the bulks of
M1a-b is constant. The differential and common-mode
gains provided by the circuit are
the bulk terminal of the pair as an additional control
node. Transistors M1ar-M1br form a replica of the differ-
ential pair. Negative feedback provided by the error
amplifier, A, sets the drain current of transistors M1ar-
M1br to IBr/2 and forces the drain of M1ar-M1br to ground,
i.e. (VDD 1 VSS )/2, by modifying the bulk voltage of the
replica pair, Vb (to be applied to the original pair), ir-
respectively of the common mode input voltage. Con-
sequently, since M1a-M1b have the same VGS and VBS as
M1ar-M1br, the current in the original pair will be forced to
be a multiple of IB, depending on the relative width of M1-
M1r. Analyzing the circuit in Fig. 3(a), with the additional
biasing/common-mode section illustrated in Fig. 3(b)
feeding the body of M1a and M1b, the differential gain of
the body-biased pair is approximately equal to (2), but
the common-mode gain is now

vout2 gm1 1 1 1 2 Agmb1r rBr 2 2 2 Agm1r gmb1 rBr

Acm 5 52
VDD VDD vin, cm 1 1 1 2Agmb1r rBr 2 gm2
VIN+ VIN– V
M1a M1b IN+ Vb VIN– gm1 gm1 gmb1r 2 gm1r gmb1
52 1 , (4)
Vb M1ar M1br 1 1 1 2 Agmb1r rBr 2 gm2 gmb1r gm2
A
VOUT– RCM RCM VOUT+ where A is the gain of the auxiliary error amplifier and
+ –
M2a M2b rBr is the output resistance of the current generator. Un-
IBR der perfect matching gm1r gmb1 5 gm1gmb1r , Acm is reduced
VSS VSS
respect to (3) by 2Agmb1rBr .
(a) (b)
C. Validation Results
Figure 3. (a) Minimum-supply differential amplifier (b) bi- Detailed validation of the two previous solutions can be
asing section.
found in [20] and [21], respectively. Here we report only
the main results. As far as the two-stage amplifier in Fig. 1
vout2 1 is concerned, we designed the solution in a 0.35-mm pro-
Adm 5 < 2 gm1RCM (2)
vin,dm 2 cess and compared its performance with the same OTA
vout2 gm1 without any bias control. The amplifiers have been de-
Acm 5 52 . (3)
vin, cm gm2 signed to drive a 10-pF load following the procedure in
[26]. Transistors dimensions are reported in Tab. 1, 0.5-pF
The absence of the tail current generator reduces the capacitors have been used for the level shifter, and Mill-
supply demand of the circuit by a saturation voltage, er compensation capacitors of 4 pF and 8 pF have been
but the quiescent current is now heavily dependent on used for the main amplifier and the replica bias feed-
temperature, supply voltage and input common-mode back loop respectively. A two-phase 100-MHz clock was
voltage variations. This means that the input transcon- used in the switched capacitor network. The quiescent
ductance gm1 and fundamental parameters of a complete current of the output branch has been nominally set to
opamp (made up with this input stage) like gain-band- 10 mA. The main parameters of the two amplifiers are
width product, slew rate, and power dissipation are ill almost the same under nominal conditions. However,
controlled. Moreover, the common-mode gain is sen- PVT variations affect the current in the output branch
sibly higher than that offered by a long-tailed pair. To of the conventional OTA [20]. As an illustrative exam-
avoid the aforementioned drawbacks we exploit again ple, Tab. 2 compares the variation of the current versus

12 IEEE CIRCUITS AND SYSTEMS MAGAZINE FOURTH QUARTER 2011

 The intrinsic voltage gain, gm/gds of a MOS transistor in deep
submicron technology is becoming unsatisfactorily low.

temperature from 210°C to 1120°C, with and without the III. Body-Driven Gain Boosting
replica control loop. The improvement produced by the The intrinsic voltage gain, gm/ gds of a MOS transistor in
body biasing is apparent as the variation of the current deep submicron technology is becoming unsatisfacto-
is decreased from 9.45 mA to only 0.69 mA. rily low [28]. Increasing the channel length (in the order
The chip photo of the minimum supply differential am- of 2–4 times Lmin ) to boost the transistor output resis-
plifier in Fig. 3 realized in a 0.35-mm technology is depict- tance cannot be easily done without losing the speed
ed in Fig. 4. Sub-blocks devoted to the main amplifier, the advantages offered by the advanced technology. A pos-
switched capacitor network and the clock phase genera- sible remedy to the gain reduction is the adoption of
tion are indicated within dashed boxes. The total die area multistage amplifier topologies (cascading approach)
is about 0.017 mm2. The main performance parameters [22]–[25]. By using simple low-voltage gain stages, the
and comparison with a standard long-tailed differential
pair are summarized in Table 3. Of course, adopting more
expensive technologies with threshold voltages around
0.3 V (e.g., 0.13-mm processes), the body-biased circuit
could be supplied even with 0.7 V [27].
Main
The measured total steady-state current was 51.2 mA Amplifier
(about 15% lower than the nominal target value, i.e.
60 mA). Fig. 5 shows the measured start-up time interval
of the body control voltage, obtained without applying
any input signal. The curve behavior shows indirectly
the stability of the loop, which reaches the steady state in
3 ms, that is, approximately 16 clock pulses (fCK 5 5 MHz).

Table 1.
Transistor dimensions and bias settings of the circuit in Fig. 1. Phase Generation SC Network
Parameter Value Figure 4. Die micrograph of the fabricated prototype of
VDD-VSS 1.5 V body-biased minimum supply differential stage.
M1, M2 15/0.5
M3, M4, M3r 2.7/0.5
Table 3.
M5, M5r 2/0.5 Differential pair main performance parameters.
M6, M15, M16 10/0.5
Body-Biased Long-Tailed
M17, M18 40/0.5
Pair (Fig. 3) Pair
M7 2/0.5
VDD2VSS 1.2 V 1.5 V
M8 25.5/0.5
CMR 100 mV 50 mV
M9 10/0.5
Current Diss. 61 mA† 58 mA
M10 12/0.5
Diff Gain 13 dB 13 dB
M11, M12, M13, M14 2.5/0.25
CMRR 50 dB 58 dB
Input Noise 10 nV/!Hz 9.2 nV/!Hz
Table 2. HD2 248.0 dB 250.1 dB
Bias current of M5-M6 for circuit in Fig. 1 vs. temperature. fin 5 5 kHz
Vin 5 50-mVpp
Temperature With Body Bias Without Body Bias
HD3 247.7 dB 249.7 dB
210° C 10.44 mA 7.39 mA fin 5 5 kHz
27° C 10.29 mA 10.18 mA Vin 5 50-mVpp
120° C 9.75 mA 16.84 mA †Steady-state current dissipation including the switched-capacitor network.

FOURTH QUARTER 2011 IEEE CIRCUITS AND SYSTEMS MAGAZINE 13

 minimum supply requirement is preserved and voltage
gain is increased. Unfortunately, an amplifier with more
Tek Stopped Single Sequence 1 Acqs 01 Aug 06 00:29 59 than two gain stages requires some kind of (nested)
Miller frequency compensation technique that limits the
maximum achievable bandwidth. An efficient technique
to increase the voltage gain without severely impairing
bandwidth is cascoding. However, the simple cascoding
scheme cannot be tolerated in a low-voltage context, so
that some low-voltage cascading variants have been de-
vised. In addition, to increase the gain of a single stage
amplifier even further (up to three or four equivalent
simple gain stages) gain boosting can also be employed
which, avoiding Miller compensation, does not incur in
the frequency limitations of the multistage cascading
approach.
Ch1 100 mv BW M 10.0 μs 1.25 Gs/s 800 ps/pt
Ch3 500 mV BW A Ch3 –10.0 mV

A. Description of the Technique

Figure 5. The upper trace shows the measured start-up The well-known standard gain boosted amplifier is de-
transient of the body-control voltage, Vb . The initial value picted in Fig. 6(a), where M1 is the common-source ampli-
is 1.142 V. The lower trace shows the clock signal.
fier, M2 is the cascode transistor and M3 is the auxiliary

VDD
VDD
VDD
Im Ia
Im Ia
Im Ia
M2
M2 VBIAS
M4
M2
VNrepl VNrepl
M3
VIN
M3 M3
M1 VIN VIN
VSS M1 M1
VSS VSS
(a) (b) (c)
VDD
VCMFB VCMFB
M4 M4 VBP M10

A M3 M3 A M9 M9
M7 M7 VI1 VI2
VDD VDD VO2 VO1
M8 M8
M6 M6 A M2 M2 A VSS VSS
VI1 VI2

M5 VBN M1 M1 VBN
VBN
VSS

(d)

Figure 6. Gain boosted amplifiers: (a) conventional, (b) body driven and (c) body driven with additional cascoding, (d) fully
differential body-driven gain boosting amplifier.

14 IEEE CIRCUITS AND SYSTEMS MAGAZINE FOURTH QUARTER 2011

 To achieve very low voltage operation a gain boosted approach that exploits
the body of the auxiliary gainboosting transistor as input terminal
was proposed independently in [29] and [30].
gain-boosting stage. Current generators Im and Ia are used
for biasing purposes. In particular, Im must be implement-
ed through a cascode approach to avoid decreasing gain.
To keep all the transistors in saturation, assuming Ia
implemented by a single transistor, the minimum sup-
ply requirement of the circuit is 2VT 1 3VDS sat . Of course,
some headroom must be left to preserve signal swing,
hence, supply lower than 1 V can be hardly adopted
even assuming thresholds as low as 0.3 V. Straightfor-
ward small-signal analysis shows that the auxiliary loop
gain provided by M3 is gm3 ro3, where gm3 is the transcon-
ductance of transistor M3 and ro3 is the total resistance
at the drain of M3. Therefore, the voltage gain vout/vin is
equal to 2gm1 gm2 gm3 rd1 rd2 ro3.
To achieve very low voltage operation a gain boosted
approach that exploits the body of the auxiliary gain-
boosting transistor as input terminal was proposed in-
dependently in [29] and [30]. The simplified schematic
of a body-driven gain boosted stage is illustrated in
Fig. 6(b). It is similar to the one in Fig. 6(a), the main dif-
ference is that now transistor M3 is driven by the body
terminal, whereas its gate voltage is kept to a constant
value, VNrepl . It is worth noting that the bias voltage VNrepl
plays a key role for the practical implementation, as will
be discussed shortly.
The minimum supply voltage keeping all transis-
tors in saturation is VT 13VDS, sat , thus saving a thresh-
old compared to the conventional gain-boosting
approach in Fig. 6(a). In this case the small signal gain
is 2gm1 gm2 gmb3 rd1rd2 ro3, where gmb3 is the source-bulk
transconductance of M3, which is typically smaller than
the gate-source transconductance by about one order
of magnitude. Additionally, also transistor M4 can be
cascoded, as illustrated in Fig. 6(c). This increases the
supply demand by one saturation voltage, because also
current generator Ia must be implemented by means of a
cascode structure, but the loop gain is increased by an
additional gain stage. In this case the small signal gain is
2gm1 gm2 gmb3 gm4 rd1rd2 rd3 ro4.
If we assume the standard expression for the threshold
voltage (1) and once Ia, VSB3 and (W/L)3 are chosen, the
required VNrepl is expressed as a first approximation by
Ia
VNrepl 5 1 VT 0 1 g 1 "2FF 2 yBS 2 "2FF 2 , (5)
Å Kn 1 WL 2 3
where, as usual, Kn is the MOS transconductance factor.
FOURTH QUARTER 2011
This voltage must be chosen properly, so as to avoid
that the bulk-source junction of M3 becomes forward bi-
ased (at this purpose, VBS lower than 0.4 V can be con-
sidered as a safe bound to limit the junction current).
Moreover, it must be avoided that transistor M1 enters
the triode region. In conclusion, a bulk-source voltage of
about 100 mV can be sufficient to keep M1 in saturation,
while causing a negligible current flowing in the bulk-
source junction.
Note the mirror action of M8 to M3r and that both tran-
sistors have the same body voltage. The circuit keeps
the body of M3r to VGND2 VGS,2r , which is slightly higher
than the saturation voltage of M1r , in order to have a
margin before entering the triode region. In principle,
the gate of M6 can be set to a different voltage to set in
turn a different bias point for the body of M3r.
It should be finally observed that the supply require-
ments of the chosen bias circuit is 2VT 14VDS,sat, (caused
by transistors M1r, M2r, M6 and M7) which is more than
that required by the basic body-driven gain boosting
circuit. However, this does not constitute a real prob-
lem in the design of a complete OTA because a com-
plementary input stage OTA topology is mandatory to
obtain rail-to-rail operation under very low supply. Oth-
erwise, non-complementary solutions would provide
strongly limited (if not useless at all) common-mode
input ranges.
B. Validation Results
A fully differential folded-cascode transconductance am-
plifier exploiting the body-driven gain boosting was de-
scribed in [31] and compared to a similar design without
and with conventional gain boosting. Figure 6(d) shows
the schematic of the fully differential folded-cascode am-
plifier in which the amplifiers A are based on the circuits
in figure 6(c). The same total current consumption (650
mA), output linear range (6VT ) and load capacitance
(350 fF) was assumed. Part of this current (150 mA) is
used by the body-driven gain-boosted amplifier in its
bias section. Observe also that while the cascoded to-
pology required the same 0.9-V supply, the conventional
gain-boosted amplifier required a 1.2-V supply. The ratio
between bandwidth and power consumption is the same
in the gate-driven and in the body-driven gain boosting
stages. It may be even better in the body-driven gain
boosting if the two complementary biasing loops (for
the replica bias generation) are shared by more than one
IEEE CIRCUITS AND SYSTEMS MAGAZINE 15
 The aim of the proposed approach is to improve the performance
of the high swing cascode current mirror in terms of output
resistance and input swing.

amplifier. Table 4 compares the performance of the three tures that employ level shifting or body-driven tech-
amplifiers. niques were also proposed [34]–[35].
The compatibility with standard CMOS processes
IV. Body Enhanced Cascode Current Mirror makes the latter approach more attractive for VLSI de-
The high-swing cascode (HSC) current mirror (CM) is sign and recently it was improved in terms of transfer
widely adopted in modern microelectronics due to its accuracy, lower input resistance and higher output re-
high performance [32]. Its circuit topology is depicted in sistance [36]. We will refer to this CM as the regulated
Fig. 8(a) where amplifier A and its connections must be body-driven (RBD) illustrated in Fig. 9.
disregarded. To improve linearity and increase output
resistance, dynamic biasing of the gates of the common A. Description of the Technique
gate transistors was suggested in [33]. To further reduce The aim of the proposed approach is to improve the
the input voltage requirements, triode-based CM struc- performance of the HSC in terms of output resistance
and input swing. These are key aspects in deep sub-
micron MOS transistors which exhibit reduced output
Table 4. resistance in the order of few kV and are subject to lim-
Performance comparison of a CMOS folded cascode amplifier ited signal excursion.
using standard cascoding approach, standard gain boosting
Fig. 8(a) depicts the schematic diagram of the body
and body-driven gain boosting.
enhanced high swing cascode (BE-HSC) CM [37]. The
Standard Standard B-D Gain solution maintains the basic topology of the HSC CM
Parameter Unit Cascoded Gain Boosting Boosting with the introduction of an additional fully-differential
Supply V 0.9 1.2 0.9 amplifier that senses the drain voltages of M1-M2 and
Gain dB 38 63 56 drives the body terminals of M3 -M4. The input voltage
fU MHz 820 790 570 requirements are the same as for the HSC. The output
Phase margin Deg 66 72 65 resistance is:
Gain margin dB 23 15 31 gm4 # 1 2Ax 1 x 1 1 2
Slew Rate V/ms 900 750 700 RO2BEHSC > (6)
g d2 gd4
Settling time ns 1.6 2.1 2.3
where A 5 1 gm5 / 1 gd6 1 gd8 22 is the gain of the auxiliary
CMRR@dc dB 64 94 81
ampifier and x 5 gmb4 / gm4 is the ratio of the body-source
PSRR@dc dB 63 101 82
transconductance to the gate-source transconuctance.
Input Noise nV/!Hz 10 12 32
In this solution the transisors operate in saturation and

VDD VDD
VDD
M7 M8
VCMFB
Ia 2Ia M1 M2
O1 O2
+
M7 A
M2r M6 –
VBIAS M5 M6
M4r +
VNrepl
Im M3 M4
M8 VG VBN
M9
M5 M1r M3r IIN IOUT VSS
VSS
(a) (b)

Figure 7. Circuit for the generation of the required bias Figure 8. (a) Proposed body-enhanced high-swing cas-
voltage VNrepl for auxiliary gain boosting amplifier in Fig. code (BE-HSC) current mirror; (b) implementation of fully
6(b) and 6(c). differential amplifier.

16 IEEE CIRCUITS AND SYSTEMS MAGAZINE FOURTH QUARTER 2011

it can be shown that a considerable improvement in the
output resistance, compared to the HSC and RBD is ob-
tained. The detailed analysis of the circuit can be found
in [37]. In the following, the BE-HSC will be compared
with the HSC and the RBD CMs.
B. Validation Results
The HSC, RBD and BE-HSC current mirrors were de-
signed using the STM HCMOS9 0.13-mm technology with
a 1.2-V supply. Transistors dimensions are reported in
Table 5. In the proposed solution the input and output
common mode voltages of amplifier A in Fig. 8(b) are
both set to VDD -VDS,SAT; in this way the body and the
source of M3 and M4 are at the same voltage and the
swing at the body is maximized. The magnitudes of the
output impedance is shown in Fig. 10.
At DC, the values of the input impedance are 4.87 kV,
1.03 kV and 4.83 kV, for the HSC, RBD and BEHSC cur-
rent mirrors, respectively.
The DC magnitudes of the output impedances for
the HSC, RBD and BEHSC current mirrors are 4.3 MV,
7.2 MV and 43 MV, respectively. The proposed circuit
exhibits an improvement factor of 10 and of about 6 with
respect to the HSC and RBD, respectively.
The DC current transfer characteristic is shown in
Fig. 11. It is seen that the proposed circuit exhibits a larg-
er input dynamic range, preserving the linear behavior.
The transfer error evaluated as (1- Iout/Iin) using low fre-
quency AC simulations is 4.9 3 1022, 4.8 3 1023 and 4.9 3
1024 for the HSC, RBD and BEHSC current mirrors, respec-
tively. The Bode diagram of the current transfer gain and
the time response to an input step of 100 mA of the three cir-
cuits are reported in [37]. The 23-dB bandwidth is 114 MHz,
512 MHz, and 504 MHz for the HSC, RBD and BEHSC CMs,
respectively. The 1% settling time is about 3.35 ns both for
the HSC and the BE-HSCCMs, whereas it is about 7.95 ns for
the RBD CM. The input-referred noise is shown in Fig. 12.
The white noise at 10 MHZ is 3.12 pA/"Hz, 3.17
pA/"Hz, and 14pA/"Hz, for the HSC, RBD and BEHSC
current mirrors, respectively. The noise performance of
the proposed solution is actually the same of the HSC
and is much better than the RBD CM.

50.0
VDD
40.0 BEHSC
M1 M2
30.0
Z0 (MΩ)

VSS VSS
20.0
M4 M5
10.0 RBD

M3 0 HSSC
VB
–10.0
IIN M6 M7 103 104 105 106 107 108 109
IOUT
VSS Frequency (Hz)

Figure 10. Magnitude of the simulated output impedances

Figure 9. Regulated body-driven (RBD) current mirror. of the three considered current mirrors.

Table 5. 300.0
Transistors dimension.
250.0 BEHSC
HSC (W/L) RDB (W/L) BEHSC (W/L) 200.0
M1 (20/0.2) M1 (3/0.2) M1 (20/0.2) RBD
150.0
I (μA)

HSSC
M2 (20/0.2) M2 (3/0.2) M2 (20/0.2)
100.0
M3 (20/0.2) M3 (20/0.2) M3 (20/0.2)
50.0
M4 (20/0.2) M4 (12/0.6) M4 (20/0.2)
0
M5 (12/0.6) M5 (1/0.2)
–50.0
M6 (3/2) M6 (1/0.2) 0 50.0 100.0 150.0 200.0 250.0 300.0
M7 (3/2) M7 (12/0.6) Lin (E-6)
M8 (12/0.6) Figure 11. DC current transfer characteristic of the three
M9 (12/0.6) considered current mirrors.

FOURTH QUARTER 2011 IEEE CIRCUITS AND SYSTEMS MAGAZINE 17


250.0
200.0 RBD
150.0
In (pA)
100.0
B SC
BEH C
BEHSC
50.0
0 HSC
–50.0
103 104 105 106 107 108 109
Frequency (Hz)
Figure 12. Output noise of the three considered current
mirrors.
V. Dual Loop Body Technique
The bulk can be exploited also as an additional control
terminal to apply local negative feedback. For instance,
this technique can be utilized for the design of a tran-
simpedance amplifier (TIA) whose advanced behavior
is its low input impedance. With the increasing perfor-
mance of CMOS technologies, which have become com-
parable to GaAs counterparts in terms of speed [38],
TIAs based on standard digital CMOS processes allow to
strongly reduce system costs and CMOS optical receiver
front ends have been recently proposed [39]–[42]. TIAs
must provide high bandwidth, high transimpedance
gain and low input noise under low-voltage and low-
power dissipation constraints imposed by the CMOS
technology and by system requirements. Therefore, a
challenging trade-off among the different specifications
has to be achieved [43]. In this scenario, the parasitic
capacitance due to the photodiode at the input of the
transimpedance amplifier has been found to strongly af-
fect the overall receiver performance [44]. Typical val-
ues for this parasitic capacitance in gigabit applications
are between 0.5 and 1 pF [40] and can be even larger in
lower bit rate applications, especially if low cost photo-
diodes are used. With these parasitic capacitance val-
ues and using a conventional transimpedance topology,
very low input impedance is needed in order to achieve
the required bandwidth.
To overcome this limitation, suitable CMOS tran-
simpedance amplifier topologies (common-gate input
stage, common-drain input stage, multiple common-
source stages and regulated cascode) have been pro-
posed [41] with the aim of decoupling the large input
capacitance of the photodiode from bandwidth deter-
mination. The common gate and common drain input
configurations allow reducing the effect of large input
parasitic capacitance on the bandwidth better than the
conventional common-source input. However, due to
the small transconductance of MOS devices they cannot
18 IEEE CIRCUITS AND SYSTEMS MAGAZINE
totally isolate the parasitic capacitance. Also, the small
transconductance deteriorates the noise performance
of the amplifiers and creates stability issues in multi-
stage common source configurations.
In the following we describe an approach to reduce
the input impedance of a conventional common source
transimpedance amplifier without changing the open
loop gain of the forward path.
A. Description of the Technique
Fig. 13(a) shows the conventional (CMOS) transimped-
ance amplifier topology. Let us denote as 2AV the
open-loop (voltage) gain between Vin and Vout (that is
approximately equal to 2gm1 R1, where gm1 is the trans-
conductance of M1). Neglecting the high-frequency limi-
tations introduced by AV and the output resistance at
the source of M2, the closed-loop transimpedance gain,
TZ is given by:
RF AV
TZ 1 s 2 5 . (7)
RF C P 1 1 A V
11s
1 1 AV
Hence, the dc transresistance gain, input resistance and
bandwidth are approximately given by
RF AV /(1 1 AV ), RF /(1 1 AV ),
11AV
and , respectively.
2pRF CP
From (7) it is apparent that TZ and Rin are not indepen-
dent parameters. Maximizing the transimpedance gain
implies also maximizing the input impedance. Besides,
unacceptable high values of AV are usually required to
obtain satisfactory input impedance values. Indeed, the
maximum value of Av is limited by supply voltages and/
or power dissipation constraints.
A possible solution is to insert further gain stages,
however this leads to stability issues, complicating fre-
quency compensation and reducing the amplifier band-
width.
The approach we describe here is based on an aux-
iliary feedback loop that exploits the bulk as an addi-
tional control terminal as illustrated in Fig. 13(b). Let
us denoting as AD the gain of the auxiliary differential
amplifier, the new open-loop voltage gain is
ArV 5 AV 1 gmb1 R1 AD < gmb1 R1 AD 5 AV AD gmb1/gm1,
where gmb1 is the source-bulk transconductance of M1,
and where the approximation holds for AD gmb1 W gm1.
With the above definitions, the expressions of the
closed-loop transimpedance gain is the same as in (7)
provided that AV is replaced by ArV . Since the open-lop
FOURTH QUARTER 2011
gain increased of the quantity AD gmb1/ gm1, the dc transre- The proposed approach requires a 10% area increase.
sistance gain accuracy is increased as Both circuits were designed with the same design strat-
egy and using the same dimensions for the common
AV AD gmb1/ gm1
TZ 5 RF . (8a) transistors. Supply voltage was 2 V, and the differential
1 1 AV AD gmb1/ gm1
amplifier was implemented as a simple source-coupled
Besides, the input resistance and bandwidth are im- pair with active load powered from the same 2-V supply.
proved with respect to the values of the conventional The main design parameters are summarized in Table 6.
solution Experimental measurements of the input resistance
gave 690 V for the conventional TIA and 159 V for the
Rin proposed one, these values are in very good agreement
Rrin < (8b)
gmb1
AD g with those expected (670 V and 155 V, respectively).
m1
The magnitude of the transimpedance gain versus
gmb1
BWr < AD BW. (8c) frequency is plotted in Fig. 15. As expected, the dc
gm1 transresistance gain of the traditional circuit is around
70 dBV, i.e. 20 log(6/7 · 4000), and about 72 dBV for the
B. Validation Results proposed one. Bandwidth of the two circuits is 217 MHz
The proposed TIA was designed using a 0.35-mm process and 353 MHz. The increase in bandwidth is lower
along with the conventional TIA for comparison purpos-
es. The micrographs of the conventional and proposed
TIA are depicted in Fig. 14(a) and 14(b), respectively.

RF

VDD (a) (b)

Figure 14. Micrograph of the (a) conventional and (b) dual-

R1
loop transimpedance amplifiers in Fig. 12.
M2
VIN VOUT

M1 VB1
Table 6.
IIN M3 Main design parameters of the circuits in Fig. 12.
CP
Parameter Value
gm1 1.8 mA/V
gmb1 0.28 mA/V
(a) AV 6
RF AD 28
RF 4 kV
VDD

R1
80
M2 75 (b)
VIN M1 VOUT
70
(a)
VB1 65
dBΩ

IIN M3 60
CP
55
50
+ 45
VREF AD 40
– 1e6 1e7 1e8 1e9
Frequency (Hz)
(b)
Figure 15. Magnitude of the transimpedance gain versus
Figure 13. (a) Schematic diagram of the conventional TIA frequency for the circuits in Fig. 12: (a) conventional and
and (b) with body dual loop. (b) proposed circuit.

FOURTH QUARTER 2011 IEEE CIRCUITS AND SYSTEMS MAGAZINE 19

 Linearity of transconductors used in the implementation of continuous-time filters
is one of the most important features and, at this purpose, suitable
linearization techniques have been devised.

than anticipated, mainly because of a peaking around
200 MHz not predicted by our oversimplified theoretical
analysis that neglected the frequency limitations of the
auxiliary differential amplifier.
VI. Linearization Technique
Linearity of transconductors used in the implementation
of continuous-time filters is one of the most important
features and, at this purpose, suitable linearization tech-
niques have been devised [45]–[49]. The simplest and
perhaps widely adopted approach is that based on re-
sistive degeneration. The schematic of the well-known
CMOS source-degenerated differential pair is shown in
Fig. 16(a). Due to the local feedback operated by the
VDD
iD1 iD 2
vG1 M1 M2
RDEG
IB
VSS
(a)
linear resistor RDEG, we trade gain for linearity, as the
maximum differential transconductance gain, (id1 2 id2)/
1 vg12vg2 2 , is lowered from gm1,2 (the transconductance of
M1 and M2) without degeneration, to about 1/RDEG , with
degeneration. Of course, overall linearity now strongly
relies on the linear properties of the resistor.
A. Description of the Technique
Fig. 16(b) depicts the schematic diagram of the transcon-
ductor exploiting the supplementary linearization tech-
nique via the bulk terminals. In order to obtain the re-
quired control signals to be applied to the bulk terminals
of the main pair M1-M2, the input signal is also applied
to an auxiliary differential pair, M3 -M4. Both the transis-
tors dimension and bias current of this auxiliary pair
are scaled down with the same ratio m 5 1 W / L 2 1/ 1 W / L 2 3 ,
compared to the dimension and bias current of the main
differential pair. Therefore, the dc source voltages of
both M1-M2 and M3 -M4 are the same, while keeping low
area and bias current overhead.
Observe that the degeneration resistor of the auxil-
vG2
iary differential pair M3 -M4 is implemented by the series
of three resistors, being the total resistance R2 1 2R 1
equal to m RDEG, according to the scaling adopted.
If we define parameter F as F 5 R2/ 1 2 R1 1 R2 2 , using
IB the usual square law model of transistors in saturation,
we can find the optimum value of F that minimizes the
third order harmonic distortion HD3, as reported in [50]
and that are summarized below.

VDD
2 C 2 "C2 2 4B
iD1 Fopt 5 (9)
iD2 2B
vG1 vG2
M1 M2
h21 3 8 1 h1 1 1 2 fF 1 3VOV 4
RDEG B5 (10a)
VOV
IB
IB
2h1 3 4fF 1 h1 1 1 2 1 3VOV 4
C5 , (10b)
VOV
VSS VSS
M3 M4
where VOV 5 VGS2V T0 is equal for all the transistors
M1-M4 and h1 5 g 1 "2fF / 4fF 2 .
IB1 R1 R2 R1 IB1

VSS B. Validation Results

(b)
Figure 16. Linearized MOS differential pair exploiting re-
sistive source degeneration: (a) conventional and with (b)
body bias feedback.
The transconductors in Fig. 16 were designed using a
0.25-mm technology. The circuits outputs were kept at
the supply voltage (2.5 V), unless otherwise stated. The
input common mode was 1.6 V and the bias current IB
was 1 mA for both circuits.

20 IEEE CIRCUITS AND SYSTEMS MAGAZINE FOURTH QUARTER 2011

 –50.00 –50.00

–53.75 –53.75
THD (Conventional)
THD (Proposed)
dB

dB
–57.50 –57.50

–61.25 –61.25

–65.00 –65.00
(a)
–50.00 –50.00

–58.75 HD3 (Conventional) –58.75

HD3 (Proposed)
dB

–67.50 –67.50

dB
–76.25 –76.25

–85.00 –85.00
0.0 1.0k 2.0k R2 3.0k 4.0k 5.0k
0.0 0.1 0.2 0.3 0.4 0.5
F
(b)

Figure 17. THD and HD3 of proposed and conventional solution as a function of R2 (R1 = 3250V). Vinpp = 1V, f = 100 MHz.

The aspect ratio of M1-M2 was 10/0.25, while current

Table 7.
sources were implemented through simple current mir- Corner analysis.
rors with 10/0.25 transistors. The degeneration resistor
of the standard solution, RDEG, was set to 1.3 kV. Best Worst
Note that the bulk and source of transistors in the Typ (60°C) (210°C) (120°C)
traditional solution were tied together, because this pro- HD3 (dB) Conventional 252 253 254
vides better linearity than connecting the bulks to VSS. Proposed 278 272 269
The degeneration resistance of the proposed trans- THD (dB) Conventional 250 251 252
Proposed 262 261 264
conductor was adjusted to 1 kV in order to achieve
roughly the same effective transconductance.
The auxiliary differential pair was ten times smaller
than the main pair (in device dimensions and bias cur- VII. Conclusion
rent) so that we have m 5 10. After using (9) as well as It is well known that the analog performance of na-
parametric analysis, the optimum value of F, for a peak noscale devices is and will be further impaired by the
differential input of 1 V, was found to be 0.35. According- ultra low supply voltages adopted and by the reduced
ly, using the additional constraint that 2R1 1 R2 > m RDEG gm/ gds maximum achievable values. In this paper we re-
(actually, we set 2R1 1 R2 5 10 kV), we obtained R2 5 viewed several techniques developed by the authors
3500 V and R1 5 3250 V. Fig. 17 depicts the THD and that can be profitably exploited to enhance the gain/
HD3 in the conditions specified above and at 100 MHz, accuracy, linearity and/or reduce the minimum sup-
as a function of F (or alternatively R2). It is evident the ply demand of analog building blocks designed in deep
peaking minimum of HD3. Moreover, it is seen that the submicron CMOS processes. Specifically, we described
proposed circuit can provide an HD3 reduction of more the following new circuits: 1) class AB output stage for
than 20 dB and a THD reduction of about 10 dB with transconductance amplifiers with well defined quies-
respect to the traditional one. cent current control; 2) minimum supply differential
The effect of process and temperature variations on stage; 3) amplifier with body-driven gain-boosting; 4)
the circuit performance were also simulated. Table 7 body-enhanced cascode current mirror; 5) dual-loop
shows the HD3 and THD of the two solutions in typical, transimpedance amplifier.
worst (slow MOS devices) and best (fast MOS devices) The proposed approaches are based on the exploi-
process conditions (for a 0.5-Vpp 100-MHz differential tation of the bulk of MOS transistors as an additional
input). A very small sensitivity of the parameters con- control terminal to be embedded in a local negative
sidered is apparent. feedback loop. At this purpose, either continuous-time

FOURTH QUARTER 2011 IEEE CIRCUITS AND SYSTEMS MAGAZINE 21

 or switched-capacitor feedback networks were adopted.
The former are preferred when linearity performance is
to be maximized, while the latter are the most suitable
for minimum supply voltage applications.
Of course, a the use of these techniques requires that
the bulk-to-source voltage must be limited to about 0.4 V,
so as to avoid that the bulk-source junction becomes ap-
preciably forward biased and conducts a significant cur-
rent. Moreover, to apply the techniques to both n- and
p-channel transistors a triple-well technology is needed.
The solutions were studied analytically and validat-
ed through either experimental measurements or com-
puter simulations. The obtained results were found in
good agreement with the expected ones.
Pietro Monsurrò was born in 1979, got
the Laurea Specialistica degree with
honors in Electronic Engineering from
the University of Roma “La Sapienza” in
2004, and the Ph.D. degree in 2008 from
the same university. His main research
interests are the design of pipeline ADCs
with low power consumption and high accuracy, in par-
ticular low-voltage circuits, behavioral modeling of
mixed-signal blocks, fast background calibration algo-
rithms, and statistical modeling for high yield design.
Salvatore Pennisi (M’01-SM’04) re-
ceived the laurea degree in electronic
engineering in 1992 and the Ph.D. de-
gree in electrical engineering in 1997,
both from the University of Catania. In
1996, he joined the Department of Elec-
trical Electronic and System Engineer-
ing (DIEES), University of Catania, as a Researcher (As-
sistant Professor) and in 2002 he was appointed an
Associate Professor. Since then, he has been engaged in
scientific projects in collaboration with national and in-
ternational academic and industrial partners. His main
research interests include circuit theory and analog de-
sign with emphasis on low-voltage and current-mode
techniques. In this field, he has developed several build-
ing blocks and unconventional architectures of opera-
tional amplifiers. More recently, his research activities
have involved multi-stage amplifiers with related fre-
quency compensation, data converters and the analysis
of high-frequency distortion in analog circuits such as
feedback amplifiers, oscillators and filters. He published
over 70 papers in international journals and more than
120 contributions in conference proceedings, he is the
co-author of the books CMOS Current Amplifiers (1999),
Feedback Amplifiers: Theory and Design (2001), both ed-
ited by Kluwer Academic Publishers, and Liquid Crystal
22 IEEE CIRCUITS AND SYSTEMS MAGAZINE
Display Drivers-Techniques and Circuits (Springer 2009)
and has written an entry in the Wiley Encyclopedia of
Electrical and Electronics Engineering.
Dr. Pennisi has served as an Associate Editor of the
IEEE Transactions on Circuits and Systems-Part II: Express
Briefs and is member of the IEEE CASS Analog Signal
Processing Technical Committee.
Giuseppe Scotti was born in Cagliari in
1975. He received his Master’s degree
and Ph.D. degree in electronic engineer-
ing from the University of Rome “La Sa-
pienza”, in 1999 and 2003 respectively.
He is currently a Researcher (Assistant
Professor) at the Department of Infor-
mation, Electronic and Communication Engineering of
the University of Rome “La Sapienza”.
His main research interests include analog design
with emphasis on low-voltage techniques, the design
methodologies of high-yield analog and digital inte-
grated circuits and the design of integrated active filters
and data converters. He published over 30 papers in in-
ternational journals and more than 50 contributions in
conference proceedings.
Alessandro Trifiletti was born in Rome,
Italy, in 1959. He received the Laurea de-
gree in electronic engineering from the
Università di Roma “La Sapienza.” In
1991, he joined the Dipartimento di In-
gegneria Elettronica, Università di Roma
“La Sapienza,” as a Research Assistant
where he is currently an Associate Professor. His re-
search interests include high speed circuit design tech-
niques and III-V device modeling.
References
[1] A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani,
S. Borkar, and V. De, “Effectiveness of reverse body bias for leakage
control in scaled dual VT CMOS ICS,” in Proc. Int. Symp. Low Power Elec-
tronics and Design, Aug. 2001, pp. 207–212.
[2] C. Neau and K. Roy, “Optimal body bias selection for leakage im-
provement and process compensation over different technology gen-
erations,” in Proc. ISLEP, Aug. 2003, pp. 116–121.
[3] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage
current mechanisms and leakage reduction techniques in deep submi-
crometer CMOS circuits,” Proc. IEEE, vol. 91, no. 2, pp. 305–327, Feb.
2003.
[4] M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto, and Y.
Hagihara, “Delay and power monitoring schemes for minimizing power
consumption by means of supply and threshold voltage control in ac-
tive and standby modes,” IEEE J. Solid-State Circuits., vol. 41, no. 4, pp.
805–814, Apr. 2006.
[5] K. K. Kim and Y.-B. Kim, “A novel adaptive design methodology for
minimum leakage power considering PVT variations on nanoscale VLSI
systems,” IEEE Trans. VLSI Syst., vol. 17, no. 4, pp. 517–528, Apr. 2009.
[6] H. J. Jeon, Y.-B. Kim, and M. Choi, “Standby leakage power reduc-
tion technique for nanoscale CMOS VLSI systems,” IEEE Trans. Instrum.
Meas., vol. 59, no. 5, pp. 1127–1133, May 2010.
FOURTH QUARTER 2011
[7] S. Narendra, D. Antoniadis, and V. De, “Impact of using adaptive
body bias to compensate die-to-die Vt variation on within-die Vt varia-
tion,” in Proc. Int. Symp. Low Power Electronics and Design, Aug. 1999,
pp. 229–232.
[8] J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis, A.
P. Chandrakasan, and V. De, “Adaptive body bias for reducing impacts
of die-to-die and within-die parameter variations on microprocessor
frequency and leakage,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp.
1396–1402, Nov. 2002.
[9] S. Narendra, M. Haycock, V. Govindarajulu, V. Erraguntla, H. Wilson,
S. Vangal, A. Pangal, E. Seligman, R. Nair, A. Keshavarzi, B. Bloechel, G.
Dermer, R. Mooney, N. Borkar, S. Borkar, and V. De, “1.1 V 1 GHz com-
munications router with on-chip body bias in 150 nm CMOS,” in Proc.
IEEE Int. Solid-State Circuits Conf., Aug. 2002, pp. 270–274.
[10] S. M. Martin, K. Flautner, T. Mudge, and D. Blaauw, “Combined dy-
namic voltage scaling and adaptive body biasing for lower power mi-
croprocessors under dynamic workloads,” in Proc. IEEE/ACM Int. Conf.
Computer Aided Design, Nov. 2002, pp. 721–725.
[11] A. Keshavarzi, S. Narendra, B. Bloechel, S. Borkar, and V. De, “For-
ward body bias for microprocessors in 130 nm technology generation
and beyond,” in Proc. Symp. VLSI Circuits Dig. Tech. Papers, pp. 312–315,
June 2002.
[12] M. Olivieri, G. Scotti, and A. Trifiletti, “A novel yield optimization
technique for digital CMOS circuits design by means of process param-
eters run-time estimation and body bias active control,” IEEE Trans.
VLSI Syst., vol. 13, no. 5, pp. 630–638, May 2005.
[13] T. Lehmann and M. Cassia, “1-V power supply CMOS cascode am-
plifier,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1082–1086, July
2001.
[14] T. Lehmann and M. Cassia, “1-V OTA using current driven bulk cir-
cuits,” J. Circuits, Syst. Comput., vol. 11, no. 1, pp. 81–91, 2002.
[15] A. Guzinski, M. Bialko, and J. C. Matheau, “Body-driven differential
amplifier for application in continuous-time active-C filter,” in Proc. Eu-
ropean Conf. Circuit Theory and Design, June 1987, pp. 315–319.
[16] B. J. Blalock, P. E. Allen, and G. A. Rincon-Mora, “Design 1-V op
amps using standard digital CMOS technology,” IEEE Trans. Circuits
Syst. II, vol. 45, no. 7, pp. 769–780, July 1998.
[17] B. J. Blalock, H. W. Li, P. E. Allen, and S. A. Jackson, “Body-driving
as a low-voltage analog design technique for CMOS technology,” in
Proc. IEEE Southwest Symp. Mixed-Signal Design (SSMSD), Feb. 2000, pp.
113–118.
[18] E. G. Friedman, J. Rosenfeld, and M. Kozak, “A 0.8 volt high per-
formance OTA using bulk-driven MOSFETs for low power mixed-signal
SOCs,” in Proc. IEEE Int. SOC Conf., Sept. 2003, pp. 245–246.
[19]T. Stockstad and H. Yoshizawa, “A 0.9-V 0.5-µA rail-to-rail CMOS
operational amplifier,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 286–
292, Mar. 2002.
[20]A. D. Grasso, S. Pennisi, and F. Centurelli, “CMOS miller OTA with
body-biased output stage,” in Proc. ECCTD 2007, Sevilla, Spain, Aug.
2007, pp. 539–542.
[21]A. D. Grasso, P. Monsurrò, S. Pennisi, G. Scotti, and A. Trifiletti,
“Analysis and implementation of a minimum-supply body-biased CMOS
differential amplifier cell”, IEEE Trans. VLSI Syst., vol. 17, no. 2, pp. 172–
180, Feb. 2009.
[22] H. Lee and P. K. T. Mok, “Active-feedback frequency-compensation
technique for low-power multistage amplifiers,” IEEE J. Solid-State Cir-
cuits, vol. 38, no. 3, pp. 511–520, Mar. 2003.
[23] S. O. Cannizzaro, A. D. Grasso, R. Mita, G. Palumbo, and S. Pen-
nisi, “Design procedures for three-stage CMOS OTAs with nested-Miller
compensation,” IEEE Trans. Circuits Syst. I, vol. 54, no. 5, pp. 382–386,
May 2007.
[24] A. D. Grasso, G. Palumbo, and S. Pennisi, “Advances in reversed
nested Miller compensation,” IEEE Trans. Circuits Syst. I, vol. 54, no. 7,
pp. 1459–1470, July 2007.
[25]S. O. Cannizzaro, G. Palumbo, and S. Pennisi, “Distortion analysis of
Miller-compensated three-stage amplifiers,” IEEE Trans. Circuits I, vol.
53, no. 5, pp. 961–976, May 2006.
[26] G. Palmisano, G. Palumbo, and S. Pennisi, “Design procedures for
two–stage CMOS OTAs: A tutorial,” Analog Integr. Circuit Signal Process-
ing, vol. 27, no. 3, pp. 179–189, May 2001.
[27]P. Monsurrò, G. Scotti, A. Trifiletti, and S. Pennisi, “Biasing tech-
nique via bulk terminal for minimum supply CMOS amplifiers,” Electron.
Lett., vol. 41, no. 14, pp. 779–780, July 2005.
FOURTH QUARTER 2011
[28]C. J.-B. Fayomi, M. Sawan, and G. W. Roberts, “Reliable circuit
techniques for low-voltage analog design in deep submicron standard
CMOS: A tutorial,” Analog Integr. Circuit Signal Processing, vol. 39, no. 1,
pp. 21–38, Apr. 2004.
[29] S. A. Zabihian and R. Lotfi, “Ultra-low-voltage, low-power, high-
speed operational amplifiers using body-driven gain-boosting tech-
nique,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS’07), May
2007, pp. 705–708.
[30] P. Monsurrò, G. Scotti, A. Trifi letti, and S. Pennisi, “Sub-1V CMOS
OTA with body-driven gain boosting,” in Proc. European Conf. Cir-
cuit Theory and Design (ECCTD’07), Sevilla, Spain, Aug. 2007, pp.
535–538.
[31]P. Monsurrò, S. Pennisi, G. Scotti, and A. Trifiletti, “0.9-V CMOS cas-
code amplifier with body-driven gain boosting,” Int. J. Circuit Theory
Appl., vol. 37, no. 2, pp. 193–202, Mar. 2009.
[32]E. Sackinger and W. Guggenbuhl, “A high-swing high-impedance
MOS cascode circuit,” IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 289–
298, Feb. 1990.
[33]G. Palmisano, G. Palumbo, and S. Pennisi, “Harmonic distortion on
class AB CMOS current output stages,” IEEE Trans. Circuits Syst. II, vol.
45, no. 2, pp. 243–250, Feb. 1998.
[34]V. I. Prodanov and M. M. Green, “CMOS current mirrors with re-
duced input and output voltage requirements,” Electron. Lett., vol. 32,
no. 2, pp. 104–105, 1996.
[35]B. J. Blalock, P. E. Allen, and G. A. Rincon-Mora, “Designing 1-V op
amps using standard digital CMOS technology,” IEEE Trans. Circuits
Syst. II, vol. 45, no. 7, pp. 769–780, July 1998.
[36]X. Zhang, and E. I. El-Masry, “A regulated body-driven CMOS cur-
rent mirror for low-voltage applications,” IEEE Trans. Circuits Syst. II, vol.
51, no. 10, pp. 571–577, Oct. 2004.
[37]C. Giannì, G. Scotti, S. Pennisi, and A. Trifiletti, “CMOS body en-
hanced cascode current mirror,” in Proc. IEEE Int. Symp. Circuits and
Systems, 2009, pp. 1593–1596.
[38] A. K. Petersen, K. Kiziloglu, T. Yoon, F. Williams, Jr., and M. R. San-
dor, “Front-end CMOS chipset for 10 Gb/s communication,” in IEEE RFIC
Conf. Dig. Papers, June 2002, pp. 93–96.
[39] S. M. Park and H. J. Yoo, “1.25-Gb/s regulated cascade CMOS tran-
simpedance amplifier for gigabit ethernet applications,” IEEE J. Solid-
State Circuits, vol. 39, no. 1, pp. 112–121, Jan. 2004.
[40] C. M. Tsai, “20mW 1.25 Gbit/s CMOS transimpedance amplifier with
30 dB dynamic range” Electron. Lett., vol. 41, no. 3, pp. 109–110, Feb.
2005.
[41] S. M. R. Hasan, “Design of a low-power 3.5–GHz broad-band CMOS
transimpedance amplifier for optical transceivers,” IEEE Trans. Circuits
Syst. I, vol. 52, no. 6, pp. 1061–1072, June 2005.
[42] Z. Lu, K. S. Yeo, J. Ma, M. A. Do, W. M. Lim, and X. Chen, “Broad-
band design techniques for transimpedance amplifiers,” IEEE Trans.
Circuits Syst. I, vol. 54, no. 3, pp. 590–600, Mar. 2007.
[43] C. Ciofi, F. Crupi, C. Pace, G. Scandurra, and M. Patanè, “A new
circuit topology for the realization of very low-noise wide-bandwidth
transimpedance amplifier,” IEEE Trans. Instrum. Meas., vol. 56, no. 5, pp.
1626–1631, Oct. 2007.
[44] A. Buchwald, and K. W. Martin, Integrated Fiber-Optic Receivers.
Norwell, MA: Kluwer, 1995.
[45]A. Nedungadi and T. R. Viswanathan, “Design of linear CMOS trans-
conductance elements,” IEEE Trans. Circuits Syst., vol. CAS-31, pp. 891–
894, Oct. 1984.
[46] Y. Tsividis, Z. Czarnul, and S. C. Fang, “MOS transconductors and
integrators with high linearity,” Electron. Lett., vol. 22, no. 5, pp. 245–
246, Feb. 27, 1986.
[47] F. Krummenacher and N. Johel, “A 4-MHz CMOS continuous-time
filter with on-chip automatic tuning,” IEEE J. Solid-State Circuits, vol. 23,
no. 3, pp. 750–758, June 1988.
[48] A. Lopez-Martin, J. Ramirez-Angulo, C. Durbha, and R. Carvajal,
“Highly linear programmable balanced current scaling technique in
moderate inversion,” IEEE Trans. Circuits Syst. II, vol. 53, no. 4, pp. 283–
285, Apr. 2006.
[49] A. Lewinski and J. Silva-Martinez, “A high-frequency transconduc-
tor using a robust nonlinearity cancellation,” IEEE Trans. Circuits Syst. II,
vol. 53, no. 9, pp. 896–900, Sept. 2006.
[50]P. Monsurrò, S. Pennisi, G. Scotti, and A. Trifiletti, “Linearization
technique for source-degenerated CMOS differential transconductors,”
IEEE Trans. Circuits Syst. II, vol. 54, no. 10, pp. 848–852, Oct. 2007.
IEEE CIRCUITS AND SYSTEMS MAGAZINE 23