solid state electronics.

transistor.

integrated circuits

semicon-
ductor electronic devices. diodes
transistors. discrete

i
 circuit models;

linear

pn
i Sections 9.1, 9.2.

Section 9.2.

Section 9.3.

Section 9.4.

9.1 ELECTRICAL CONDUCTION IN

SEMICONDUCTOR DEVICES

semiconductors.

semiconductor
Si Si

Si Si

Figure 9.1 covalent bonding.

free electrons
 Si + Si Si

+ = Hole Electron jumps

to fill hole

Si Si + Si

hole.
The net effect is a hole
moving to the right

A vacancy (or hole) is created

whenever a free electron leaves
the structure.
This “hole” can move around
the lattice if other electrons
mobility replace the free electron.

Figure 9.2

Electric field
+ –
+ –
– + – +

Net current
flow

recombination, An external electric field forces

holes to migrate to the left and
free electrons to the right. The
net current flow is to the left.

Figure 9.3

intrinsic
concentration ni
ni (9.1)

An additional free electron is

created when Si is “doped” with a
group V element.
doping
Si Si Si

_
Si As Si

_
donors
As Si Si

Figure 9.4
 acceptor,

n-type semiconductors.

p-type semiconductor.

n p n

n ni (9.2)

p pi (9.3)
majority carriers n
minority carriers. p

9.2 THE pn JUNCTION AND THE

SEMICONDUCTOR DIODE

p n
pn junction, pn
semiconductor diode,
pn p
n

depletion region,

n p
n

The p-side depletion region is negatively The n-side depletion region is positively
charged because its holes have recombined charged because its free electrons have
with free electrons from the n side recombined with holes from the p side
Depletion
region
_ +
p _ + n
+ + _ _
_ +
+ _ _
+
_ + _ _
+ + _ +
_ +

Figure 9.5 pn
 p
p n

n p
contact potential

offset voltage V
n
p

Electric field
p
reverse saturation current IS
p n

Drift
current Hole
current
Diffusion
current
IS Electron
IS current
diffusion current Id
p n
Depletion
n n region

Figure 9.6
pn
p
n n

pn + p _
vD VB
pn reverse-biased _ n +
forward-biased _
i D = I0

ohmic contact
(a) Reverse-biased
pn junction

iD + p +
vD VB
iD I IS (9.4) _ n _

_
i D = Id I0 Id
pn
VB (b) Forward-biased
pn junction

Figure 9.7
pn
Id I eq D kT
(9.5)
 D pn k
q T
kT q

LO1 iD Id I I eq D kT
(9.6)

diode equation. i

iD I eq D kT
(9.7)

50 Diode i-v curve

40
Diode current, mA

30

20

10

0
0 0.2 0.4 0.6 0.8 1.0
Diode voltage, V

Figure 9.8 i
The arrow in the circuit symbol for
the diode indicates the direction of
current flow when the diode is pn
forward-biased.

iD pn
+ semi-
vD
_
conductor diode diode

pn
Circuit symbol
i i

i reverse
p breakdown
Ohmic contacts
n
VZ
in the reverse direction
avalanche break-
pn junction down pn
Figure 9.9
 iD

Reverse
breakdown
region Reverse
bias
region Forward
bias LO1
_ region
VZ
I0 V vD

Complete i-v curve of a iD

semiconductor diode +
vD
_

Figure 9.10 i

impact ionization

Zener breakdown

Zener voltage VZ

voltage regulators,

D
V
D V
VZ
I
D VZ

9.3 CIRCUIT MODELS FOR THE

SEMICONDUCTOR DIODE
user designer
i

i
circuit models
large-signal models

small-signal models
 MAKE THE
CONNECTION

Hydraulic Large-Signal Diode Models

Check
Valves Ideal Diode Model

i
D
D i

ideal diode model.

iD, mA

15 Actual diode
characteristic +
+ vD
vD _
Figure 1 10 _
Approximation
LO2
(thick line) Circuit models for
5 vD 0 (short) and Symbol for
vD < 0 (open) ideal diode

0 5 10 15 v D, V

Figure 9.11
 + vD – + vD – + vD –

+ + +
1.5 V 1k 1.5 V 1k 1.5 V 1k
_ _ _
iD iD iD
MAKE THE
Figure 9.12 Figure 9.13 Figure 9.14 CONNECTION

D D
iD

D iD

D
D

D iD D (9.8)
Figure 2
D D

F O C U S O N M ET H O D O L O GY
DETERMINING THE CONDUCTION STATE OF AN IDEAL DIODE

ID

+ VD –

Figure 3
 LO2

+ vD _

R1 R3
R2 +
VS VB VS VB R R R
_

Figure 9.15

_
v1 + vD v2
R
VS
R R
5 10
+
8V 10 +
VS = _ VB =
12 V 11 V VB
_ D D

Figure 9.16

_ VS VB
v1 + vD v2
R R R
iD = i2
5 10 VS VB
R R R R R
+
VS = VB =
12 V 10 11 V
_

Figure 9.17 VB
VB
 R

LO2

R1 v1 R2
+ +
_
VS vD VB
_ + _

VS VB R R

Figure 9.18

5 v1 4
_
+ i = 1/9 A v +
D
VS VB 12 V 11 V
i _
+
_
R R

Figure 9.19

D
 10 D1
v1
vout
10 D2
v2

100

D D

rectification

+ vD _ i t

+
+ v = 155.56 sin t RL vL
_ i D
_
iD

D
Figure 9.20

D L iD

i
iD i (9.9)
RL

L iD RL (9.10)

L i

t dt (9.11)

half-wave rectifier,
 vi , V
0

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time, s
60-Hz source voltage
vL i , V

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
iD, mA
Time, s
Rectified voltage
Physical diode
Figure 9.21 10

Offset diode model

5 (thick line)

full-wave rectifier.

Offset Diode Model 0.6 2 4 vD, V

On Off

+
offset diode model 0.6 V
_

V Device Circuit models

Figure 9.22

D D

+
D 0.6 V
(9.12) _
D

Figure 9.23

LO2

R
 + i
_ 3 cos t R
S t t V
Actual circuit

+ vD _ + V _

i +
+ R vR
_ vs(t) _ D

Circuit with offset diode model

Figure 9.24 D

D S

0.6 V D
+ vD _ + _

+ S
vS +
_ R vR
_

(a) Diode off

0.6 V
+ vD _ + _ i
S
iR
R S
R
i +
vS +
_ R vR
_
S
R
(b) Diode on S S

Figure 9.25 S

3
2
1
Volts

0
_1
_2
_3
0 0.005 0.01 0.015 0.02 0.025 0.03
Time

Figure 9.26

V V
 i
t

LO2

D
D1

+ R1 +
+
v1 V R2 vo
_B _
_
VB R R V
Figure 9.27
D

R
D V VB

+ vD1 _ +0.6 V
_

+ 1k D1
+ +
v1 2V Vo
_ _
_

Figure 9.28
 D1 12 D2 6

+ 5.4 V 18 5V +
_ _

Small-Signal Diode Models

i
small-signal behavior
small-signal behavior

once it is conducting
i

small-signal resistance
RT

+
vT vD
iD _ iD RT (9.13)
T D

Figure 9.29
iD I eq D kT
(9.14)

D
transcendental equations
iD D
load-line equation
R VT RT

iD D VT (9.15)
RT RT

IQ VQ
quiescent (operating) point, Q point.
D VQ iD IQ

iD

VT
RT

Q point (IQ, VQ)

IQ

VQ V T vD

Figure 9.30

F O C U S O N M ET H O D O L O GY
DETERMINING THE OPERATING POINT OF A DIODE LO2

or
F O C U S O N M ET H O D O L O GY
USING DEVICE DATA SHEETS
device data sheet.
general-purpose rectifier

1N4001 – 1N4007
Features
• Low forward voltage drop
• High surge current
capability

DO-41
Color band denotes cathode
1.0-A General-purpose rectifiers

ABSOLUTE MAXIMUM RATINGS

surge current
power rating
derating

Absolute Maximum Ratings T

Symbol Parameter Value Units

I
TA

it

PD

R
T

TJ

Continued
Concluded

ELECTRICAL CHARACTERISTICS

Electrical Characteristics T

Device
Parameter 4001 4002 4003 4004 4005 4006 4007 Units

VR

VR TA
TA

TA

VR f

TYPICAL CHARACTERISTIC CURVES

Forward current derating curve Forward characteristics

1.6 20
10
1.4
4
Forward current, A
Forward current, A

1.2
2
1 1
0.8 Single-phase 0.4
half-wave 80-Hz 0.2
0.6 resistive or TJ = 25 C
0.1
0.4 inductive load Pulse width = 500 s
0.04 2% Duty cycle
0.2 .375" 9.0-mm lead 0.02
lengths
0 0.01
0 20 40 60 80 100 120 140 160 180 0.6 0.8 1 1.2 1.4
Ambient temperature, ºC Forward voltage, V
 LO2

R1 R3
iD
+
VS R2 D1 vD
_

R4

Figure 9.31

VS R R R R

54
Diode current, mA

42

30

18

6
0
0.2 0.6 1.0 1.4 1.8
Diode voltage, V

Figure 9.32 i

RT R R R R
R
VT VS
R R

RT = 48.33 y VT RT x VT
iD quiescent Q operating
+
point VQ IQ
VT = 2 V D1 vD
_
PB IB IB R
R
Figure 9.33 IQ
 60

54

48

42
Diode current, mA

36

30

24 Q point
21
18
Load line
12

0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Diode voltage, V

Figure 9.34 i

R R R R
D
VR IQ R R VQ
R IR VR R

PB IB

50 25

+
_ 5V 50 D1

IQ VQ
 Piecewise Linear Diode Model

piecewise linear diode model.

V

Q
Q
rD
iD
(9.16)
rD D IQ VQ

rD

iD Diode off
VS circuit model
R rD
V
1
rD Diode on
Q point circuit model

0
0 V Vs VD

Figure 9.35

LO2

I kT q T IQ
rD

iD I eq D kT
 iD qI qVQ kT
e
rD D IQ V Q kT

IQ

kT IQ
VQ e
q I

VQ rD

e rD
rD

rD

LO2

RS + vD _

+
vS +
_ RL vL
_

S t t V rD RS RL

L Figure 9.36
 0.6 V
1 0.5 + vD _ + _
+ v1 _ + v2 _
+
Ideal
vS +
_ diode 10 vL
_

Figure 9.37

S D L

D S L

S L

D S

S
L RL
S V t S
RS rD RL

10 9
8
5 vs
7
6
vL, V

0
vL, V

vL 5
_5 4
3
_10 2
0 0.005 0.01 0.015 0.02 0.025 0.03
1
t, s
0
–10–8 –6 –4 –2 0 2 4 6 8 10
vS , V
(a) (b)

Figure 9.38

transfer characteristic
L S L
 i t

V rD

VL

9.4 RECTIFIER CIRCUITS

full-wave rectifier bridge rectifier

limiter peak detector

The Full-Wave Rectifier

i1 iL
1:2N
+
+ RL vL
N + v _ NvS _
_ S +
_ NvS
S
N S
N i2

Figure 9.39
 S

N S
iL i S (9.17)
RL

N S
iL i S (9.18)
RL
iL
i
RL
i i
RL N

The Bridge Rectifier

integrated-
circuit package bridge rectifier

D D
D D

c d

10 10
i 1, A
vS, V

0 5

–10 0.005 0.01 0.015 0.02 0.025 0.03 0 0.005 0.01 0.015 0.02 0.025 0.03
t, s t, s

10 10
i 2, A
vL, V

5 5

0 0.005 0.01 0.015 0.02 0.025 0.03 0 0.005 0.01 0.015 0.02 0.025 0.03
t, s t, s

Figure 9.40 RL
 a a
D1 D2
D1 D2
+
vS (t) + c RL d vS (t) c RL d
_
_ iL
D4 D4 D3
D3
b b
Bridge rectifier During the positive half-cycle of
vS (t), D1 and D3 are forward-biased
and iL = vS (t)/RL (ideal diodes).
a c
IC
b
AC in
rectifier
DC out
d
a LO3
D1 D2
+
Corresponding IC package
vS (t) c RL d
_ iL
Figure 9.41
D4 D3

b
During the negative half-cycle of
vS (t), D2 and D4 are forward-biased
and iL = –vS (t)/RL (ideal diodes).

Figure 9.42

30 30 30

20 25 25

10 20 20
RL • iL (t), V

RL • iL (t), V
vs (t), V

0 15 15
–10 10 10

–20 5 5

–30 0 0
0 0.01 0.02 0.03 0 0.01 0.02 0.03 0 0.01 0.02 0.03
t, s t, s t, s

(a) (b) (c)

Figure 9.43
 ripple

(9.19)

170
+
+
vAC(t) +
_ Bridge vR(t) 470 F vL
rectifier
_
_
Antiripple filter
Volts

Load voltage vL

Unfiltered
rectifier
output v(t)

0 8.33 16.67 25 t, ms

Figure 9.44

LO3
 S R

i
RL RL

T T T
i i t dt t dt dt
T T RL T

RL RL

LO3

L iL

L
RL
iL
 T T
RL RL
L RL iL i t dt t dt
T T RL

9.5 DC POWER SUPPLIES, ZENER DIODES,

AND VOLTAGE REGULATION

DC power supply.

110 V AC + +
Line + Bridge
vAC(t) vR (t) Regulator Load
voltage _ rectifier
_ _

Filter
Step-down
transformer

Figure 9.45
 regulated

V reverse Zener voltage

VZ i

VZ

rD

+
V
_
D V

Figure 9.46
VZ D V
LO4
D VZ
VZ

rZ
_
VZ
VS +
VZ
S VZ Figure 9.47

VZ

rZ RS RL

VZ
 "Forward" "Reverse"
branch branch

rD rZ

+ _
LO4 V VZ
_ +
The Zener diode may be
modeled as consisting of two
Complete model Circuit parallel branches, representing
for Zener diode symbol forward and reverse operation.

Figure 9.48

Series current
Unregulated Voltage
limiting resistor
source regulator Load
RS RS

iZ + iL iZ + iL
iS iS
vS + VZ RL vS + VZ RL
_ _
_ _

(a) (b)

Figure 9.49

VZ

VZ
iL (9.20)
RL

VZ iS
iZ
iL iS iZ (9.21)

VZ

S VZ
iS (9.22)
RS
 PZ
PZ iZVZ (9.23)
iZ

RL RL RL (9.24)
RL RL

LO4

S VZ RS RL

rZ

S VZ
iS
RS
VZ
iL
RL

iZ iS iL

PZ iZVZ

worst-case
 S VZ
iZ iS
RS

PZ iZ VZ
PZ

LO4

10 20
+

VS RL vL

Figure 9.50 VS VZ PZ
RL

rZ

Determining the minimum acceptable load resistance

VZ VZ
RL
iS VS VZ
 Determining the maximum acceptable load resistance

PZ
iZ
VZ

VS VZ
iS

VZ
RL
iS iZ
RL
cannot

PZ

LO4

RS VS(t) 100 mV
+
VS + vripple +
_ VZ RL 14 V
–

t
Figure 9.51
Figure 9.52
 S VZ rZ RS
RL

RS

rZ
VS RL DC equivalent circuit
VZ
VZ

rZ RL RS RL
VL VS VZ
DC equivalent circuit rZ RL RS rZ RL RS

RS AC equivalent circuit

+ V
_~ ripple rZ RL rZ RL
L
rZ RL RS

AC equivalent circuit
Figure 9.53

RS RL

rZ

Conclusion

Understand the basic principles underlying the physics of semiconductor devices in

general and of the pn junction in particular. Become familiar with the diode equation
and i- characteristic.
 i

Use various circuit models of the semiconductor diode in simple circuits. These are
divided into two classes: the large-signal models, useful to study rectifier circuits, and
the small-signal models, useful in signal processing applications.

pn

Study practical full-wave rectifier circuits and learn to analyze and determine the
practical specifications of a rectifier by using large-signal diode models.

Understand the basic operation of Zener diodes as voltage references, and use simple
circuit models to analyze elementary voltage regulators.

Section 9.2:
no po
T

nio pio nio pio

po Nd no Na n p

no
po
Na
Nd NA Na Nd
 5 vD 10
n p
VC = 5 V
Vi = 12 V VB = 10 V
5

Figure P9.9
Na Na Nd Nd
VB
VC
n p VC VB
iD t

rD
V

v s ( t ) (V)

100
10

pn
v S (t ) iD ( t )

0 10 20 30 t (mS)

Figure P9.13

V
D

1k
5 vD 10
+ +
D1
Vi = 12 V VB = 10 V

Vin 500 Vo
Figure P9.7

+
Vi VB 2V

Figure P9.14
 RS D
+

vS +
_
R1 RL vL

Figure P9.16
iD

D
iD
S
D D
R RS RL iD D

D T
D T
i V
R
VD
R
E

E=5V I

Figure P9.19
T

10 k

+ +
15 V vD
iD
V = 0.7 V

+ 220
50 Vrms _
Figure P9.15

Figure P9.20

L
D
S L
S
 +5 V +10 V

R R
+5 V S t
t

(a) (b)

10
_ 10 V _ 12 V +
R
R
(c) +5 V (d) + v (t)
~
_ S 10 vo (t)
_5V
4V
R
_

(e) _ 10 V
Figure P9.24
Figure P9.21

V
D
1k
V
+ S t t
D1
D2
Vin 500
+
_ _ 1.5 V rD

Figure P9.22
VT
iD Io e D

T
kT
Io VT
q
+5 V S t
R
R
D1 Q
+5 V
_5 V D2
vout
D3
+5 V
D4
_5 V
(a)

+15 V _ 10 V

R R
R
D1 _5 V D1
+5 V vout vout
D2 D2
0V +5 V +
D3 + V VD
_10 V _ S
–
iD
(b) (c)

Figure P9.23 Figure P9.27

 VS

VT
iD Io e D

T R
kT +
Io VT VD
q + –
_ VS1
S t +
_ VS2
R

Figure P9.32
Q

100 nF
+ +
i
vin vout

_ _

Figure P9.33

t A t

VT
iD Io e D

T A
kT
Io VT
q
S VS s t

R v(t) +
~
_ R

Q
Q
Figure P9.34
IDQ VDQ rd

R VS
 T
T

IL VL V
V t

n
n C
C RL
VL(t)
V t
VM
VL min

t
t2 2

D1 iL
Figure P9.40
+
Vs1
–
+
Vline C RL VL IL VL
–
+ Vr
Vs2 V t
–

D2 n
Figure P9.38 C

IL VL
n Vr
C RL V t
V t
n
C

P T
V
 V t
S t
n Vr
L t
S t IL VL

RL RL

L t

IL VL

D1 D2 Vr
+
V t
vS(t) _

_
RL vL(t)
D3 D4
+
Source Rectifier Load
IL VL
Figure P9.43
Vr
V t

n
C
V t
n
C RL
IL VL
Vr
V t

n
C
D4 D1
+ + iL
Vline Vs
– – +
C RL VL
D3 D2 –

Figure P9.44
 i

100

+ S VS Vr

2V v
VS Vr
i _
R IL VL
Vz rz P
Figure P9.49
iz
RL

iL
1,800 R
+ +
+
+ V RL VL
_ S
_ _
18 V RL Vout
VZ = 5.6 V
_

Figure P9.53
Figure P9.50

Vz rz P

izk rzk

Vz rz
iz iz
iD
VS IL
–5 V –2.5 V
VD
R
–20 mA

–40 mA
Vz rz
–60 mA
iz iz
–80 mA VS
Figure P9.52 IL
 R i
VZ
V
VS

Vz rz iz
P iz
VS R

iD

VZ vD
vD
0
Vz rz
iz iz
PR
(a)
VS R
100

I1
50

VS ~ D1 Vout

50
10 20

(b)
50 V RL VL
Figure P9.60

Figure P9.59
pn i
 Section 10.1

Section 10.2

Section 10.3

Section 10.4

Section 10.5

10.1 TRANSISTORS AS AMPLIFIERS

AND SWITCHES

amplification switching.

bipolar junction transistors,

BJTs; field-effect transistors, FETs.

gain

ro

+
iin ro vin +
_
iin ri vin ri
_

(a) Current-controlled current source (b) Voltage-controlled voltage source

ro

+
vin ro iin +
vin ri iin ri _

(c) Voltage-controlled current source (d) Current-controlled voltage source

Figure 10.1
 iin 0 iin iin 0
iin ri ri

Current-controlled switch

+ +
vin 0 vin 0
vin ri vin ri
_ _

Voltage-controlled switch

Figure 10.2

LO1

ro C
RS B +
+
+ vin vin +
– RL vL
vS – ri

– –
E

Figure 10.3

ri ro
RS RL
L
AV
S
 ri
S
ri RS

ri
S
ri RS

ri RL
L S
ri RS ro RL

L ri RL
AV
S ri RS ro RL

ri RS ro RL

A RS

RS ro RL ri
A
ro RL ri
RS ro RL ri RL ri RS ro
A ro ri A
ro RL RL

10.2 OPERATION OF THE BIPOLAR JUNCTION

TRANSISTOR
pn

pn bipolar junction
transistor (BJT)
i
 n
p p p n n

pnp npn

Collector Collector
C n
C C C
IB
B
p n p

Base n B B Base p B B +
VS n+
–
p+ n+
IE
E E E E
E
Emitter Circuit symbols Emitter Circuit symbols

pnp transistor npn transistor = Electron flow

Figure 10.4
= Hole flow

npn The BE junction acts very much as

pn base-emitter (BE) junction an ordinary diode when the
collector is open. In this case,
IB = IE.

BE Figure 10.5
npn

n
C

+ IC
base-collector (BC) junction Collector
V2

BE – I
B B
Base
BC +

V1
Emitter
–
IE

E
= Electron flow

= Hole flow

When the BC junction is reverse-

biased, the electrons from the
IE IB IC (10.1) emitter region are swept across the
base into the collector.

Figure 10.6

IC IB (10.2) npn
 pnp
npn
pnp

npn pnp

i npn
i

The operation of the BJT is defined

in terms of two currents and two
voltages: iB , iC , vCE, and vBE.
C
+
vCB iC +
i
– iB iB
B vCE BE iC
+ CE family
vBE iE – i i
–
E
BE
KCL: iE = iB + iC IBB
KVL: vCE = vCB + vBE
IBB BE i
Figure 10.7
CE iC

500
450
400
350
C
300
iB , A

250
B iB 200
+ 150
IBB vBE 100
_
E 50
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VBE , V

Figure 10.8 BE
 C IC 50
Active region IB = 275 A
45 Saturation region IB = 250 A
IB + 40 IB = 225 A
B +
VCE 35 IB = 200 A
+ VCC IB = 175 A
_ _ 30
VBE IB = 150 A

IC , mA
IBB
_ 25 IB = 125 A
E IB = 100 A
20
15 IB = 75 A
IB = 50 A
10
Cutoff region IB = 25 A
5
Figure 10.9(a) 00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
i VC E , V

(b)

Figure 10.9(b)

iB

collector characteristic.
iC CE
iB iC CE

cutoff region,

active linear region,

BE CB LO2
saturation region,
breakdown region,

CE

BVCEO

iB
iC

Determining the Operating Region of a BJT

 RC
1k

C
RB
40 k B V3
VCC
VB V VE V VC V
VBB E
V1 12 V
4V RE V2
321 VB VE VBE
VB VE BE

Figure 10.10
VBB VB
IB
RB

VCC VC
IC
RC

IC
IB

VCE
VCE VC VE

IB IC VCE
IC VCE IB VBE

LO2

VBB

VBB VCC RB
RC RE
 VBB

VB VE
VC RC

pnp npn

LO2

RC

C
VCC
RB B

V3
V1 E
VBB
V VB V VE RE V2
V VC
VBE VBC
BE BC saturation Figure 10.11
region
active region BE BC

VBE VB VE
VBC VB VC

VCE VC VE

VCC V
IC
RC
 V V V

10.3 BJT LARGE-SIGNAL MODEL

i

large-
signal model

Large-Signal Model of the npn BJT

BE

cutoff region.
VBE IB
ICEO BE
active region,

IC IB (10.3)

VCE

saturation region.

BE

BE
 C C

ICEO IB IC
Cutoff state conditions: Active state conditions:
IB = 0
VBE V VBE = V
I =0 B I 0 B
B B + –
IC = ICEO IC = IB V
VCE 0 VCE V
E E

C LO3
IC

+
Saturated state conditions: IB Vsat
VBE = V –
IB 0 B
+ –
IC IB V
VCE = Vsat
E

Figure 10.12 npn

50
45 Saturation region
40
Collector current, mA

35
30
25 Linear region
20
15
10
Cutoff region
5
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Collector-emitter voltage, V

Figure 10.13

pn

F O C U S O N M ET H O D O L O GY
USING DEVICE DATA SHEETS
device data sheet.
npn
general-purpose amplifier

Continued
 2N3904

NPN general-purpose amplifier

This device is designed as a general-
purpose amplifier and switch.
The useful dynamic range extends
C TO-92 to 100 mA as a switch and to
DE
100 MHz as an amplifier.

ELECTRICAL CHARACTERISTICS

large-signal model
hFE

CE BE

Electrical Characteristics TA

Symbol Parameter Test Conditions Min. Max. Units

Off Characteristics

V BR CEO IC IB

V BR CBO IC IE

V BR EBO IE IC

IBL VCE VEB

ICEX VCE VEB

On Characteristics
hFE IC VCE
IC VCE
IC VCE
IC VCE
IC VCE

VCE IC IB
IC IB

VBE IC IB
IC IB

THERMAL CHARACTERISTICS
power rating,
derating

Continued
 Concluded

Thermal Characteristics TA

Max.
Symbol Characteristic 2N3904 PZT3904 Units
PD

R JC

R JA

TYPICAL CHARACTERISTIC CURVES

packages

Base-emitter on voltage vs. Power dissipation vs.

collector current ambient temperature
Base-emitter on voltage VBB (ON) , V

1 1.00
VCE = 5 V
Power dissipation PD, W

0.8 0.75
–40 C SOT-223
25 C TO-92
0.6 0.5
125 C SOT-23
0.4 0.25

0.2
0.1 1 10 100 0
0 25 50 75 100 125 150
IC, mA Temperature, C

LO3
 RC 5V

RB RC
= 95

Vcomputer
RB V V I
VCC V VCE
Figure 10.14
V I P

VCE
V

VCE

VCC R C IC V VCE

VCC V VCE
RC
IC IC

RC

IC
RC
RC 5V
+
1.4 V
_ 5V V VLED

1,000 C
+
VCE
_
+ VCE sat = 0.2 V
5V _ 0.7 V
IB E

(a) (b) (c)

Figure 10.15 BE
 V V
IB
RB

P V IC

BE CE

CE
CE

RS

RS

LO3

VCC R R
Q

VCC R R

Q
 VCC

iC
9-V NiCd

R1
R2
Q1
iB

Figure 10.16

iB
VCC V
iB
R R
iC iB

VCC V
iC
R R
R R
R R
VCC V
R VCC V
R
VCC

R
R

R VCC V R

V VCEQ
 LO3

R R

VCC 9V

R1 M
R2
iC2
Q1
iB1
Q2
iE1=iB2

(a) BJT driver circuit (b) Lego ® 9V Technic motor, model 43362
Courtesy: Philippe “Philo” Hurbain.

Figure 10.17

Darlington
pair
Q iE ( ) iB Q

iC iE iB

VCC V
iB
R R

VCC V
iC iC
R R

R R
 R R
VCC

VCC V
iC R VCC V
R

R
R

R VCC V R

i i

10.4 Selecting an Operating Point for a BJT

i

iB iC CE

Q point, Q
By appropriate choice of IBB , RC quiescent idle currents voltages
and VCC , the desired Q point may
be selected.
IC
DC bias circuit, Q

C
IB + RC
B
VCE
+
_
IBB VBE VCC
_ E
IB IBB (10.4)

Figure 10.18
VCE VCC IC RC (10.5)
 50
45 IB = 250 A
40

Collector current, mA
35 IB = 200 A
30 IB = 150 A
Q
25
20 IB = 100 A
15
IB = 50 A
10
5
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Collector-emitter voltage, V

Figure 10.19

VCC VCE
IC (10.6)
RC

IC IC VCC RC VCE
VCE VCC RC IB
IBB

IB IBB
Q

VCC VCC RC IBB Q

IC VCE

ICQ IBQ

LO4

IC

C
+
RB IB B RC
VCE
+
_
BE VBB VBE VCC
E
_
IBQ ICQ
VCEQ

RB RC Figure 10.20
 VBB VCC V

VCE VCC R C IC IC
Q

BE

VBB VBE VBB V

IB
RB RB

VCEQ ICQ IBQ

PCQ VCEQ ICQ

ICQ VCEQ

VBE IB VCE IC
IC + IC

C
+ RC
IB + IB VB
VCE + VCE
+ B IB Q
+
~ VBE + VBE
– IBQ
_
VB VCC IB
– E

VBB

Figure 10.21
IB IC VBE VCE IB t IC t
VBE t VCE t
 IC, mA
50
IB = 230 A
190 A
28.6
Q 150 A
22 110 A t
15.3
75 A

0
0 5 10 15
VCE , V

Figure 10.22

iC t IC IC t
i

current amplifier,

RC

LO4

iC (t)

+
AV Vo VB C
+ vo (t) RC
iB (t)
vCE (t)
RB + B –
+ –
~
_ VB vBE (t)
VCC
BE – E
VBB
IBQ ICQ
VCEQ IC IB AV Vo VB
RB RC Figure 10.23
VBB VCC V

BE

t V Q V t
 10 k Analysis:

IB DC operating point BE
2.1 V 0.6 V RB BE t VBEQ V

VBB RB IBQ VBEQ

Figure 10.24

VBB VBEQ VBB V

IBQ
RB RB

VCE VCC RC IC IC

VCEQ ICQ IBQ

IC , mA
50
IB = 230 A
190 A
28.6 150 A
Q
22
110 A
15.3
75 A
35 A
0
0 5 10 15
VC E , V

Figure 10.25

AC gain

IC Q
IB

IC
IB

AC voltage gain AV Vo VB
Vo VB o t RC iC t RC ICQ RC IC t

Vo t RC IC t RC IB t

IB t

VB t RB IB t VBE t
 BE
RB VBE t
VB
IB
RB
Vo t
RC VB t
Vo t RC IB t
RB

Vo t RC
AV
VB RB

Q RC

ICQ IBQ VCEQ

IC

R1 RC
IB +
VCC
VCC + VCE
–
VBB VBE IE
–
R2
RE

Figure 10.26
VCC R R
 R
VBB VCC (10.7)
R R

RB R R (10.8)

VBB RB

IC IC

IB + RC IB + RC
R1
VCE VCE
+ +
_ RB _
VBE _ VBE _
VCC R2 IE VCC VBB IE VCC
RE RE

(a) (b)

Figure 10.27

BE

VBB IBRB VBE IE RE RB RE IB VBE (10.9)

VBE BE IE IB

VCC IC RC VCE IE RE IC RC RE VCE (10.10)

IE IB IC IC

VBB VBE
IB (10.11)
RB RE
IC IB

VCE VCC IC RC RE (10.12)

 RC

RC RE RC RE

LO4

BE

IBQ ICQ
VCEQ
R R RC
RE VCC V

R
VBB VCC
R R

RB R R

VBB VBE VBB V

IB
RB RE RB RE

IC IB

VCE VCC IC RC RE

Q
VCEQ ICQ IBQ
 VBB IC
VBE RB
RE RC B VCC

IE IC
RE VCE VBB

10.5 BJT SWITCHES AND GATES

analog digital
gates.

electronic gate
T, C
50
40 analog digital.
30
20
analogy analog
10

4 8 12 16 20 24 0 4 t, h
Atmospheric temperature
over a 24-h period binary signals,
temperature
Desired

T, C
20

t
Vcontrol

t
Average temperature in a house
and related digital control voltage

Figure 10.28
Diode Gates DA
vA

DB
vB vout

OR gate;
R

A B
A DA A DA
OR gate
DB
R A B A OR gate operation
B Diodes are off
vA = vB = 0 V and vout = 0
V
vA = 5 V DA is on, DB is off
A B vB = 0 V
Equivalent circuit
A B A B 0.6 V
+ –
+
5V DB
vout

R
vout = 5 – 0.6 = 4.4 V
BJT Gates

i Figure 10.29
cutoff

saturation,
iC
Saturation
Collector characteristic
VCC
iB = 50 A
RC
BJT switch 6 B iB = 40 A
1
4 –
RC
VCC i C RC (10.13) iB = 20 A
CE
2 A
Cutoff

CE (10.14) 0 1 2 3 4 5 VCE, V
VCC
VCE sat 0.2 V

+VCC = 5 V

CE VCC (10.15) iC RC

vout
+
RB
vin vCE
+
vBE –
VCE –
B
Elementary BJT inverter

Figure 10.30
VCC
RB
iB V RB
LO4

VCE
 TTL, transistor-transistor logic.
inverter

NAND gate,

LO5

VCC

1 2 State of Q1 State of Q2 out

R1 R2 R3

vout
v1
Q1 Q2

v2
Q3

R4
VBE VCE

Figure 10.31 R R
R R VCC VBE V VCE

BE BC Q

Q
Q

Q Q
BE Q
Q Q Q
Q
 Q Q R
R

D
v1
D
Q v2
Q Q

Q Q Q
D D
Q D1
v1
D D D
D3
Q Q Q D2
v2
Q Q
Q
Figure 10.32
VCC IC R VCE

VCC VCE VCC VCE

IC
RC RC

VCC IC R

1 2 State of Q2 State of Q3 out

RB

RB
 Conclusion

Understand the basic principles of amplification and switching

Understand the physical operation of bipolar transistors; determine the operating point
of a bipolar transistor circuit

Understand the large-signal model of the bipolar transistor, and apply it to simple
amplifier circuits

Select the operating point of a bipolar transistor circuit

Understand the operation of a bipolar transistor as a switch and analyze basic analog
and digital gate circuits

+
_ 0.7 V +
BE BC _
_ 4V 0.2 V

0.6 V + _
+
(a) (b)
npn VBE VCE _
_
+ 0.6 V
npn VCB VCE +
+ 0.3 V 5.4 V
pnp VCB VCE
_ +
npn VBE VCB 0.7 V
_
(c) (d)

Figure P10.1
 820 k 2.2 k
BE

12 V 20 k 39 k

20 V 20 V
910

Figure P10.7
Figure P10.3

pnp

VCE
IC IB VCE IB
IC

P VCE IC VBE IB IB VCE

V iC , mA
100
90 600 A
15 k 30 k
80 500 A
70 400 A
10 V 15 V
60
300 A
50
Figure P10.5 40 200 A
30
20 IB = 100 A

10

0 2 4 6 8 10 12 14 16 18 vCE , V

Figure P10.9

62 k 3.3 k
Hint:

P IC VCE P
18 V IC VCE

15 k 1.2 k
IC VC VCE
Figure P10.6 IC VC VCE
 +30 V
VBB
VCE VBE

750 k 6.2 k 20 k

+12 V
Q2

RC 1k
Q1
4.7 k

Vout

Figure P10.10 10 k
T

npn ICQ VBB

VCEQ

5k Figure P10.14

2N3904
npn
50 V +
_
20 A VBE
VCB V IE IB VCE

Figure P10.11 npn

ICQ VCEQ

Hint: V Collector characteristic curves for the 2N3904 BJT

V
0.14
IB 1.0 mA
0.12
IB 0.8 mA
RB = 50 k RC = 1 k 0.1
Collector current, A

IB 0.6 mA
= 200 0.08
5.7 V 10 V IB 0.4 mA
0.06
IB 0.2 mA
0.04
Figure P10.12
0.02
IB 0 mA
0
VCC RC RE
–0.02
0 5 10 15 20
IC IB VBE Collector-emitter voltage, V
IC IB VBE (a)

IC IB VBE Figure P10.16 Continued

 Collector characteristic curves for the 2N3904 BJT
–3
10
20
IB 100 A
RB
IB 80 A
15 RB
Collector current, A

IB 60 A

10 IB 40 A

IB 20 A V
5

IB 0 A
0

–5
0 5 10 15 20
Collector-emitter voltage, V RL
(b)
R
5k L

2N3904 VCE
50 V

20 A RB

5k
V
RB

(c)

Figure P10.16 R

R R
VCC

VCC
I

RC 9-V NiCd
R1 Q1

VCC R
5.6 V ZD1
R
R2
V

RC
I
Figure P10.25
 IBB RC VCC
IC IE VCE VCB

VCC R R R VCC
R
VCC
VCC
R R
RC RE
R1 RL RS
Q1 S t

11 V ZD1 iE
9-V NiCd RC
R1 C +
C V
B C + _ CC
+
RL _Vo
Figure P10.26 RS
E

Vi + R2
V RE C
_S
_

Figure P10.31

Rb

npn
VCEQ Q

VCC 9V VCC
R R
M RS RE
Rb iC2 RL
Q1
iB1
vin Q2
iE2=iB2 +
R1 VCC
C _
B

E
Figure P10.27 RS C
+ R2
V RE RL
_S
RC VBB VCC
RB
Figure P10.32

VCC RC RB
VBB npn
 RE IE
RC VC
VCEQ
RL
VCC VEE
RB
RC RE
RL RS +15 V

S t
RC
C
+ C
VCC RB
_ B
RC 100 RL
C
C E
C
B ~ vS
E
C
RE
RS
RE RL
RB
+ C
V +
_S VEE
_ Figure P10.35

Figure P10.33

RC
npn

VCEQ
i i
VCC ri
RB ro
RC RE
RL RS
S t
VCC

+ R1 RC
RC VCC ri
_ RS iin
250 hfe
+
C Cb
RB
C vS _ +
C vin
B
R2 RE iout vout
E _ _
RS
RE RL
+ C
V
_S RE 250 R1 9,221
VCC 15 V CB
R2 6,320
Figure P10.34
Figure P10.36
S

RB
 Vsignal

Vbatt
I

0 t
(c)

KC VCIT
KC
(ms)
2 ms 16 mS V
VCIT = 2
Vbatt

KC
TC
0 8 12 16 Vbatt 20 20 60 100 TC C
(d)
KC
Figure P10.37
Q VCE VBE

V TC
V TC

Injector
V
Vbatt
+
Vinj Air
Vsignal
_ RW L
Intake
manifold
+
Valve 5.5 V
D1 –
Ra RB = 200 RDON = 25
Q1
VS(t) = 75
40
80 Spark plug

+5 V
Cylinder 0
(a) Figure P10.38

+ Iinj

10 Q Q

V R R
1 mH VCEQ
ICQ

_
R R
(b)

Figure P10.37 Continued

 C' VCC
RC
vo1

RB3
I = IC1 + IC2 Q3
RC
IC1

vo2
IC2 Q1 Q2
B' RB1 RB2
Q1 v1 v2
Q2
IB1
IE1 = IB2
Figure P10.41
IE2
Vcc

Rc
E'
vo1
Figure P10.39 Rc
RB3
Q3

+25 V

vo2
R2 1.5 k RB1
v1 Q1

RB2
v2 Q2

Figure P10.43
R1 1k

Q
RB
Q
Figure P10.40
+VCC = 5 V

2k

vout
RB
o vin Q1
+
vBE
–
o

o Figure P10.45
 VCC
R C R C
R B R B

B Q
R RC

B Q vo

vA
vB

+VCC = 5 V

+VCC = 5 V
R2C Figure P10.49

R1C vout
R2B
Q2
vB +
R1B
vBE B B B C
vin Q1 –
+
vBE
–
5V

Figure P10.46

RB 4k 1.6 k 150 k
RC RC
Q Q
v B1 Q4
vC 2
D1
5V vB2
v1 Q1 Q2 vout
v2
v3 v B3
Q3

RB RC1 RC2 1k

D1 D2
vout
Q1
vin
Figure P10.50
Q2

0.5 k

Figure P10.47
VCC

RB
RC Q
v1 v2
RC
Q

vo

Figure P10.51
channel,
 Section 11.1.

i Section 11.2.
Section 11.3.
LO1

Section 11.4.
Section 11.5
Section 11.5.
Enhancement MOS

p channel n channel 11.1 CLASSIFICATION OF FIELD-EFFECT

Depletion MOS TRANSISTORS

metal-oxide semicon-
p channel n channel ductor field-effect transistors, MOSFETs: enhancement-mode MOSFETs
JFET
depletion-mode MOSFETs. junction field-effect
transistors, JFETs.
n-channel p-channel n p
p channel n channel

Figure 11.1

11.2 OVERVIEW OF ENHANCEMENT-MODE

MOSFETS

n gate
Gate drain
Source Drain
source bulk substrate
n+ p n+

Bulk (substrate) p metal-

oxide semiconductor n
VDD
D p
iD n p
+
pn
VDS
_
G
+V pn
_
GS
S n
Figure 11.2 n normally off
 iD Gate
D
Source Drain
+ n+ p n+
vDS + VDD
_
G Bulk (substrate) + V
DD

(a)

LO2
VGG
iD Gate

+
_ D
Source ++++++ ++++++
vGD
+ n– – – – – – –
n+ n+ Drain
vDS + V
_ DD p
+
G Bulk (substrate) + VDD
+ vGS _
S
VGG +

(b)

Figure 11.3

p
channel

enhancement mode
enhances n
field-effect

depletion-mode

pnp p
n

n p
 Threshold Voltage, VT

on
off
n

n depletion mode

Conductance Parameter K

K
W C
K (11.1)
L
W L
n p
C

Early Voltage VA

DS
VA
DS

Operation of the n-Channel Enhancement-Mode

MOSFET
n

D +
_
vGD
vDS vGD
+ G
+ Region 3:
vGS Triode
_ _
S Cutoff Region
VT
GS VT GD VT
VT vGS
Region 1: Region 2: cutoff region,
Cutoff Saturation

iD (11.2)
Figure 11.4
Saturation Region

GS VT GD VT
 DS
saturation region,
voltage-controlled current source.

VA DS
VA
DS

DS
iD K GS VT
VA (11.3)
K GS VT

Triode or Ohmic Region

GS VT GD VT
DS
GS triode ohmic region,

iD K GS VT DS DS (11.4)

DS GS GD GS DS GS
DS

voltage-controlled resistor

GS VT GD VT

iD K DS

voltage-controlled current
source

DS
GS GD GS DS GS

iD DS

breakdown voltage VDSS

 Drain curves for n-channel enhancement MOSFET; K = 0.0015, VT = 2
15
vGS = 5

2
iD = K – vDS
10 vGS = 4.5

Drain current, mA
vGS = 4

5
vGS = 3.5

vGS = 3
vGS = 2.5
0
vGS < VT

–5
0 1 2 3 4 5 6 7
Drain-source voltage, V

Figure 11.5
VT K

breakdown region

LO2

VDD VGG
VGG VDD DS iD RD
VGG VDD DS iD RD
VGG VDD DS iD RD

iDQ DSQ

VT K

GS VT GD VT
 A
RD
iD
D

vGD
RG vDS VDD
G V
vGS
VGG S

Figure 11.6

GS VGG VT GD G D
VT
iD K GS VT
VDD DS
iD RD

GS VGG G VT
DS D GD VT

iD K GS VT DS DS
VDD DS V
iD RD

VGG VDD DS iD RD

11.3 BIASING MOSFET CIRCUITS

n
 LO2

iD (mA)

100 vGS = 2.8 V

80
2.6 V

60 Q 2.4 V
52
D iD
40 2.2 V
+ RD
G
2.0 V vDS
+
20 –
1.8 V VGG vGS
– S VDD
1.6 V
1.4 V
0
0 2 4 4.75 6 8 10 vDS (V)

Figure 11.7 n

iDQ DSQ

VGG VDD RD

Q
VDD R D iD DS

iD DS

VDD RD
VDD Q
VGG iDQ DSQ

Q
 GS

LO3

iDQ DSQ

VGG VDD VT
K RD

VGG GSQ VGG GSQ VT

iDQ K GS VT

DSQ VDD RD iDQ

GS VT
GD VT
GD GS SD GS DS GD VT

RD
 LO3

VDD Q
RS DSQ
RD
R1 iD
+
iG VDS
+ – VT K DSQ
VGS
– GSQ iDQ
R2
GS RS DSQ

VDD RD
R R VT K DSQ

(a)

VDD
VGG
RD
R
iD VGG VDD
R R

iG +
RG VDS
–
+ VGS –
GSQ iGQ RG iDQ RS VGG
VGG
RS RG R R iGQ

GSQ iDQ RS (a)

(b)
Figure 11.8

DSQ iDQ RD iDQ RS VDD (b)

iDQ K GS VT (c)

GSQ iDQ DSQ

VDD
iDQ RS VGG GSQ GSQ

VDD
VDD iDQ RD DSQ GSQ

VDD
iDQ DSQ GSQ
RD
 iDQ
GSQ DSQ

VDD
DSQ GSQ K GSQ VT
RD
VDD
K GSQ KVT GSQ KVT DSQ GSQ
RD RD
VDD
GSQ VT GSQ VT DSQ
KRD KRD
GSQ GSQ

GSQ GSQ

GS VT

iDQ

RS

RS
DSQ GSQ iDQ

RS GS iD
RS GS

LO3
 GS DS iD

RD R R RD
R1
vD
RS VDD VT K
D
vG
G S
vS
VDD
R R
R2
RS
R
G VDD VDD
R R

GS G S G RS iD iD
Figure 11.9

iD K GS VT iD

iD iD

iD iD

iD GS iD iD GS iD
GS VT

iD GS

D DD RD iD iD

DS D S D iD R S

GS VT
GD GS DS VT

Operation of the P-Channel Enhancement-Mode

MOSFET
p
n
n p

VT GS
SG GD DG DS SD VT VT
 S –
VGG +
iD Gate vGD

+
_ vSG
S –– ––– – –– ––
vSG +
++++++ vDS
Region 3:
Drain p+ p p+ Source – G Triode
vDS
– + VDD n Channel
– vDG VT
G Bulk (substrate) + VDD
– + +
vDG + + D
vGG + D VT vGS
Region 1: Region 2:
Cutoff Saturation

Figure 11.10 p
Figure 11.11

SG VT DG VT

iD (11.5)

SG VT DG VT

iD K SG VT (11.6)

SG VT DG VT

iD K SG VT SD SD (11.7)

11.4 MOSFET LARGE-SIGNAL AMPLIFIERS

iD K GS VT (11.8)

common-
source source-follower
 VDD

iD RLOAD
vLOAD
D
–
vGD
vDS
G
–
vGS S

VG

Figure 11.12

R iD R K GS VT R K VG VT (11.9)

R iD
iD K GS VT K S K K R iD
(11.10)
VG VT

iD K R iD K K R iD R iD
(11.11)
K
iD R
K R R

K
iD R
K R iD R

iD K R
R (11.12)
K
R
K R R

K VT

iD
 VDD

iD

vGD
v DS
G

vGS S

VG
RLOA D
v LO AD

(a ) ( b)
Figure 11.13
K VT

VG

VDD VG

VDD VDD

iD iD
D
9-V NiCd
D
Q
1

Q1 VG G S

VG G S
9-V NiCd

(a) Common-source current source (b) Common-drain current source

Figure 11.14 Continued

 VT K

GS VT GD
VT
VG
VDD
iD K GS VT G

i
GD VT
DS GS VT
GD VT
VDS VGS VT VGD

GD G D D VDD VB VB
GD VT

GD VT
G D VT
D G VT
VDD VB G VT VDD VB G VT

VDD VDD

(c) Gate voltage––drain current curve for the circuit of Figure 11.14(a)
Figure 11.14 Continued
 GS VT

iD K GS VT K VG VB VT

GS

Charging current for NiCd battery source-follower circuit

0.045

0.04

0.035

0.03
Charging current, A

0.025

0.02

0.015

0.01

0.005 (d) Charging current profile for the circuit of Figure 11.14(b)

0
0 2000 4000 6000 8000 10000 12000
Time, s

(d) Charging current profile for the circuit of Figure 11.14(b)

Figure 11.14

iD S D iD DS P
iD S D iD DS P
 Lego 9V Technic motor, model
43362

R R
VT K

GS VT
GD VT
VG
VDD
iD K GS VT G

VDD

iD

M Va

D
Q1

VG G S

(a) MOSFET DC motor driver circuit (b) Lego 9V Technic motor, top: model
43362; bottom: family of Lego motors
Courtesy: Philippe “philo” Hurbain.
Figure 11.15 Continued
(c) Drain current––gate voltage curve for the MOSFET in saturation

VG
Shorter duty cycle
Longer duty cycle
5

0
t
(d) Pulse-width modulation (PWM) gate voltage waveforms
Figure 11.15

pulse-width modulated
On duty cycle
 11.5 MOSFET SWITCHES

complementary metal-oxide semiconductor, CMOS.

VDD
Digital Switches and Gates
CMOS inverter
p n
VDD
p
+ n
+
logic high
vout VDD logic low
vin

– – VDD p

Figure 11.16 off

VDD
on

VDD VDD

LO5
+ + + +

vin = vDD vout = 0 vin = 0 vout = VDD

– – – –
(a) (b)

Figure 11.17

VDD
 LO5
RD

vDD

+
_ vsignal (t)

VDD
Q Figure 11.18

RD VDD
t t t t

iD , mA
80
vGS = 2.6 V

60
2.4 V

2.2 V

2.0 V
1.8 V
1.6 V
0
0 2 2.5 4 6 8 10 vDS , V
VDD

Figure 11.19

VDD RD iD DS iD DS

DS iD

t
Q
GSQ iDQ DSQ
 t
Q
GSQ iDQ DSQ

RD iD

RD DS

LO5

1 2 State of M 1 State of M 2 State of M 3 State of M 4 out

VDD

The transistors in this circuit

M1 show the substrate for each
v1 transistor connected to its
respective gate. In a true
vout CMOS IC, the substrates for
M2 the p-channel transistors are
connected to 5 V and the
v2 substrates of the n-channel
transistors are connected to
M3 M4 ground.

Figure 11.20
 VDD
VT VDD

M1
v1

M M M2
v2
M vout
M M
M VDD
M3 M4
M M M v2
M v1

M M 5V

5V 5V 5V M1

M2
M1 M1
M1
vout

M2 M2 M2 M3 M4

vout vout vout

M3 M4 M3 M4 M3 M4
With both v1 and v2 at 0 V,
M3 and M4 will be turned off
(in cutoff), since vGS is less than
VT (0 V 1.7 V). Both M1 and
(a) (b) (c) M2 will be turned on, since the
gate-to-source voltages will
Figure 11.22 be greater than VT .

Figure 11.21

1 2 M1 M2 M3 M4 out
 VDD

vout

v1
VT = 1.5 V
out 2 1

v2

Figure 11.23 Analog Switches

GS

GS VT DS GS VT (11.13)

DS
vC

+
vGS
vin
– rDS (11.14)
K GS VT
+
RL vout
MOSFET analog switch
– DS
iD DS GS VT GS VT (11.15)
rDS
vC

GS
RDS
vin vout
GS VT GS
vC VT switch “off ”
vC > VT switch “on”
C
Functional model
Figure 11.24 RL
C VT
 VT vC
C GS
RDS RDS RL
vin vout

vC = V on state
vC = –V off state

Figure 11.25
Conclusion

n
p

Understand the classification of field-effect transistors.

Learn the basic operation of enhancement-mode MOSFETs by understanding their i–

curves and defining equations. i

cutoff triode
saturation

breakdown
Learn how enhancement-mode MOSFET circuits are biased.
Q

Understand the concept and operation of FET large-signal amplifiers.

Understand the concept and operation of FET switches.

Analyze FET switches and digital gates.

VT VT
n
 + –

VT K G
2.5 V 1V
– +
2.5 V + – 2V – +

(a) (b)

– + 1k
vD
D
1V 6V VDD = 5 V
– –
vG
5V + + 2V + – G S
(c) (d)

Figure P11.1

D
vG 5V
D

D 0

p Figure P11.9
VT K R
D iD
iD
+20 V VT k

R iD
iD vD 0.1 V
D

G S VDD 15 V

Figure P11.4

VT iD GS DS
iD GS
Figure P11.10
n
DS
VT
RDS VGS iD
iD D
GS RDS GD
VT k

VT RD
RD

D k VT
GS

VT iD GS DS
iD DS
DS

iD GS DS
 iD VGG VDD RD

Q
R1 S
G + VGG VDD VT K
vDS RD
_ VDD = 10 V
+ Q
D
vGS
_
R2 VDD RD R R
RD
VT K
RS DSQ iDQ
GS DS iD
VDD
Figure P11.11
RD R R RS
VT K

K VT
VG RL
i n
RL VG
n

iDQ DS

12 V

2.0 ID RL
TA = 25 C RL
1.8
12 V
1.6
vGS = 10 V VG
1.4
Drain current iD , A

9V
1.2
1.0 8V

0.8 7V Figure P11.17

0.6 6V
0.4 5V
0.2
source
4V
3V follower
0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
Drain-source voltage vDS, V
(a)
12 V
RD
iD
_ D
vGD
+
+ vDS + VDD
G _
VG
+ VL
RG vGS _ S
VGG +

IL RL

(b)

Figure P11.13 Figure P11.18

 IL VG RL K
VT

RL
K VT VG
ID

VG t
K VT
ID

t 0.002

VG 12.7 V

15 V

60
ID Figure P11.21

Vout

VG

Figure P11.19 I f VG
K VT

K VT
VG t
VDD 12
IL
V
t IRef 0.01 A

RL
+
VG
12 V
_

Figure P11.22
VG
Vout

IL 4

Figure P11.20 K VT
 VDD 6V VDD 6V 12 V
IL RL 1

VG VG
VL

VG
IL RL 1 2 IL

Figure P11.23

Figure P11.26

n p
Kn Kp VTn
VTp V t
VL IL

+12 V

VL
Vin
IL RL 1
2

12 V

Figure P11.24

V I

VDD

Q1

Figure P11.25
vin vout

VL IL
Q2
K VT
VG
VG
VG t Figure P11.33
 VDD

VDD

Q3

Q3
vout
vout

Q1
v1
Q1 Q2
v1 v2

Q2
Figure P11.34 v2

Figure P11.35