EXPERIMENT NO.

1
JFET AMPLIFIERS
______________________________________________________________________________________

Because the transconductance curve of a JFET is parabolic, large signal operation

of a CS amplifier produces square law distortion. This is why a CS amplifier is usually
operated small signal, JFET amplifier cannot compete with bipolar amplifiers when it
comes to voltage gain. Because gm is relatively low, the typical CS amplifier has a
relatively low voltage gain.
The CD amplifier, better known as the source follower, is analogous to the
emitter follower. The voltage gain approaches infinity, limited only by the external biasing
resistors connected to the gate.
The source follower is a popular circuit often found near the front end of measuring
instruments
In this experiment, you will build a CS amplifier and a source follower to verify the
relation discussed in your textbooks.

REQUIRED READING
th
Chapter 14 (Sec. 14-5) of Electronic Principle 5 Ed by Paul Malvino

EQUIPMENT
1 audio generator
1 power supply: 15V
3 JFETs: MPF102 (or equivalent)
4 ½-W resistors: 1kΩ, three 1kΩ, two 2.2kΩ, 220kΩ
5 capacitors: two 1µF, 100 µF (16-V rating or better)
1 potentiometer: 5kΩ
1 oscilloscope

PROCEDURE

CS Amplifier

1. Assume the JFET of Fig. 1-1 has a typical gm of 200µS. Calculate the unloaded
voltage gain, output voltage, and output impedance. Record your answer in Table
1-1
2. Connect the circuit with RL equal to infinity (no load resistor).
3. Adjust the audio generator to 1 kHz. Set the signal level to 0.1 V p-p across the
input.
4. Look at the output signal. It should be an amplified sine wave. Measure and record
the peak-to-peak output voltage. Then calculate the voltage gain. Record your
answer as the measured A in Table 1-1.
5. Connect the 5-kΩ potentiometer as a variable load resistance. Adjust this load
resistance until the output
voltage is half of the unloaded output voltage.
6. Disconnect the 5-kΩ potentiometer and measure its resistance. Record this as rout
in Table 1-1. (Note: You have just found the Thevenin or output impedance by the
matched-load method.)
7. Repeat Steps 1 to 6 for the other JFET’s

1
+ 15 V

2
 2.2 kΩ 1 µF
VOUT

1µF RL
MPF
102

0.1 V p – p
1kHz
AC 220 kΩ 2.2 100 µF
kΩ

Figure 1 – 1
Source
Follower
8. Assume a typical gm if 2000 µS in Fig. 1-2. Calculate the unloaded voltage gain,
output voltage, and output impedance. Record your answers in Table 1-2.
9. Connect the circuit with RL equal to infinity. Adjust the frequency to 1 kHz and
the signal level to 1V p-p across the input.
10. Measure and record the output voltage. Calculate the voltage gain and record as
the measured A in table
1-2.
11. Measure and record the output impedance by the matched-load method used
earlier.
12. Repeat Steps 8 to 11 for the other JFET’s.
+ 15V

C1
MPF102
1µF

C2
100
µF VOUT
0.1 V p – p
1kHz R1 RL

R2

3
 AC 220kΩ 2.2kΩ

Figure 1 – 2

Troubleshooting (Optional)

13. Table 1-3 lists dc and ac symptoms for Fig. 1-2. Try to figure found out what
trouble would produce these
14. Repeat Step 13 for the other symptoms listed in Table 1-3

DATA FOR EXPERIMENT 1

Table 1-1. CS
Amplifier Calculated Measured
JFET Vout A rout Vout A
rout
1

Table 1-2. Source

Follower Calculated Measured
JFET vout A rout vout A
rout
1
2
3

Table 1-3. Troubleshooting

DC Symptoms AC Symptoms
VG VD VS Vg Vd Vs Vout Trouble
0 15V 3.7V 1V 0 0 0
0 15V 3.7V 1V 0 0.82 0
0 15V 3.7V 0 0 0 0
0 0 0 1V 0 0 0

QUESTIONS FOR EXPERIMENT 1

1. The calculated voltage gain of Table 1–1 is approximately ( )

(a) 0.44V; (b) 1V; (c) 4.4V;(d) 9.4V.
2. The output impedance of Fig. 1-1 is closest to ( )
(a) 407Ω; (b) 2.2k Ω; (c) 5kΩ; (d) 220kΩ.
3. The voltage gain of the source follower was closest to: ( )
(a) 0.5; (b) 0.8; (c) 1; (d) 4.4
 EXPERIMENT NO. 2
CASCADED CE STAGES
____________________________________________________________________________________

The amplified signal out of a CE stage can be used as the input to another CE
stage. In this way, we can build a multistage amplifier with very large voltage gain.
Because a CE stage has input impedance, there is loading effect on the preceding
stage. In other words, the loaded voltage gain is less than the unloaded voltage gain.
In this experiment, you will build a two-stage amplifier using swamped stages to
stabilize the overall gain.

REQUIRED READING
th
Chapter 10 (Sec. 10-6) of Electronic Principle 5 Ed by Paul Malvino

EQUIPMENT
1 audio generator
1 power supply: 10V
2 transistors: 2N3904 (or equivalent)
2 ½-W resistors: two 68Ω, three 1k Ω, one 1.2k Ω, two 2.2k Ω, two 3.6k Ω, two 10k Ω
5 capacitors: three 1µF. two 47 µF (10 V rating or better)
1 VOM (analog or digital multimeter)
1 oscilloscope

PROCEDURE

Calculations
1. In Fig. 2-1, calculate the dc voltages at the base, emitter and collector of each
stage. Record your answers in Table 2-1.
2. Next, examine Fig. 11 of the 2N3904 data sheet in the Appendix. Read the
typical value of hfe. Record this value at the top of Table 2-2.
3. Calculate the peak-to-peak ac voltage at the base, emitter and collector of
each stage (Fig. 2-1) using the hfe of Step 2. Record all ac voltages in Table 2-
2.

Tests
4. Connect the two-stage amplifier of Fig. 2-1.
5. Measure the dc voltage at the base, emitter and collector of each stage.
Record your data in Table 2-1. Within the tolerance of the resistors being
used, the measured voltages should agree with your calculated voltages.
6. Measure the peak-to-peak ac voltage at the base, emitter and collector of each
stage. Record your data in Table 2-2. These measured ac voltages should agree
with your calculated values.

Loading Efects
7. Open the coupling capacitor between the first and second stage. Look at
the ac voltage on the first collector. Reconnect the coupling capacitor and
notice that the ac signal decreases significantly. Do not continue until you
understand and can explain why the signal decreases.
8. Open the coupling capacitor between the second stage and the load resistor.
Look at the ac voltage on the second collector. Reconnect the coupling
capacitor and notice the decrease in signal strength. Once more, you should be
able to explain why this happens.
Troubleshooting (Optional)
9. In Fig. 2-1, assume C4 is open. Does this produce a trouble in the first or
second stage? Record your answer (1 or 2) in Table 2-3.
10.Insert the forgoing trouble in your circuit. You will know whether or not it is a
clue to the trouble.
11. Estimate each voltage in Table 2-3 for the stage with the trouble. Measure and
record the voltage.
12. Repeat Steps 9 to 11 for each of the troubles listed in Table 2-3.
13. Ask the instructor to insert a trouble in your circuit.
14. Locate, repair and fix the trouble.
15. Repeat Steps 13 and 14 as often as indicated by the instructor.
 1

+V
R2 R4 R7 0
R9
R1 C1 10 3.6k 10 3.6 C3 V
1k F 1u k uF k k 1u
F
+ C2 +
1
+

Q1 Q2
2N3904 2N3904

20mV R
R5 1
2
1.
1kHz R10 2
68 68 k

R3 R6

+
R8 R1

+
2.2k 1k C4 C5
47u 2.2 1
k 47uF
F 1k

Figure 2-1
DATA FOR EXPERIMENT 2

Table 2-1. DC VOLTAGES

Calculated Measured
Stage VB VE VC VB VE V C`
1
2

Table 2-2. AC Voltages: hfe =

Calculated Measured
Stage Vb Ve Vc Vb Ve
Vc
1
2

Table 2-3. Troubleshooting

DC Voltages AC Voltages
Trouble Stage VB VE VC Vb Ve
Vc Open C4
Shorted R4
Shorted R10
Open R3
Open C5 __

QUESTIONS FOR EXPERIMENT 2

1. The calculated dc base voltage of the first stage was approximately: ( )

(a) 1.1V; (b) 1.8V; (c) 6.28V; (d) 10V
2. The measured dc collector voltage of the second stage was closest to: (
)
(a) 1.1V; (b) 1.8V; (c) 6.28V; (d) 10V
3. The ac base voltage of the first stage was closest to: ( )
(a) 5mV; (b) 12mV; (c) 100mV; (d) 1.4V
4. The ac emitter voltage of the second stage was closest to: ( )
(a) 5mV; (b) 12mV; (c) 100mV; (d) 1.4V
5. The voltage gain from the base of the first stage to the collector of the second
stage was closest to: ( )
(a) 10; (b) 115; (c) 230; (d) 1000
6. Explain why the signal decreased when the coupling capacitor was
reconnected in Step 7.
 EXPERIMENT NO. 3
THE DIFFERENTIAL AMPLIFIER
______________________________________________________________________________________________

The differential amplifier is the direct-coupled input stage of the typical op amp. The most
common form of a diff. amplifier is the double-ended input and single-ended output circuit.
Some of the important characteristics of a diff. amp are the input offset current, input bias
current, input offset voltage and common-mode rejection ratio. In this experiment you will
build a diff amp and measure the foregoing quantities

REQUIRED READING
th
Chapter 17 (Secs. 17-1 to 17-6) of Electronic Principle 5 Ed by Paul Malvino

EQUIPMENT
1 audio generator
2 power supplies +/- 15V
10 ½-W resistors: two 22Ω, two 100 Ω, two 1.5k Ω, two 4.7k Ω, two 10k Ω (5% tolerance)
2 transistors: 2N3904
1 capacitor: 0.47µF
1 VOM (analog or digital multimeter)
1 oscilloscope

PROCEDURE

Tail Current and Base Currents

1. Notice the pair of swamping resistors (22Ω) in Fig. 3-1. These have to be
included in this experiment to improve the match between the discrete transistors.
In Fig. 3-1, you may assume the typical hfe is 200. Calculate the approximate tail
current. Record in Table 3-1. Also calculate and record the base current in each
transistor.
2. Connect the circuit of Fig. 3-1.
3. Measure and record the tail current.
4. Use the VOM as an ammeter to measure the base current in each transistor. If
your VOM is not sensitive enough to measure microampere currents, then use
the oscilloscope on dc input to measure the voltage across each base resistor and
calculate the base current. Record the base currents in Table 3-1.

Input Ofset and Bias Currents

5. With the calculated data of Table 3-1, calculate the values of input offset current
and input bias current.
Record your theoretical answers in Table 3-2.
6. With the measured data of table 3-1, calculate the values of Iin(off) and
Iin(bias). Record your experimental answers in 3-2

Figure 3-1
Output Offset Voltage
7. In Fig. 3-2, assume the base of Q1 is grounded by a jumper wire. If both of the
transistors are identical and
all components have the values shown, then the dc output voltage would have a
value of approximately
+7.85V. For this part of the experiment, any deviation from +7.85V is called output
offset voltage, designated
Vout(off).
8. Connect the circuit of Fig. 3-2. Ground the base of Q1 with a jumper wire.
Measure the dc output voltage.
Calculate the output offset voltage and record Vout(off) in Table 3-3.
9. Remove the ground from the Q1 base. Adjust the potentiometer until the output
voltage is +7.85V.
10. Measure the base voltage of Q1. Record in Table 3-3 as Vin(off).

Figure 3-2

Diferential Voltage Gain

11. Because of the swamping resistors in Fig. 3-3, the differential voltage gain is
given by Rc/2(r E + re’).
Calculate and record A in table 3-4.
12. Connect the circuit. Set the audio generator at 1kHz with a signal level of 10mV p-
p.
13. Measure the output voltage. Calculate and record the experimental value of A.

Common Mode Voltage Gain

14. Calculate the common mode voltage gain of Fig. 3-3. Record ACM in Table 3-4.
15. Put a jumper wire between the bases of your built-up circuit.
16. Increase the signal level until the output voltage is 0.5V p-p.
17. Measure the peak-to-peak input voltage. Calculate and record the experimental
value of ACM.
 Figure 3-3

Common Mode Rejection Ratio

18. Calculate and record the theoretical value of CMRR using the calculated data of
Table 3-4.
19. Calculate and record the experimental value of CMRR using the experimental data
of Table 3-4.

Troubleshooting (Optional)
20. In this part of the experiment, a collector-emitter short means all three
transistor terminals are shorted
together. A collector-emitter open means the transistor is removed from the circuit.
21. In Fig. 3-3, estimate the dc output voltage for each trouble listed in Table 3-5.
22. Insert each trouble, measure and record the dc voltages of Table 3-5.
DATA FOR EXPERIMENT 3

Table 3-1. Tail and Base Currents

Calculated Measured
IT = _ IT =
IB IB1 =
1
IB2 =_ IB2 =_

Table 3-2. Input Ofset and Bias Currents

Theoretical Experimental
Iin(off) = Iin(off) =
Iin(bias)= Iin(off) =

Table 3-3. Input and Output Ofset Voltages

Vout(off)
Vin(off)

Table 3-4. VoltageGains and CMRR

Calculated Experimental
A =_ A =_
ACM = ACM =
CMRR = CMRR =

Table 3-5. Troubleshooting

Trouble Estimated Vout Measured Vout
Q1 CE short
Q1 CE open
Q2 CE short
Q2 CE open

QUESTIONS FOR EXPERIMENT 3

1. The tail current of Table 3-1 is closest to: ( )
(a) 1µA; (b) 23.8 µA; (c) 47.6 µA; (d) 9.53 µA
2. The calculated base current of Fig. 3-1 us approximately: ` ( )
(a) 1µA; (b) 23.8 µA; (c) 47.6 µA; (d) 9.53 µA
3. The calculated input bias current of Fig. 3-1 is approximately: ( )
(a) 1µA; (b) 23.8 µA; (c) 47.6 µA; (d) 9.53 µA
4. The input offset voltage is the input voltage that
removes the:
(a) tail current; (b) dc output voltage; (c) output (d) supply voltage
5. offset
The voltage;
CMRR of Table 3-4 is closest to:
(a) 0.5; (b) 27.5; (c) 55; (d) ň
6. Why is a high CMRR an advantage with a diff amp?
7. In Fig. 3-3, somebody mistakenly uses 150Ω instead of 1.5kΩ for the tail resistor.
What are the some of the dc and ac symptoms you can expect?
8. You are the troubleshooting in the circuit of Fig. 3-3. What should an oscilloscope
display for the
AC voltage between the 22Ω resistor and ground?
 EXPERIMENT NO. 4
THE OPERATIONAL AMPLIFIER
____________________________________________________________________________________________

An operational amplifier, or op amp, is a high-gain dc amplifier usable from 0 to 1 Mhz

(typical). By connecting external resistors to an op amp, you can adjust the voltage gain and
bandwidth to your requirements. Whether troubleshooting or designing you have to be
familiar with the characteristics of an op amp. These include the input offset current, input
bias current, input offset voltage, common-mode rejection ratio, MPP value, short-circuit
output current, slew rate and power bandwidth. In this experiment you will connect test a
basic op amp circuit.

REQUIRED READING
th
Chapter 18 (Secs. 18-1 to 18-6) of Electronic Principle 5 Ed by Paul Malvino

EQUIPMENT
1 audio generator
2 power supplies: +/- 15V
8 ½-W resistors: two 100Ω, 1k Ω, two 10k, 100k Ω, two 220k Ω
3 op amps: 741C
2 capacitors: 0.47µF
1 VOM (analog or digital multimeter)
1 oscilloscope

PROCEDURE
1. The 741C has a typical Iin(bias) of 80nA. Assume that this is the base current in each
220k Ω resistor of
Fig. 4-1. Calculate dc voltages at the non-inverting and inverting outputs. Record in
Table 4-1.
2. Connect the circuit of Fig. 4-1.
3. Measure dc voltage at the noninverting input. Record in Table 4-1.
4. Measure and record the inverting input voltage.
5. Repeat Steps 1 to 4 for the other 741Cs.
6. With the measured data of Table 4-1, calculate the base currents, then the values of
Iin(off) and Iin(bias).
Figure 4-1.
Output Ofset Voltage
7. Connect the circuit of Fig. 4-2. Note: Bypass capacitors are used on each
supply voltage to prevent
oscillations, discussed in Chap. 22 of your textbook. These capacitors should be
connected as close to the
IC as possible.
8. Measure the dc output voltage. Record this value as Vout(off) in Table 4-3.
9. Repeat Step 8 for the other 741Cs.
10. With the resistors shown in Fig. 4-2, the circuit has a voltage gain of 1000.
Calculate the input offset voltage with

Vin(off) = Vout(off)
1000
Record your results in Table 4-3.

Figure 4-2

Maximum Output Current

11. Disconnect the right end of the 100k Ω resistor from the output.
12. Connect the right end of the 100k Ω resistor to the +15V. This will apply
approximately 15mV to the inverting input, more than enough to saturate the op
amp.
13. Replace the 10k Ω load resistor by a VOM used as an ammeter. Since the
ammeter has a very low resistance, it indicates the short-circuit output current.
14. Read and record Imax in Table 4-3.
15. Repeat Step 14 for the other 741Cs.

Slew Rate
16. Connect the Circuit of Fig. 4-3 with an R2 of 100k Ω.
17. Use the oscilloscope (time base around 20µs/cm) to look at the output of the
op amp. Set the audio generator at 5kHz. Adjust the signal level to get a hard
clipping on both peaks of the output signal (overdrive condition).
18. Measure the voltage change and the time change of the waveform. Calculate and
record the slew rate in
Table 4-4.
19. Repeat Step 18 for the other 741Cs.
Power Bandwidth
20. Change R2 to 10k Ω. Set the ac generator at 1kHz. Adjust the signal level to get
20V p-p out of the op amp.
21. Increase the frequency from 1 to 20kHz and watch the waveform. Somewhere
above 8kHz, slew rate distortion will become evident because the waveform
will appear triangular and the amplitude will
decrease
22. Record the approximate (ballpark) frequency where slew-rate distortion begins
(Table 4-4).
23. Repeat Steps 20 to 22 for the other 741Cs.

Figure 4-3. MPP Value

24. Set the ac generator at 1kHz. Increase the signal level until clipping just starts on
either peak.
25. Record the MPP of all transistors in Table 4-4.

Troubleshooting (Optional)
26. Measure the dc and ac output voltage for each trouble listed in Table 4-5.
27. Record your data in Table 4-5.
DATA FOR EXPERIMENT 4

Table 4-1. Input Voltages

Calculated Measured
Op Amp V1 V2 V1 V2
1
2
3

Table 4-2. Input Ofset and Bias Currents

Op Amp Iin(off) Iin(bias)
1
2
3

Table 4-3. Input and Output Ofset Voltages

Op Amp Vout(off) Vin(off)

Imax
1

Table 4-4. Slew Rate, Power Bandwidth, and MPP Value

Op Amp SR fmax MPP

Table 4-5. Troubleshooting

Trouble DC output Voltage AC Output Voltage No +15V
No -15V
Pin 2 shorted to GND

QUESTIONS FOR EXPERIMENT 4

1. The calculated dc voltages in Table 4-1 are approximately; ( )
(a) 1mV;(b) 5.6mV; (c) 12.3mV (d) 17.6mV
2. The input bias current of Table 4-2 is closest to: ( )
(a) 1nA; (b) 80nA; (c) 2mA; (d) 25mA
3. The short-circuit currents of Table 4-3 are closest to : ( )
(a) 1nA; (b) 80nA; (c) 2mA; (d) 25mA
4. When the input frequency was much higher than the fmax of Table 4-4, the ( )
output looked:
(a) sinusoidal;(b) triangular; (c) square; (d) undistorted
5. The MPP value of Table 4-4 is closest to: ( )
 (a) 5mV; (b) 15V; (c) 25V;
(d) 30V
6. Explain the meaning of the input offset current and input bias current
 EXPERIMENT NO. 5
LINEAR IC AMPLIFIERS
______________________________________________________________________________________________

Linear op-amp circuits preserve the shape of the input signal. If the input is
sinusoidal, the output will be sinusoidal. Two basic voltage amplifiers are possible the non-
inverting amplifier and the inverting amplifier. The inverting amplifier consists of a source
resistance cascaded with a current – to –voltage converter. As discussed in your textbook,
the closed – loop voltage gain equals the ratio of the feedback resistance to the source
resistance.
In this experiment you will build and test both types of voltage amplifiers. You will
also connect non-inverter/inverter with a single adjustment that allows you to vary the
voltage gain.

REQUIRED READING
th
Chapter 20 (Secs. 20-1, to 20-3) of Electronic Principle 5 Ed by Paul Malvino

EQUIPMENT
1 sine/square generator
2 power supplies: 15V
13 1/2-W resistors: 100Ω, two 1.1k Ω, two 6.8kΩ, 10kΩ,47 kΩ, 68 kΩ, 100kΩ, 220kΩ,
330kΩ, 470kΩ
1 potentiometer: 1kΩ
1 op amp 741C
4 capacitors: two 0.47µF, two 1µF
1 VOM (analog or digital multimeter)
1 oscilloscope
1 frequency counter

PROCEDURE

Single – Supply Noninverting Amplifier

1. Assume a typical funity of 1 MHz for the 741C of Fig. 5-1. Calculate ACL and
f2(CL). Also calculate the input, output, and bypass critical frequencies. Estimate
the MPP value. Record all answers in Table 5-1.
2. Connect the circuit. Adjust the audio generator to 100mV p-p at 1 kHz. Measure
and record ACL.
3. Measure and record the upper critical frequency. (Try both the sine and square –
wave methods.)
4. Measure and record the lower critical frequency.
5. Measure and record the MPP value.

Inverting Amplifier
6. For each R value of Table 5-2, calculate ACL and f2(CL) in Fig. 5-2.
7. Connect the circuit with R equal to 4.7kΩ. Set the input frequency to 100 Hz.
Adjust the signal level to get
an output of 5V p-p.
8. Measure vin. Calculate the record ACL as a measured quantity.
9. Measure and record f2(CL).
10. Repeat Steps 7 to 9 for other R values in Table 5-2.
 +15V
0.
R1 47
6.8 µF C
C1 3 + 2
kΩ 1µ
F
1µF 7
6
 2 VOUT
6.8 741
kΩ -C
100mV R3
p -p 4
1kHz R2 47kΩ
6.8kΩ
AC R4
470
R kΩ
5
10
kΩ

C
3

Figure 5 – 1

Noninverter/Inverter
11. Calculate the maximum noninverting and inverting voltage gains for the circuit
of Fig. 5-3. Record in
Table 5-3.
12. Connect the circuit.
13. Look at the output signal with an oscilloscope. Vary the potentiometer and notice
what happens.
14. Measure the maximum noninverting voltage gains. Record the data in Table 5-3.

+15V

0.47µF

1kΩ
2+ 7
6 VOUT
3
741C 0.4
-4
100mV p 7µ
100 F
-p Ω
1kHz
6.8kΩ
AC

Figure 5 - 2
1kΩ 10kΩ
 +15V

R4 0.47µF

1kΩ
2 + 7
8 VOUT
3
741
- 0.
C
1V p - 10 47
0Ω 4
p µF
1kHz -15V
AC

1kΩ

Figure 5 – 3

Troubleshooting (Optional)
15. For each trouble listed in Table 5-4, estimate and record the dc voltage at pin 6
(Fig. 5-1).
16. Insert each trouble into the circuit. Measure and record the dc voltage at pin 6.
DATA FOR EXPERIMENT 5

Table 5-1. Noninverting Amplifier

Calculated
ACL =
f2(CL) =
fin = fout = fBY = MPP =
Measured ACL = F2(CL) = F1(CL) = MPP =
Table
5-2. Calculated Measured
R ACL f2(CL) ACL f2(CL)
47kΩ
68kΩ
100kΩ
220kΩ
330kΩ
470kΩ

Table 5-3. Noninverter/Inverter

Calculated
Anon = Ainv = Measured Anon =
Ainv =
 EXPERIMENT NO. 6
LOWER CRITICAL FREQUENCIES
______________________________________________________________________________________________

At lower frequencies the coupling capacitors no longer look like ac shorts. This
implies that some of the ac voltage is dropped across the coupling capacitors. Likewise the
emitter bypass capacitor no longer appears as an ac short when the frequency is low
enough. The input coupling capacitor, the output coupling capacitor, and the emitter
bypass capacitor have a critical frequency associated with it. The highest of the critical
frequencies is the dominant one because the amplifier response breaks first at this
frequency. In this experiment you will build and measure the lower critical frequencies of a
CE amplifier. This will allow you to see how coupling and bypass capacitors affect the
response of an amplifier at low frequencies.
Up to now, we have limited the troubleshooting to shorted and open components
caused either by defective components or by cold- solder joints and solder bridges. In the
production of electronic equipment, you sometimes encounter component of incorrect
value. For instance, in the stuffing of printed circuit boards, someone may occasionally
insert the wrong values for a resistor or capacitor. In this experiment the troubleshooting
option introduces components of the wrong size.

REQUIRED READING
th
Chapter 16 (Sec. 16-1 to 16-4) of Electronic Principle 5 Ed by Paul Malvino

EQUIPMENT
1 audio generator
1 power supply: 10V
1 transistor: 2N3904
9 ½-W resistors: 220 Ω, three 1kΩ, three 1kΩ, 2.2kΩ, 3.6kΩ, 8.2kΩ, 10kΩ, 36kΩ
5 capacitors: 0.1µF, 1µF, two 10µF, 470µF (16-V rating or better)
1VOM (analog or digital multimeter)
1 oscilloscope
1 frequency counter

PROCEDURE

Dominant Input Critical Frequency

1. Assume C1 = 0.1µF, C2 = 10µF, C3 = 470µF in Fig. 6-. Also assume a typical hfe
of 120. Calculate the three lower critical frequencies. Record your answers in Table
6-1.
2. Connect the circuit with the foregoing values.
3. Set the audio generator to 10 kHz with a peak – to – peak value of 20mV. This is
measured from the left end of the 1kΩ resistor to ground.
4. Look at the output voltage with the oscilloscope. Also measure the output voltage
with the VOM
5. Decrease the input frequency until the output voltage is down to 0.707 of its value at
10 kHz.
6. Check that the source voltage is still 200mV p-p. If it has change, readjust it until it
again equals 20mV p-p.
7. Repeat steps 5 and 6 until the source vo0ltage is 20mV p-p and the output voltage
is down to 0.707 of its value at 10 kHz. The frequency is now approximately at the
dominant lower critical frequency.
8. Measure the frequency with an electronic frequency counter. (If a counter is
not available, use the oscilloscope to measure the period; then calculate the
frequency with f = 1/T.) Record the critical frequency in Table 6-1.

+10V

R2 R4
 10 3.6kΩ C2
kΩ
+
R1 C1
+
1kΩ
2N3904
R5
200mV 8.2kΩ

R3
p-p +
2.2kΩ C3
AC
1kΩ

Figure 6 - 1

Dominant Output Critical Frequency

9. Assume C1 = 10µF, C2 = 0.1µF, and C3 = 470µF. Calculate and record the three
lower critical frequencies.
10. Repeat Steps 2 to 8.

Dominant Emitter Bypass Critical Frequency

11. Assume C1 = 10µF, C2 = 10µF, CE = 10µF. Calculate and record the three critical
frequencies.
12. Repeat Steps 2 to 8.

Troubleshooting (Optional)

17. Connect the circuit C1 = 10µF, C2 = 0.1µF, and C3 = 470µF. Measure the lower
critical frequency.
It should be in the vicinity of 20 Hz. (Note: All critical frequencies are fairly close to
10Hz, so the
combined effect of the three effects is an amplifier critical frequency near 20Hz.)
18. Set the input frequency at 10 kHz and the source voltage at 20mV p-p.
19. As mentioned in the preliminary remarks, sometimes the trouble is a component
of incorrect
size. In this part of the experiment, the possible troubles are the following:
R 2 = 1kΩ, R3 = 220Ω, R4 = 36kΩ, and R5 = 220Ω. Table 6-2 lists representative
dc and ac voltages for each of the foregoing troubles. Try to figure out what each
trouble is.
When you think you have it, insert the trouble in the circuit.
20. Check the dc and ac voltages to verify that you have found the trouble. Record
each trouble in Table 6-2.
DATA FOR EXPERIMENT 6

Table 6-1. Lower Critical Frequencies

Calculated
Measured
Circuit fin fout fE
fc
1

Table 6-2. Troubleshooting

DC Voltages AC Voltages
VB VE VC vb ve vc Troub
1.8V 1.1V 6V 10.4mV 0 1.14V le
0.24V 0V 10V 3.6mV 0 0
1.2V 0.57V 0.58V 1.5mV 0 0 0
5V 4.3V 4.31V 0V 0 0 0
1.38V 0.7V 0.76V 1mV 0 2mV

QUESTIONS FOR EXPERIMENT 6

1. Of the three lower critical frequencies, the dominant or most important one is the:
( )
(a) input critical frequency; (b)output critical frequency; (c) emitter bypass
critical frequency;
(d) highest of the three.
2. Which of the following usually has the largest capacitance in an amplifier in an
( )
amplifier stage like Fig. 6-1
(a) Input coupling capacitor; (b) output coupling
capacitor; (c) emitter
Bypass capacitor.
3. If any capacitor increases by a factor of 10, the critical frequency associated
( )
with this capacitor:
(a) decreases by a factor 10; (b) increases by factor of
10; (c) stays the same;
(d) none of the foregoing.
4. When C3 is 10µF, the calculated critical frequency for the emitter bypasscapacitor
( )
is closest to:
(a) 7.63 Hz; (b) 12.1 Hz; (c) 135 Hz; (d) 569 Hz.
 EXPERIMENT NO. 7
UPPER CRITICAL FREQUENCIES
__________________________________________________________________________________________

At higher frequencies the internal capacitances of an active device like a JFET or

bipolar transistor produce upper critical frequencies. With a JFET amplifier there are two
upper critical frequencies: the gate critical frequency and the drain critical frequency. With
a bipolar amplifier the two critical frequencies are the base critical frequency and the
collector critical frequency. In this experiment you will build a JFET amplifier and measure
upper critical frequencies.

REQUIRED READING
th
Chapter 16 (Secs. 16-5, to 16-13) of Electronic Principle 5 Ed by Paul Malvino

EQUIPMENT
1 audio generator
2 power supplies: 15V
1 JFET: MPF102 (or any n-channel JFET with an IDSS greater than 2mA)
5 1/2-W resistors: 100Ω, two 2.2k Ω, 10kΩ, 24kΩ
7 capacitors: three 1000pF, 0.0027µF, 0.01µF, 0.033µF, 100µF, (16-V rating or better)
1 VOM (analog or digital multimeter)
1 oscilloscope
1 frequency counter

PROCEDURE
JFET Amplifier
1. To simplify this experiment, we add large capacitors to the JFET as shown in Fig.
7-1. This brings the upper critical frequency down low enough to measure easily.
Because internal FET capacitances are normally less than 10pF, the effective values
to use in this experiment become:

Cgs = Cgd = Cds ≈ 1000pF

2. In Fig. 7-1, calculate the approximate value of rG in the gate bypass network.
Using a gm of 2000µS, calculate the capacitance CG for the gate bypass network.
Record rG and CG in table 7-1.
3. Calculate the critical bypass frequency of the gate network and record the value in
Table 7-1.
4. In Fig 7-1, what is the drain resistance rD? Record the answer in Table 7-2.
5. Calculate the capacitance CD and the critical frequency fD of the drain bypass
network. Record the values in Table 7-2.
6. Connect the JFET amplifier of Fig. 7-1.
7. Adjust the audio generator to 100Hz with a peak-to-peak input voltage of 200mV.
8. Look at the output voltage with an oscilloscope. It should be a sine wave with a
peak-to-peak voltage in the vicinity of 1V.
9. Measure the rms output voltage with a VOM.
10. The gate bypass network is dominant (see Tables 7-1 and 7-2). The critical
frequency of the gate lag network should be in the vicinity of the fG in Table 7-1.
Find the actual frequency by locating the frequency where the voltage gain is down
to 0. 707 of its value at 100Hz. Record this critical frequency in Table 7-3.
11. Short out the 10-kΩ resistor. This removes the gate bypass network. Find the
critical frequency of the drain
bypass network by increasing the frequency until the output voltage is down to
0.707 of its value at 100Hz. Record the value of fD for the drain bypass network in
Table 7-3.

+15V
 R3
2.2k
Ω
VOUT
C2
1000
pF

R2 C3
1000pF
MPF
10kΩ 102

200mV R
C1
AC 1
V 1000pF
10
Ω I
N

+ C
R4 4
100µF
2.2kΩ

Figure 7 - 1

Troubleshooting (Optional)

12. Suppose the circuit of Fig. 7-1 has an upper critical frequency in the vicinity of 1
kHz. Assume this trouble is being caused by a component of incorrect size. Try to
locate four troubles that produce this symptom. Insert each trouble in the circuit
and verify that the critical frequency is in the vicinity of 1 kHz. Record each
trouble in Table 7-4.
DATA FOR EXPERIMENT 7

Table 7-1. Gate Bypass Network

r G CG f G

Table 7-2. Drain Bypass Network

r D = CD = f D =

Table 7-3. Measured Critical Frequencies

fG
fD

Table 7-4. Troubleshooting

Number Trouble
1
2
3
4

QUESTIONS FOR EXPERIMENT 7

1. Of the two upper critical frequencies, the dominant or most important one is the: (
)
(a) lower of the two; (b)drain critical frequency;(c) 1source bypass crit- ical
frequency;
(d) higher of the two.
2. The gate critical frequency was closest to:: ( )
(a) 2.49 kHz; (b) 36.2kHz; (c) 45kHz; (d) 67 kHz.
3. In this experiment which of the following was the dominant critical frequency?: (
)
(a) source critical frequency; (b) gate critical frequency;
(c) drain critical frequency;
(d) none of the foregoing.
4. If the value gain is 4.4, the Miller input capacitance of Fig. 7-1 is: ( )
(a) 1000pF; (b) 2000pF; (c) 4400pF; (d) 5400pF.
 EXPERIMENT NO. 8
ACTIVE AND PASSIVE FILTERS
_______________________________________________________________________________________

Filters are ubiquitous in communication systems, which are used to suppress the
unwanted signals and pass the wanted signals in the frequency domain. Whether the signal
pass through or not depends on the frequency characteristics of the signal, therefore filters
can be separated into low-pass filter (LPF), high- pass filter (HPF), bandpass filter (BPF), and
band-reject filter. Butterworth filter is also knows as maximally fat filter since no ripple is
permitted in its passband. Chebyshev filter is also known as ripple filter since the ripple is
equally in its passband.

REQUIRED READING
th
Chapter 15 of Electronic Devices : Conventional Current Version 8 Ed by Thomas L. Floyd

EQUIPMENT

1 ETEK CE-2002-00
1 ETEK CE-2002-01
1 oscilloscope
1 frequency counter
1 function generator Banana plugs Jumpers

PROCEDURE

Second order passive low – pass filter

1. To implement a second order passive low – pass filter with R = 15kΩ as shown in figure
8 – 3 refer ti
figure CE1–1(a) on ETEK CE–2002–01 module.
2. Setting the input amplitude to 1V and frequency to 10 Hz sine wave. Then observe the
output signal by oscilloscope and record the amplitude in table 8- 1.
3. Input signal amplitude remains, change the frequency to 30 Hz, 50 Hz, 70 Hz, 100 Hz, 300
Hz, 500 Hz, 700
Hz, 1 kHz, 5 kHz, 7 kHz, 10 kHz. Then observe the output signal by oscilloscope and
record the amplitude in table 8 – 1.
4. Find the voltage gain of each frequency and record the result in table 8 – 1.
5. Sketch the Bode plot of each frequency and record the results in table 8 – 1.
6. To implement a second order passive low – pass filter with R = 15kΩ and C = 3.3nF as
shown in figure 8 –
3 or refer CE –1(b) on ETEK CE–2002–01 module.
7. Repeat steps 2 to 5, then observe the output signal by oscilloscope and record the output
signal in table 8 –
2 and figure 8 – 16.

Second order active low – pass filter

1. To implement a second order active low-pass filter as shown in figure 8 – 6 or refer to
figure CE1-2 on
ETEK CE-2002-01 module. Let J1 and J2 be short circuit, J3 and J4 be open circuit, i.e. C1
= C2 = 10nF.

2. Setting the input amplitude to 500mV and frequency to 10 Hz sine wav. Then observe the
output signal by oscilloscope and record the amplitude in table 8 – 3.
3. Input signal amplitude remains, change the frequency to 30 Hz, 50 Hz, 70 Hz, 100 Hz, 300
Hz, 500 Hz. 700
Hz, 1 kHz, 3 kHz, 5 kHz, 7 kHz, 10kHz. Then observe the output signal by oscilloscope
 and record the amplitude in table 8 – 3.
4. Find the voltage gain of each frequency and record the result in table 8 – 3.
5. Sketch the Bode plot of voltage gain in figure 8 – 17 by using the data in table 8 – 3.
6. Let J3 and J4 be short circuit, J1 and J2 be open circuit, i.e. change the C 1 = C2 =
10nF to C3 = C4 =
3.3nF.
7. Repeat steps 2 to 5, then observe the output signal by oscilloscope and record the output
signal in table 8 –
4 and figure 8 – 18.
Second order passive high-pass filter
1. To implement a second order passive high-pass filter with R = 15kΩ and C = 2.2nF as
shown in figure 8 –
7 or refer to figure CE1-3(a) on ETEK CE-2002-01 module.
2. Setting the input amplitude to 1V and frequency to 700 Hz sine wave. Then observe
the output signal by oscilloscope and record the amplitude in table 8 – 5.
3. Input signal amplitude remains, change the frequency to 1 kHz, 3 kHz, 5 kHz, 7 kHz,
10 kHz, 30 kHz, 50 kHz, 70 kHz, 100 kHz, 300 kHz, 500 kHz, 1000 kHz. Then observe
the output signal by oscilloscope and record the amplitude in table 8 – 5.
4. Find the voltage gain of each frequency and record the result in table 8 – 5.
5. Sketch the Bode plot voltage gain in figure 8 – 19 by using the data in table 8 – 53.
6. To implement a second order passive high-pass filter with R = 15kΩ and C = 1nF as
shown in figure 8 – 7 or refer to figure CE1-3(b) on ETEK CE-2002-01 module.
7. Repeat steps 2 to 5, then observe the output signal by oscilloscope and record the
output signal in table 8 –
6 and figure 8 – 20.

Second order active high-pass filter

1. To implement a second order active high-pass filter as shown in figure 8 – 9 or refer
to figure CE1-4 on
ETEK CE-2002-01 module. Let J1 and J2 be short circuit, J3 and J4 be open circuit, i.e.
C1 = C2 = 2.2nF
2. Setting the input amplitude to 500mV and frequency to 70 Hz sine wave. Then observe
the output signal by
oscilloscope and record the amplitude in table 8 – 7.
3. Input signal amplitude remains, change the frequency to 100 Hz, 300 Hz, 500 Hz, 700
Hz, 1 kHz, 3 kHz, 5 kHz, 7 kHz, 10 kHz, 30 kHz, 50 kHz, 100 kHz. Then observe the
output signal by oscilloscope and record the amplitude in table 8-7.
4. Find the voltage gain of each frequency and record the results in table 8-7.
5. Sketch the Bode plot of voltage gain in figure 8-21 by using the data in table 8-7.
6. Let J3 and J4 be short circuit, J1 and J2 be open circuit, i.e. change the C 1 = C2 =
2.2nF to C3 = C4 = 1nF.
7. Repeat steps 2 to 5, then observe the output signal by oscilloscope and record the
output signal in table 8 -
8 and figure 8- 22.

Second order passive bandpass filter

1. To implement a second order passive bandpass filter with R = 20Ω, L = 470µF and C
= 470nF as shown
in figure 8-11 or refer to figure CE1-5(a) on ETEK CE-2002-01 module.
2. Setting the input amplitude to 1V and frequency to 500Hz sine wave. Then observe
the output signal by oscilloscope and record the amplitude in table 8-9.
3. Input signal amplitude remains, change the frequency to 700Hz, 1kHz, 3kHz, 5kHz,
7kHz, 10kHz, 30kHz,
50kHz, 70kHz, 100kHz, 300kHz, 500kHz. Then observe the output signal by
oscilloscope and record the amplitude in table 8-9.
4. Find the voltage gain of each frequency and record the results in table 8-9.
5. Sketch the Bode plot of voltage gain in figure 8-23 by using the data in table 8-9.
6. To implement a second order passive bandpass filter with R = 120Ω, L = 250µH and C
= 10nF as shown
in figure 8-11 or refer to figure CE1-5(b) on ETEK CE-2002-01 module.
7. Repeat steps 2 to 5 then, observe the output signal by oscilloscope and record the
output signal in table 8-10 and figure 8-24.

Second order active bandpass filter

1. To implement a second order active bandpass filter as shown in figure 8-13 or refer
to figure CE1-6 on
ETEK CE-2002-01 module. Let J1 and J2 be short circuit, J3 and J4 be open circuit, i.e.
C 1 = C2 = 1nF.
2. Setting the input amplitude to 500mV and frequency to 700Hz sine wave. Then observe
the output signal by
oscilloscope and record the amplitude in table 8-11.
3. Input signal amplitude remains, change the frequency to 1 kHz, 3kHz, 5kHz, 7kHz,
10kHz, 30kHz, 50kHz,
70kHz, 100kHz, 300kHz, 500kHz, 700kHz. Then observe the output signal by
oscilloscope and record the amplitude in table 8-11.
 4. Find the voltage gain of each frequency and record the results in table 8-11.
5. Sketch the Bode plot of voltage gain in figure 8-25 by using the data in table 8-11.
6. Let J3 and J4 be short circuit, J1 and J2 be open circuit, i.e. change the C 1 = C2 = 1nF to
C3 = C4 = 3.3nF.
7. Repeat steps 2 to 5, then observe the output signal by oscilloscope and record the output
signal in table 8-
12 and figure 8-26.

QUESTIONS FOR EXPERIMENT 8

1. According to the signal selection of the filter, filters can be divided into how many types?
2. Compare Butterworth filter and Chebyshev filter.
3. Describe the advantages of using OP to design the filter.
DATA FOR EXPERIMENT 8

Table 8-1 Measured results of frequency responses of the second order passive low-
pass filter (R=15kΩ, C =
10nF).

Input
Frequenci 10 30 50 70 100 300 500 700 1k 3k 5k 7k 10k
es
(Hz)
Output
Amplitude
s
(mV)
Voltage
Gain
(dB)

Figure 8-15 Bode plot of voltage gain of second order passive low-pass filter.
Table 8-2 Measured results of frequency responses of the second order passive low-
pass filter ( R = 15kΩ, C
= 3.3nF)

Input
Frequenci 10 30 50 70 100 300 500 700 1k 3k 5k 7k 10k
es
(Hz)
Output
Amplitude
s
(mV)
Voltage
Gain
(dB)

Figure 8-16 Bode plot of voltage gain of second order passive low-pass
filter.
Table 8-3 Measured results of frequency responses of the second order active low-
pass filter ( C1 = C2 =
10nF)

Input
Frequenci 10 30 50 70 100 300 500 700 1k 3k 5k 7k 10k
es
(Hz)
Output
Amplitude
s
(mV)
Voltage
Gain
(dB)

Figure 8-17 Bode plot of voltage gain of second order active low-pass filter.
Table 8-4 Measured results of frequency responses of the second order active low-
pass filter ( C1 = C2 =
3.3nF)

Input
Frequenci 10 30 50 70 100 300 500 700 1k 3k 5k 7k 10k
es
(Hz)
Output
Amplitude
s
(mV)
Voltage
Gain
(dB)

Figure 8-18 Bode plot of voltage gain of second order active low-pass filter.
Table 8-5 Measured results of frequency responses of the second order passive high-
pass filter (R = 15kΩ, C
= 2.2nF)

Input
Frequenci 1 3 5 7 10 30 50 70 100 300 500 700 1000
es
(Hz)
Output
Amplitude
s
Voltage
Gain
(dB)

Figure 8-19 Bode plot of voltage gain of second order passive high-pass
filter.
Table 8-6 Measured results of frequency responses of the second order passive high-
pass filter (R = 15kΩ, C
= 1nF).

Input
Frequenci 1 3 5 7 10 30 50 70 100 300 500 700 1000
es
(Hz)
Output
Amplitude
s
(mV)
Voltage
Gain
(dB)

Figure 8-21 Bode plot of voltage gain of second order passive high-pass
filter.
Table 8-7 Measured results of frequency responses of the second order active high-
pass filter ( C1 = C2 =
2.2nF).

Input
Frequenci 10 30 50 70 100 300 500 700 1k 3k 5k 7k 10k
es
(Hz)
Output
Amplitude
s
(mV)
Voltage
Gain
(dB)

Figure 8-21 Bode plot of voltage gain of second order active high-pass filter.
Table 8-8 Measured results of frequency responses of the second order active low-
pass filter ( C3 = C4 =
1nF)

Input
Frequenci 10 30 50 70 100 300 500 700 1k 3k 5k 7k 10k
es
(Hz)
Output
Amplitude
s
(mV)
Voltage
Gain
(dB)

Figure 8-22 Bode plot of voltage gain of second order active high-pass filter.
 EXPERIMENT NO. 9
OSCILLATORS
______________________________________________________________________________________________

Wireless communication is widely used and expanded rapidly. RF oscillator becomes

one of the important members in wireless communications. The characteristic of oscillator
is it can produce sinusoidal wave or square wave at output terminal without any input
signal. Oscillator becomes an important role no matter for modulated signals or carrier
signals.

REQUIRED READING
th
Chapter 16 of Electronic Devices : Conventional Current Version 8 Ed by Thomas L.
Floyd

EQUIPMENT

1 ETEK CE-2002-00
1 ETEK CE-2002-02
1 oscilloscope
1 frequency counter Banana plugs Jumpers

PROCEDURE

Wien Bridge oscillator circuit

8. To implement a Wien Bridge oscillator circuit as shown in figure 9-3(a) which R2 =
R4 = 10kΩ, R1 = 2kΩ, R3 =4.7kΩ, C1 = C2 = 100pF or refer to figure CE2-1 on
ETEK CE-2002-02 module and then let J2 and J3 be short circuit, J1 and J4 be open
circuit.
9. Change the oscilloscope to AC channel, then observe on the output signal port
(O/P) of the oscillator and the positive terminal Vf of the OP amplifier. Finally,
record the signal waveforms and frequencies in table
9-1.
10. To implement a Wien Bridge oscillator circuit as shown in figure 9-4 which R2 =
R4 = 10kΩ, R1 = 2kΩ, R5
= 3.3kΩ, VR1 = 5kΩ, C1 = C2 = 100pF or refer to figure CE2-1 on ETEK CE-2002-
02 module and then let
J1 and J4 short circuit, J2 and J3 open circuit.
11. Adjust the variable resistor Vr1, so that the maximum output signal of the
oscillator can be obtained without distortion. Then, turn off the power of the
oscillator circuit and use multimeter to measure the value of VR1. Finally record
the measured results in table 9-1.
12. Repeat steps 2 and record the signal waveform and frequencies in table 9-1.

P/S: As a result of the input impedance of the probe, therefore, the probe must be
switch to position “X10”.

Phase-shift oscillator circuit

1. To implement a phase-shift oscillator circuit as shown in figure 9-6 which R1 =
R2 = R3 = 1kΩ, R4 =
2kΩ, VR1 = 100kΩ, C1 = C2 = C3 = 10nF or refer to figure CE2-2 on ETEK
CE-2002-02 module and
then let J2,J4 and J5 be short circuit, J1, J4 and J6 be open circuit.
2. Adjust the variable resistor VR1, so that the maximum output signal of the
oscillator can be obtained without distortion. Next let J4 be open circuit and
turn off the power of the oscillator circuit. Then use multimeter to measure the
value of VR1 and record the measured results in table 9-2.
3. Change the oscilloscope to AC channel, then observe on the output signal port
(O/P) of the oscillator and the positive terminal Vf of the OP amplifier. Finally,
record the signal waveforms and frequencies in table 9-2.
 4. Let J2, J3 and J5 be short circuit, J1,J4, and J6 be open circuit, then repeat
steps 2 and 3. Finally, record the signal waveforms, frequencies and VR1 in
table 9-2.
5. To implement a phase-shift oscillator circuit as shown in figure 9-7 which R1 =
R2 = R3 = 1kΩ, R4 =
2kΩ, R5 = 33kΩ, VR1 = 100kΩ, C1 = C2 = C3 = 10nF or refer to figure CE2-2
on ETEK CE-2002-02
module and then let J1, J4 and J6 be short circuit, J2, J3 and J5 be open circuit.
6. Repeat steps 2 and 3. Then record the signal waveforms, frequencies and VR 1
in table 9-3.
7. Let J1, J3 and J6 be short circuit, J2, J4 and J5 be open circuit, then repeat
steps 2 and 3. Finally,
record the signal waveforms, frequencies and VR1 in table 9-3.

Colpitts Oscillator circuit

1. To implement a Colpitts oscillator circuit as shown in figure 9-12 which L1 -
27µH, C3 = 1nF. C4 =
15nF or refer to figure CE2-3 on ETEK CE-2002-02 module and then let J1 be
short circuit, J3 and J4
be open circuit.
2. Change the oscilloscope to AC channel, then observe on the output signal port
(O/P) of the oscillator.
Then, record the signal waveforms and frequencies in table 9-4.
3. Let J3 and J4 be short circuit, J1 and J2 be open circuit, i.e. L 1 changes to L2 =
2.7µH, C3 changes to C5 = 100pF, C4 changes to C6 = 1nF, then repeat step
2. Finally, record the signal waveforms and frequencies in table 9-4.

Hartley oscillator circuit

1. To implement a Hartley oscillator circuit as shown in figure 9-14 which L1 =
68µH, L2 = 2.7µH, C3 =
100pF or refer to figure CE2-4 on ETEK CE-2002-02 module and then let J1 and
J2 be short circuit,
J3 and J4 be open circuit.
2. Change the oscilloscope to AC channel, then observe on the output signal port
(O/P) of the oscillator.
Then, record the signal waveforms and frequencies in table 9-5.
3. Let J3 and J4 be short circuit, J1 and J2 be open circuit, i.e. L 1 changes to L3 =
470µH, L2 changes to L4 = 47µH, C3 changes to C4 = 150pF, then repeat
steps 2. Finally, record the signal waveforms and frequencies in table 9-5.

Crystal controlled oscillator circuit

1. To implement a crystal controlled oscillator circuit as shown in figure 9-17
which C1 = C2 = 150pF,
X’tal = 6MHz or refer to figure CE2-5 on ETEK CE-2002-02 module and then J1
be short circuit, J2
be open circuit.
2. Change the oscilloscope to AC channel, then observe on the output port O/P of
the oscillator, Then, record the signal waveforms and frequencies in table 9-6.
3. Let J2 be short and J1 open circuit, i.e. the X’tal changes from 6MHz to 12MHz,
then repeat steps 2.
Finally, record the signal waveforms and frequencies in table 9-6.

Voltage controlled oscillator circuit

1. To implement a voltage controlled oscillator circuit a shown in figure 9-20
which C2 = C3 = 680pF, CV1 = CV2 = 1SV55, L1 = 100µH or refer to figure
CE2-6 on ETEK CE-2002-02 module.
2. Adjust the variable resistor VR1, so that the DC voltage (V1) if the varactor
diode is varied from the
 values in table 9-7.
3. Change the oscilloscope to AC channel, then observe on the output signal port
(O/P) of the oscillator.
Then record the signal frequencies in table 9-7.
4. According to the data in table 9-7, sketch the characteristics curve of
frequency versus voltage in figure 9-21.
DATA FOR EXPERIMENT 9

Table 9-1 Measured results of Wien Bridge Oscillator

Output
Signal
Waveform
(O/P)

A: Phase
Without shift:
Diode Theoretical Value:
Amplitud (fO):
e Limiter
Measured value (fO):

Feedback
Signal
Waveform
(Vf)

Output
Signal
Waveform
(O/P)

VR1: A:
Phase
With shift:
Diode Theoretical value (fO):
Amplitud
e Limiter Measured value (fO):

Feedback
Signal
Waveform
(Vf)
Table 9-2 Measured Results of phase-shift oscillator

Output
Signal
Waveform
(O/P)
VR1: A:
Phase
Without shift:
Voltage Theoretical value (fO):
Follower
Measured value (fO):

Feedback
Signal
Waveform
(Vf)

Output
Signal
Waveform
(O/P)

VR1: A:
With Phase
Voltage shift:
Follower Theoretical value (fO):

Measured value (fO):

Feedback
Signal
Waveform
(Vf)
Table 9-3 Measured results of phase-shift oscillator with capacitor as the feedback
point

Output
Signal
Waveform
(O/P)
VR1: A:
Phase
Without shift:
Voltage Theoretical value (fO):
Follower
Measured value (fO):

Feedback
Signal
Waveform
(Vf)

Output
Signal
Waveform
(O/P)

VR1: A:
Phase
Without shift:
Voltage Theoretical value (fO):
Follower
Measured value (fO):

Feedback
Signal
Waveform
(Vf)
Table 9-4 Measured results of Colpitts oscillator
The Components Output Signal Waveforms
Values
Of Resonant

L 1:
C 3:
C 4:

Theoretical value (fO):

Measured value (fO):

The Components Output Signal Waveforms

Values
Of Resonant

L 2:
C 5:
C 6:

Theoretical value (fO):

Measured value (fO):
Table 9-5 Measured results of Hartley oscillator
The Components Output Signal Waveforms
Values
Of Resonant

L 1:
L 2:
C 3:

Theoretical value (fO):

Measured value (fO):

The Components Output Signal Waveforms

Values
Of Resonant

L 3:
L 4:
C 4:

Theoretical value (fO):

Measured value (fO):
Table 9-6 Measured results of crystal oscillator
The Components Output Signal Waveforms
Values
Of Resonant Circuit

C 1:
C 2:
X’tal1:

Theoretical value (fO):

Measured value (fO):

The Components Output Signal Waveforms

Values
Of Resonant Circuit

C 1:
C 2:
X’tall2:

Theoretical value (fO):

Measured value (fO):
 Table 9-7 Measured results of voltage controlled oscillator

Input DC 3 4 5 6 7 8 9 10 11 12
Bias
(Vt)
Output
Signal
Frequency
(MHz)

Figure 9-21 Characteristic curve of frequency versus voltage

QUESTIONS FOR EXPERIMENT 9

1. Describe the condition of oscillation that the oscillator can operate in a proper
way.
2. Describe the conditions of oscillation that the Wien Bridge oscillator and
phase-shift oscillator can operate in a proper way.
3. Explain the reasons that the Wien Bridge oscillator in figure 9-4 has the function
of amplitude limited.
4. In figure 9-4 if R2 = R4 = 10kΩ, C1 = C2 = 10nF, R1 = R5 = 2kΩ, then find
the values of VR1 and the oscillation frequency in order to oscillate.
5. In figure 9-6, if R1 = R2 = R3 = 10kΩ, C1 = C2 = C3 = 10nF, R4 = 2kΩ, R5 =
33kΩ, then find the values
of VR1 and the oscillation frequency in order to oscillate.
6. Describe the conditions of oscillation that the Colpitts oscillator and Hartley
oscillator can operate in a
proper way.
7. Try to design a Hartley oscillator as shown in figure 9-14 with 5MHz outpout
frequency, then the values of C3, L1 and L2.
8. Briefy describe the advantage of crystal oscillator.
9. Briefy describe the design concepts of voltage controlled oscillators.
 EXPERIMENT NO. 10
THE 555 TIMER
_____________________________________________________________________________________

The 555 timer combines a relaxation oscillator, two comparators and an RS fip –
fop. This versatile chip can be used as an astable multivibrator, monostable multivibrator.
VCO, ramp generator, etc. In this experiment you will build and test some basic 555 timer
circuits.

REQUIRED READING
th
Chapter 22 (Secs. 21-9) of Electronic Principles 5 Ed by Paul Malvino

EQUIPMENT
1 audio generator
1 power supply: 15V
10 1/2-W resistors: two 1kΩ, 4.7kΩ, two 10kΩ, 22kΩ, 33kΩ, 47kΩ, 68kΩ, 100kΩ
1 potentiometer
4 capacitors: 0.01µF, 0.1µF, four 0.74µF
1 transistor: 2N3906
1 op amp: 741C
1 timer: NE555
1 oscilloscope
1 frequency counter

PROCEDURE

Astable 555 Timer

1. Calculate the frequency and duty cycle in Fig. 10 – 1 for the resistances listed in
Table 10 – 1. Record your
answer.
2. Connect the circuit of Fig. 10 – 1 with RA = 10kΩ and RB = 100kΩ.
3. Look at the output with an oscilloscope. Measure and record the frequency.
4. Measure W. Calculate and record the duty cycle as measured D in Table 10 – 1.
5. Look at the voltage across the timing capacitor (pin6). You should see an
exponentially rising and falling wave between 5 and 10V.
6. Repeat Steps 2 through 5 for the other resistances of Table 10 – 1.
 +15V

0.47µF

RA
4 8
7 3
VOUT
 555
RB 5
6

2 1 0.1µF

0.01µF

Figure 10 – 1

Voltage – Controlled Oscillator

7. Connect the VCO of Fig. 10 – 2.
8. Look at the output with an oscilloscope.
9. Vary the 1kΩ potentiometer and notice what happens. Measure and record the
minimum and maximum
frequencies in Table 10 – 2.

+15V
0.47µF

10kΩ 1kΩ
4 8
7 3
VOUT
555
1 1kΩ
6
00kΩ
5

2 1

1kΩ
0.01µF

Figure 10 – 2
Monostable 555 Timer
10. Figure 10 – 3 shows a Schmitt trigger driving a monostable 555 timer. Assume it
produces a normal
trigger input for the 555. Calculate and record the pulse width out of the 555 timer
for each R listed in
Table 10 – 3.
11. Connect the circuit of Fig. 10 – 3 with an R of 33kΩ.
12. Look at the output of the Schmitt trigger (pin of 6 of the 741C). Set the frequency of
the sine-wave input to 1 kHz. Adjust the sine-wave level until you get a Schmitt-
trigger output with a duty cycle of approximately 90 percent.
13. Look at the output of the 555 timer. Measure and record the pulse width.
14. Repeat Steps 11 through 13 for the remaining R values of Table 10 – 3.

+15V
0.47µF
 R
4 8

7 3 VOUT

555
6 5
+15V 0.01µ
F 2 1

0.47µF

2+ 7
6
3 -741C
4

AC 1kΩ

1kΩ 100kΩ

Figure 10 – 3

Ramp Generator
15. Figure 10 – 4 shows a ramp generator. As before, the Schmitt trigger drives a
555 timer connected for
monostable operation. But now the timing capacitor is charged by a pnp current
source rather than a resistor. For each value of R listed in Table 10 – 4, calculate
the slope of the output waveform.
16. Connect the circuit of Fig. 10 – 4 with a 10kΩ.
17. Set the ac generator to 1 kHz. Adjust the level to get a duty cycle of
approximately 90 percent out of the
Schmitt trigger.
18. Look at the output voltage; it should be a positive ramp. Measure the ramp
voltage and time. Then work out the slope. Record the value in Table 10 – 4.
19. Repeat Steps 16 to 18 for the remaining values of R (Table 10 – 4).
 +
1
R4 5
R 4.
7kΩ V
 R4
2N3906
R5
+1 10kΩ
5V C1
0.4
7µ
F
4 8
V
2+ 7
6 2
7 O
U
T
3
741C
- 4 555
R1
AC 1kΩ 5
C3
0.01µF
6
R2
1
C2
R 0.01µF
10
3 0k
1k Ω
Ω

Figure 10 - 4

Troubleshooting (Optional)

20. Assume that R equals 22kΩ in Fig. 10 – 4. Here are the symptoms: (1) no ramp
appears at the final output; (2) a normal Schmitt-trigger output drives pin 2 of the
555 timer; (3) approximately +10V appears at the base of the 2N3904. Try to
figure out what troubles (there is more than one possibility) van cause these
symptoms. Insert each suspected trouble to verify that is does cause the symptoms.
Record all the troubles you locate (Table 10 – 5).
DATA FOR EXPERIMENT 10

Table 10-1. Astable Multivibrator

Calculated Measured
RA RB f D f
D

10 kΩ 100 kΩ

100 kΩ 10 kΩ

10 kΩ 10 kΩ Table 10-2. VCO Operation fmin =

fmax =

Table 10-3. Monostable Multivibrator

R Calculated W Measured W

33 kΩ

47 kΩ

68 kΩ

Table 10-4. Ramp Generator

R Calculated Slope Measured Slope

10 kΩ

22 kΩ

33 kΩ

Table 10-5. Troubleshooting

Trouble Description

4
 EXPERIMENT NO. 11
WAVESHAPING CIRCUITS
_____________________________________________________________________________________________

By using positive feedback with a comparator, we can build a Schmitt trigger. It

has hysteresis, which makes it less sensitive to noise. A Schmitt trigger is useful for
waveshaping because it produces a square – wave output no matter what the shape of the
input signal.
If we add an RC circuit to a Schmitt trigger, we get a relaxation oscillator. This type
of circuit generates a square – wave output without an external input signal. By cascading
a relaxation oscillator and an integrator, we can build a circuit that generates square waves
and triangular waves.

REQUIRED READING
th
Chapter 21 (Secs. 21-3, to 21-6) of Electronic Principles 5 Ed.

EQUIPMENT
1 sine/square generator
2 power supplies: adjustable form 0 to 15V
8 1/2-W resistors: 100Ω, 1k Ω, two 2.2kΩ, 10kΩ,18kΩ, 22kΩ, 100kΩ
3 op amp 318C, two 741C
6 capacitors: two 0.1µF, four 0.74µF
1 oscilloscope
1 frequency counter

PROCEDURE

Schmitt Trigger
1. In Fig. 11-1, what shape do you think the output signal will have? Estimate the
peak – to – peak output
voltage. Record your answer in Table 11-1. Also calculate and record the trip points.
2. Connect the circuit. Adjust the input voltage to 1V p-p at 1 kHz.
3. Look at the output with an oscilloscope. Record the approximate shape of the
signal in Table 11-1. Also measure and record the peak – to – peak output voltage.
4. Look at the noninverting voltage with the oscilloscope on dc input. Measure the
positive peak and record this as the UTP. Measure the negative peak and record as
the LTP.

Efect of Slew – Rate Limiting

5. Increase the frequency to 20 kHz. The output should be approximately
rectangular. (Note: You may see some overshoot or ringing because of the high
slew rate of a 318C, but the transition between high and low
should still appear almost vertical.)
6. Change the frequency back to 1 kHz. Replace the 318C by a 741C. The
output should appear approximately rectangular.
7. Increase the frequency and notice how the slew rate of a 741C affects the vertical
transitions.
 +12V
0.47µF

2+ 7
8
 3 VOUT
741 0.4
-C
1V 4 7µ 22
10
p -p F k
0
1kHz AC Ω Ω
-
12V

100kΩ
1
kΩ
 Figure 11 – 1

Relaxation Oscillator and Integrator

8. In Fig. 11-2, a relaxation oscillator drivers an integrator. Calculate the frequency
out of the relacation
oscillator. Record in Table 11-2.
9. Assume +VSAT is +14V and –VSAT is -14V. Calculate and record the peak – to –
peak output voltage from the relaxation oscillator.
10. Calculate and record the peak – to – peak output voltage from the integrator.
11. Connect the circuit.
12. Look at the signal out of the relaxation oscillator. Measure its frequency and
peak – to – peak value.
Record these data.
13. Look at the signal at the inverting input of the relaxation oscillator. It should look
like Fig. 21 -23b in your textbook.
14. Look at the signal our of the integrator. Measure and record its peak – to – peak
value.

Troubleshooting (Optional)

15. For each trouble listed in table 11-3, calculate the output frequency and the
peak – to – peak output voltage in Fig. 11-2. Record your answers.
16. Insert each trouble into the circuit. Measure and record the output frequency and
peak – to – peak voltage.
 R5
100kΩ
C2
R1 0.1µF
2.2kΩ

+
+15V
0.4 15 0.47µF
7µ V
F

2+ 7 R4
8 10kΩ 2+ 7
741C 3 8
-
3 VOUT
4 0.4 741
-C 0.4
C1 7µ R6
4 7µ 22kΩ
- F
0.1µ F
F 1 -
5 15V
V

DATA FOR EXPERIMENT 11

Table 11-1. Schmitt Trigger

Calculated:

Shape : MPP : UTP : LTP :

Measured:

Shape : MPP : UTP : LTP :

Table 11-2. Relaxation Oscillator and Integrator

Calculated:

f: vout(1) : vout(2) :

Measured:

f: vout(1) : vout(2) :

Table 11-3. Troubleshooting

Calculated Measured
Trouble f vout f vout
R1 is 22kΩ R2 is 1.8 kΩ R4 is 22kΩ
REFERENCES:

Boylestead, Robert L. (2009). Electronic Devices and circuit theory (10th ed.).
Pearson Education South Asia PTE Ltd.

Boylestad, Robert L. (2006). An introduction to Electronic Devices and Circuit

Theory (9th ed.). Prentice Halll

Meade, Russell L. (2007). Foundations of Electronics. Thomson Delmar

Learning

Schultz, Mitchel E. (2007). Grob's Basic Electronics. McGraw-Hill

Gates, Earl D. (2007). Introduction to Electronics. Thomson Course

Technology

Dorf, Richard C. (2004). Introduction to Electronic Circuits. John Wiley & Sons