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D 88 12 PDF
D 88 12 PDF
ELECTRONIC SCIENCE
Signature and Name of Invigilator
1. (Signature) __________________________ OMR Sheet No. : ...............................................
(Name) ____________________________ (To be filled by the Candidate)
Paper-III 2 D-88-12
10. For IOLmax = 16 mA and IILmax = 15. Which of the ports in 8255, in which
0.0016 A, the fan-out (low) is part of the port pins can be used as
input lines and part of the port pines
(A) 16 (B) 10 can be used as output lines ?
(C) 1 (D) 1.6 (A) PA (B) PB
(C) PC (D) PD
11. Which Boolean expression describes
the output ‘X’ in the arrangement 16. Which loop structure would execute its
given below : statements atleast once even if the test
condition fails for the first time itself ?
(A) for (B) if-else
(C) do-while (D) while
23. In a low level AM system, amplifiers 29. What will be the output of K-type
following the modulated stage must be thermocouple at 100 C ?
(A) Linear devices (A) 40 V (B) 400 V
(B) Harmonic devices (C) 4000 V (D) 4 V
(C) Class C amplifier
(D) Non linear devices 30. A system is said to be stable if and
only if
(A) All poles lie on the right half of
24. Indicate the false statement. The square
S. plane.
of the thermal noise voltage generated
(B) All poles lie in the left half of the
by a resistor is proportional to
S-plane.
(A) its temperature
(C) All poles and zeros lie on the
(B) its resistance right half of S-planes.
(C) Boltzmann constant (D) Some poles lie on the half of the
(D) the bandwidth over which it is S-plane and some lie on the right
measured half of the S-plane.
25. The output of a dc motor depends 31. Which of the following is/are valid
mainly on statement(s) ?
(A) Speed and torque I. AJFET has one built-in diode.
(B) Speed and back emf II. AJFET has two built-in diode.
(C) Speed and applied voltage III. The pinch off voltage of a JFET
(D) Speed and load resistance has same magnitude as that of
gate voltage.
26. Which one of the following is an IV. A JFET is a voltage controlled
adjustable IC voltage regulator ? device.
(A) IC 7824 (B) IC 7912 (A) I, III, IV (B) II, III,IV
(C) LM 338 (D) IC 7808 (C) II, III (D) II, IV
Paper-III 4 D-88-12
32. Is it necessary to separately define Z 34. Which of the following circuit come
and Y parameters as Z can be obtained under the class of combinational logic
from Y and vice a versa ? circuits ?
I. Not necessary to define Y and Z I. Full Adder
separately as Y = 1/Z.
II. Full Subtractor
II. Necessary as Z-parameters
cannot be defined at high III. Counter
frequency. IV. Multiplexer
III. Y = 1/Z is applicable only at low (A) I and II are correct.
frequency, so conversion is not
valid under all conditions. (B) I, II, IV are correct.
IV. Hybrid -model enables Z to be (C) II, III, IV are correct.
determined using Z = 1/Y. (D) I, III and IV are correct.
(A) Options I and III are correct.
(B) Options II and IV are correct. 35. For using 8253 in counter mode from a
(C) Options III and IV are correct. initial value.
(D) Options IV and I are correct. I. The control world for selection
of counter is done.
33. Which of the following three pin II. The initial value will be kept in
regulators yield + 9 V output ? the counter before the selection
of counter.
I. III. Selection of BCD mode is done.
IV. The initial value will be loaded
to counter after the selection of
counter.
II. (A) I, III and IV are to be fulfilled.
(B) I, II and III are to be fulfilled.
(C) II, III and IV are to be fulfilled.
(D) II, I and IV are to be fulfilled.
III.
D-88-12 5 Paper-III
37. In optical fiber communications 40. During the process of milk boiling, the
I. Inter modal dispersion can be heater is to be put off before the bubble
avoided by using SMF. gets over spilled. The following controls
II. Inter modal dispersion can be are put in operation while switching off
avoided by using MMF. the heater. They are
III. Third transmission window I. Only proportional
wavelength is used to avoid II. Only integral
Rayleigh scattering losses. III. proportional and derivative
IV. 800-900 nm window is used to controls are followed.
avoid Rayleigh’s scattering
IV. Only derivative
losses.
(A) I as well as II are followed.
(A) Options II and III are correct.
(B) Options II and IV are correct. (B) I as well as IV are followed.
(C) Options I and III are correct. (C) Only III is followed.
(D) Options IV and I are correct. (D) I, II and IV are followed.
Paper-III 6 D-88-12
42. Assertion (A) : Number of mesh 48. Assertion (A) : In the super
current equations in a network heterodyne receiver, the signal
depend upon the number of voltage is combined with local
branches B and nodes N in a oscillator voltage and normally
network. converted into a signal of a lower
Reason (R) : Number of mesh current fixed frequency.
equations are B + N – 1. Reason (R) : The intermediate
frequency of receiving system may
43. Assertion (A) : Offsets in op-amp are be neither low or high, but in a
introduced due to mismatch at certain range between the two.
differential input stage. The offsets
49. Assertion (A) : PIN diodes are used
change with time and temperature.
as photo detectors. This is achieved
Reason (R) : The offsets must be by doping lightly doped in material
removed as they introduce noise in in between p and n junctions.
a.c. signals. Reason (R) : These are used because
higher frequency infra-red
44. Assertion (A) : Dual slope A/D penetrate more deeply in the
converter is the most preferred A/D semiconductor material.
conversion technique employed in
most digital multimeters. 50. Assertion (A) : Due to two metal with
Reason (R) : Dual slope A/D different coefficient of expansion,
converter provides high accuracy when the junction is formed, the
and also suppresses the HUM effect junction produces a voltage
on the input signal. corresponding to temperature.
Reason (R) : The metals which are
45. Assertion (A) : The default address, used for making thermocouples are
for starting the execution of the non homogeneous.
program, is from 0000H. This is 51. Arrange the following configurations
valid for Intel processors. of BJT in the increasing order of their
Reason (R) : The starting address of input impedance.
RAM is from 0000H. I. CE II. CB
III. CC IV. Darlington pair
46. Assertion (A) : The break; statement is (A) III, II, IV, I (B) I, II, III, IV
used to exit from if statement. (C) IV, III, II, I (D) II, I, III, IV
Reason (R) : In while (1) loop break;
statement is put at the end of a 52. The sequence to the venise a network
loop. and calculate current through the load is
(i) obtain VTH or RTH
47. Assertion (A) : Magic Tee is a 4- (ii) remove the load
junction hybrid Tee and displays (iii) put VTH and RTH in series
power dividing properties in E and (iv) connect the load in series
H plane and has advantage of being The correct sequence is
fully matched. (A) (i), (ii), (iii), (iv)
Reason (R) : It has a hybrid junction (B) (ii), (i), (iii), (iv)
about an imaginary plane bisecting (C) (iii), (i), (iv), (ii)
two arms. (D) (iv), (iii), (i), (ii)
D-88-12 7 Paper-III
53. The correct order in which data is most 57. Following are the mediums of
reliably transmitted communication :
(i) Current loop (i) sea water
(ii) V to F conversion (ii) sky waves
(iii) Voltage transmission
(iii) space waves
(iv) Digital data communication
(A) (iii), (i), (ii), (iv) (iv) glass fibers
(B) (ii), (iv), (i), (iii) The correct sequence of operating
(C) (i), (iv), (iii), (ii) frequencies in increasing order are :
(D) (iv), (iii), (ii), (i) (A) (iv), (iii), (ii), (i)
(B) (i), (ii), (iii), (iv)
54. Consider the Analog to Digital (C) (ii), (iii), (iv), (i)
convertion given below :
(D) (iv), (ii), (iii), (i)
I. Successive approximation ADC
II. Dual-slope ADC
III. Counter method ADC 58. Following are the steps for A to D
IV. Simultaneous ADC conversion of the signal :
The correct sequence of the ascending (i) Quantization
order in terms of speed of the above (ii) Sampling
ADC’s are :
(iii) Filtering
(A) I, II, III, IV (B) II, I, III, IV
(C) IV, II, I, III (D) III, II, I, IV (iv) Encoding
The correct sequence of A to D
55. The following operations are done conversion is
during the execution of an instruction : (A) (i), (ii), (iii), (iv)
(i) Decode (B) (ii), (i), (iv), (iii)
(ii) Fetch
(C) (iv), (iii), (ii), (i)
(iii) Signal transfer
(iv) Execute (D) (iii), (ii), (i), (iv)
(A) (i), (ii), (iii), (iv)
(B) (ii), (i), (iv), (iii) 59. Following are the detectors used in
(C) (iii), (i), (ii), (iv) optical communication :
(D) (ii), (i), (iii), (iv) (i) Photo diode
(ii) Photo-transistor
56. The correct sequence of hierarchy of
(iii) Avalanche photodiode
operators is _____. from highest to
lowest. (iv) Pin diode
(i) – or + (ii) ( ) Correct sequence of gain in decreasing
(iii) / or * (iv) * * order is given by
(A) (i), (iii), (iv) (A) (iii), (iv), (ii), (i)
(B) (ii), (iv), (iii) (B) (iv), (iii), (ii), (i)
(C) (ii), (iii), (i) (C) (i), (ii), (iii), (iv)
(D) (iv), (ii), (i) (D) (iv), (ii), (iii), (i)
Paper-III 8 D-88-12
60. The correct sequence to be followed to 63. Match List – I with List – II and select
build data acquisition system is by the correct answer using codes given
arranging the steps as follows : below :
(i) transducer List – I List – II
(ii) software development
a. Duty cycle 1. Variable voltage
(iii) range of parameter
regulator
(iv) signal conditioning
(A) (i), (ii), (iii), (iv) b. AGC 2. Astable
(B) (iv), (iii), (ii), (i) multivibrator
(C) (iii), (i), (iv), (ii) c. LM317 3. Voltage regulator
(D) (ii), (iii), (iv), (i) d. Crow-bar 4. FET
protection
61. Match List – I with List – II. Codes :
List – I List – II
a b c d
a. Monostable 1. No-stable state
multivibrator (A) 1 2 3 4
b. Astable 2. One-stable state (B) 3 4 1 2
multivibrator
(C) 4 3 2 1
c. Free-running 3. Two-stable state
multivibrator (D) 2 4 1 3
d. Bistable 4. Alternate high
multivibrator and low output
64. Match List – I with List – II and select
Codes :
the correct answer by using the codes
a b c d given below the lists :
(A) 2 3 1 4
(B) 3 2 4 1 List – I List – II
(C) 1 3 4 2 a. Multiplexer 1. Sequential
(D) 2 1 4 3 memory
b. De-multiplexer 2. Converts
62. Match List – I with List – II and select decimal number
the correct answer using codes given to binary
below : c. Shift-register 3. Data Selection
List – I List – II
a. Cut set 1. KVL d. Encoder 4. Routes out
many data input
b. RC-differentiator 2. Branch voltage
with single data
c. Dual of KCL 3. Frequency output
response
d. Bode plots 4. High pass filter Codes :
Codes : a b c d
a b c d (A) 3 4 1 2
(A) 2 4 1 3
(B) 4 3 1 2
(B) 3 2 4 1
(C) 4 3 1 2 (C) 3 4 2 1
(D) 1 2 4 3 (D) 1 2 3 4
D-88-12 9 Paper-III
65. Match the following lists with correct 68. Match the following :
ones : List – A List – B
List – I List – II a. Modem 1. Noise immunity better
a. QUE 1. Z flag not affected
b. FSK 2. error correction
b. DX 2. Slow memory
c. DCX D 3. Reg B c. Codes 3. frequency shift keying
d. MUL/DIV 4. Variable port d. PCM 4. signal translator
addressing Codes :
Codes : a b c d
a b c d (A) 4 3 2 1
(A) 4 2 3 1 (B) 3 2 1 4
(B) 2 4 3 1
(C) 2 1 3 4
(C) 4 2 1 3
(D) 2 4 1 3 (D) 1 4 2 3
66. Match List – I with List – II and select 69. Match List – I with List – II and select
the correct answer using codes given the correct answer using the codes
below : given below :
List – I List – II
a. if-then 1. hex-data List – I List – II
b. % x 2. garbage to calling a. Choppers 1. pn pn devices
function b. SCR 2. V number
c. gets( ) 3. on-off controller c. SMF 3. Speed control of
d. return; 4. multi word string d.c. motors
Codes : d. LASER 4. Quantum well
a b c d Codes :
(A) 3 1 4 2
a b c d
(B) 2 3 4 1
(C) 1 2 3 4 (A) 3 2 4 1
(D) 4 3 2 1 (B) 3 1 2 4
(C) 4 2 1 3
67. Match List – I with List – II and select
the correct answer using the codes (D) 4 3 2 1
given below :
List – I List – II 70. Match the following :
a. Wave –
– – D List – I List – II
equation 1. H = J + dt a. 3½ digit 1. Guarding/shielding
b.–H
E – 2. . D = b. Pt – 100 2. Bridge
c.Gauss’s Law 3. Poynting vector c. RTD 3. Temperature
d.Ampere’s Law 1 2E d. Interference 4. DVM
4. 2 = 2 E
C t2 Codes :
Codes : a b c d
a b c d (A) 1 2 3 4
(A) 4 3 2 1
(B) 4 3 2 1
(B) 3 4 2 1
(C) 1 2 3 4 (C) 3 1 4 2
(D) 4 2 3 1 (D) 3 4 1 2
Paper-III 10 D-88-12
The World’s first microprocessor, 71. Expansion of ASIC is :
(A) Applied Science Integrated
4004, was introduced by Intel in 1968. It was
Circuit.
a 4 bit processor, but later it has introduced a (B) Application Specific Integrated
new processor almost every year, like 8080, Circuit.
8085, 8086, 8031 and 8051. Only 8086 (C) Application Specific Internal
Circuit.
processor handles 16 bit data and a micro
(D) Application of Science and
computer was developed based on this Integrated Circuit.
processor. Intel also introduced 80186,
80286, 80386, 80486 and made possible to 72. 8 bit date lines is not employed by the
get mini computers and personal computers. following processor :
(A) 8080
Other companies like Texas (B) 8085
instruments, Motorola, Zilog and Analog (C) 8086
devices have specialized in signal processing (D) 8051
processors, communication oriented
73. Which one is not enhanced feature
processors, better architectural processor,
inspite of VLSI advances ?
and discrete signal processing devices. (A) Pipelining
(B) Branch prediction
All the advancements mentioned above
(C) Power consumption
are made possible because of continuous
(D) Cache
upgradation of VLSI technology. Some of
the features like cache, pipelining and branch 74. Which of the following is not signal
prediction have contributed for improving processing ?
performance parameters, like execution (A) Date filtering
speed, large memory, fast data transfers and (B) Convolution
(C) Noise addition
reduction in number of instructions. A
(D) Date storing
transformation has been seen from CISC to
RISC.
75. Expansion of RISC :
(A) Reduced Integrated Systems
Identification of application and its
Circuit
potential for marketing provides the (B) Reduced Instructions Set
opportunity to companies to produce ASICs Computer
sometimes. Digital Signal Processors are (C) Reduction Integrated System
Computer
employed for processing streamed data of
(D) Reduced Instructions System
either voice or video data. Circuit
D-88-12 11 Paper-III
Space For Rough Work
Paper-III 12 D-88-12