DRAM Memory

System: Lecture 3

Spring 2003 Memory System Organization

Bruce Jacob
David Wang Dimm1 Dimm2 Dimm3 Dimm4
University of
Maryland

Single
Channel
SDRAM
Controller

Addr & Cmd

“Mesh Topology” Data Bus
Chip (DIMM) Select
 DRAM Memory
System: Lecture 3

Spring 2003 DRAM System Organization

Bruce Jacob
David Wang
Where is the data?
University of
Maryland Rank?
CPU Bank?
Row?
Request (Read)
(Physical Address) Data Column?
(Cachline length = 64B)

Data
Magic
Memory
Controller
Command
Sequence

Rank Address = ?
Bank Address = ?
Row address = ?
Column Address ?
 DRAM Memory
System: Lecture 3

Spring 2003 Rank Part 1

Bruce Jacob
David Wang Bank Rank
University of
Maryland

Magic
Memory
Controller

It’s a “bank” of chips that responds to a

single command and returns data.

“Bank” terminology already used.

 DRAM Memory
System: Lecture 3

Spring 2003 Rank Part 2

Bruce Jacob
David Wang

University of
Maryland
Rambus RIMM
Rank Count is
Number of Devices

SDRAM
Double Sided Dimm
Two Ranks
SDRAM
Single Sided Dimm
One Rank

SDRAM/DDR SDRAM system: 4~6 ranks

RDRAM system: <= 32 ranks
 DRAM Memory
System: Lecture 3
Row, Bitlines and Wordlines

Spring 2003 Bank

Bruce Jacob Bank 2
David Wang Bank 3
Bank 1
University of
Maryland

Control Bank 0 Array

Logic Bank
(8196 0 xArray
512 x 16)
Bank
(8196 0 xArray
512 x 16)
Bank 0 Array
(8196 x 512 x 16)
(8196 x 512 x 16)

Sense Amp
Sense Amp
Sense Amp
Sense Amp

I/O Gating

“Banks” of indepedent memory arrays

inside of a DRAM Chip

SDRAM/DDR SDRAM system: 4 banks

RDRAM system: “32” split or 16 full banks
 DRAM Memory
System: Lecture 3

Spring 2003 Row and Column Revisited

Bruce Jacob
David Wang
“Column” Defined
University of
Maryland
Column: Smallest addressable quantity of DRAM on chip

SDRAM*: column size == chip data bus width (4, 8,16, 32)
RDRAM: column size != chip data bus width (128 bit fixed)

SDRAM*: get “n” columns per access. n = (1, 2, 4, 8)

RDRAM: get 1 column per access.

4 bit wide columns

#0 #1 #2 #3 #4 #5

“One Row” of DRAM

 DRAM Memory
System: Lecture 3

Spring 2003 Channel Part 1

Bruce Jacob
David Wang
Memory
DDR SDRAM
University of Controller
Maryland
Current “PC Class” memory system.
1 physical channel of DDR SDRAM

Memory DRDRAM
Controller
DRDRAM

Intel i850 DRDRAM memory system.

2 physical channel. 1 logical channel

DDR SDRAM
Memory
Controller
DDR SDRAM
Intel “Granite Bay” memory system.
2 physical channel. 1 logical channel
 DRAM Memory
System: Lecture 3

Spring 2003 Channel Part 2

Bruce Jacob
David Wang DRDRAM
University of
Maryland Memory DRDRAM
then the data is valid on the data
bus ... depending on what you
Controller
are using for in/out buffers, you DRDRAM
might be able to overlap a litttle
or a lot of the data transfer with
the next CAS to the same page DRDRAM
(this is PAGE MODE)

DRDRAM

Memory DRDRAM
Controller
DRDRAM

DRDRAM

Alpha EV7 DRDRAM memory system

8* physical channels. 2 logical channels
 DRAM Memory
System: Lecture 3

Spring 2003 Address Mapping I

Bruce Jacob
David Wang

University of CPU
Maryland
then the data is valid on the data
bus ... depending on what you Physical
are using for in/out buffers, you
might be able to overlap a litttle Address
or a lot of the data transfer with
the next CAS to the same page
(this is PAGE MODE)
Magic
Memory
Controller
Memory
Address

Variable numbers of
rank, coumn, row.
 DRAM Memory
System: Lecture 3

Spring 2003 Address Mapping II

Bruce Jacob Device config 64 Meg x 4 32 Meg x 8 16 Meg x 16
David Wang
Configuration 16 M x 4 x 4 bks 8 M x 8 x 4 bks 4 M x 16 x 4 bks
University of
Maryland row addressing 8K (A0 - A12) 8K (A0 - A12) 8K (A0 - A12)
then the data is valid on the data
bus ... depending on what you
bank addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
are using for in/out buffers, you
might be able to overlap a litttle col addressing 2K(A0-A9,A11) 1K (A0-A9) 512 (A0- A8)
or a lot of the data transfer with
the next CAS to the same page
(this is PAGE MODE)
“DRAM page size” differs
with different configurations.

8 of the x8 devices
form 64 bit wide
data bus

4 of the x16 devices

form 64 bit wide
data bus
 DRAM Memory
System: Lecture 3

Spring 2003 Address Mapping III

Bruce Jacob 32 bit physical address (byte addressable)
David Wang

University of
Maryland
then the data is valid on the data
bus ... depending on what you
are using for in/out buffers, you 31 29 28 27 26 1413 12 11 32 0
might be able to overlap a litttle
or a lot of the data transfer with
the next CAS to the same page
(this is PAGE MODE)
no rank row bank column not
memory id id id id used

Device config 16 Meg x 16

Configuration 4 M x 16 x 4 bks
row addressing 8K (A0 - A12)
bank addressing 4 (BA0, BA1)
col addressing 512 (A0- A8)

One Address Mapping Scheme for 512 M B of M em ory

 DRAM Memory
System: Lecture 3

Spring 2003 Where’s the data? Part 1

Bruce Jacob
David Wang
Read Request
University of Physical Address:
Maryland
then the data is valid on the data
0x0AC75C38
bus ... depending on what you
are using for in/out buffers, you
might be able to overlap a litttle
or a lot of the data transfer with
the next CAS to the same page
(this is PAGE MODE)

Magic
Memory
Controller Rank id = 1
Bank id = 1
32 bit physical address (byte addressable)
Row id = 0x0B1D
Column id = 0x187
31 29 28 27 26 1413 12 11 32 0

no rank row bank column not

memory id id id id used
 DRAM Memory
System: Lecture 3

Spring 2003 Where’s the data? Part 2

Bruce Jacob
David Wang
Bank id = 1
University of
Maryland Rank id = 1 Column id = 0x187
then the data is valid on the data
bus ... depending on what you
are using for in/out buffers, you
might be able to overlap a litttle Row id = 0x0B1D
or a lot of the data transfer with
the next CAS to the same page
(this is PAGE MODE)

FPM / EDO / SDRAM / etc.

 DRAM Memory
System: Lecture 3

Spring 2003 Where’s the data? Part 3

Bruce Jacob
David Wang
c1
University of
Maryland d1 d1 d1 d1
then the data is valid on the data
bus ... depending on what you
Col id Col id
are using for in/out buffers, you 0x186
might be able to overlap a litttle 0x187
or a lot of the data transfer with Col id Col id
the next CAS to the same page
(this is PAGE MODE) 0x184 0x185

Given one column address, SDRAM bursts

back “n” beats”, with critical word first.

“n” is programmable. n = 4 for 32 byte

cache line. n = 8 for 64 byte cache line.

FPM / EDO / SDRAM / etc.

 DRAM Memory
System: Lecture 3

Spring 2003 Memory Modules I

Bruce Jacob
David Wang
Bare DIP’s shoved into sockets
University of
Maryland
then the data is valid on the data
bus ... depending on what you
are using for in/out buffers, you
might be able to overlap a litttle
or a lot of the data transfer with
the next CAS to the same page
(this is PAGE MODE)

Put chips on PCB, make a module

Data Data
Address

FPM / EDO / SDRAM / etc.

 DRAM Memory
System: Lecture 3

Spring 2003 Memory Modules II

Bruce Jacob
David Wang

University of
Registered DIMM
Maryland
then the data is valid on the data
bus ... depending on what you
are using for in/out buffers, you
might be able to overlap a litttle
or a lot of the data transfer with
the next CAS to the same page
(this is PAGE MODE)

Latch
Data Data
Address

One extra cycle to buffer and distribute

address.
More chips (load) can be placed on module
 DRAM Memory
System: Lecture 3

Spring 2003 Memory Modules III

Bruce Jacob Samsung Elpida Samsung
David Wang CL2 CL3 CL2
University of
Maryland
then the data is valid on the data
bus ... depending on what you
are using for in/out buffers, you
might be able to overlap a litttle Magic
or a lot of the data transfer with Memory
the next CAS to the same page Controller
(this is PAGE MODE)

tRAS ?
tRP ?
tCL ?
Row count?
Column count?

128 Mb *4 128 Mb *8 256 Mb *4

= 64 MB = 128 MB = 128 MB

How does the system configure itself? SPD.

 DRAM Memory
System: Lecture 3

Spring 2003 SPD: Serial Presence Detect

Bruce Jacob
David Wang

University of
Maryland SPD: Tiny EEPROM
then the data is valid on the data
bus ... depending on what you
are using for in/out buffers, you Contains Parameters
might be able to overlap a litttle
or a lot of the data transfer with
the next CAS to the same page - Speed settings
(this is PAGE MODE)

- Configurations
- Programmed by
module maker
 DRAM Memory
System: Lecture 3

Spring 2003 SDRAM Chip: 54 Pin TSOP

Bruce Jacob 16M x 16
David Wang 32M x 8
64M x 4
University of VCC VCC VCC 1 54 V SS V SS VSS
Maryland DQ0 DQ0 NC 2 53 NC DQ7 DQ15
VCCQ VCCQ VCCQ 3 52 V SSQ V SSQ V SSQ
then the data is valid on the data DQ1 NC NC 4 51 NS NS DQ14
bus ... depending on what you DQ2 DQ1 DQ0 5 50 DQ3 DQ6 DQ13
are using for in/out buffers, you V SSQ V SSQ V SSQ 6 49 VCCQ VCCQ VCCQ
might be able to overlap a litttle DQ3 NC NC 7 48 NC NC DQ12
or a lot of the data transfer with DQ4 DQ2 NC 8 47 NC DQ5 D Q 11
the next CAS to the same page VCCQ VCCQ VCCQ 9 46 V SSQ V SSQ V SSQ
(this is PAGE MODE) DQ5 NC NC 10 45 NC NC DQ10
DQ6 DQ3 DQ1 11 44 DQ2 DQ4 DQ9
V SSQ V SSQ V SSQ 12 43 VCCQ VCCQ VCCQ
DQ7 NC NC 13 42 NC NC DQ8
VCC VCC VCC 14 41 V SS V SS VSS
DQML NC NC 15 40 R E S E RV E D R E S E RV E D R E S E RV E D
W E# W E# W E# 16 39 DQM DQM DQM
CAS# CAS# C A S# 17 38 CLK CLK C LK
RAS# RAS# R A S# 18 37 CLKE CLKE C LKE
CS# CS# C S# 19 36 A 14 A 14 A14
A 13 (B A 0) A 13 (B A 0) A 1 3(B A 0) 20 35 A 11 A 11 A 11
A 12 (B A 1) A 12 (B A 1) A 1 2(B A 1) 21 34 A9 A9 A9
A 10 (A P )
A 10 (A P ) A 1 0(A P ) 22 54 pin 33 A8 A8 A8
A0 A0 A0 23 32 A7 A7 A7
A1 A1 A1 24 T SO P 31 A6 A6 A6
A2 A2 A2 25 30 A5 A5 A5
A2 A2 A2 26 29 A4 A4 A4
VCC VCC VCC 27 28 V SS V SS VSS

“Same pinout”, except for DQ - data pins

 DRAM Memory
System: Lecture 3

Spring 2003 Kingston SDRAM DIMM

Bruce Jacob
David Wang

University of
Maryland 8 Chips. 128 Mbit each. (Infineon) SPD

PC133 CAS 3

Dual Inline Memory Module