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7.An8-Channel 2.1 U. Gain Mismatch Bio-Potential Recording AFE
7.An8-Channel 2.1 U. Gain Mismatch Bio-Potential Recording AFE
7.An8-Channel 2.1 U. Gain Mismatch Bio-Potential Recording AFE
04% Gain
Mismatch Bio-potential Recording AFE using Group-
Chopping Technique
Tao Tang1, Jeonghoan Park1, Lian Zhang1, Kian Ann Ng2, Jerald Yoo1,2
1
Department of Electrical and Computer Engineering, National University of Singapore, 2Singapore Institute for
Neurotechnology, Singapore
Email: elett@nus.edu.sg
F3 C3
I. INTRODUCTION FP1 InN
Correct result for
F7
T3
OutN=AN' ×(InN-Ref) FP1-F7 :
AN
Multichannel bio-potential recording amplifier is an A1
Ref
essential tool for healthcare diagnosis and biomedical research Group Chopping
[1]-[5]. Gain mismatch across channels for such amplifier often Instrumentation Amplifier (GCIA)
MUX
LPF ADC DOUT
In5P NM1 NM2
In5N A5 PM4 PM5
In6P
LPF NM3 NM4
In6N A6 VCM
LPF
In7P A7
In7N
LPF
In8P A8 GND
In8N
CPA CPB CPC CPD CPD CPC CPB CPA
Fig. 4. Schematic of RC-free open loop amplifier.
Digital Control
ɸ1 ɸ2 ɸ3 ɸ4 ɸ5 ɸ6 ɸ7 ɸ8
Fig. 2. Proposed 8-channel Bio-potential Recording AFE with GCIA CPD
CPC
where Gn and Gm are the gain of channel n and m, suppose gain CPB
mismatch is presented as α = Gn/Gm, then the worst case for
CPA
between-channel CMRR (CMRRbtw-chn-worst):
ଵାςಿ
భ ሺଵାఈ ሻ
500ns 500ns 500ns Non-overlapping
ܴܴܯܥ௧௪ିି௪௦௧ ൌ ʹͲ݈ ݃൬ ൰ (2) (a)
clock edges
ଶ൫ςಿ
భ ሺଵାఈ ሻିଵ൯
Output with overlapping clocks Output with 8-nonoverlapping clocks
Based on equation (2), for 1% (1000 ppm) gain mismatch 250 250
Amplitude (mV)
Amplitude (mV) 1.1 mV
A2
CSD
Out2P
Out2N
In2P
In2N
CSD A1
A2
CSD
Out2P
Out2N
clock signals.
In3P A3 Out3P In3P A3 Out3P
In3N Out3N In3N Out3N
A4 A4
In4P Out4P In4P Out4P
In4N
In5P
In5N A5
Out4N
Out5P
Out5N
In4N
In5P
In5N A5
Out4N
Out5P
Out5N
8 Group-Chopping Instrumentation Amplifiers (GCIA), low-
In6P
In6N
In7P
A6
A7
Out6P
Out6N
Out7P
In6P
In6N
In7P
A6
A7
Out6P
Out6N
Out7P
pass filters, an 8-to-1 mux and a 10-bit SAR-ADC. There are 4
In7N
In8P
In8N
A8
Out7N
Out8P
Out8N
In7N
In8P
In8N
A8
Out7N
Out8P
Out8N
levels of chopper switches, CSA~CSD, where CSA is for internal
Phase: ɸ3
CSA CSB
CSC
A3 used
CSC
CSB CSA
Phase: ɸ4
CSA CSB
CSC
A4 used
CSC
CSB CSA
chopping within each channel to suppression dynamic offset
In1P Out1P In1P Out1P
In1N
In2P
In2N
CSD A1
A2
CSD Out1N
Out2P
Out2N
In1N
In2P
In2N
CSD A1
A2
CSD Out1N
Out2P
Out2N
(such as 1/f noise), while CSB~CSD are for channel-swapping
In3P
In3N
A3
A4
Out3P
Out3N
Out4P
In3P
In3N
A3
A4
Out3P
Out3N
Out4P
between two adjacent group of channels. The clocks for
In4P In4P
In4N
In5P
In5N A5
Out4N
Out5P
Out5N
In4N
In5P
In5N A5
Out4N
Out5P
Out5N
CSA~CSD are designated CLKA~CLKD respectively and they
In6P
In6N
In7P
A6
A7
Out6P
Out6N
Out7P
In6P
In6N
In7P
A6
A7
Out6P
Out6N
Out7P
have frequencies of 4 kHz, 2 kHz, 1 kHz and 500 Hz,
In7N Out7N In7N Out7N
In8P
In8N
A8
Out8P
Out8N
In8P
In8N
A8
Out8P
Out8N
respectively. The control strategy is to ensure that every
Phase: ɸ5
In1P
CSA CSB
CSC
A5 used CSC
CSB CSA
Out1P
Phase: ɸ6
In1P
CSA CSB
CSC
A6 used CSC
CSB CSA
Out1P
differential input signal is modulated and dynamically swapped
In1N
In2P
In2N
CSD A1
A2
CSD Out1N
Out2P
Out2N
In1N
In2P
In2N
CSD A1
A2
CSD Out1N
Out2P
Out2N
amongst all 8 channels, so that each input signal will be
In3P
In3N
In4P
A3
A4
Out3P
Out3N
Out4P
In3P
In3N
In4P
A3
A4
Out3P
Out3N
Out4P
sequentially amplified by all GCIAs and the final amplified
In4N
In5P
In5N A5
Out4N
Out5P
Out5N
In4N
In5P
In5N A5
Out4N
Out5P
Out5N output is the averaged result of all GCIAs. Fig. 3 shows the
In6P
In6N
In7P
A6
A7
Out6P
Out6N
Out7P
Out7N
In6P
In6N
In7P
A6
A7
Out6P
Out6N
Out7P
Out7N
signal flow path during each phase, taking channel 1 as an
In7N In7N
In8P
In8N
A8
Out8P
Out8N
In8P
In8N
A8
Out8P
Out8N example: during phase 1 (φ1), channel 1 input (IN1P, IN1N) is
Phase:
CS
In1P
CS
ɸ7
A B
CSC
A7 used
CSC
CSB CSA
Out1P
Phase:
CS
In1P
CS
ɸ8
A B
CSC
A8 used
CSC
CSB CSA
Out1P
modulated by CSA and routed to A1 while CSB~CSD routes A1’s
Out1N Out1N
In1N
In2P
In2N
CSD A1
A2
CSD
Out2P
Out2N
In1N
In2P
In2N
CSD A1
A2
CSD
Out2P
Out2N
output to the demodulator (CSA) before (OUT1P, OUT1N). In the
In3P
In3N
In4P
A3
A4
Out3P
Out3N
Out4P
In3P
In3N
In4P
A3
A4
Out3P
Out3N
Out4P
next phase (φ2), (IN1P, IN1N) are swapped (group chopped) with
In4N Out4N In4N Out4N
In5P
In5N A5
Out5P
Out5N
In5P
In5N A5
Out5P
Out5N channel 2 input (IN2P, IN2N) using CSB. As a result, channel 1’s
In6P Out6P In6P Out6P
In6N
In7P
In7N
A6
A7
Out6N
Out7P
Out7N
In6N
In7P
In7N
A6
A7
Out6N
Out7P
Out7N
input is routed to A2 for amplification during φ2 while CSC and
In8P
In8N
A8
Out8P
Out8N
In8P
In8N
A8
Out8P
Out8N CSD routes A2‘s output to the demodulator (CSA) before (OUT1P,
Fig. 3. The Channel 1’s view showing signal flow path during each OUT1N). (IN1P, IN1N) would be sequentially routed to the
clock phase using group chopping technique. remaining GCIAs for the remaining phases (φ3 -φ8) but each
GCIA’s output is always routed to the same demodulator before
II. CIRCUIT IMPLEMENTATION (OUT1P, OUT1N). Note that as channel 1 is sequentially routed
to A1-A8, the other channel inputs are also routed to A1-A8 but
Fig. 2 shows the system diagram of the proposed 8-channel at different phases. Collectively, this group chopping technique
group-chopping bio-potential recording AFE, which consist of sequentially cycle (at different instances) all inputs through each
of the eight GCIAs during phases φ1 to φ8. while the amplified
outputs of A1-A8 are averaged after demodulation at the same
830μm
320μm 0.04
0.03 Eyes look up
416μm
490μm
MUX
8-channel
LPF SAR ADC 0.02
Amplitude (V)
GCIA Eyes look down
0.01
0.00
Digital -0.01
-0.02
Fig. 6. Die Photo of the proposed GCIA.
-0.03
-0.04
0 2 4 6
55 Time (Second)
Fig. 9. Measured EOG signal with eyes looking up/down
50.7dB
50
-40
Gain (dB)
0.1Hz – 220 Hz
Eyes closed
-60
Magnitude (dB)
45
-80
-100
40
0.1 1 10 100 Eyes open
-120
Frequency (Hz)
Fig. 7. AC response of the proposed GCIA 5 10 15 20 25
Frequency (Hz)
Fig. 10. Spectrum of measured EEG signal with eyes open/closed
10-6
Noise density (V/sqrt(Hz))
0
Output Power Spectrum (dBV)
-40
10-7
-60
39nV/sqrt(Hz) -80
-100
10-8
0.1 1 10 100 -120
20 40 60 80 100
Frequency (Hz) Frequency (Hz)
Fig. 8. Input-referred noise of the proposed GCIA Fig. 11. Measured crosstalk between two channels
50.70
capacitors have been used in front of all choppers to ensure rail-
45
to-rail DC offset tolerance.
50.68
efficiency, an open-loop structure is now a viable choice as Performance summary is shown in Table I. With the group
inter-channel gain variance can be averaged out using the chopping technique, the present work is the first to explore gain
proposed technique. The open-loop gain amplifier shown in Fig. matching technique for more than two-channel applications and
4 is used as the GCIA in the proposed design, and only consumes achieves the minimum gain mismatch of less than 400 ppm
2.1µW while occupying 0.017 mm2 (per channel). The current- among all multi-channel IAs reported so far. The GCIA achieves
reuse technique is employed at the input stage to obtain high an optimal NEF of 2.1 and occupies the smallest area of 0.017
transconductance to reduce the thermal noise floor with mm2/ch compared with other works and consumes 2.1µW with
minimum current consumption. The two input transistor pairs a PSD of 39nV/ĜHz.
(PM1/NM1 and PM2/NM2) are biased in weak inversion region
to maximize the transconductance efficiency. Transistors NM3
IV. CONCLUSION
and NM4 provide common-mode feedback to fix the output DC
level, while two PMOS transistors (PM4 and PM5) are chosen as This paper has presented a novel technique as group
pseudo-resistor to set the DC bias for the inputs. The control chopping to minimize the gain mismatch for multi-channel
signals for GCIAs are shown in Fig. 5 (a), to avoid large ripples applications. An 8-channel bio-potential recording AFE has
appearing in the final output, the digital logic unit adopts the 8- been fabricated and achieved less than 0.04% gain mismatch
phase overlapping-free clocking scheme for all the with only 0.017 mm2 area consumption for each channel.
complimentary control clocks, which ensures there is 500 ns
delay for adjacent clock edges. Consequently, output ripple ACKNOWLEDGMENT
voltage is reduced by 45% as depicted(simulated) in Fig. 5 (b).
The work was funded by National University of Singapore
(NUS) Hybrid-Integrated Flexible Electronic Systems (HiFES)
III. MEASUREMENT RESULTS Program.
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design is 50.7 dB from 0.1 Hz to 220 Hz as shown in Figure 7. 2006.
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Hz, which indicates as alpha wave activity when eyes are closed classification and recording processor,” IEEE Journal of Solid-State
Circuits, vol. 48, no. 1, pp. 214-228, Jan. 2013.
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[5] M. Altaf, J Yoo, “A 1.83 μJ/Classification, 8-Channel, Patient-Specific
crosstalk has been measured and shown in Fig. 11. A sine wave Epileptic Seizure Classification SoC Using a Non-Linear Support Vector
signal has been sent to channel 1 and check the output spectrum Machine,” IEEE Trans. Biomedical Circuits and Systems, vol. 10, no. 1,
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40 Hz) are chosen to verify the gain mismatch among 8 [7] Yi-Lin Tsai, Feng-Wen Lee, Tzu-Ying Chen, Tsung-Hsien Lin, “A 2-
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