UNIT-4

DC to AC Converters
1.0 Voltage Source Inverters
We will be able to:

(i) Identification of the essential components of a voltage source inverter.

(ii) The principle behind dc to ac conversion.
(iii) Identification of the basic topology of single-phase and three-phase inverters
and explanation of its principle of operation.
(iv) The gate drives circuit requirements of inverter switches.

1.1 Introduction
The word ‘inverter’ in the context of power-electronics denotes a class of power conversion (or
power conditioning) circuits that operates from a dc voltage source or a dc current source and
converts it into ac voltage or current. The ‘inverter’ does reverse of what ac- to-dc ‘converter’
does (refer to ac to dc converters). Even though input to an inverter circuit is a dc source, it is
not uncommon to have this dc derived from an ac source such as utility ac supply. Thus, for
example, the primary source of input power may be utility ac voltage supply that is ‘converted’
to dc by an ac to dc converter and then ‘inverted’ back to ac using an inverter. Here, the final ac
output may be of a different frequency and magnitude than the input ac of the utility supply.

[The nomenclature ‘inverter’ is sometimes also used for ac to dc converter circuits if the
power flow direction is from dc to ac side. However in this lesson, irrespective of power
flow direction, ‘inverter’ is referred as a circuit that operates from a stiff dc source and
generates ac output. If the input dc is a voltage source, the inverter is called a voltage
source inverter (VSI) . One can similarly think of a current source inverter (CSI), where
the input to the circuit is a current source. The VSI circuit has direct control over ‘output
(ac) voltage’ whereas the CSI directly controls ‘output (ac) current’. Shape of voltage
waveforms output by an ideal VSI should be independent of load connected at the output.]

The simplest dc voltage source for a VSI may be a battery bank, which may consist of several
cells in series-parallel combination. Solar photovoltaic cells can be another dc voltage source. An
ac voltage supply, after rectification into dc will also qualify as a dc voltage source. A voltage
source is called stiff, if the source voltage magnitude does not depend on load connected to it.
All voltage source inverters assume stiff voltage supply at the input.

Some examples where voltage source inverters are used are: uninterruptible power supply (UPS)
units, adjustable speed drives (ASD) for ac motors, electronic frequency changer circuits etc.
Most of us are also familiar with commercially available inverter units used in homes and offices
to power some essential ac loads in case the utility ac supply gets interrupted. In such inverter
units, battery supply is used as the input dc voltage source and the inverter circuit converts the dc
into ac voltage of desired frequency. The achievable magnitude of ac voltage is limited by the
magnitude of input (dc bus) voltage. In ordinary household inverters the battery voltage may be
just 12 volts and the inverter circuit may be capable of supplying ac voltage of around 10 volts
(rms) only. In such cases the inverter output voltage is stepped up using a transformer to meet the
load requirement of, say, 230 volts.
How to Get AC Output From DC Input Supply?
Figs. 33.1(a) and 33.1(b) show two schematic circuits, using transistor-switches, for generation
of ac voltage from dc input supply. In both the circuits, the transistors work in common emitter
configuration and are interconnected in push-pull manner. In order to have a single control signal
for the transistor switches, one transistor is of n-p-n type and the other of p-n-p type and their
emitters and bases are shorted as shown in the figures. Both circuits require a symmetrical
bipolar dc supply. Collector of n-p-n transistor is connected to positive dc supply (+E) and that
of p- n-p transistor is connected to negative dc supply of same magnitude (-E). Load, which has
been assumed resistive, is connected between the emitter shorting point and the power supply
ground.

In Fig. 33.1(a), the transistors work in active (amplifier) mode and a sinusoidal control voltage of
desired frequency is applied between the base and emitter points. When applied base signal is
positive, the p-n-p transistor is reverse biased and the n -p-n transistor conducts the load current.
Similarly for negative base voltage the p-n-p transistor conducts while n-p-n transistor remains
reverse biased. A suitable resistor in series with the base signal will limit the base current and
keep it sinusoidal provided the applied (sinusoidal) base signal magnitude is much higher than
the base to emitter conduction-voltage drop. Under the assumption of constant gain (hfe) of the
transistor over its working range, the load current can be seen to follow the applied base signal.
Fig. 33.2(a) shows a typical load voltage (in blue color) and base signal (green color) waveforms.
This particular figure also shows the switch power loss for n-p-n transistor (in brown color). The
other transistor will also be dissipating identical power during its conduction. The quantities in
Fig. 33.2(a) are in per unit magnitudes where the base values are input supply voltage (E) and the
2
load resistance (R). Accordingly the base magnitudes of current and power are E/R and E /R
respectively. As can be seen, the power loss in switches is a considerable portion of circuit’s
input power and hence such circuits are unacceptable for large output power applications.

As against the amplifier circuit of Fig. 33.1(a), the circuit of Fig. 33.1(b) works in switched
mode. The conducting switch remains fully on having negligible on-state voltage drop and the
non-conducting switch remains fully off allowing no leakage current through it. The load voltage
waveform output by switched-mode circuit of Fig. 33.1(b) is rectangular with magnitude +E
when the n-p-n transistor is on and –E when p-n-p transistor is on. Fig. 33.2(b) shows one such
waveform (in pink color). The on and off durations of the two transistors are controlled so that (i)
the resulting rectangular waveform has no dc component (ii) has a fundamental (sinusoidal)
component of desired frequency and magnitude and (iii) the frequencies of unwanted harmonic
voltages are much higher than that of the fundamental component. The fundamental sine wave in
Fig. 33.2(b), shown in blue color, is identical to the sinusoidal output voltage of Fig. 33.2(a).

Both amplifier mode and switched mode circuits of Figs. 33.1(a) and 33.1(b) are capable of
producing ac voltages of controllable magnitude and frequency, however, the amplifier circuit is
not acceptable in power-electronic applications due to high switch power loss. On the other hand,
the switched mode circuit generates significant amount of unwanted harmonic voltages along
with the desired fundamental frequency voltage. As will be shown in some later lessons, the
frequency spectrum of these unwanted harmonics can be shifted towards high frequency by
adopting proper switching pattern. These high frequency voltage harmonics can easily be
blocked using small size filter and the resulting quality of load voltage can be made acceptable.
 +E

* LOAD (R)
+E S

S * LOAD (R)
-E
Fig. 33.1 (b): A push-pull
switched mode circuit

-E
Fig. 33.1 (a): A push-pull
active amplifier circuit
The magnitude, phase and frequency of the fundamental voltage waveform in Fig. 33.2(b) is
solely determined by the magnitude of supply voltage and the switching pattern of the push-pull
circuit shown in Fig. 33.1(b). Thus, as long as the transistors work in the switch-mode (fully on
or fully off), the output voltage is essentially load-independent.

1.3 What If The Load Is Not Resistive?

Circuit of Fig. 33.1(b) will not be able to output proper voltage waveform for a non-resistive load
for the reasons mentioned below.

Transistors used in the circuit of Fig. 33.1(b) are meant to carry only unidirectional current (from
collector to emitter) and thus if the upper (n-p-n) transistor is on, the current must enter the star
(*) marked terminal of the load and this same terminal will get connected to the positive dc
supply (+E), other load terminal being at ground potential. When n-p-n transistor turns off and p-
n-p type turns on, the load voltage and current polarities reverse simultaneously (p-n-p transistor
can only carry current coming out of star marked end of load). Such one to one matching
between the instantaneous polarities of load voltage and load current can be achieved only in
purely resistive loads. For a general load the instantaneous current polarity may be different from
instantaneous load-voltage polarity. As pointed out in section 33.1, the inverter switching-pattern
fixes the output waveform irrespective of the load. Thus the magnitude, phase and frequency of
the fundamental voltage output by a VSI is independent of the nature of load. Thus it turns out
that for a non-resistive load the switches in the circuit of Fig. 33.1(b) should be able to carry bi-
directional current and at the same time be controllable. [A mechanical switch realized using
an electromagnetic contactor is one example of the bi-directional current carrying
controllable switch. However electromagnetic contactors are not capable of operating at
high frequency, in the range of kilohertz, and may not be suitable for present application.]
If an anti-parallel diode is connected across each transistor switch, as shown in Fig. 33.3(a), the
combination can conduct a bi-directional current. Now the transistor in anti-parallel with the
diode may be considered as a single switch. [A major difference exists between this bi-
directional electronic switch and a bi -directional current carrying mechanical switch. The
mechanical switch can be subjected to bi-directional voltage. When off, the mechanical
switch can block both positive and negative voltage across its terminals. The electronic
switch of Fig. 33.3(a) can block only one polarity of voltage, the one that keeps the diode
reverse biased. Under this polarity of voltage the switch can remain off as long as the base
(or the gate) terminal is not given the turn-on signal. When applied voltage polarity is
reversed the diode starts conducting and so the switch is not able to block the flow of
reverse current.] In spite of unidirectional voltage blocking capability, the new electronic
switch (similar to the one shown in Fig. 33.3(a)) suffices for the inverter application as pointed
out in the following paragraphs.
The push-pull circuit operation is now revisited using bi-directional current carrying switches.
The modified circuit is shown in Fig. 33.3(b). It may be noted that both IGBT and BJT type
transistors, when bypassed by anti-parallel diode, qualify as bi-directional current carrying
switches. However, IGBT switch is controlled by gate voltage whereas the BJT
 +E
Input /
SW1
Output
+ LOAD
Gate Analogous to
(control) Control S

_ SW2
Input /
Output -E
Fig. 33.3(a): Bi-directional controlled Fig. 33.3 (b): Modified push-pull circuit
switch
switch is controlled using base current. [IGBT switches are easier to use, are much faster and
are available in higher voltage and current ratings. As a result BJT switches are becoming
obsolete.] In the circuit of Fig. 33.3(b), n -p-n transistor (Q1) together with diode (D1)
constitutes the upper switch (SW1). Similarly lower switch (SW2) consists of p-n-p transistor
(Q2) in anti-parallel with diode (D2). By applying positive base-to-emitter voltage of suitable
magnitude to transistor ‘Q1’, the upper switch is turned on. Once the upper switch (diode ‘D1’or
transistor ‘Q1’) is conducting star end of load is at ‘+E’ potential and diode ‘D2’ of lower switch
gets reverse biased. Transistor ‘Q2’ is also reverse biased due to application of positive base
voltage to the transistors. Thus while switch ‘SW1’is conducting current, switch ‘SW2’ is off and
is blocking voltage of magnitude ‘2E’. Similarly when applied base voltage to the transistors is
made negative, ‘Q1’ is reverse biased and ‘Q2 ’ is forward biased. This results in ‘SW1’ turning
off and ‘SW2’ turning on. Now ‘SW1’ blocks a voltage of magnitude ‘2E’.

It may be interesting to see how diodes follow the switching command given to the transistor
part of the switches. To illustrate this point some details of circuit operation with an inductive
load, consisting of a resistor and an inductor in series, is considered. As is well known, current
through such loads cannot change abruptly. The electrical inertial time constant of the load,
given by its L (inductance) / R (resistance) ratio, may in general be large compared to the chosen
switching time period of the transistor switches. Thus the transistors ‘Q1’ and ‘Q2’ may turn-on
and turn-off several times before the load current direction changes. Let us consider the time
instant when instantaneous load current is entering the star end of the load in Fig. 33.3(b). Now
with the assumed load current direction when ‘Q1’ is given turn-on signal current flows from
positive dc supply, through transistor ‘Q1’, to load. Next, when ‘Q1’ is turned- off and ‘Q2’ is
turned on (but load current direction remaining unchanged) the load current finds its path
through diode of lower switch (D2). Whether ‘D2’ or ‘Q2’ conducts, voltage drop across ‘SW2’
is virtually zero and it can be considered as a closed or a fully-on switch. In the following
switching cycle when ‘Q1’ is turned on again (load current direction still unchanged) the load
current path reverts back from ‘D2 ’ to ‘Q1’. It may not be difficult to see how this happens.
While current flowed through ‘D2’ the load circuit got connected to negative emf (-E) of the
supply. When ‘Q1’ conducts the positive (+E) emf supports the load current. The natural choice
for load current is to move from ‘D2’ to ‘Q1’. In fact turning on of ‘Q1’ will make ‘D2’ reverse
biased. The reader may repeat a similar exercise when the instantaneous load current comes out
of the star end of load. Thus it will be evident that diodes do not need a separate command to
turn on and off. Irrespective of the load current direction, turning on of ‘Q1’ makes ‘SW1’ on and
similarly turning off of ‘Q1’ (with simultaneous turn-on of ‘Q2’) makes ‘SW2 ’on. ‘Q1’ and ‘Q2’
are turned on in a complementary manner. It may not be difficult to see that the circuit of Fig.
33.3(b) will work satisfactorily for a purely resistive load and a series connected resistor-
capacitor load too.The push-pull circuit of Fig. 33.3(b) has some technical demerits that have
been discussed below.First, it needs a bipolar dc supply with identical magnitudes of positive and
negative supply voltages. For practical reasons it would have been simpler if only one (uni-polar)
dc source was required. In fact some circuit topologies realize a bi-polar dc supply by splitting
the single dc voltage-source through capacitive potential divider arrangement. [A resistive
potential divider will be terribly inefficient.] Two identical capacitors of large magnitude are
put across the dc supply and the junction point of the capacitors is used as the neutral (ground)
point of the bi-polar dc supply. Fig. 33.3(c) shows one such circuit where a single dc supply has
been split in two halves. In such circuits the voltages across the two capacitors may not remain
exactly balanced due to mismatch in the loading patterns or mismatch in leakage currents of the
individual capacitors. Also, unless the capacitors are of very large magnitude, there may be
significant ripple in the capacitor voltages, especially at low switching frequencies. The
requirement of splitting a single dc source is eliminated if a full bridge circuit, as mentioned in
the next section, is used.

The second demerit of the push-pull circuit shown in Fig. 33.3(b) is the requirement of two
different kinds of transistors, one n-p-n type and the other p-n-p type. The switching speeds of n-
p-n and p-n-p transistors are widely different unless they are produced carefully as matched
pairs. In power electronic applications, n-p-n transistors are preferred as they can operate at
higher switching frequencies. Similarly n-channel MOSFETs and IGBTs are preferred over their
p-channel counterparts. The difficulty in using two n-p-n transistors in the above discussed push-
pull circuit is that they can no longer have a common base and a common emitter point and thus
it won’t be possible to have a single base drive signal for controlling both of them. The base
signals for the individual transistors will then need to be separate and isolated from each other.
The difficulty in providing isolated base signals for the two transistors is, often, more than
compensated by the improved capability of the circuit that uses both n-p-n transistors or n-
channel IGBTs. The circuit in Fig. 33.3(c) shows identical transistors (n-channel IGBTs) for both
upper and lower switches. The gate drive signals of the two transistors (IGBTs) now need to be
different and isolated as the two emitter points are at different potentials. The circuit in Fig.
33.3(c) is better known as a half bridge inverter.
 P

+ D1
0.5Edc Q1
_

+
Edc _ O LOAD A
+ Q2 D2
_ 0.5Edc

N
Fig. 33.3(c): Topology of a 1-phase half bridge VSI

1.4 General Structure of Voltage Source Inverters

Figs. 33.4 (a) and 33.4(b) show the typical power-circuit topologies of a single- phase and a
three-phase voltage source inverter respectively. These topologies require only a single dc source
and for medium output power applications the preferred devices are n-channel IGBTs. ‘Edc’ is
the input dc supply and a large dc link capacitor (Cdc) is put across the supply terminals.
Capacitors and switches are connected to dc bus using short leads to minimize the stray
inductance between the capacitor and the inverter switches. Needless to say that physical layout
of positive and negative bus lines is also important to limit stray inductances. Q1, Q2, Q3 etc. are
fast and controllable switches. D1, D2, D3 etc. are fast recovery diodes connected in anti-parallel
with the switches. ‘A’, ‘B’ and ‘C’ are output terminals of the inverter that get connected to the
ac load. A three- phase inverter has three load-phase terminals whereas a single-phase inverter
has only one pair of load terminals.

The current supplied by the dc bus to the inverter switches is referred as dc link current and has
been shown as ‘idc’ in Figs 33.4(a) and 33.4(b). The magnitude of dc link current often changes
in step (and some times its direction also changes) as the inverter switches are turned on and off.
The step change in instantaneous dc link current occurs even if the ac load at the inverter output
is drawing steady power. However, average magnitude of the dc link current remains positive if
net power -flow is from dc bus to ac load. The net power-flow direction reverses if the ac load
connected to the inverter is regenerating. Under regeneration, the mean magnitude of dc link
current is negative. [The dc link current may conceptually be decomposed into its dc and ac
components. The individual roles of the ‘dc voltage source’ and the ‘dc link capacitor’ may
be clearly seen with respect to the dc and ac components of the dc link current. For the dc
component of current the capacitor acts like open circuit. As expected, under steady state,
the capacitor does not supply any dc current. The dc part of bus current is supplied solely
by the dc source. A practical dc voltage source may have some resistance as well as some
inductance in series with its internal emf. For dc component of bus current, the source
voltage appears in series with its internal resistance (effect of source inductance is not felt).
But for ac component of current, the internal dc emf of source appears as short and its
series impedance (resistance in series with inductance) appears in parallel with the dc-link
capacitor. Thus the ac component of current gets divided into these two parallel paths.
However, the high frequency component of ac current mainly flows through the capacitor,
as the capacitive impedance is lower at high frequencies. The step change in dc link current
is associated with significant amount of high frequency components of current that
essentially finds its path through the capacitor.]

For an ideal input (dc) supply, with no series impedance, the dc link capacitor does not have any
role. However a practical voltage supply may have considerable amount of output impedance.
The supply line impedance, if not bypassed by a sufficiently large dc link capacitor, may cause
considerable voltage spike at the dc bus during inverter operation. This may result in
deterioration of output voltage quality, it may also cause malfunction of the inverter switches as
the bus voltage appears across the non-conducting switches of the inverter. Also, in the absence
of dc link capacitor, the series inductance of the supply line will prevent quick build up or fall of
current through it and the circuit behaves differently from the ideal VSI where the dc voltage
supply is supposed to allow rise and fall in current as per the demand of the inverter circuit.

[It may not be possible to reduce supply line inductance below certain limit. Most dc
supplies will inherently have rather significant series inductance, for example a
conventional dc generator will have considerable armature inductance in series with the
armature emf. Similarly, if the dc supply is derived after rectifying ac voltage, the ac
supply line inductance will prevent quick change in rectifier output current. The effect of
ac line inductance is reflected on the dc side as well, unless this inductance is effectively
bypassed by the dc side capacitor. Even the connecting leads from the dc source to the
inverter dc bus may contribute significantly to the supply line inductance in case the lead
lengths are large and circuit lay out is poor. It may be mentioned here that an inductance,
in series with the dc supply, may at times be welcome. The reason being that for some types
of dc sources, like batteries, it is detrimental to carry high frequency ripple current. For
such cases it is advantageous if the dc source has some series inductance. Due to series
inductance of the source, the high frequency ripple will prefer to flow through the dc link
capacitor and thus relieve the dc source.]

The dc link capacitor should be put very close to the switches so that it provides a low
impedance path to the high frequency component of the switch currents. The capacitor itself
must be of good quality with very low equivalent series resistor (ESR) and equivalent series
inductor (ESL). The length of leads that interconnect switches and diodes to the dc bus must also
be minimum to avoid insertion of significant amount of stray inductances in the circuit. The
overall layout of the power circuit has a significant effect over the performance of the inverter
circuit.
 idc idc

Q1 D1 Q3 D3 Q1 D1 Q3 D3 Q5 D5

Edc + Cdc Edc + Cdc A B C

_ _
A LOAD B
D2 Q4 D4 D2 D4 D6
Q2 Q2 Q4 Q6

Fig. 33.4(a): Topology of a 1-phase VSI Fig. 33.4(b): Topology of a 3-phase VSI

[One of the thumb rules for good circuit layout is to put the conductor pairs carrying same
magnitude but opposite direction of currents close by, the minimum distance between them
being decided only by their voltage isolation requirement. Thus the positive and negative
terminals of the dc bus should run close by. A twisted wire pair may be an example of two
closely running wires.]
The details of the inverter circuits shown in Figs. 33.4(a) and 33.4(b) are discussed in later
lessons. However it may be mentioned here that these circuits are essentially extension of the
half bridge circuit shown in Fig. 33.3(c). For example, the single-phase bridge circuit of Fig.
33.4(a) may be thought of as two half-bridge circuits sharing the same dc bus. Thus the single
phase ‘full-bridge’ (often, simply called as ‘bridge’) circuit has two legs of switches, each leg
consisting of an upper switch and a lower switch. Junction point of the upper and lower switches
is the output point of that particular leg. Voltage between output point of legs and the mid-
potential of the dc bus is called as ‘pole voltage’ referred to the mid potential of the dc bus. One
may think of pole voltage referred to negative bus or referred to positive bus too but unless
otherwise mentioned pole voltages are assumed to be referred to the mid-potential of the dc bus.
The two pole voltages of the single-phase bridge inverter generally have same magnitude and
0
frequency but their phases are 180 apart. Thus the load connected between these two pole
outputs (between points ‘A’ and ‘B’) will have a voltage equal to twice the magnitude of the
individual pole voltage. The pole voltages of the 3-phase inverter bridge, shown in Fig. 33.4(b),
0
are phase apart by 120 each.

1.5 Need For Isolated Gate-Control Signals For The Switches

As already mentioned the switches in bridge configurations of inverters, as in Figs. 33.3(c),
33.4(a) and 33.4(b), need to be provided with isolated gate (or base) drive signals. The individual
control signal for the switches needs to be provided across the gate (base) and source (or emitter)
terminals of the particular switch. The gate control signals are low voltage signals referred to the
source (emitter) terminal of the switch. For n-channel IGBT and MOSFET switches, when gate
to source voltage is more than threshold voltage for turn-on, the switch turns on and when it is
less than threshold voltage the switch turns off. The threshold voltage is generally of the order of
+5 volts but for quicker switching the turn-on gate voltage magnitude is kept around +15 volts
where as turn-off gate voltage is zero or little negative (around –5 volts). It is to be remembered
that the two switches of an inverter-leg are controlled in a complementary manner. When the
upper switch of any leg is ‘on’, the corresponding lower switch remains ‘off’ and vice- versa.
When a switch is ‘on’ its emitter and collector terminals are virtually shorted. Thus with upper
switch ‘on’, the emitter of the upper switch is at positive dc bus potential. Similarly with lower
switch ‘on’, the emitter of upper switch of that leg is virtually at the negative dc bus potential.
Emitters of all the lower switches are solidly connected to the negative line of the dc bus. Since
gate control signals are applied with respect to the emitter terminals of the switches, the gate
voltages of all the upper switches must be floating with respect to the dc bus line potentials. This
calls for isolation between the gate control signals of upper switches and between upper and
lower switches. Only the emitters of lower switches of all the legs are at the same potential (since
all of them are solidly connected to the negative dc bus) and hence the gate control signals of
lower switches need not be isolated among themselves. As should be clear from the above
discussion, the isolation provided between upper and lower switches must withstand a peak
voltage stress equal to dc bus voltage. Gate-signal isolation for inverter switches is generally
achieved by means of optical-isolator (opto-isolator) circuits. Fig.33.5 shows a typical opto-
isolator circuit. The circuit makes use of a commercially available opto-coupler IC, shown within
dotted lines in the figure. Input stage of the IC is a light emitting diode (LED) that emits light
when forward biased. The light output of the LED falls on reverse biased junction of an optical
diode. The LED and the photo-diode are suitably positioned inside the opto-coupler chip to
ensure that the light emitted by the LED falls on the photo-diode junction. The gate control
pulses for the switch are applied to the input LED through a current limiting resistor of
appropriate magnitude. These gate pulses, generated by the gate logic circuit, are essentially in
the digital form. A high level of the gate signal may be taken as ‘on’ command and a low level
(at ground level) may be taken as ‘off’ command. Under this assumption, the cathode of the LED
is connected to the ground point of the gate-logic card and anode is fed with the logic card
output. The circuit on the output (photo-diode) side is connected to a floating dc power supply,
as shown in Fig. 33.5. The control (logic card) supply ground is isolated from the floating-supply
ground of the output. In the figure the two grounds have been shown by two different symbols.
The schematic connection shown in the figure indicates that the photo-diode is reverse biased. A
resistor in series with the diode indicates the magnitude of the reverse leakage current of the
diode. When input signal to LED is high, LED conducts and the emitted light falls on the reverse
biased p-n junction. Irradiation of light causes generation of significant number of electron-hole
pairs in the depletion region of the reverse biased diode. As a result magnitude of reverse leakage
current of the diode increases appreciably. The resistor connected in series with the photo-diode
now has higher voltage drop due to the increased leakage current. A signal comparator circuit
senses this condition and outputs a high level signal, which is amplified before being output.
Thus an isolated and amplified gate signal is obtained and may directly be connected to the gate
terminal of the switch (often a small series resistor, as suggested by the switch manufacturer, is
put between the output signal and the gate terminal of the switch).
 +VCC (floating)
Photo-diode

Signal
L comparatorand Output
E
power amplifier
D circuit

Control Floating
Ground Ground
Fig.33.5: A schematic opto-isolator circuit

1.6 Classification of Voltage Source Inverters

Voltage source inverters can be classified according to different criterions. They can be classified
according to number of phases they output. Accordingly there are single- phase or three-phase
inverters depending on whether they output single or three-phase voltages. It is also possible to
have inverters with two or five or any other number of output phases. Inverters can also be
classified according to their ability in controlling the magnitude of output parameters like,
frequency, voltage, harmonic content etc. Some inverters can output only fixed magnitude
(though variable frequency) voltages whereas some others are capable of both variable voltage,
variable frequency (VVVF) output. Output of some voltage source inverters is corrupted by
rd th th th th
significant amount of many low order harmonics like 3 , 5 , 7 , 11 , 13 order of the desired
(fundamental) frequency voltage. Some other inverters may be free from low order harmonics
but may still be corrupted by some high order harmonics. Inverters used for ac motor drive
applications are expected to have less of low order harmonics in the output voltage waveform,
even if it is at the cost of increased high order harmonics. Higher order harmonic voltage
distortions are, in most ac motor loads, filtered away by the inductive nature of the load itself.

Inverters may also be classified according to their topologies. Some inverter topologies are
suitable for low and medium voltage ratings whereas some others are more suitable for higher
voltage applications. The inverters shown in Figs. 33.3(c), 33.4(a) and 33.4(b) are two level
inverters as the pole voltages may acquire either positive dc bus or negative dc bus potential. For
higher voltage applications it may not be uncommon to have three level or five level inverters.

Question for Practice

Choose the Best Answer
1. A large capacitor, put across dc bus of a voltage source inverter, is intended to:
(a) allow a low impedance path to the high frequency component of dc link
current.
(b) to minimize high frequency current ripple through the ideal dc source.
(c) to maintain a constant dc link current.
(d) to protect against switch failure.
2. A diode in anti-parallel with the controlled switch, like IGBT, is used in VSI to:
(a) prevent reversal of dc link current.
 (b) allow a non-unity power factor load at the output.
(c) protect the circuit against accidental reversal of dc bus polarity.
(d) none of the above.
3. The inverter switches work in fully-on or fully-off mode to achieve:
(a) easier gate control circuit for the switching devices.
(b) minimum distortion in the output voltage waveform.
(c) reduced losses in the switches.
(d) satisfactory operation for non-resistive load at the output.
4. Gate (base) signals to the VSI switches, using n-channel IGBTs, need to be isolated
to allow:
(a) protection of switches against short at the inverter output terminals.
(b) switches to be connected in bridge fashion.
(c) lower losses in the gate drive circuit.
(d) a dc link voltage higher than the switch voltage rating.

Answers

1-a, 2-b, 3-c, 4-b

2.0 Analysis of 1-Phase,Square - Wave Voltage

Source Inverter
We will be able to:
• The operating principle of a single-phase square wave inverter.
• Comparison of the performance of single-phase half-bridge and full-bridge
inverters.
• Harmonic analysis of load voltage and load current output by a single-phase
inverter.
Voltage source inverters (VSI) have been introduced in Lesson-33. A single-phase square wave
type voltage source inverter produces square shaped output voltage for a single-phase load.
Such inverters have very simple control logic and the power switches need to operate at much
lower frequencies compared to switches in some other types of inverters, discussed in later
lessons. The first generation inverters, using thyristor switches, were almost invariably square
wave inverters because thyristor switches could be switched on and off only a few hundred
times in a second. In contrast, the present day switches like IGBTs are much faster and used at
switching frequencies of several kilohertz. As pointed out in Lesson-26, single-phase inverters
mostly use half bridge or full bridge topologies. Power circuits of these topologies are redrawn
in Figs. 34.1(a) and 34.1(b) for further discussions.
 P P idc
Sw1 Sw3
+ Sw1
C_ 0.5Edc
Edc
+ + Cdc
Edc _ _ A LOAD
O LOAD A
+
C_ 0.5Edc
Sw2 Sw2 Sw4
N N
Fig. 34.1(a): A 1-phase half bridge VSI Fig. 34.1(b): A 1-phase full-bridge VSI
In this lesson, both the above topologies are analyzed under the assumption of ideal circuit
conditions. Accordingly, it is assumed that the input dc voltage (Edc) is constant and the
switches are lossless. In half bridge topology the input dc voltage is split in two equal parts
through an ideal and loss-less capacitive potential divider. The half bridge topology consists of
one leg (one pole) of switches whereas the full bridge topology has two such legs. Each leg of
the inverter consists of two series connected electronic switches shown within dotted lines in
the figures. Each of these switches consists of an IGBT type controlled switch across which an
uncontrolled diode is put in anti-parallel manner. These switches are capable of conducting bi-
directional current but they need to block only one polarity of voltage. The junction point of the
switches in each leg of the inverter serves as one output point for the load.

In half bridge topology the single-phase load is connected between the mid-point of the input
dc supply and the junction point of the two switches (in Fig. 34.1(a) these points are marked as
‘O’ and ‘A’ respectively). For ease of understanding, the switches Sw1 and Sw2 may be
assumed to be controlled mechanical switches that open and close in response to the switch control
signal. In fact in lesson-33 (section 33.2) it has been shown that the actual electronic switches
mimic the function of the mechanical switches. Now, if the switches Sw1 and Sw2 are turned on
alternately with duty ratio of each switch kept equal to 0.5, the load voltage (VAO) will be square
wave with a peak- to-peak magnitude equal to input dc voltage (Edc). Fig. 34.2(a) shows a typical
load voltage waveform output by the half bridge inverter. VAO acquires a magnitude of +0.5 Edc
when Sw1 is on and the magnitude reverses to -0.5 Edc when Sw2 is turned on. Fig. 24.2 also
shows the fundamental frequency component of the square wave voltage, its peak-to-peak
4
magnitudebeing equal to π Edc . The two switches of the inverter leg are turned on in a
complementarymanner. For a general load, the switches should neither be simultaneously on
nor be simultaneously off. Simultaneous turn-on of both the switches will amount to short
circuit across the dc bus and will cause the switch currents to rise rapidly. For an inductive
load, containing an inductance in series, one of the switches must always conduct to maintain
continuity of load current. In Lesson-33 (section 33.2) a case of inductive load has been
considered and it has been shown that the load current may not change abruptly even though
the switching frequency is very high. Such a situation, as explained in lesson-33, demands that
the switches must have bi-directional current carrying capability.
+ 2.1Harmonic Analysis of The Load Voltage And Load
Current Waveforms
The load voltage waveform shown in Fig. 34.2(a) can be mathematically described in terms of its
Fourier’s components as:
2E
VAO = ∑ nπ sin(nwt) ……………………………………… (34.1)
dc

n=1,3,5,7,...,∞
w
,where ‘n’ is the harmonic order and 2π is the frequency (‘f’) of the square wave. ‘f’ also
happens to be the switching frequency of the inverter switches. As can be seen from the
expression of Eqn. 34.1, the square wave load voltage consists of all the odd harmonics and their
magnitudes are inversely proportional to their harmonic order. Accordingly, the
2
fundamentalfrequency component has a peak magnitude of π Edc and the nth harmonic voltage (n
2
being oddinteger) has a peak magnitude of n π Edc . The magnitudes of very high order harmonic
voltages become negligibly small. In most applications, only the fundamental component in load
voltage is of practical use and the other higher order harmonics are undesirable distortions. Many
of the practical loads are inductive with inherent low pass filter type characteristics. The current
waveforms in such loads have less higher order harmonic distortion than the corresponding
distortion in the square-wave voltage waveform. A simple time domain analysis of the load
current for a series connected R-L load has been presented below to corroborate this fact. Later,
for comparison, frequency domain analysis of the same load current has also been done.

2.2 Time Domain Analysis

The time domain analysis of the steady state current waveform for a R-L load has been presented
here. Under steady state the load current waveform in a particular output cycle will repeat in
successive cycles and hence only one square wave period has been considered. Let t=0 be the
instant when the positive half cycle of the square wave starts and let I0 be the load current at this
instant. The negative half cycle of square wave starts at t=0.5T and extends up to T. The circuit
equation valid during the positive half cycle of voltage can be written as below:
 di
Ri + L dt = 0.5Edc , for 0 < t < 0.5T ………………………..………….(34.2)

Similarly the equation for the negative half cycle can be written as
di
Ri + L dt = −0.5Edc , for 0.5T < t < T ………………………………….(34.3)
, where T (=1/f) is the time period of the square wave.

The instantaneous current ‘i’ during the first half of square wave may be obtained by solving
Eqn.(34.2) and putting the initial value of current as I0.
−t −t
0.5Edc τ
Accordingly, i (t) = R (1 − e ) + I 0 e τ for 0 < t < 0.5T ……………..(34.4)
, where τ= L/R is the time constant of the R-L load.

The current at the end of the positive half cycle becomes the starting current for the negative half
cycle.
−T −T
0.5Edc 2τ 2τ
Thus the next half cycle starts with an initial current = R (1− e ) + I 0 e . The
circuit equation for the next half cycle may now be written as
T T
− (t − ) − (t − )
0.5E 0.5E −T −T
i (t) = −
R
dc (1−e 2 τ )+ dc
R
(1− e 2τ )+I0e 2τ e 2 τ for 0.5T <t< T

Simplifying the above equation one gets:

T
− (t − )
−t −t 2
0.5 Edc τ
i (t) = − R (1 + e ) + I 0e τ + ERdc e τ , for 0.5T < t < T …….(34.5)
Under steady state, the instantaneous magnitude of inductive load current at the end of a periodic
cycle must equal the current at the start of the cycle. Thus putting t=T in Eqn. (34.5), one gets the
expression for I0 as,
0.5 Edc −T −T E −T
I0 =− R (1 + e τ )+I e
0 τ + R e 2τ
dc

−T τ 0.5Edc −T τ Edc −T 2τ
or, I 01 −e = (1− e )+ e −1

R R
−T
E
0.5Edc dc 1 0.5Edc 1 −e 2τ
=− ………….(34.6)
or, I0 = R − R −T 2τ R −T 2τ
1+e 1+ e

Substituting the above expression for I0 in Eqn. (34.4) one gets,

 −T 2τ
i (t) =
0.5Edc 1 + e − 2e −t τ , for 0 < t < 0.5T ………..………..(34.7)
R −T
2τ
1+e
It may be noted from Eqn. (34.7) that the load current at the end of the positive half cycle of
square wave (at t=0.5T) simply turns out to be –I0. This is expected from the symmetry of the
load voltage waveform. Load current expression for the negative half cycle of square wave can
similarly be calculated by substituting for I0 in Eqn. (34.5). Accordingly,

T
− (t − )
2
0.5E E e τ
i (t) = − dc
+ dc
, for 0.5T < t < T
R R −T
1+e 2τ

T
− (t − )
−T 2
2τ
0.5E 1+e − 2e τ
or, i (t) = − dc
, for 0.5T < t < T ............... (34.8)
R −T
1 + e 2τ

The current expressions given by Eqns. (34.7) and (34.8) have been plotted in Figs. 34.2(b) to
34.2(e) for different time constants of the R-L load. The current waveforms have been
E dc
normalized against a base current of 0.5 R . The square wave voltage waveform, normalized

against a base voltage of 0.5Edc has also been plotted together with the current waveforms. It can
be seen that the load current waveform repeats at fundamental frequency and the higher order
rd
harmonic distortions reduce as the load becomes more inductive. For L/R ratio of 2, the 3 order
harmonic distortion in the load current together with its fundamental component has been shown
in Fig. 34.2(e). In this case, it can be seen that the relative harmonic distortion in load current
waveform is much lower than that of the voltage waveform shown in Fig. 34.2(a). The basis for
calculating the magnitude of different harmonic components of load current waveform has been
shown in the next subsection that deals with frequency domain analysis.
2.3 Frequency Domain Analysis
The square shape load voltage may be taken as superposition of different harmonic voltages
described by Eqn. 34.1. The load current may similarly be taken as superposition of harmonic
currents produced by the different harmonic voltages. The load current may be expressed in
terms of these harmonic currents. To illustrate this the series connected R-L load has once again
been considered here. First the expressions for different harmonic components of load current are
calculated in terms of load parameters: R and L/R (or τ) and inverter parameters: dc link voltage
(Edc) and time period of square wave (T).
For the fundamental harmonic frequency the load impedance (Z1) and load power factor angle
(φ1) can be calculated to be

2 4π
2 2
L −1
2πL
) ……….…….(34.9)
Z1 = R +( T 2 and φ1 = tan TR th
The load impedance and load power factor angle for the n harmonic component (Zn and φn
respectively) will similarly be given by,

2 4π
2 2
n L
2 −1 2πnL
) …….…….(34.10)
Zn = R + ( T and φn = tan TR 2
th
The fundamental and n harmonic component of load current, (Iload)1 and (Iload)n respectively,
can be found to be

2E 2E
dc dc
(Iload)1 = πZ sin(wt − Φ1 ) and (Iload)n = nπZ sin(nwt −Φn ) ………(34.11)
1 n
The algebraic summation of the individual harmonic components of current will result in the
following expression for load current.

2E
I
Load
=
∑ dc
nπ Z sin(nwt − Φn ) ……………………………….(34.12)
n=1,3,5,7,...,∞ n

From Eqns. 34.10 and 34.12 it may be seen that the contribution to load current from very higher
order harmonics become negligible and hence the infinite series based expression for load
current may be terminated beyond certain values of harmonic order ‘n’. For L/R ratio = 2T, the
individual harmonic components of load current normalized against a base current of
0.5Edc
have been calculated below:

R
4 −1
(Iload)1,normalized = 2 sin(wt − tan 4π) = 0.1sin(wt −1.491)
π 1 +16π
4 −1
(Iload)3,normalized = sin(3wt − tan
12π) = 0.011sin(3wt −1.544)
2
3π 1+144π
4 −1
(Iload)5,normalized = sin(5wt − tan 20π) = 0.004sin(5wt −1.555)
2
5π 1 + 400π
4 −1
(Iload)7,normalized = sin(7wt − tan 28π) = 0.002sin(7wt −1.559)
2
7π 1 + 784π
4 −1
(Iload)11,normalized = sin(11wt − tan 44π) = 0.0008sin(11wt −1.564)
2
11π 1 +1936π
th
t may be concluded that for L/R = 2T, the contribution to load current from 13 and higher order
harmonics are less than 1% of the fundamental component and hence they may be neglected
without any significant loss of accuracy.

Fig. 34.2(f) shows the load voltage and algebraic summation of the first five dominant harmonics
rd th th th
(fundamental, 3 , 5 , 7 and 11 ) in the load current, the expressions for which have been
given above. In Fig. 34.2(g) the load current waveforms of Fig. 34.2(e) and 34.2(f) have been
superimposed for comparison. It may be seen that the load current waveform of Fig. 34.2(f)
calculated using truncated series of the frequency domain analysis very nearly matches with the
exact waveform of Fig. 34.2(e), calculated using time domain analysis.
2.4 Analysis Of The Single-Phase Full Bridge Inverter
Single-phase half bridge inverter has already been described above. The single-phase full bridge
circuit (Fig. 34.1(b)) can be thought of as two half bridge circuits sharing the same dc bus. The
full bridge circuit will have two pole-voltages (VAO and VBO), which are similar to the pole
voltage VAO of the half bridge circuit. Both VAO and VBO of the full bridge circuit are square
waves but they will, in general, have some phase difference. Fig. 34.3 shows these pole voltages
staggered in time by ‘t’ seconds. It may be more convenient to talk in terms of the phase
displacement angle ‘Φ’ defined as below:
t
Φ = (2π) T Radians.……………………………….(34.13)
1where ‘t’ is the time by which the two pole voltages are staggered and ‘T’ is the time period of
the square wave pole voltages.
The pole voltage VAO of the full bridge inverter may again be written as in Eqn. 34.1, used
earlier for the half bridge inverter. Taking the phase shift angle ‘Φ’ into account, the pole-B
voltage may be written as
2E
VBO = ∑ nπ sin n(wt −Φ) ………………………………………(34.14)
dc

n=1,3,5,7,...,∞
Difference of VAO and VBO gives the line voltage VAB. In full bridge inverter the single phase
load is connected between points ‘A’ and ‘B’ and the voltage of interest is the load voltage VAB.
Taking difference of the voltage expressions given by Eqns. 34.1 and 34.14, one gets
2E
V AB = ∑ nπ [sin nwt −sin n(wt − Φ)]………………………………………(34.15)
dc

n=1,3,5,7,...,∞
The fundamental component of VAB may be written as
2E 4E Φ Φ
V = dc dc
AB,1
th
π [sin wt − sin(wt − Φ ) ] = π cos(wt − 2 )sin 2 ……………………...(34.16)
The n harmonic component in VAB may similarly be written as
2E 4E Φ nΦ
V = dc dc
AB , n nπ [sin nwt − sin n ( wt − Φ ) ] = nπ
cos n ( wt − 2 )sin 2 ………….……(34.17)
From Eqn. 34.16, the rms magnitude of the fundamental component of load voltage may be
written as
Φ
(V AB ,1 )rms = 0.9Edc sin 2 …………………………………………...……………….(34.18)

The rms magnitude of load voltage can be changed from zero to a peak magnitude of 0.9Edc .
The peak load voltage magnitude corresponds to Φ = 180 degrees and the load voltage will be
0
zero for Φ = 0 . For Φ = 180 degrees, the load voltage waveform is once again square wave of
time period T and instantaneous magnitude E.
0
As the phase shift angle changes from zero to 180 the width of voltage pulse in the load voltage
waveform increases. Thus the fundamental voltage magnitude is controlled by pulse-width
modulation.
Also, from Eqns. 34.17 and 34.1 it may be seen that the line voltage distortion due to higher
0
order harmonics for pulse width modulated waveform (except for Φ = 180 ) is less than the
corresponding distortion in the square wave pole voltage. In fact, for some values of phase shift
angle (Φ) many of the harmonic voltage magnitudes will drastically reduce or may even get
0 rd
eliminated from the load voltage. For example, for Φ = 60 the load voltage will be free from 3
and multiples of third harmonic.
2.5 Voltage And Current Ratings Of Inverter Switches
Switches in each leg of the inverter operate in a complementary manner. When upper switch of a
leg is on the lower switch will need to block the entire dc bus voltage and vice versa. Thus the
switches must be rated to block the worst-case instantaneous magnitude of dc bus voltage. In
practical inverters the switch voltage ratings are taken to be somewhat higher than the worst-case
dc voltage to account for stray voltages produced across stray inductances, the turn-on transient
voltage of a power diode etc. For a well laid out circuit a 50% margin over the dc-bus voltage
may be the optimum switch voltage rating. Each switch of the inverter carries load current during
half of the current cycle. Hence the switches must be rated to withstand the peak magnitude of
instantaneous load current. The semiconductor switches have very small thermal time constant
and they cannot withstand overheating for more than a few milli seconds. Thus even though the
load current passes through the switches only in alternate half cycles, the thermal limit may be
reached during half cycle of current itself. It may be pointed out that each inverter switch
consists of a controlled switch in anti-parallel with a diode. The distribution of current between
the diode and the controlled switch will depend on the load power factor at the operating
frequency. In general both diode as well as the controlled switch should be rated to carry the
peak load current.

2.6 Applications Of Square Wave Inverter

The square wave voltage-source inverter discussed in this lesson finds application in many low
cost ac motor drives, uninterruptible power supply units and in circuits utilizing electrical
resonance between an inductor and a capacitor. Some examples of circuits utilizing resonance
phenomenon are induction heating units and electronic ballasts for fluorescent lamps.

Question for Practice

Choose the Best Answer

1. A single-phase full bridge inverter with square wave pole voltages is connected to a
dc input voltage of 600 volts. What maximum rms load voltage can be output by the
rd
inverter? How much will be the corresponding rms magnitude of 3 harmonic
voltage
rd
(a) Approximately 270 volts of fundamental and 30 volts of 3 harmonic voltage
rd
(b) Approx. 480 volts fundamental and 160 volts of 3 harmonic voltage
rd
(c) Approx. 540 volts fundamental and 180 volts of 3 harmonic voltage
rd
(d) Approx. 270 volts fundamental and 90 volts of 3 harmonic voltage
2. How does the output power handling capacity of a single-phase half bridge inverter
compare with that of a single-phase full bridge inverter when they are connected to
same dc bus voltage and the peak current capability of the inverter switches is also
same. Also compare their costs.
(a) The half bridge inverter can output double power but cost also doubles.
(b) The half bridge inverter can output only half the power but cost is less.
(c) The half bridge inverter can output only half the power but cost is nearly
same
(d) The output power capability is same but half bridge inverter costs less.
 3. A single-phase full bridge inverter is connected to a purely resistive load. Each
inverter switch consists of an IGBT in anti-parallel with a diode. For this load how
does the diode conduction loss compare with the IGBT conduction loss?
(a) Diode and IGBT will have nearly same conduction loss
(b) Diode conduction loss will be nearly half of the IGBT loss
(c) Diode will have no conduction loss
(d) IGBT will have no conduction loss
th th
4. Using frequency domain analysis estimate the ratio of 5 and 7 harmonic currents
in a purely inductive load that is connected to the output of a single phase half
bridge inverter with square wave pole voltages.
th th
(a) 5 harmonic current will be nearly double of the 7 harmonic current
th th
(b) 5 harmonic current will be 40% more than the 7 harmonic current
th th
(c) 5 harmonic current will be zero while 7 harmonic current will be present
th th
(d) Both 5 and 7 harmonic currents will be zero

Answer
1-d, 2-b, 3-c, 4-a

3.0 3-Phase Voltage Source Inverter With Square

Wave Output
We will be able to:
• The operating principle of a three-phase square wave inverter.
• The limitations and advantages of square-wave inverters.
• Harmonic analysis of load voltage and load current output by the three-
phase sq. wave inverter.

The basic configuration of a Voltage Source Inverter (VSI) has been described in Lesson 33.
Single-phase half-bridge and full-bridge configurations of VSI with square wave pole voltages
have been analyzed in Lesson 34. In this lesson a 3-phase bridge type VSI with square wave pole
voltages has been considered. The output from this inverter is to be fed to a 3-phase balanced
load. Fig. 35.1 shows the power circuit of the three-phase inverter. This circuit may be identified
as three single- phase half-bridge inverter circuits put across the same dc bus. The individual
pole voltages of the 3-phase bridge circuit are identical to the square pole voltages output by
single-phase half bridge or full bridge circuits. The three pole voltages of the 3-phase square
wave inverter are shifted in time by one third of the output time period. These pole voltages
along with some other relevant waveforms have been plotted in Fig. 35.2. The horizontal axis of
the waveforms in Fig. 35.2 has been represented in terms of ‘ωt’, where ‘ω’ is the angular
frequency (in radians per second) of the fundamental component of square pole voltage and ‘t’
stands for time in second. In Fig. 35.2 the phase sequence of the pole voltages is taken as VAO,
VBO and VCO. The numbering of the switches in Fig. 35.1 has some special significance vis-à-
vis the output phase sequence.
 P idc B
Sw1 Sw3 Sw5

Edc + Cdc A
_ N
3-phase
balanced load

Sw4 Sw6 Sw2

n C
Fig. 35.1: A 3-phase Voltage Source Inverter (VSI) feeding a balanced load

AO
0.5Edc
Sw1 Sw1
0
Sw4 Sw4
- 0.5Edc ωt

VBO 0.5Edc
Sw3 Sw3
0 Sw6 Sw Sw6
6
- 0.5Edc ωt

VCO Sw5 0.5Edc

Sw5 Sw5
0
Sw2 Sw2
- 0.5Edc ωt

VAB Edc

0
ωt
-Edc
2/3Edc
VAN
1/3Edc
0
-1/3Edc ωt
-2/3Edc
1/3Edc 2/3E dc
VBN
 Sw1
A
X

0
-1/3Edc
-2/3Edc
π/3 π π π ωt
0 2 /3 4 /3 5π/3 2π 7π/3 8π/3 3π 10π/3 11π/3 3π
Fig. 35.2: Some relevant voltage waveforms output by a 3-phase square wave VSI

To appreciate the particular manner in which the switches have been numbered, the conduction-
pattern of the switches marked in Fig. 35.2 may be noted. It may be seen that with the chosen
numbering the switches turn on in the sequence:- Sw1, Sw2, Sw3, Sw4, Sw5, Sw6, Sw1, Sw2,
….and so on. Identifying the switching cycle time as 360 degrees (2π radians), it can be seen
0
that each switch conducts for 180 and the turning on of the adjacent switch is staggered by 60
degrees. The upper and lower switches of each pole (leg) of the inverter conduct in a
complementary manner. To reverse the output phase sequence, the switching sequence may
simply be reversed.
Considering the symmetry in the switch conduction pattern, it may be found that at any time
three switches conduct. It could be two from the upper group of switches, which are connected to
positive dc bus, and one from lower group or vice-versa (i.e., one from upper group and two
from lower group). According to the conduction pattern indicated in Fig. 35.2 there are six
combinations of conducting switches during an output cycle:- (Sw5, Sw6, Sw1), (Sw6, Sw1,
Sw2), (Sw1, Sw2, Sw3), (Sw2, Sw3, Sw4), (Sw3, Sw4, Sw5), (Sw4, Sw5, Sw6). Each of these
0
combinations of switches conducts for 60 in the sequence mentioned above to produce output
phase sequence of A, B, C. As will be shown later the fundamental component of the three
output line-voltages will be balanced. The load side phase voltage waveforms turn out to be
somewhat different from the pole voltage waveforms and have been dealt with in the next
section.

3.1 Determination Of Load Phase-Voltages

Fig. 35.1 shows a star connected balanced 3-phase load. The three load terminals are connected
to the three output points (A, B, C) of the inverter. The neutral point ‘N’ of the load is
deliberately left open for some good reasons mentioned later. The load side phase voltages VAN,
VBN and VCN can be determined from the conduction pattern of the inverter switches. With
reference to Fig. 35.2, it may be seen that for 0≤ωt≤π/3, switches Sw5, Sw6 and Sw1 conduct.
Under the assumption of ideal switches Fig. 35.3(a) will represent the equivalent inverter and
load circuit during the time interval 0≤ωt≤π/3. In the equivalent circuit representation the non-
conducting switches have been omitted and a cross (X) sign is used to represent a conducting
switch. For a balanced 3-phase load the instantaneous phase voltage waveforms have been
derived below for the following two cases (i) when the 3-phase load is purely resistive and (ii)
when the load, in each phase, consists of a resistor in series with an inductor and a back e.m.f. In
both the cases the equivalent circuit of Fig. 35.3(a) has been referred to derive the expression for
load-phase voltage.
 Fig. 35.3(a):
VAN = 1/3 Edc Schematic
Sw5 C VBN = -2/3 Edc load circuit
X N
+ VCN = 1/3 Edc during
Edc _ conduction
Sw6 B of Sw5, Sw6
X and Sw1

For case (i), when the load is a balance resistive load, it is very easy to see that the instantaneous
phase voltages, for 0≤ωt≤π/3, will be given by VAN = 1/3 Edc, VBN = -2/3 Edc, VCN = 1/3 Edc.

For case (ii), the following circuit relations hold good.

di di di
V = Ri + L A +E ,V B C
AN A dt A BN = RiB + L dt + EB , VCN = RiC + L dt + EC .…..……(35.1)
V AN − VBN = Edc , VAN =VCN ..………………………………………………………..(35.2)
where, iA , iB , iC are the instantaneous load-phase currents entering phases A, B and C
respectively. EA , EB and EC are the instantaneous magnitudes of load phase-emfs. R and L are
the per-phase load resistance and inductance that are connected in series with the corresponding
phase-emf. Since the load is balanced (with its neutral point floating) the algebraic sum of the
instantaneous phase currents and the phase emfs will be zero. Accordingly,
iA + iB + iC = 0 and EA + EB + EC = 0………………………………………(35.3)
From Eqns. 35.1 and 35.3, the following may be deduced:
d (i + iC ) di B
V AN + VCN = R (i A + iC ) + L A + ( E A + EC ) = − ( RiB + L + E B ) = −VBN .... (35.4)
dt dt
Now from Eqns. 35.2 and 35.4 it can be easily found that VAN = 1/3 Edc, VBN = -2/3 Edc, VCN =
1/3 Edc.

Thus the instantaneous magnitudes of load phase voltages, in case of a more general (but
balanced) R-L-E load are same as in case of a simple balanced resistive load.

Fig. 35.3(b) shows the equivalent circuit during π/3≤ωt≤2π/3, when the switches Sw6, Sw1 and
Sw2 conduct. The instantaneous load phase voltages may be found to be VAN = 2/3 Edc, VBN =
VCN = -1/3 Edc.
Sw1
X A
+
Edc _ VAN = 2/3 Edc
Sw2
X C N VBN = -1/3 Edc
VCN = -1/3 Edc
Sw6 B
X
Fig. 35.3(b): Schematic load circuit during conduction of Sw6, Sw1 and Sw2

The load phase voltage waveforms for other switching combinations may be found in a similar
manner. Two of the phase voltages,VAN and VBN , along with line voltage VAB have been plotted
over two output cycles in Fig. 35.2. It may be seen that voltage VBN is similar to VAN but lags it by
one third of the output cycle period. Further, it can be verified that the load phase voltage VCN also
has a waveform identical to the two other phase voltages but time displaced by one third of the
output time period. VCN waveform leads VAN by 120 degrees in the time (ωt) frame. It
should be obvious that the fundamental component of the phase voltage waveforms will
constitute a balanced 3-phase voltage having a phase sequence A, B, C. It may also be recalled
that by suitably changing the switching sequence the output phase sequence can be changed. The
phase voltage waveforms of Fig. 35.2 show six steps per output cycle and are also referred as the
six-stepped waveform. A more detailed analysis of the load voltage waveforms is done in the
following section.
3.2 Harmonic Analysis Of Load Voltage Waveforms
The individual pole voltage waveforms output by the 3-phase square wave inverter are identical
to the output waveform of a single-phase half bridge inverter. As a consequence, the harmonic
analysis of the voltage waveform presented in section 34.1 of Lesson 34 is valid here too. The
expression for line voltage VAB is identical to the one given in Lesson 34 (Eqn.34.15), with ‘Φ’
of Eqn. 34.15 replaced by 2π/3 radians. For convenience the expressions for pole-A voltage
‘VAO ’ and line voltage ‘VAB ’ are reproduced below in Eqns.35.5 and 35.6. The relevant
waveforms are shown in Fig.35.2.

2E
VAO = ∑ dc
nπ sin(nwt) ………………………………………....….(35.5)
n=1,3,5,7,...,∞

V AB = ∑ 2E dc
sin nwt −sin n(wt −
2π
) ………………………....(35.6)
nπ
n=1,3,5,7,...,∞ 3
Using equations 35.5 and 35.6, the expressions for remaining pole and line voltages can be
written simply by shifting the time (ωt) origin by the phase shift angle shown in Fig.35.2.
Accordingly the expressions for pole voltage VBO and line voltage VBC are written below in
Eqns. 35.7 and 35.8 respectively.
2E dc 2π
VBO = ∑ nπ sin n(wt − 3 ) ……………………………………...(35.7)
n=1,3,5,7,...,∞

VBC = ∑ 2E dc
nπ
sin n(wt −
2π
) −sin n(wt −
4π
) …………….…...(35.8)
n=1,3,5,7,...,∞ 3 3
V
It may be verified that difference of AO and VBO leads to the expression for VAB . The
expression for a particular harmonic component in the voltage waveforms is determined simply
by substituting ‘n’ in above equations by the harmonic order. Accordingly the fundamental
magnitude of line voltages VAB , VBC and VCA can be written as:
2E 2π 2 3E π
V dc ) = dc
AB,1 = π sin wt − sin(wt − 3 π sin(wt + 6 )
2 3E π 2 3E 7π
V dc
V = dc
= π sin(wt − 2 ) , CA,1
BC,1 π sin(wt − 6 )
The three fundamental line voltages are balanced (have identical magnitudes and are phase apart by
0
120 ). For most practical loads only the fundamental component of the inverter output voltage is of
interest. However the inverter output also contains significant amount of higher order harmonic
voltages that cause undesirable distortion of the output waveform. It may, though, be noted that there
rd rd
are no even harmonics and the line voltages are free from 3 and multiples of 3 order harmonics.
Also, as the harmonic order (n) increases their magnitudes decrease inversely with the harmonic
order. When expressed as a fraction of fundamental voltage magnitude, the line voltage distortions
th th th th
are mainly due to 20% of 5 harmonic, nearly 14% of 7 , nearly 9% of 11 and nearly 8% of 13
harmonic. Since most loads are inductive in nature with a low pass filter type characteristics the
effect of very high order harmonics may be neglected.
rd rd
It may be noted that though the pole voltages have 3 and multiples of 3 order harmonic
distortions, the line voltages are free from these distortions. Hence the load neutral point, rather
than being connected to the mid-potential point of the input dc supply (as in a single-phase half
bridge inverter), is deliberately left floating. The floating neutral point does not allow a closed
rd rd rd rd
path for the 3 and multiples of 3 harmonic currents to flow (3 or multiples of 3 harmonic
current, if present in the load phases, have identical instantaneous magnitudes in all the three
phases and their algebraic sum needs to flow in or out of the load neutral point). By keeping the
load neutral point floating, not only the need for bringing out the mid-potential point of dc
supply is done away with, the triplen harmonic distortions of the load current is totally
eliminated. Since there are no triplen harmonic currents in the load, the load- phase voltages are
also free from triplen harmonic distortions. In fact the six-stepped load-phase voltages shown in
Fig. 35.2 are found to be free from triplen harmonics. It turns out that by removing all triplen
harmonics from the square-shaped pole voltage waveform one can arrive at the corresponding
load-phase (six-stepped) voltage waveform. Accordingly the load-phase voltages may be
expressed in terms of its harmonic contents as shown below.
2E
VAN = ∑ dc
nπ sin(nwt) ……………………………………….....(35.9)
n=1,5,7,11,13...,∞
2E 2π
VBN = ∑ dc
nπ sin n(wt − 3 ) …………………………………...(35.10)
n=1,5,7,11,13...,∞

2E 2π
VCN = ∑ dc
nπ sin n(wt + 3 ) …………………………………...(35.11)
n=1,5,7,11,13...,∞

For a balanced three-phase load, the instantaneous magnitude of any phase current can be
determined by superposition of different harmonic currents of the phase. For a simple three-
phase R-L load, the phase-A current ( iA ) expression in terms of resistance (R) and inductance
(L) of the load may be written as:

iA = ∑ 2E dc
sin[nwt − tan −1 (
nωL
)] …………….....(35.12)
2 2 2 2
R
n=1,5,7,11,13...,∞ nπ R +nωL

Phase-B and phase-C current expressions can be obtained simply by replacingωt in Eqn. 35.12
2 π 2 π
by (ωt − 3 ) and (ωt + 3 ) respectively. A close look at Eqn. 35.12 will reveal that for a
th th th th
purely inductive 3-phase load the 5 , 7 , 11 and 13 harmonic distortion in the load current
(as a percentage of fundamental component of current) will respectively be 4%, 2.04%, 0.83%
and 0.59%. These distortions are much less than the corresponding distortions in the load voltage
waveforms. As a result the load current for highly inductive R-L load will have close to
sinusoidal shape.
3.3 Voltage And Current Ratings Of Inverter Switches
As in a single-phase square-wave inverter, switches in each leg of the three-phase inverter
operate in a complementary manner. When upper switch of a leg is on the lower switch will need
to block the entire dc bus voltage and vice versa. Thus the switches must be rated to block the
worst-case instantaneous magnitude of dc bus voltage. An extra safety margin over the worst-
case dc voltage, as discussed in Lesson-34, section 34.3, is recommended. Each inverter-switch
carries load-phase current during half of the current cycle. Hence the switches must be rated to
withstand the peak expected magnitude of instantaneous load-phase current. For a non-unity
power factor load, the diode connected in anti-parallel with the switch will conduct part of the
switch current. The distribution of current between the diode and the controlled switch will
depend on the load power factor at the operating frequency. In general both diode as well as the
controlled switch should be rated to carry the peak load current. These diodes also need to block
a peak reverse voltage equal to worst case voltage across the switches.

3.4 Use And Limitations Of 3-Phase Square Wave Inverter

The three-phase square wave inverter as described above can be used to generate balanced three-
phase ac voltages of desired (fundamental) frequency. However harmonic voltages of 5th, 7th
and other non-triplen odd multiples of fundamental frequency distort the output voltage. In many
cases such distortions in output voltages may not be tolerable and it may also not be practical to
use filter circuits to filter out the harmonic voltages in a satisfactory manner. In such situations
the inverter discussed in this lesson will not be a suitable choice. Fortunately there are some
other kinds of inverters, namely pulse width modulated (PWM) inverters, discussed in the next
lesson, which can provide higher quality of output voltage.

The square wave inverter discussed in this lesson may still be used for many loads, notably ac
motor type loads. The motor loads are inductive in nature with the inherent quality to suppress
the harmonic currents in the motor. The example of a purely inductive load discussed in the
previous section illustrates the effectiveness of inductive loads in blocking higher order harmonic
currents. In spite of the inherent low-pass filtering property of the motor load, the load current
may still contain some harmonics. These harmonic currents cause extra iron and copper losses in
the motor. They also produce unwanted torque pulsations. Fortunately the torque pulsations due
to harmonic currents are of high frequencies and their effect gets subdued due to the large
mechanical inertia of the drive system. The motor speed hardly changes in response to these
torque pulsations. However in some cases torque pulsations of particular frequencies may cause
unwanted resonance in the mechanical system of the drive. A special notch filter may then be
required to remove these frequencies from the inverter output voltage.

The input dc voltage to the inverter is often derived from an ac source after rectification and
filtering. A simple diode bridge rectifier followed by a filter capacitor is often the most cost-
effective method to get dc voltage from ac supply. In some applications, like in un-interrupted
power supplies, the dc input may be coming from a bank of batteries. In both these examples, the
input dc magnitude is fairly constant. With fixed input dc voltage the square-wave inverter can
output only fixed magnitude of load voltage. This does not suit the requirement in many cases
where the load requires a variable voltage variable frequency (VVVF) supply. In order that ac
output voltage magnitude is controllable, the inverter input voltage will need to be varied using
an additional dc-to-dc converter. However a better solution will be to use a PWM inverter (to be
discussed in the next lesson), which can provide a VVVF output with enhanced output voltage
quality.

In spite of the limitations, discussed above, the square wave inverter may be a preferred choice
on account of its simplicity and low cost. The switch control circuit is very simple and the
switching frequency is significantly lower than in PWM inverters. This results in low switching
losses. The switch cost may also be lower as one may do away with slower switching devices
and slightly lower rated switches. Another advantage over PWM inverter is its ability to output
higher magnitude of fundamental voltage than the maximum that can be output from a PWM
inverter (under the given dc supply condition). Listed below are two applications where a 3-
phase square wave inverter could be used.
+ A low cost solid-state frequency changer circuit: This circuit converts the 3-phase ac
(input) voltages of one frequency to 3-phase ac (output) voltages of the desired
frequency. The input ac is first converted into dc and then converted back to ac of new
frequency. The square wave inverter discussed in this lesson may be used for dc to ac
conversion. Such a circuit may, for example, convert 3-phase ac voltages of 50 Hz to 3-
phase ac voltages of 60 Hz. The input to this circuit could as well have come from a
single-phase supply, in which case the single-phase ac is first converted into dc and
then converted back to 3-phase ac of the desired frequency.
+ An uninterrupted power supply circuit: Uninterrupted power supply circuits are used to
provide uninterrupted power to some critical load. Here a critical load requiring 3-phase
ac supply of fixed magnitude and frequency has been considered. In case ac mains
supply fails, the 3-phase load may be electronically switched, within few milliseconds,
to the output of the 3-phase square wave inverter. Input dc supply of the inverter often
comes from a battery bank.

Question for Practice

Choose the Best Answer

2 1.A 3-phase square wave inverter feeds a balanced 3-phase resistive-inductive load.
The load phase current will contain, apart from the fundamental frequency current,
the following harmonic currents:
a. All odd multiples of fundamental
b. All odd and even multiples of fundamental
th th
c. All even multiples of fundamental except 6 and multiples of 6
rd rd
d. All odd multiples of fundamental except 3 and multiples of 3
3 2.The six-stepped load phase voltage of a 3-phase square wave inverter, with a dc
st rd th
link voltage of 100 volts, will have the following rms magnitudes of 1 , 3 and 5
harmonic voltages:
a. 10V, 30V and 50V respectively
b. 100V, 33.3V and 20V respectively
c. 90V, 30V and 0 respectively
d. 45V, 0 and 9V respectively

4 3.A 3-phase square wave inverter, fed from a fixed dc input, is capable of producing
the following type of ac (fundamental component) voltages:
 (a) Variable voltage variable frequency type
(b) Fixed voltage variable frequency type
(c) Variable voltage fixed frequency type
(d) None of the above

4.A 3-phase square wave inverter feeds a balanced 3-phase inductance type
load. The worst-case load phase current (peak magnitude) is expected to be 100 amps
and the worst-case dc input voltage is expected to be 600 volts. The diodes of the
inverter will be subjected to the following peak voltage and current stresses:
(e) 600V, 100A
(f) 600V, 70.7A
(g) 424V, 70.7A
(h) 424V, 100A

Answers:
1-d, 2-d, 3-b, 4-a

4.0 3-Phase Pulse Width Modulated (PWM) Inverter

We will be able to:
o The philosophy behind PWM inverters.
o The advantages and disadvantages of PWM inverters.
o The quality of output voltage produced by different PWM inverters

Pulse width modulated (PWM) inverters are among the most used power-electronic circuits in
practical applications. These inverters are capable of producing ac voltages of variable magnitude
as well as variable frequency. The quality of output voltage can also be greatly enhanced, when
compared with those of square wave inverters discussed in Lesson-35. The PWM inverters are
very commonly used in adjustable speed ac motor drive loads where one needs to feed the motor
with variable voltage, variable frequency supply. For wide variation in drive speed, the frequency
of the applied ac voltage needs to be varied over a wide range. The applied voltage also needs to
vary almost linearly with the frequency. PWM inverters can be of single phase as well as three
phase types. Their principle of operation remains similar and hence in this lesson the emphasis
has been put on the more general, 3-phase type PWM inverter.

There are several different PWM techniques, differing in their methods of implementation.
However in all these techniques the aim is to generate an output voltage, which after some
filtering, would result in a good quality sinusoidal voltage waveform of desired fundamental
frequency and magnitude. As will be discussed later in this chapter, for the inverter topology
considered here, it may not be possible to reduce the overall voltage distortion due to harmonics
but by proper switching control the magnitudes of lower order harmonic voltages can be reduced,
often at the cost of increasing the magnitudes of higher order harmonic voltages. Such a situation
is acceptable in most cases as the harmonic voltages of higher frequencies can be satisfactorily
filtered using lower sizes of filter chokes and capacitors. Many of the loads, like motor loads have
an inherent quality to suppress high frequency harmonic currents and hence an external filter may
not be necessary.

To judge the quality of voltage produced by a PWM inverter, a detailed harmonic analysis of the
voltage waveform needs to be done. In the following discussions some of the results of harmonic
analysis done in the previous lessons have been borrowed. In Lesson-35, while discussing the 3-phase
square wave inverter it was shown that the magnitudes of fundamental components of the inverter
pole voltage (voltage between the output of an inverter leg and the mid potential point of the input dc
supply) and the load phase voltage are identical provided the load is a balanced 3-phase load. In fact,
rd rd
after removing 3 and multiples of 3 harmonics from the pole voltage waveform one obtains the
corresponding load phase voltage waveform. The pole voltage waveforms of 3-phase inverter are
simpler to visualize and analyze and hence in this lesson the harmonic analysis of load phase and line
voltage waveforms is done via the harmonic analysis of the pole voltages. It is implicit that the load
rd rd
phase and line voltages will not be affected by the 3 and multiples of 3 harmonic components that
may be present in the pole voltage waveforms.

4.1 Nature Of Pole Voltage Waveforms Output By

PWM
Inverters
Unlike in square wave inverters the switches of PWM inverters are turned on and off
at significantly higher frequencies than the fundamental frequency of the output
voltage waveform. The typical pole voltage waveform of a PWM inverter is shown in
Fig. 36.1 over one cycle of output voltage. In a three-phase inverter the other two pole
voltages have identical shapes but they are displaced in time by one third of an output
cycle. Compared to the square pole voltage waveform seen in Lesson-35, the pole
voltage waveform of the PWM inverter changes polarity several times during each
half cycle. The time instances at which the voltage polarities reverse have been
referred here as notch angles. It may be noted that the instantaneous magnitude of pole
voltage waveform remains fixed at half the input dc voltage (Edc). When upper switch
(SU), connected to the positive dc bus is on, the pole voltage is + 0.5 Edc and when the
lower switch (SL), connected to the negative dc bus, is on the instantaneous pole
voltage is - 0.5 Edc. The switching transition time has been neglected in accordance
with the assumption of ideal switches. It is to be remembered that in voltage source
inverters, meant to feed an inductive type load, the upper and lower switches of the
inverter pole conduct in a complementary manner. That is, when upper switch is on
the lower is off and vice-versa. Both upper and lower switches
Pole
Voltage

0.5Edc

SU SU SU SU SU SU SU SU SU

ωt
0

SL SL SL SL SL SL SL SL SL
 -0.5Edc
α1 α3 π/2 π-α3 π-α1 π+α1 π+α 3 3π/2 2π-α3 2π-α1
π
0 α2 α4 π-α4 π-α2 π+α2 π+α4 2π-α4 2π-α2 2π
Fig.36.1: A typical pole-voltage waveform of a PWM inverter
should not remain on simultaneously as this will cause short circuit across the dc bus.
On the other hand one of these two switches in each pole (leg) must always conduct to
provide continuity of current through inductive loads. A sudden disruption in inductive
load current will cause a large voltage spike that may damage the inverter circuit and
the load.

4.2 Harmonic Analysis Of Pole Voltage Waveform

The pole voltage waveform shown in Fig. 36.1 has half wave odd symmetry and quarter-wave
mirror symmetry. The half wave odd symmetry of any repetitive waveform f(ωt), repeating
after every 2π/ω duration, is defined by f(ωt) = - f(π+ωt). Such a symmetry in the waveform
amounts to absence of dc and even harmonic components from the waveform. All inverter
output voltages maintain half wave odd symmetry to eliminate the unwanted dc voltage and
the even harmonics. The half wave odd symmetry followed by quarter wave mirror
symmetry, defined by f(ωt) = f(π-ωt), results in presence of only sine components in the
Fourier series representation of the waveform. It may be verified that quarter wave
symmetry may not hold good once the time origin is shifted arbitrarily. However the half-
wave odd symmetry is maintained in spite of shifting of time origin. This is quite expected,
as by just shifting the time origin new (even) harmonic frequencies will not creep up in the
voltage waveform, whereas by shifting time origin the sine wave may become cosine or
may have some other phase-shift. The quarter wave symmetry talked above is not necessary
for improvement of the output waveform quality; it merely simplifies the Fourier analysis
of the pole voltage waveform. It may also be noted that the quarter wave symmetry is not
achieved at the cost of compromising the inverter’s output capability (in terms of
magnitude and quality of achievable output voltage).

With the assumed quarter wave mirror symmetry and half wave odd symmetry the waveform
shown in Fig. 36.1 may be decomposed in terms of its Fourier components as below:-

V AO = ∑ bn sin nωt ……………………………………………………..(36.1)

n=1,3,5,....∞

where VAO is the instantaneous magnitude of the pole voltage shown in Fig. 36.1 and bn
th
is the peak magnitude of its n harmonic component. Because of the half wave and quarter
wave symmetry of the waveform, mentioned before, the pole voltage has only odd harmonics and
has only sinusoidal components in the Fourier expansion. Thus the pole voltage will have
fundamental, third, fifth, seventh, ninth, eleventh and other odd harmonics. The peak magnitude
th
of n harmonic voltage is given as:
b = 2 E (1 − 2 cos nα + 2 cos nα
− 2 cos nα + 2 cos nα ) …………………..(36.2)
nnπ 1 2 3 4

, where α1 , α2 ¸α3 and α4 are the four notch angles in the quarter cycle ( 0 ≤ ω t ≤π 2 ) of
the waveform.
 Now, as described in the beginning of this lesson, the third and multiples of third harmonics
do not show up in the load phase and line voltage waveforms of a balanced 3-phase load. Most of the
three phase loads of interest are of balanced type and for such loads one need not worry about triplen
rd rd
(3 and multiples of 3 ) harmonic distortion of the pole voltages. The peak magnitudes of
fundamental ( b1 ) and three other lowest order harmonic voltages that matter
most to the load can be written as:
2E
b = (1 − 2 cosα + 2 cosα − 2 cosα + 2 cosα ) ….…………………..(36.3)
1 π 1 2 3 4
2E
b = (1 − 2 cos 5α + 2 cos 5α − 2 cos 5α + 2 cos 5α ) ………………...(36.4)
5 5π 1 2 3 4

b = 2 E (1 − 2 cos 7α + 2 cos 7α − 2 cos 7α + 2 cos 7α ) ………………..(36.5)

7 5π 1 2 3 4
2E
b11 = 11 π (1 − 2 cos11α1 + 2 cos11α 2 − 2 cos11α3 + 2 cos11α4 ) …………...(36.6)
rd th
It can be seen that the 3 and 9 harmonics have been not considered, as they will not appear in
the load side phase and line voltages. Most of the industrial loads are inductive in nature with an
inherent quality to attenuate currents due to higher order harmonic voltages. Thus after
th th th
fundamental voltage, the other significant voltages for the load are 5 , 7 and 11 etc.
Generally, only the fundamental frequency component in the output voltage is of interest and all
other harmonic voltages are undesirable. As such one would like to eliminate as many low order
harmonics as possible. Accordingly the fundamental voltage magnitude ( b1 ) may be set at the
desired value and the magnitudes of fifth ( b5 ), seventh ( b7 ) and eleventh ( b11 ) harmonics may
be set to zero. These voltage magnitudes when substituted in the expressions given by Eqns. 36.3
to 36.6 will lead to the solutions of the notch angles. One may like to eliminate many more
unwanted harmonic frequencies from the load voltage waveform but this will require introduction
of more notch angles per quarter cycle of the pole voltage. In fact if there are ‘k’ notch angles per
quarter cycle, ‘k’ number of equations may be written each of which determines the magnitude of
a particular harmonic voltage. Now, each time a notch angle is encountered in the pole voltage
waveform, the top and bottom switches of that particular pole undergo a switching transition (on
to off or vice versa). The switching frequency (fsw) of the inverter switches can be equated to

fsw = 2 k f1 …………...…………...………………………….....(36.7)

, where one turn-on and one turn-off has been taken as one switching cycle, ‘k’ is the number of
notches per quarter cycle and f1 is the frequency of fundamental component in the output voltage.
Thus it can be seen that a better quality output waveform (in terms of elimination of more
numbers of unwanted harmonic voltages) comes at the cost of increasing the switching frequency
of the inverter. The switching frequency is directly proportional to the switching losses in the
inverter switches. Also, the switch must be capable of being switched on and off at the required
frequency. The IGBT switches used in medium power inverters are generally switched at a
frequency of 20 kHz or more. With a switching frequency of 20 kHz and the output (fundamental)
frequency of 50 Hz there will be up to 200 notches per quarter cycle of the output waveform. The
load voltage can thus be made virtually free of low order harmonics and the load current (for an
inductive load) can be expected to have a good quality sinusoidal waveform. The switching
frequency of 20 kHz is important in another sense too. The range of audible noise for human
beings extends from few Hertz to 20 kHz. Thus if the switching frequency is 20 kHz or beyond,
the switching frequency related audible noise will not be present when the inverter operates. The
inverter operation can then be very quite. If the inverter operates at low frequency, the connecting
wires to the switches etc. also carry low frequency current producing low frequency vibrations
(due to interaction of current with the stray magnetic field produced by other conductors etc.) and
result in audible noise. Similarly low frequency current through inductors and transformers also
produce audible noise. The humming or whistling type noise due to low switching frequency may
at times be too annoying and unacceptable.

4.4 Two-Level Versus Three-Level PWM Inverters

As described in section 36.3, the three-phase bridge inverter consisting of six switches (shown in
Lesson-35) can output pole voltages of only two levels +0.5Edc and -0.5Edc. In contrast to a two-level
inverter, a three-level inverter is capable of producing three different pole-voltage levels, namely,
+0.5Edc, zero and -0.5Edc. The circuit details of three-level
in this course but it can easily be shown that the three-level inverter will have better harmonic
spectrum in comparison to the two-level inverter. As described by Eqn. (36.8) in section 36.3, any
reduction in the fundamental output voltage magnitude of a two level inverter results in increased
rms magnitude of unwanted ripple in the output waveform. Now, let Eqn. (36.8) be considered in
relation to a three-level inverter. Since the pole voltage can now have zero level too, the rms
magnitude of the pole voltage can be brought below 0.5Edc. For lower magnitude of fundamental
pole-voltage, as given by Eqn. (36.9), suitable intervals of zero voltage level may be introduced
such that with lowering of fundamental voltage the rms of the overall pole voltage also reduces.
Thus the rms of the ripple voltage, in case of three-level inverter, can be made lower than that of
the two-level inverter.

P idc
Sw1 Sw3

Edc + Cdc
_
A LOAD B

Sw2 Sw4
N
Fig. 36.3: A 1-phase full-bridge VSI
The three-level versus two-level comparison can be applicable to a single- phase PWM inverter
too. Consider the single-phase full bridge circuit shown in Fig.36.3. For this circuit if all the time
one of the two diagonal pair of switches, (Sw1 and Sw4) or (Sw2 and Sw3), conduct the load
voltage will have two levels; +E or –E. By suitably switching between one diagonal pair to
another diagonal pair one can obtain a PWM waveform similar to the pole voltage waveform of a
three-phase PWM inverter (only change is in the voltage magnitude). Now if the allowed
switching combination includes conduction of Sw1 along with Sw3 (or Sw2 along with Sw4) the
load voltage may have three-levels, i.e., +E, zero and –E. As with a three-phase inverter, the
single phase PWM inverter too will have lower voltage distortion in case of three-level load
voltage (than the corresponding distortion in two level output).
 4.5 Considerations On Switch Voltage And Current Ratings
As in square wave inverter the switches of PWM inverter must also be rated for the maximum
dc link voltage. There will, however, be a significant difference in the switch current ratings of the
square wave and PWM inverter for comparable magnitudes of inverters’ output current. This is due to
the increased switching losses in the PWM inverter. Since the switches in PWM inverter operate at
much higher frequencies than in square wave inverter, the switching losses in the former are
comparable to the conduction losses. This calls for suitable de-rating of the switch current rating. For
medium power rated inverters mostly IGBT switches (with fast acting anti-parallel diodes) are used.
Generally molded blocks of six switches and six diodes, connected inbridge fashion with their power
and control terminals brought out, are commercially available. These molded blocks come with isolated
metallic case that need to be mounted on suitably sized heat sinks for dissipation of thermal losses in
the switch. The switch manufacturers provide the turn-on and turn-off loss data for the switches for
different magnitudes of dc link voltage, switch current and gate-to-emitter voltages. Similarly
conduction loss data for the switches and the diodes are also provided. The thermal resistance data
(thermal resistance between case and semiconductor-junction) for the switches and diodes are also
provided. The heat-sink manufacturers provide data / guide lines for calculating the thermal resistance
between heat sink and ambient. The inverter designer needs to do a detailed analysis of the worst-case
thermal losses and temperature rise and need to limit the switch current accordingly. In PWM inverters,
because of large number of switching per output cycle, the load current frequently jumps from
controlled switch (say, IGBT) to diode and hence the diodes of the switches must also be rated to carry
the peak magnitude of load current. It is to be kept in mind that in PWM inverters the load current
polarity changes only according to the output frequency and not according to the switching frequency.
For load power factor close to one, as the PWM inverter’s output voltage decreases the diode
conduction duration increases. The worst-case diode losses also need to be determined for deciding on
the de-rating factor for diode currents.

Question for Practice

Choose the Best Answer
1 A PWM inverter is operated from a dc link voltage of 600 volts. The maximum rms
line voltage (fundamental component) will be less than or equal to:
* 600 volts
* 300 volts
* 467 volts
* 582 volts
2 In the harmonic analysis of the pole-voltage waveform (produced by a three-phase
rd rd
PWM inverter feeding a balanced three-phase load) the 3 and multiples of 3
harmonics are ignored because:
a. They will not appear in pole voltage
b. They will not appear in load phase voltage
c. They will not appear in load phase and line voltage
d. They will appear in line voltage but not in phase voltage
3 An IGBT based PWM inverter, with very large number of (nearly) evenly
distributed notches per output cycle, is used to feed a three-phase balanced R-L load
with a load power factor of 0.9. The peak magnitude of diode current and the IGBT
current will have the following relation:
a. They will be equal
b. Peak diode current will be less than half of the peak IGBT current
 c. Diode current will nearly be zero
d. Peak diode current will be less than one third of the peak IGBT current
4 A PWM inverter is capable of producing the following type of output voltage:
a. Variable in magnitude and frequency
b. Variable voltage, fixed frequency
c. Fixed voltage, variable frequency
d. Fixed voltage, fixed frequency
Answers
1-c, 2-c, 3-a, 4-a

6.0 PWM and its Realization

Shall be able to:

The concept of sine-modulated PWM inverter

a simple controller for the sine-PWM inverter

Calculation output voltage magnitude from the inverter operating parameters

Comparison sine-modulated PWM inverter with square wave inverter

The PWM inverter has been introduced in Lesson 36 and Fig. 36.1 shows a typical pole voltage
waveform, over one output cycle of the PWM inverter. It can be seen that the pole voltage
consists of large number of rectangular pulses whose widths are modulated suitably to provide
control over the output voltage (fundamental component) magnitude and, additionally, control
over the harmonic spectrum of the output waveform.

In Sine-PWM inverter the widths of the pole-voltage pulses, over the output cycle, vary in a
sinusoidal manner. The scheme, in its simplified form, involves comparison of a high frequency
triangular carrier voltage with a sinusoidal modulating signal that represents the desired
fundamental component of the pole voltage waveform. The peak magnitude of the modulating
signal should remain limited to the peak magnitude of the carrier signal. The comparator output
is then used to control the high side and low side switches of the particular pole. Fig. 37.1 shows
an op-amp based comparator output along with representative sinusoidal and triangular signals as
inputs. In the comparator shown in Fig. 37.1, the triangular and sinusoidal signals are fed to the
inverting and the non -inverting input terminals respectively and the comparator output
magnitudes for high and low levels are assumed to be +VCC and -VCC.

+VCC

Modulating
Q
signal
+
Q -VCC
 A
+
0.5Edc _ SU
Time in m.sec.
+ Edc
_ Pole
+VCC 0.5Edc O Voltag
+
Q
VAO 0.5Edc _ SL

-VCC - 0.5Edc
Carrier
-
signal

Time (mili sec.)

Fig. 37.1: A schematic circuit for comparison of Modulating and Carrier signals

The comparator output signal ‘Q’ is used to turn-on the high side and low side switches of
the inverter pole. When ‘Q’ is high, upper (high side) switch of the particular pole is turned on
and when ‘Q’ is low the lower switch is turned on.
The pole voltage, thus obtained is a replica of the comparator output voltage. When ‘Q’= + VCC,
the pole voltage (measured with respect to the mid potential point of the dc supply) is +0.5Edc and

when ‘Q’= (-)VCC, the pole voltage becomes (-0.5)Edc. The input dc voltage to the
inverter (Edc) has been assumed to be of constant magnitude. Thus, on a normalized scale,
the harmonic contents in the comparator output voltage and the pole voltage waveforms
are identical.

6.1Analysis Of The Pole Voltage Waveform With A Dc

Modulating Signal
Before analyzing the sine-modulated pole voltage waveform, it would be revealing to
consider a pure dc signal (of constant magnitude) as the modulating wave. The
magnitude of the dc modulating signal is constrained to remain between the minimum
and maximum magnitudes of the triangular carrier signal. Fig. 37.2 illustrates one such
case where the triangular carrier signal varies between -1.0 and +1.0 units of voltage and
the magnitude of the modulating wave is kept at 0.4 unit of voltage. Now, the high
frequency triangular carrier waveform is compared with the dc modulating signal and the
comparator output is used to control the high and low level switches (SU and SL
respectively) of the inverter pole shown in Fig. 37.2.
The figure also shows the comparator output (Q) and the pole voltage (VAO) waveforms for this
case. As can be seen, with pure dc modulating signal the pole voltage consists of pulses of identical
shapes repeating at carrier frequency. The Fourier series decomposition of pole voltage waveform
results into a mean (dc) voltage and harmonic voltages whose frequencies are integral multiples of
carrier frequency. By using simple mathematics the high-duration of the pulses ( th ),
during which the pole voltage magnitude is 0.5Edc, can be found to be

Fig. 37.2: Inverter pole voltage for a pure dc modulating waveform

 Tc Vm
th = (1 + ) …………………………………………………………………....
(37.1),
2
Vl c
where Tc is the time period of the triangular carrier waveform, Vm is the magnitude of the
l
modulating signal and V c is the peak (positive) magnitude of the carrier signal.
In a similar manner the low-duration ( tl ) of pulses during which the pole voltage magnitude is -
0.5Edc, can be found as:
Tc Vm
tl = (1 − ) …………………………………………………………………...
l
(37.2) 2 V c
The dc component of the pole voltage (V0 ) can be found to be
V0 = 0.5Edc Vm
…………………………………………………………………... (37.3)
l
Vc
l l
The dc modulating signal could acquire any magnitude between +V c and -V c and accordingly
the mean magnitude of pole voltage can vary within +0.5Edc and -0.5Edc. When the modulating
signal magnitude (Vm ) is zero, the high and low durations of the pole output pulses will be
identical and the mean pole voltage magnitude will be zero.
As mentioned before, apart from the dc component, the pole voltage consists of harmonics of
integral multiples of carrier frequency. The lowest order harmonic-frequency being same as the
carrier frequency.

6.2 Pole Voltage Waveform With Sinusoidal Modulating

Signal
In the previous section a pure dc modulating signal was considered. Let now a slowly varying
sinusoidal voltage, with the following constraints, be considered as the modulating signal:
5 The peak magnitude of the sinusoidal signal is less than or equal to the peak magnitude of
the carrier signal. This ensures that the instantaneous magnitude of the modulating signal
never exceeds the peak magnitude of the carrier signal.
6 The frequency of the modulating signal is several orders lower than the frequency of the
carrier signal. A typical figure will be 50 Hz for the modulating signal and 20 Kilohertz
for the carrier signal. Under such high frequency ratios, the magnitude of modulating
signal will be virtually constant over any particular carrier-signal time period.

Because of the above assumptions some results of the previous section, where a pure dc
modulating signal was considered, may be used. Since the slowly varying modulating signal is
virtually constant over a high frequency carrier time period, the mean magnitude of the inverter
pole voltage averaged over a carrier time period will be proportional to the mean magnitude of
the modulating signal. Thus the discretely averaged magnitude of pole voltage (averaged over
successive high frequency carrier time period) is similar to the modulating signal. The pole
voltage waveform thus has a low frequency component whose instantaneous magnitude is
proportional to the modulating signal (also implying that they will have same frequency and will
be in-phase). Apart from this low frequency component the pole voltage will also have high
frequency harmonic voltages. However, unlike in the case of pure dc modulating signal the
harmonic frequencies are now not simply integral multiples of carrier frequency. This is so
because here the widths of the high frequency pole-voltage pulses do not remain constant
through out. The pulse widths get modulated as per equations (37.1) and (37.2) due to slowly
varying modulating signal. As a result the harmonics in the pole voltage waveform are of
frequencies that are shifted from the carrier (and multiples of carrier frequency) by the integral
multiples of modulating wave frequency. In fact one gets a band of harmonic frequencies
centered around the carrier and integral multiples of carrier frequency. The individual
frequencies that form the band are displaced from these central frequencies by integral multiples
of modulating wave frequency. However, the modulating wave frequency being negligible
compared to the carrier frequency, the dominant harmonics are still in the vicinity of carrier
frequency and multiples of carrier frequency. A more detailed harmonic analysis of the sine-
modulated pole voltage waveforms is beyond the scope of this course. The low frequency
(modulating frequency) component of the pole output voltage is often referred as fundamental
frequency component.

Now, in some cases the ratio of carrier and modulating frequencies may not be very high but the
pole voltage still has a fundamental frequency component proportional to and in-phase with the
modulating signal. The essential advantage of having very high carrier frequency, in comparison
to the modulating wave frequency, is that the useful fundamental frequency component of pole
voltage and the unwanted harmonics (having frequencies close to the carrier and multiples of
carrier frequency) are far apart on the frequency spectrum and one can virtually filter away the
harmonic voltages without attenuating the magnitude of the fundamental frequency component
by putting a suitable low pass filter. The filter size requirement remains small if the harmonics
are of high frequencies. In some applications, like ac motor drive application, the inherent low
pass filtering characteristics of the motor-load itself is enough to satisfactorily block the flow of
harmonic currents to the load. In such cases the need for external filter may not arise.

It may be obvious that high carrier frequency calls for high switching frequency of the inverter
switches. In fact the switches turn-on and turn-off once during each carrier cycle. Generally the
switches used in high power applications (say, more than few hundred kW) can be switched only
at sub kilohertz frequency and hence the carrier frequency cannot be arbitrarily high. The
switching frequency related losses are also to be considered before deciding the carrier frequency
of the sine-PWM inverter.

What Is Modulation Index?

Modulation index is the ratio of peak magnitudes of the modulating waveform and the carrier
waveform. It relates the inverter’s dc-link voltage and the magnitude of pole voltage
m
(fundamental component) output by the inverter. Now let ‘V m sin(ωt) ’ be the modulating signal
l
and let the magnitude of triangular carrier signal vary between the peak magnitudes of +V c and -
l m l
V c . The ratio of the peak magnitudes of modulating wave (V m ) and the carrier wave (V c ) is
defined as modulation-index ( m ). In other words:
 Vmm
m= …………………………………………………………………... …...(37.4)
l
Vc
Normally the magnitude of modulation index is limited below one (i.e., 0< m <1). From the
discussion in the previous section it can be concluded that for 0< m <1, the instantaneous
magnitude of fundamental pole voltage (VAO,1) will be given by:

VAO,1 = 0.5Edc( msinωt ) ………………………………………………... …....(37.5),

where ‘ω ’ is the angular frequency of the modulating waveform. For m = 1 the pole output
1
voltage (fundamental component) will have a rms magnitude of 0.35Edc (= 2 2 Edc). This
magnitude, as can be found out from Sec. 34.1 of Lesson 34, is only 78.5% of the fundamental
pole voltage magnitude output by a square wave inverter operating from the same dc link
voltage.

What Is Over-Modulation?
When the peak magnitude of modulating signal exceeds the peak magnitude of carrier signal
(resulting in m >1), the PWM inverter operates under over-modulation. During over-modulation
the fundamental component of the pole voltage increases slightly with increase in modulation
index but the linear relation between them, as shown by Eqn. (37.5), no longer continues. Also,
lower frequency harmonics crop up in the pole-output waveform. It may easily be seen that for ‘
m ’ very high (say m = infinity), the pole voltage shape will be identical to the square wave shape
discussed in Lesson-34. Over modulation is generally not preferred because of the introduction
of lower frequency harmonics in the output waveform and subsequent distortion of the load
current.

6.4 1-Phase Sine-PWM Inverter Of H-Bridge Topology

Lesson-34 shows the half bridge and full bridge topologies of a single phase square-wave
inverter. The single-phase full bridge is also called as H-bridge because of its resemblance with
the letter ‘H’. [The two legs (poles) of the inverter resemble the two vertical lines of ‘H’ and the
horizontal line denotes the load, which is connected to the pole output points.] The switches and
the load in a single-phase full bridge PWM inverter are connected exactly as in a square-wave
inverter circuit. The difference lies in the conduction pattern of the inverter switches. In the
0
square-wave inverter the switches conduct continuously for 180 in each output cycle whereas in
PWM inverter large number of switching take place in each output cycle.

The half bridge sine-PWM inverter employing only one leg has already been described in the
previous section. The full bridge inverter employs one additional leg but the control signals of
the half bridge circuit may still be employed for switches of the other leg. As in the square-wave
inverter (Lesson-34) the diagonal switches of the two legs may be turned on together to produce
a load voltage that has double the magnitude of individual pole voltage. The PWM signals for
the high and low level switches of one leg (obtained by sine-triangle comparison) may again be
used for low and high level switches, respectively, of the other leg.
 Modulating Modulating
Signal for Signal for
Pole-A Pole-B

Carrier
signal

0.5Edc

0
VAO

-0.5Edc
0.5Edc

0
VBO

-0.5Edc
Edc Angular freq. for fundamental
component in rad./sec

VAB

- Edc
 Fig. 37.3: Sine-PWM waveforms for single-phase H-Bridge inverter

Alternately (also, preferably), the modulating waveform for the other leg may be inverted
(keeping the carrier waveform same). The two inverted modulating waveforms are then
compared with the same carrier waveform using two different comparators. The comparator
outputs, one for each leg, are then used to switch the high and low level switches as in the half
bridge circuit.

Fig.37.3 shows the relevant waveforms that use two inverted sine waves as modulating signals
for the two legs of the inverter. For better visibility the ratio between the carrier and modulating
wave frequencies has been assumed equal to ‘eight’ (normally carrier frequency is much higher)
and circuit waveforms for only part of the modulating wave cycle has been shown. In Fig.37.3,
the blue colored modulating wave is used for pole-A of the inverter and the green colored for
pole-B. The corresponding pole voltages (VAO, VBO) and the load voltage (VAB) are also shown
in the figure.

The scheme, using two inverted modulating waves, has the following advantages over the one
that uses single modulating wave and employs simultaneous switching of the diagonal switches
of the two legs:- (i) Overall harmonic distortion of the load voltage waveform is reduced and (ii)
the frequency of the ripple voltage in the load waveform doubles. Both these points may be
verified by mere inspection of the load voltage waveform shown in Fig.37.3. In case of single
modulating wave, the instantaneous load voltage has double the amplitude of pole-A voltage and
thus the harmonic distortion of the load voltage and pole voltage remains same. It may be noted
that the instantaneous magnitude of load voltage, in this case, has two levels (+0.5Edc and -
0.5Edc). In the alternate scheme, using two inverted modulating waves, the load voltage has
double the number of pulses per carrier time period, thus doubling the ripple frequency. Now,
higher the frequency of unwanted ripple-voltage, easier it is to filter out the ripple current. Also,
the load voltage now has three levels (+0.5Edc, zero, and -0.5Edc). Presence of zero duration
reduces the rms magnitude of the overall load voltage (fundamental component along with
harmonics), while keeping the magnitude of fundamental component of load voltage same as in
the previous case (the rms of the overall load voltage for the two-level waveform equals Edc).
Thus the overall distortion of the load voltage waveform is less.

6.5 Generation Of 3-Phase Sine-PWM Waveform

A three-phase inverter, as discussed in Lessons 36, can be used to output a three-phase sine
modulated pole-voltage pulses. Switches in each of the three poles of the inverter are
individually controlled as per the technique discussed in the previous section. For a balanced
three-phase output voltage from the inverter poles, the three sinusoidal modulating signals (one
for each pole) must also be balanced three-phase signals. The carrier waveform for all the three
poles may remain identical. The fundamental components of individual pole output voltages (for
0< m <1) will thus be proportional to the corresponding modulating signals. For m = 1, the rms
magnitude of line-to-line voltage (fundamental component) output by the inverter will be equal
3
to 2 2 Edc (= 0.612Edc). A typical line voltage waveform (difference of two pole voltage
waveforms) will appear similar to the line voltage waveform (VAB) shown in Fig.37.3.
6.6 A Typical Circuit For Generation Of PWM Waveforms
As mentioned in the preceding section, a three-phase sine-PWM inverter would require a
balanced set of three sinusoidal modulating signals along with a triangular carrier signal of high
frequency. For a variable-voltage-variable-frequency (VVVF) type inverter, a typical
requirement for adjustable speed drives of ac motors, the magnitude as well as frequency of the
fundamental component of inverter’s output voltage needs to be controlled. This calls for
generation of three-phase balanced modulating signals of variable magnitude and frequency
which it may be emphasized, need to have identical magnitudes and phase difference of 120
degrees between them at all operating frequencies.
Generating a balanced three phase SINE waveforms of controllable magnitude and frequency
is a pretty difficult task for an analog circuit and hence a mixed analog and digital circuit is
often preferred. Fig. 37.4 shows a scheme, in block diagram, where the 3-phase analog SINE
waves are generated with the help of EPROMs, D/A converters etc.

EPROM#1 SINE
D/A
Frequency Wave
(1K) loaded Converter
Control with SINE #1
Wave Data +V

Voltage to Divide by 10 bit Ref. Volt.

10 8 bit
Freq. (V/f) 2 VM
address Data
Converter counter
EPROM#2 D/A
loaded with Converter
0
120 shifted #2
SINE Data
0
120 shifted
SINE Wave
Fig.37.4: Schematic circuit for generation of balanced sinusoidal signals

In the circuit of Fig.37.4, two EPROMs are loaded with discrete values of SINE wave. The
0 0
first EPROM contains Sin(Φ) values and the second EPROM contains Sin(Φ-120 ) , for 0 <
0
Φ < 360 . Let us assume that the EPROMs have 1K (=1024) memory locations. In
EPROM#1 Sin(Φ) values are stored serially at discrete but regular intervals of Φ values.
0
Accordingly the first location of EPROM#1 contains Sin(0 ) in digital form, i.e., all the bits
0
are zeroes. The second memory location contains Sin(360 /1024) in the digital form and so
0
on. Similarly the first memory location of EPROM#2 contains Sin(120 ) and second memory
0 0
location has Sin(120 + 360 /1024) in digital form. The contents of a particular memory
location can be accessed asynchronously by feeding the corresponding address word. A 1K
EPROM will have 10 address lines. All address bits, when zero, point to first memory
location. As the address word increments the subsequent memory locations are addressed.
The EPROMs generally have a 8 – bit word length. Now, Sin(Φ) value, over the full range of
Φ , may either be positive or negative. So while digitizing them care must be taken to
identify one bit of the word as the sign bit. For example, in the 8 bit (byte length) word the
MSB may be used as sign bit with the understanding that if this sign bit is zero the number is
positive and if this bit is 1 the number is negative (alternately, one may store ‘1+ Sin(Φ)’ in
 the memory and the need to store negative numbers will not arise). Leaving one bit (say
7
MSB) as sign bit the 0.0 to 1.0 scale of Sin(Φ) magnitude is divided in 2 = 128 equal parts
and accordingly the SINE value is digitized. Thus when Sin(Φ) = 1/128 the word to be stored
should be 0000 0001. For lesser but positive value of Sin(Φ) the word is 0000 0000. If, for
example, Sin(Φ) = -1/64, the word to be stored should be 1000 0010. Here “1” at the MSB
location indicates that the number is negative. As seen in the block diagram of Fig.37.4, each
EPROM output is fed to a D/A (Digital to Analog) converter to finally come up with analog
value of Sin(Φ). Now in the D/A converter, the sign bit is not to be fed. The MSB input of
D/A could be grounded. A separate simple logic circuit could take the MSB output of
EPROM for sign changing of the D/A output. One such simple arrangement (Fig.37.5) uses
an analog switch, an op-amp and a few resistors to assign correct sign to the analog output of
the D/A converter.

R Sign
Corrected
R -
D/A output
O/P Op-
+ Amp
of
D/A
Analog
Switch
1 = ON MSB of

GND
0 = Off { EPROM

Fig.37.5: A simple sign corrector Circuit

As mentioned earlier, an alternative arrangement for storing data in the EPROM could be to store
[1+ Sin(Φ)] value in the memory locations so that negative numbers are not encountered. While
decoding the digital value into analog form (using Digital to Analog converter) the analog
equivalent of this extra “1” may be subtracted using a simple Op-amp based subtractor circuit.
In the circuit of Fig.37.4, a control voltage VC is applied to a voltage to frequency (V/f) converter. The
V/f converter should preferably have a linear relation between the applied voltage and output
10
frequency. The V/f converter output is fed as clock to a divide by 2 ripple counter circuit. Ten
address lines for the 1K EPROM are connected to the ten output lines of the ripple counter. For a 2K
11
EPROM eleven address lines are required and the appropriate counter would then be a divide by 2
counter. The consecutive clock pulses to the ripple counter increment the EPROM’s address word
sequentially, pointing to the next EPROM memory location after each clock. The EPROM outputs
data of the addressed memory location asynchronously. Since the SINE wave data is loaded in the
EPROM sequentially, the digital value of SINE wave is output by the EPROM in the correct
sequence. The D/A converter then converts the EPROM output into an analog signal. The SINE
wave output by D/A converter is however only a stepped approximation of the continuous SINE
wave but the number of steps per sine-wave cycle being large (=612), the resolution is sufficient for
the present purpose. The Address lines for the two EPROMs are tied together. Thus when, say, first
memory location of EPROM#1 is addressed the first location of EPROM#2 is also simultaneously
0
addressed. The SINE waves stored in the two EPROMs are phase shifted by 120 and hence the
0
corresponding D/A converters output 120 shifted SINE waves. The ten -bit address word generated
by ripple counter repeats after 1024 counts and accordingly SINE wave data from the EPROMs are
also repeated after 1024 counts (this count represents one output cycle time period of the sinusoidal
modulating wave). The rate at which the address bus data changes decides the frequency of the
output waveform, which eventually is controlled by the control voltage VC. D/A converters have
reference voltage (+VRef and - VRef) pins provided for setting the maximum and minimum
excursion of the output voltage waveform. In the circuit of Fig.37.4, it is assumed that -VRef pins are
grounded and +VRef pins are connected to the reference voltage ‘VM’. Thus ‘VM’ decides the
magnitude of analog sinusoidal signal output by the D/A converter. The magnitude control signal
‘VM’ may be tied to frequency control signal ‘VC’ and one may achieve proportional change in
inverter’s output voltage and frequency. The circuit in Fig.37.4 produces two SINE waveforms
0
having identical magnitude and frequency but phase shifted by 120 . The third modulating SINE
wave could be generated simply by adding these two waveforms followed by a sign inversion.
0 0
[Sin(Φ) + Sin(Φ-120 ) = - Sin(Φ-240 )]. Thus a simple circuit using a couple of op-amps will get
the third SINE wave.High frequency triangular carrier waveform generator and comparator etc. are
pretty simple circuits to realize. The comparator output gives the required PWM pattern. The output
frequency (as well as magnitude) can be varied in an open-loop or closed-loop by varying the control
voltages VC and VM.

Question for Practice

Choose the Best Answer

1 The over-modulation of sine-PWM inverter is generally avoided because it

introduces:
a. lower frequency harmonics in the inverter output waveform
b. non-linearity between the magnitudes of modulating signal and fundamental
voltage output by the inverter
c. both the above
d. none of the above

2 A three-phase sine-PWM inverter operates from a dc link voltage of 600 volts. For
modulation index = 1.0 the rms magnitude of line voltage of fundamental frequency
will be equal to:
a. 600 volts
b. nearly 367 volts
c. nearly 481 volts
d. nearly 581 volts

3 The carrier waveform of a sine-modulated PWM inverter is of 10 kHz frequency.

When the fundamental output frequency of the inverter is 50 Hz, the inverter
switches need to be turned-on and turned-off at a rate of
a. 1000 times per second
b. 10,000 times per second
c. 50,000 times per second
d. 50 times per second
 4 A three-phase sine-modulated PWM inverter is used to get a balanced 3-phase
fundamental output voltage. The modulating waveforms must have
i. Three DC signals of identical magnitude
ii. Three balanced ac signals of fundamental frequency
iii. Three identical and in-phase ac signals of fundamental frequency
iv. Three balanced ac signals of carrier frequency

Answers
1-c, 2-b, 3-b, 4-b.

7.0 Current Source Inverter

Objectives
We will be able

The circuit for single-phase Current Source Inverter (CSI) using thyristors

Auto-Sequential Commutated mode of operation for 1-ph. Inverter (ASCI), with
waveforms

Three-phase Current Source Inverter (CSI) − circuit and operation, with
waveforms

7.1 Introduction
In the previous six (5.1-5.6) lessons in this module, the circuit and operation of single-phase
and three-phase Voltage Source Inverters (VSI), with waveforms, were described in detail. Also,
the presence of harmonics in voltage waveforms, along with its reduction mainly by Pulse Width
Modulation (PWM) techniques, was presented. Presently, mainly self-commutated switching
devices, like say transistors, are used in the above circuits, replacing thyristors, with bulky
commutation circuits needed to turn them OFF, these being force-commutated ones. In the last
two (5.7-5.8) lessons in this module, the circuit and operation of different types of single-phase
and three-phase Current Source Inverters (CSI), with waveforms, will be described in detail. The
device used here is thyristor. In this lesson (5.7), initially, the circuit of single-phase CSI will be
presented. The Auto-Sequential Commutated mode of operation for this Inverter (ASCI), using
thyristors, will be discussed in detail, with waveforms. Then, the circuit and operation of three-
phase CSI, along with relevant waveforms, will be presented. Finally, the advantages and
disadvantages of CSI over VSI, in brief, are described
For the VSI, as the full form denotes, the output voltage is constant, with the output current
changing with the load − type, and/or the values of the components. But in the CSI, the current is
nearly constant. The voltage changes here, as the load is changed. In an Induction motor, the
developed torque changes with the change in the load torque, the speed being constant, with no
acceleration/deceleration. The input current in the motor also changes, with the input voltage
being constant. So, the CSI, where current, but not the voltage, is the main point of interest, is
used to drive such motors, with the load torque changing.
Keywords: Single-phase and Three-phase Current Source Inverter (CSI), ASCI mode of
operation, CSI using thyristors
Single-phase Current Source Inverter
I a

Th1
C1 = C/2 Th2
a + - I

I D1 I D2
L'

+
Load (L)
D3
VS D4
+ -
b I
C2 = C/2
Th4 Th3

b
Fig. 39.1: Single phase current source inverter (CSI) of ASCI type.

The circuit of a Single-phase Current Source Inverter (CSI) is shown in Fig. 39.1. The type
of operation is termed as Auto-Sequential Commutated Inverter (ASCI). A constant current
source is assumed here, which may be realized by using an inductance of suitable value, which
must be high, in series with the current limited dc voltage source. The thyristor pairs, Th1 & Th3,
and Th2 & Th4, are alternatively turned ON to obtain a nearly square wave current waveform.
Two commutating capacitors − C1 in the upper half, and C2 in the lower half, are used. Four
diodes, D1–D4 are connected in series with each thyristor to prevent the commutating capacitors
from discharging into the load. The output frequency of the inverter is controlled in the usual
way, i.e., by varying the half time period, (T/2), at which the thyristors in pair are triggered by
pulses being fed to the respective gates by the control circuit, to turn them ON, as can be
observed from the waveforms (Fig. 39.2) . The inductance (L) is taken as the load in this case,
the reason(s) for which need not be stated, being well known. The operation is explained by two
modes.
 ig1,
ig3

0
T/2 T
ig2,
ig4

0
T/2 T

VCo

vC

0
t T/2 T
-VCo
t2 t1

i0
0
T/2 T

-I

I iC1 iD1 iD2

i01,
iD

0
T/2 T

-I

Th1 & Th3 Th2 & Th4 Th1 & Th3

triggered triggered triggered
Fig. 39.2: Voltage and current waveforms

Mode I: The circuit for this mode is shown in Fig. 39.3. The following are the assumptions.
 −
Starting from the instant, t = 0 , the thyristor pair, Th2 & Th4, is conducting (ON), and the
current (I) flows through the path, Th2, D2, load (L), D4, Th4, and source, I. The commutating
capacitors are initially charged equally with the polarity as given, i.e., vC1 = vC 2 = −VC 0 . This
mans that both capacitors have right hand plate positive and left hand plate negative. If two
capacitors are not charged initially, they have to pre-charged.
I a

I Th1 Th2
e - + f
C1=C/2 I
D1 D2
I c d
L I
D4 D3
I - +
g h

Th4 C2=C/2 Th3

I

b
Fig. 39.3: Mode I (1 phase CSI)
At time, t = 0, thyristor pair, Th1 & Th3, is triggered by pulses at the gates. The conducting
thyristor pair, Th2 & Th4, is turned OFF by application of reverse capacitor voltages. Now,
thyristor pair, Th1 & Th3, conducts current (I). The current path is through Th1, C1, D2, L, D4,
C2, Th3, and source, I. Both capacitors will now begin charging linearly from ( −VC 0 ) by the
constant current, I. The diodes, D2 & D4, remain reverse biased initially. The voltage, vD1 across
D1, when it is forward biased, is obtained by going through the closed path, abcda

∫
as vD1 +Vco −(1/(C / 2)) I dt = 0 It may be noted the voltage across load inductance, L is zero
(0), as the current, I is constant. So, vD1 = −Vco + (2 / C) ∫I dt
As the capacitor gets charged, the voltage vD1 across D1, increases linearly. At some time,
say t1, the reverse bias across D1 becomes zero (0), the diode, D1.starts conducting. An identical
equation can be formed for diode, D3 also. Actually, both diodes, D1 & D3, start conducting at the
same instant, t1. The time t1 for which the diodes, D1 & D3, remain reverse biased is obtained by
equating, vD1 = −Vco +((2 I t1 ) / C)= 0 . The time is given by, t1 = (C /(2 I )) VC 0 . The
capacitor voltages vC1 = vC 2 = vC , appear as reverse voltage across the thyristors, Th2 & Th4,
when the thyristors, Th1 & Th3, are triggered. The value of vC is
v =v
C1
v =v
C 2 = vC = −Vco + (2 / C) ∫I dt , which, if computed at t = t1 , comes out as,
C1 C 2 = vC (t1 ) = −Vco +((2 I t1 ) / C)= −Vco +((2 I ) / C) (C /(2 I )) VC 0 = 0 ,
using the value of t1 obtained earlier. This means that the voltages across C1 & C2, varies
linearly from −VC 0 to zero in time, t1. Mode I ends, when t = t1 , and vC = 0 . Note that t1 is the
circuit turn-off time for the thyristors.

I Th1 Th2
+ - iC1
e
f
C1=C/2
D1 D2
L
I c d
i0

D4 C+2=C/2- D3
g h
iC2
Th4 Th3
I

b
Fig. 39.4(a): Mode II (1-phase CSI)

I + C-
e (g)
f (h)
I ie

c i0
d
L
I

Fig. 39.4(b): Equivalent circuit for mode II

Mode II: The circuit for this mode is shown in Fig. 39.4a. Diodes, D2 & D4, are already
conducting, but at t = t1 , diodes, D1 & D3, get forward biased, and start conducting. Thus, at the
end of time t1, all four diodes, D1–D4 conduct. As a result, the commutating capacitors now get
connected in parallel with the load (L). For simplicity in analysis, the circuit is redrawn as
shown in Fig. 39.4b, where the equivalent capacitor is C / 2 , as C1 = C2 = C . The equation for
the current at the node is, I +i0 = iC (= iC1 +iC 2 ) , where, iC1 = iC 2 = iC / 2 The voltage balance
equation is,
di 0

∫
L dt = −(1/ C) iC dt = = −(1/ C) (I +i0 ) dt
2 2
∫
d i 0i I d i i I
or, L + 0
=− or, + =− 0 0

2 2
dt C C dt (L C) (L C)
2
d i0
or, (L C) 2 +i0 = −I
dt
The solution of the equation is, i0 = A cos (ω0 t) + B sin (ω0 t) + K ,
where, A, B & K are constants, natural frequency,
f0 =1/ (2 π) ( )
(L C) , ω0 = (2 π) f0 =1/ (L C) , and time period,
T =1/ f0 = (2 π) /ω0 = (2 π) (L C) .
The initial conditions at t = 0 are, i0 = I and di0 / dt = 0 . It should be noted that the time, t is
measured from the instant, the diodes, D1 & D3, start coducting, i.e., from the instant, mode I is
over. Using the initial conditions stated earlier, the current is, i0 = I (2 cos(ω0 t) −1). The
capacitor current is iC = I +i0 = 2 I cos(ω0 t) .
1 2 I
The voltage across capacitor is, vC = iC dt = sin (ω0 t) .
∫
ω C
C 0

This expression can also be obtained as,

vC = vL = L (di0 / dt) = ((2 I ) (ω0 L)) sin (ω0 t) , where, ω0 L =1/(ω0 C) , as can be
derived using ω0 =1/ (L C) . So, the above expressions are same, and can be written as,
( )
vC = (2 I ) ( L / C ) sin (ω0 t) , substituting the expression for ω0 in any of the above
expressions. So, iC1 = iC 2 = I cos(ω0 t) , and
iD1 = I −iC1 = I (cos(ω0 t) −1), in the interval 0 < t < t2 .
As the current, iC1 tends to reverse, diode, D3 prevents its reversal. Similarly, the diode, D4
prevents the reversal of the current, iC 2 . From the initiation of mode II, a time, t2 must elapse for
the current, iC1 to become zero (0). The time, t2 is,
t = (π / 2) /ω0 = (π / 2) (L C) = (1/(4 f0 ))= T / 4 , as (ω0 t2 ) = (π / 2) , using,
i2
C1 = I cos(ω0 t2 ) = 0 . The capacitor voltage at time, t2 is, vC = ((2 I ) /(ω0 C))=VC 0 . Note
that this is also the maximum value. Now, the load current is, i0 = I (2 −1) = I . This shows that
the load current has reversed from +I to –I during mode II, after time, t2. It is also seen that the
capacitor voltage changes by 2 VC0 (from −VC 0 to VC 0 ) during each commutation interval. The
time t1 , after substituting VC 0 , comes out as,
t1 = (C /(2 I ) VC 0 = (C /(2 I ) ((2 I ) /(ω0 C))=1/ω0 = (L C) .
The total commutation interval is, tc = t1 +t2 = (1+ (π / 2))/ω0 = (1 +(π / 2)) (L C) .
 At the end of the process, constant current flows in the path, Th1, D1, load (L), D3, Th3, and
source, I. This continues till the next commutation process is initiated by the triggering of the
thyristor pair, Th2 & Th4.
The complete commutation process is summarized here. The process (mode I) starts with the
triggering of the thyristor pair, Th1 & Th3. Earlier, the thyristor pair, Th2 & Th4 were conducting.
With the two commutating capacitors charged earlier with the polarity as shown (Fig. 39.3), the
conducting thyristor pair, Th2 & Th4 turns off by the application of reverse voltage. Then, the
voltages across the capacitors decrease to zero at time, t1 (end of mode I), as constant (source)
current, I flows in the opposite direction. Mode II now starts (Fig. 39.4a), as the diodes, D1 &
D3, get forward biased, and start conducting. So, all four diodes D1-D4, conduct, and the load
inductance, L is now connected in parallel with the two commutating capacitors. The current in
the load reverses to the value –I, after time, t2 (end of mode II), and the two capacitors also are
charged to the same voltage in the reverse direction, the magnitude remaining same, as it was
before the start of the process of commutation (t = 0). It may be noted that the constant current, I
flows in the direction as shown, a part of which flows in the two capacitors.
In the above discussion, one form of load, i.e. inductance L only, has been considered. The
procedure remains nearly same, if the load consists of resistance, R only. The procedure in mode
I, is same, but in mode II, the load resistance, R is connected in parallel with the two
commutating capacitors. The direction of the current, I remains same, a part of which flows in
the two capacitors, charging them in the reverse direction, as shown earlier. The derivation,
being simple, is not included here. It is available in books on this subject.
6.2 Three-phase Current Source Inverter
X
+

Th1 Th3 Th5

C1 C3

D1 C5 D3 D5
L
iA
A L R R
B iB
Vdc N
iC
R
C
D4 D6 D2
L
C4 C6

Th4 C2 Th6 Th2

-
Y
Fig. 39.5(a): Three-phase current source inverter (CSI)
 The circuit of a Three-phase Current Source Inverter (CSI) is shown in Fig. 39.5a. The type
of operation in this case is also same here, i.e. Auto-Sequential Commutated Inverter (ASCI). As
in the circuit of a single-phase CSI, the input is also a constant current source. The output current
(phase) waveforms are shown in Fig. 39.5b. In this circuit, six thyristors, two in each of three
arms, are used, as in a three-phase VSI. Also, six diodes, each one in series with the respective
thyristor, are needed here, as used for single-phase CSI. Six capacitors, three each in two (top
and bottom) halves, are used for commutation. It may be noted that six capacitors are equal, i.e.
C1 = C2 = = C6 = C . The diodes are needed in CSI, so as to prevent the capacitors from
discharging into the load. The numbering scheme for the thyristors and diodes are same, as used
in a three-phase VSI, with the thyristors being triggered in sequence as per number assigned
(Fig. 39.5b).
 I
iA
180° 300°
0
120° 360°
θ
-I

I
IB 120°
300° 360°
0
240°
60°
-I

I
IC
60° 180°
0
240° 360°

-I

on Th1 Th2 Th3 Th4 Th5 Th6 Th1

off
Th5 Th6 Th1 Th2 Th3 Th4 Th5

Th1 Th1 Th3 Th3 Th5 Th5 Th1

Th6 Th2 Th2 Th4 Th4 Th6 Th6

0
60° 120° 180° 240° 300° 360°
Thyristors conducting
Fig. 39.5(b): Phase current waveforms
 The commutation process in a three-phase CSI is described in brief. The circuit, when two
thyristors, Th1 & Th2 , and the respective diodes, are conducting, is shown in Fig. 39.6a. The
current is flowing in two phases, A & C. The three capacitors in the top half, are charged
previously, or have to pre-charged as shown. But the capacitors in the bottom half are not shown.
I X
+
L′
Th1 Th3 Th5
C1 C3
+ - - +
I

D1 + - D3 D5
C5
I (iA)
A A
B
C
I (iC)
D2
I Th2

-
I
Y
Fig. 39.6(a): Three-phase CSI with two thyristors, Th1 & Th2 conducting
Mode I: The commutation process starts, when the thyristor, Th3 in the top half, is triggered, i.e.
pulse is fed at its gate. Immediately after this, the conducting thyristor, Th 1 turns off by the
application of reverse voltage of the equivalent capacitor. Mode I (Fig. 39.6b) now starts. As the
diode D1 is still conducting, the current path is via Th3, the equivalent capacitor, D1, and the load in
phase A (only in the top half). The other part, i.e. the bottom half and the source, is not considered
here, as the path there remains same. The current, I from the source now flows in the reverse
direction, thus the voltage in the capacitor, C1 (and also the other two) decreases. It may be noted the
equivalent capacitor is the parallel combination of the capacitor, C1 and the other part, being the
series combination of the capacitors, C3 & C5 ( C′ = C / 2 ). It may be shown the its
value is Ceq = C / 3 , parallel combination of C & C / 2 , as C1 = C3 = C5 = C . Also, the current
in the capacitor, C1 is (2 / 3) I , and the current in other two capacitors, C3 & C5 is I / 3 . When
the voltage across the capacitor, C1 (and also the other two) decreases to zero, the mode I ends.
 I X

L′ I
Th1 2I/3 C1 Th3 C3 I/3 Th5
+ - - +
I

+ -
D1 C5 D3 I/3 D5
I (iA)
A
B
C
I (iC)
D2

I
Th2

I
Y
Fig. 39.6(b): Mode I (3-phase CSI)

Mode II: After the end of mode I, the voltage across the diode, D3 goes positive, as the voltage
across the equivalent capacitor goes negative, assuming that initially (start of mode I) the voltage was
positive. It may be noted that the current through the equivalent capacitor continues to flow in the
same direction. Mode II (Fig. 39.6c) starts. Earlier, the diode, D1 was conducting. The diode, D3 now
starts conducting, with the voltage across it being positive as given earlier. A circulating current path
now exists between the equivalent capacitor, two conducting diodes, D1 & D3 and the load (assumed
to be inductive − R & L, per phase) of the two phases, A & B, the two loads and also the two diodes
being now connected in series across the equivalent capacitor. The current in this path is oscillatory,
and goes to zero after some time, when the mode II ends. The diode, D1 turns off, as the current goes
to zero. So, at the end of mode II, the thyristor, Th3 & the diode, D3 conduct. This process has been
described in detail in the earlier section on single-phase CSI (see mode II). It may be noted that the
polarity of the voltage across the equivalent capacitor (at the end of mode II) has reversed from the
initial voltage (at the beginning of mode I). This is needed to turn off the outgoing (conducting)
thyristor, Th3, when the incoming thyristor, Th5 is triggered. The complete commutation process as
described will be repeated. The diodes in the circuit prevent the voltage across the capacitors
discharging through the load.
 I X
+
L′
I
Th1 Th3 Th5
- + + -

C1 C3
- +
D1 C5 D3 D5
iA
A
iB B
C
I (iC)
D2

I
Th2

-
Y I

Fig. 39.6(c): Mode II (3-phase CSI)

The circuit is shown in Fig. 39.6d, with two thyristors, Th3 & Th2, and the respective diodes
conducting. The current now flows in two phases, B & C, at the end of the commutation process,
instead of phase A at the beginning (Fig. 39.6a). It may be noted the current in the bottom half
(phase C) continues to flow, and also the thyristor, Th2 & the diode, D2 remain in conduction
mode. This, in brief, is the commutation process, when the thyristor, Th3 is triggered and the
current is transferred to the thyristor, Th3 & the diode, D3 (phase B), from the thyristor, Th1 &
the diode, D1 (phase A).
 I
+
L′ I
Th1 Th3 Th5

- C1 + + -

C3
-
C5 +
D1 I D3 D5

I (iB) A
B B
C C
I (iC)
D2
I
Th2

-
Y I

Fig. 39.6(d): Three-phase CSI with two thyristors, Th3 & Th2 conducting

Comments
In the introductory remarks, one merit of CSI has been stated, i.e. it can be used for the speed
control of ac, specially induction, motors subject to variation in load torque. In recent years, self-
commutated power switching devices, such as power transistors etc., are being used in VSI, but
not costly inverter-grade thyristors (having low turn-off time), along with bulky commutation
circuits. These circuits also need additional diodes for feeding the reactive power back to the
supply, when used with heavily inductive loads. The advantages and disadvantages of CSI vis-à-
vis VSI are given.
Advantages
7 The circuit for CSI, using only converter grade thyristor, which should have reverse
blocking capability, and also able to withstand high voltage spikes during commutation, is
simple.
8 An output short circuit or simultaneous conduction in an inverter arm is controlled by the
‘controlled current source’ used here, i.e., a current limited voltage source in series with a
large inductance.
9 The converter-inverter combined configuration has inherent four-quadrant operation
capability without any extra power component.
Disadvantages
5 A minimum load at the output is required, and the commutation capability is dependant
upon load current. This limits the operating frequency, and also puts a limitation on its use
for UPS systems.
6 At light loads, and high frequency, these inverters have sluggish performance and
stability problems.
In this lesson − the seventh one of this module, the current source inverter (CSI) vis-à-vis
VSI, is introduced. The commutation process for Auto-Sequential Commutated Inverter (ASCI)
mode of operation in single-phase CSI, is mainly described, along with circuit diagram and
relevant waveforms, in detail. Then, the commutation process for the same mode of operation,
i.e. ASCI, in three-phase CSI, is described, along with various circuit diagrams, in brief. Finally,
the advantages and disadvantages of CSI over VSI, are presented. In the next lesson, eighth and
last one, of this module, the load-commutated CSI, and also the Pulse Width Modulation (PWM)
techniques used in CSI, will be discussed.

7.0 Load-commutated Current Source Inverter (CSI)

Objectives
The circuit and operation for Load-commutated Current Source Inverter (CSI)

Introduction
In the last lesson (5.7) – seventh one in this module, the circuit and operation of single-phase
and three-phase Current Source Inverters (CSI), with relevant waveforms, have been described in
detail. The device used is thyristor. The type is the Auto-Sequential Commutated Inverter
(ASCI). In this lesson (5.8) – eighth and final one in this module, the circuit and operation of
load-commuted CSI, including waveforms, will be presented in detail.
Keywords: Load-commutated current source inverter (CSI)

Load-Commutated CSI
In the last lesson, ASCI mode of operation for a single -phase Current Source Inverter (CSI)
was presented. Two commutating capacitors, along with four diodes, are used in the above
circuit for commutation from one pair of thyristors to the second pair. Earlier, also in VSI, if the
load is capacitive, it was shown that forced commutation may not be needed. The operation of a
single-phase CSI with capacitive load (Fig. 40.1) is discussed here. It may be noted that the
capacitor, C is assumed to be in parallel with resistive load (R). The capacitor, C is used for
storing the charge, or voltage, to be used to force-commutate the conducting thyristor pair as will
be shown. As was the case in the last lesson, a constant current source, or a voltage source with
large inductance, is used as the input to the circuit.
+ a
i
Th1 Th2
iC

C
+ - i
 c v0
I Vin d
= vC

Load (R)
Th3
Th4

- b

Fig. 40.1: Load-commuted CSI

The power switching devices used here is the same, i.e. four thyristors only in a full- bridge
configuration. The positive direction for load current and voltage, is shown in Fig. 40.1. Before t
= 0, the capacitor voltage is vC = −V1 , i.e. the capacitor has left plate negative and right plate
positive. At that time, the thyristor pair, Th2 & Th4 was conducting. When (at t = 0), the thyristor
pair, Th1 & Th3 is triggered by the pulses fed at the gates, the conducting thyristor pair, Th2 & Th4 is
reverse biased by the capacitor voltage vC = −V1 , and turns off immediately. The current path is
through Th1, load (parallel combination of R & C), Th3, and the source. The current in the thyristors
is iTh1 = iTh3 = I , the output current is iac = I ; the capacitor voltage, vC changes from
−V1 to V1 , as the capacitor gets charged by the current iC during the time, (T / 2) > t > 0 . The
load voltage is v0 = vC . Thus, the waveform of the current, i0 = (v0 / R) = (vC / R) through load
resistance, R has the same nature as that of vC (Fig. 40.2). Similarly, when (at t = T / 2 ), the
thyristor pair, Th2 & Th4 is triggered by the pulses fed at the gates, the conducting thyristor pair,
Th1 & Th3 is reverse biased by the capacitor voltage vC =V1 , and turns off immediately. The
current path is through Th2, load (parallel combination of R & C), Th4, and the source. The
current in the thyristors is iTh2 = iTh4 = I , but the output current is iac = −I ; the capacitor
voltage, vC changes from V1 to −V1 , as the capacitor gets charged by the current iC during the
time, T > t > (T / 2) .
 ig1,
ig3
0 T/2 T I
iTh1,
ig2,
iTh3
ig4
0 t T/2 T 0 T/2 T

I1, I
iTh2,
v0, V1
iTh4
i0 0
T/2 T 0 T/2 T
-I1,
-V1,

I+I1 I

I-I1 iac
0 T/2 T
0
iC T/2 T
-I
-(I-I1)
Th1, Th3 Th2, Th4
-(I+I1)
Th1, Th3 Th2, Th4 Th1, Th3
triggered triggered triggered
V1

vin
0
T/2 T

-V1

V1
vTh1,

vTh3

0 T/2 T
-V1

Fig. 40.2: Voltage and current waveforms.

 Various current and voltage waveforms during one cycle T > t > 0 , are shown in Fig. 40.2.
At t = 0, the capacitor voltage is vC = −V1 , then v0 = vC = −V1 , and the load current through R is
i0 = −(V1 / R) = −I1 . As stated earlier, during the time (T / 2) > t > 0 , the capacitor gets charged,
with its voltage changing from −V1 to V1 . So, At t = T / 2 , the load current is
v
i0 = (vC / R) = (v0 / R) = (V1 / R) = I1 . The input voltage is in = v0 , during (T / 2) > t > 0 , and
v
in = −v0 , during T > t > (T / 2) .

It may be observed that, when the thyristor pair, Th1 & Th3 is conducting for (T / 2) > t > 0 ,
the currents iC , i0 are leaving node A (Fig. 40.1), and the current, I is entering node A.
Therefore, the equivalent circuit for (T / 2) > t > 0 , is shown in Fig. 40.3a. The current in node A,
is iC +i0 = I or, iC = I −i0 . At t = 0, i0 = −I1 , and iC = I + I1 . The mathematical steps for a steady
solution of the output current, and other parameters, such as input voltage etc., are given later.
Just after (T/2), when the thyristor pair, Th2 & Th4 is conducting, the currents iC , i0 are entering
node B (Fig. 40.1), and so also the current, I. The equivalent circuit for T > t > (T / 2) ,
is shown in Fig. 40.3b. The current in node B is iC +i0 + I = 0 or, iC = −(I +i0 ) . At t = (T/2),
i0 = I1 , and iC = −(I + I1 ) . The cycle repeats itself.

I c (a) - I c (a) +
i0 iC i0 i C

I
I
R v0 = vC V
R v0 = vC V1 1

C C

-
d (b) + d (b)
(a) (b)

Fig. 40.3: (a) Equivalent circuit for 0 < t < T/2

(b) Equivalent circuit for T/2 < t < T

The steps to be followed to find the expression of the output current, and other parameters
are described. The voltage balance equation for the equivalent circuit (Fig. 40.3a) is,
∫
R i0 − (1/ C) (I −i0 ) dt + v1 =0
di i I
0 0 =
Differentiating it, we get R dt + C C
Solving it, with the initial condition for i0 as given earlier,
−t /( R C ) −t /( R C )
i0 = I (1 −e )− I1 e
To arrive at a steady solution only, the following steps are followed. At t = (T/2), the current is
i0 = I1 , as shown later. So, I1 = I (1−e−T /(2 R C ) )− I1 e
−T /(2 R C )

1 −e−T /(2 R C )
=I
or, I1 = I −T /(2 R C ) , if (T /(2 R C))>>1 or, T >> (R C)

1+e
6
So, using the above expression, the output current, or the current in resistance, R comes out as,

i0 = I 1 − 2 (e−t /( R C ) ) −T /(2 R C )

1+e
The output voltage v0 , or the capacitor voltage vC is,
2 (e −t /( R C ) )
v0 = vC = i0 R = (R I ) 1 − + −
1 e T /(2 R C )
The turn-off time provided by the circuit for each thyristor is obtained from the condition that,
when t =tOFF , v0 = vC = i0 R = 0 . So,

2 (e
− tOFF /( R C )
)
v =v =i R =( R I ) 1− =0

0 C 0 1+e
− T /(2 RC )

− t /( R C ) − T /(2 R C )
or, e OFF
= (1 +e )/ 2
or, t = ( R C ) log 2 = − ( R C ) log 1+e− T /(2 R C ) /2
OFF e 1 +e− T /(2 R C ) e ( )
The average value of the input voltage, Vin is,
1 T/2 2 I R T/2 2 (e −t /( R C ) )
V in = (i R) dt = 1− dt
∫ 0 ∫ −
T /(2 R C )

T/2 0 T 0 1+e
4 R C 1 −e −T /(2 R C )
or, V = (I R) 1 −
in −T /(2 R C )

T 1+e
When the input power (Vin I ) is positive, power is delivered to the load.
The following points may be noted.
1. It may be observed from the equation given earlier that, as the inverter frequency ( f =1/ T )
is increased, the turn-off time provided by the circuit decreases. But, the circuit commutation
time, toff , should be more than the turn-off time of the thyristor, tq , for reliable operation.
This means that there is an upper limit to the inverter frequency, beyond which the thyristors
in the inverter circuit will fail to commutate.
2. When the inverter frequency ( f =1/ T ) is low, or time period, T is high, the graph of i0 (t)
or v0 (t) as given in Fig. 40.2, becomes flatter as shown by dotted line in Fig. 40.4. As this
graph is nearer to a square wave, it can be inferred that, for low inverter frequencies, the
inverter has square wave output for load current or load voltage ( i0 / v0 ).
When the inverter frequency ( f =1/ T ) is high, or time period, T is low, the waveform
of v0 or i0 is shown by full line in Fig. 40.4. As this graph is closer to a sine wave, it can be
noted that, for higher frequency, the CSI has sinusoidal wave shape for load (output) current
or voltage.
 v0, i0
Small T

Large T
T
T/2 t

Fig. 40.4: Waveforms for CSI with resistive (R) load

(a) Square wave output: It has been found that, for obtaining square wave of the load current,
T /(2 R C) > 5.0 . If tq is the turn-off time for the thyristors used in CSI, then form the
equation given earlier,
−5
tq = (R C) loge (2 /(1 + e ))≈ (R C) loge 2 = 0.69 (R C)
or, C = tq /(0.69 R)
For T /(2 R C) = 5.0 or T =10 R C , the maximum frequency is,
fmax =1/ T =1/(10 R C)
Substituting the value of C obtained earlier, fmax = 0.069 / tq
(b) Sinusoidal wave output: For obtaining sinusoidal wave of the load current, the capacitive
reactance, X C at three times the minimum frequency, fmin , should be lower than R / 2 , i.e.,
at 3 f , X = 1 ≤
R
,
min C 2π 3 f min C 2
or C ≥ 0.106 /(R fmin)
The inverter should therefore be operated at frequencies higher than f min in order to obtain
the sinusoidal wave shape.

In this lesson (5.8) – eighth and final one in this (last) module (5), the circuit and operation,
of load-commuted CSI, including waveforms, are discussed in detail. In this module (5), mainly
two types of dc-ac converters, termed as inverters – Voltage Source (VSI) and Current Source
(CSI), have been presented. Both single-phase and three-phase inverters have been described,
with relevant waveforms. Starting with the use of Pulse Width Modulation (PWM) techniques,
used for voltage control in VSI, other variations, such as Sine PWM, have been taken up.
Incidentally, this is the last lesson for the course on ‘Power Electronics’.
8.0 Power Factor, Improvement, Harmonic
Reduction, Filter
Objectives
We will be able to know
o Schemes for the improvement of power factor in AC-DC converters.
o Methods for harmonic reduction in the current waveforms of the
converters.
o Types of filters used to obtain ripple free (dc) output voltage and
currents, reducing the harmonics.

8.1 Introduction
After the discussion of various types of ac to dc converters (rectifiers), both single-
and three-phase, in the lessons (#2.1-2.6) of this module (# 2), the drop in the output
voltage due to the commutation overlap in the converter, was presented, the inductance
on the source (ac) side being taken into account, in the previous lesson (#2.7).
In this (last) lesson (#2.8), three important points – power factor improvement,
harmonic reduction, and filters, as applicable to converters, are described. The three
schemes for power factor improvement are discussed. Then, the use of various filters to
reduce the harmonics in the output voltage and current waveforms, are presented. Lastly,
the harmonic reduction techniques are taken up, in brief. In all these cases, the circuit of a
single phase full wave half (semi) controlled bridge converter (ac-dc) is used mostly as an
example.
8.2 Power Factor Improvement
For phase-controlled operation in both single phase full wave half and full controlled
bridge converters as discussed in this module (#2), the displacement factor (or power
factor, which is lagging) decreases, as the average value of output voltage (Vdc)
decreases, with the increase in firing angle delay, . This is also applicable for both three
phase half wave and full wave (bridge) converters. The three schemes used for power
factor (pf) improvement are:

+ Extinction angle control

+ Symmetrical angle control
+ Pulse width modulation (PWM) control

8.3 Extinction Angle Control

 The circuit diagram of a single phase full wave half-controlled (semi) force-
commutated bridge converter is shown in Fig. 16.1(a). The thyristors, T1 & T2, are
replaced by the switches, self-commutated devices, such as power transistor or
equivalent. The power transistor is turned on by applying a signal at the base, and turned
off by withdrawing the signal at the base. A gate turn-off thyristor (GTO) also may be
used, in which case, it may be turned off by applying a short negative pulse to its gate, but
is turned on by a short positive pulse, like a thyristor.
In extinction angle control, switch, S1 is turned on at t 0 , and then turned off by
forced commutation at t π . The switch, S2 is turned on at t , and then turned off at t
2 π . The output voltage is controlled by varying the extinction angle, . Fig. 16.1(b) shows
the waveforms for input voltage, output voltage, input current, and the current through
thyristor switches. The fundamental component of input current leads the input voltage,
and the displacement factor (and power factor) is leading. This feature may be desirable
to simulate a capacitive load, thus compensating the line voltage drops.

iT1
+
S1 S2 i0 = Ia
v0
+ is iT2 L
vs DF
O

- A
D
D2 D1
iDF
-
(a) Circuit
 vs
vs = Vmsin t
Vm
π
t
0 2π

v0

t
0 π- π 2π - 2π
iT1
Ia
t
0 π 2π
π- 3π -
Ia iT2
t
π 2π -
0 iDF Ia

t
π- π 2π - 2π
0 i
s is1
Ia 2π - t
π- π 2π 3π -
0
io
- Ia
Load current
Ia
 t
0
(b) Waveforms for extinction angle control
Fig. 16.1 Single-phase forced-commutated semi-
converter.

The average output voltage is

2 2
π∫
π-
Vdc = 2 2Vsin t d t =
0 V 1 + cos π
The value of Vdc is varied from (2 2 / π)V to 0, as varies from 0 to π.
The rms value of output voltage is

V
o
= 2∫ 0
π- 2 2
2V sin t d t
12

=V
1
π
1
sin 2
12

2π π 2

Here also, Vo varies from V to 0.

This scheme of extinction angle control can also be used for single phase full wave full
controlled bridge converter with four switches, instead of two needed in the earlier case.
The students are requested-to study this matter form text books, but details are not
included here.

8.4 Symmetrical Angle Control

This control can be applied for the same half-controlled force commutated bridge
converter
turne
with two switches, S1 and S2 as shown in Fig. 16.1(a). The switch, S1 is d on at
2 and then 2 . The other switch, turne
t π turned off at t S2
is d on at
2 . The output voltage is varied by
t 3π 2 and then turned off at t 3 varying
conduction angle, . The gate signals are generated by comparing half-sine waves with a
dc signal as shown in Fig. 16.2(b). The half-sine waves can be obtained using a full wave
diode (uncontrolled) bridge converter. The gate signals can also be generated by
comparing triangular waves with a dc signal as shown in Fig. 16.2(c). In the second case,
the conduction angle varies linearly with the dc signals, but in inverse ratio, i.e., when the
dc signal is zero, full conduction
takes place, and the dc signal being same as the peak of the triangular reference signal,
no conduction 0 takes place. Fig. 16.2(a) shows the waveforms for input voltage,
output
voltage, input current and the current through the switches. The fundamental component
of input current is in phase with input voltage, and the displacement factor is unity (1.0).
Therefore, the power factor is improved.
vs

Vm vs = Vmsin t

π
0 t
v

Vm
π 2 π 3π t

0
is1
π 2π 5π /2 t
Ia π
/2
0
is2
Ia π t
3π /2 2π
is1
0 π

is π- π+ 2π t
2 2
Ia

0
Load current
- Ia
t
i0 (a)
Ia v
vr
vc
0
Ar
-Ar

0 π 2π 3π t

S1 S2 S1
vg
2π 3π
0 π (b t
)
Fig. 16.2 Symmetrical angle control.
 The average output voltage is
2 2 2
V /2 2V sin t d t V sin
dc ∫π
π /2
π 2

The value of Vdc varies from 2 2π V to 0 as varies from π to 0.

The rms value of output voltage
is 1 1
2 2
2 π+ / 2 2 2 1
sin
V = 2V sin t d t =V
o ∫ π- / 2
2π π
8.5 Pulse Width Modulation (PWM) Control
If the output voltage of single phase half-controlled converter is controlled by delay
angle, extinction angle or symmetrical, there is only one pulse per half cycle in the input
current of the converter, and as a result, the lowest order harmonic is third. It is difficult to
filter out the lower order harmonic current. In Pulse Width Modulation (PWM) control,
the converter switches are turned on and off several times during a half cycle, and the
output voltage is controlled by varying the width of pulses. The gate signals are generated
by comparing a triangular wave with a dc signal as shown in Fig. 16.3c. In this case, all the
pulse widths obtained are equal. Fig. 16.3a shows the input voltage, output voltage, and
input current. The lowest order harmonic can be eliminated or reduced by selecting the
number of pulses per half cycle. However, increasing the number of pulses would also
increase the magnitude of higher order harmonics, which could easily be filtered out. The
earlier case of symmetrical angle control can be considered as single pulse PWM. For
more details of PWM methods used, the students are requested to study the two lessons
(#5.4-5.5) in module 5 (DC-AC converter, or inverter).
 v

0
π 2π 3π t

v0

m
0
is1 m π 2π 3π t
Ia
m
0 m
π 2π 3π t
is3
Ia
0
π π+ m 2π 3π t
is
Ia
m
π+ m
0
π
i0 m 2π 3π t

- Ia
Ia Load current
0
t
(a)

v
vr
Ar
vc
-
Ac

0 π
vg2
S1 S1
S1

m m

t π
1 m

(b)
 v
vr
vc
Ar
-Ac

π t

vg2
S1 S1 S1

0 m π t

(c)
Fig. 16.3 Pulse-width-modulation
control.

The details of output voltage and current waveforms of the converter are given. The
output voltage (i.e., performance parameters) can be obtained in two steps: (i) by
considering only one pair of pulses such that, if one pulse starts at t 1 , and ends at t 1 1 ,
the other pulse
starts at t 1 , and ends at t 1 1 , and (2) then by combining the effects of all
pairs of pulse.
th
pulse starts at t m and its width is m , the average output voltage due to p
If m number
of pulses is found
as
p p
V 2 m m
2V sin t d t 2V cos cos
∑ ∫m
dc
m1 π π ∑m 1 m m m

If the load current with an average value of Ia is continuous and has negligible ripple, the
instantaneous input current is expressed in a Fourier series as
is t I dc ∑ an cos n t b n sin n t
n 1,3,5,...

Due to symmetry of the input current waveform, even harmonics are absent, and Idc is
zero. The Fourier coefficients are obtained as
1
an
p
π ∫ 0
2π
is t cos n t d t
1 m m 1 m m

∑ ∫ m
I cos n t d t
a ∫ m
I
a
cos n t d t 0

m1 π π
1 2π s
n π∫ 0

b i t si n t d t
 n
p 1 m m 1 m m

∑ m1 π
∫ m I a sin n t d t
π
∫ m I a sin n t d t
p
2I cos n cos n
∑
a

nπ m1 m m m

So, the equation for is(t) is written

as
is t ∑ 2 In sin n t n
n 1,3,...
1 2 2 12

where n tan an bn 0 , and In an b n 2 bn 2

8.6 Sinusoidal Pulse Width Modulation (SPWM) Control

Various types of modifications in PWM techniques have been proposed. One
important method is sinusoidal pulse width modulation (SPWM) control, the pulse widths
are generated by comparing a triangular reference voltage vr of amplitude Ar and
frequency fr, with a carrier half sinusoidal voltage vc of variable amplitude Ac and
frequency 2fs. The sinusoidal voltage vc is in phase with the input phase voltage vs and has
twice the supply frequency fs. The widths of the pulses (and the output voltage) are
varied by changing the amplitude Ar or the modulation index M from 0 to 1. The
modulation index, M is Ac/Ar. It may be noted that the width of the pulses obtained are
variable. The width are smaller at the centre of the carrier signal (sinusoidal), and
increases as one goes to the start and end of the above signal. Fig. 16.4 shows the various
waveforms, including the currents through thyristors and the input current and load
current (assumed to be continuous). It may be noted that, in the earlier case (multiple
PWM control), the pulse widths are uniform (equal). In this type of control, the
displacement factor is unity, and the power factor is improved. The lower order
harmonics one eliminated or reduced. For example, width four pulses per half cycle, the
lowest order harmonic is the fifth, and so on.Different modifications have been suggested
to take one such example, as the pulse width one small in the centre as shown in Fig. 16.4,
the carrier signal is modified to care of this. The triangular waveforms are kept same, upto
some point from the start and end of the cycle, and then the pulse widths can be made
uniform. For more on the matter as given earlier, the students can, either study lesson
#5.5 (module 5), or text books on various PWM methods applied for inverters (dc-ac
converters).
So, the power factor is improved with various control methods discussed. For
different PWM methods used, the harmonic components of the voltage waveforms are
also decreased or eliminated.
 Reference signal Carrier
v signal
Ar
vr
Ac
vc

0 t
iT1

+Ia

0 t
m π 2π 3π
iT2 m

+Ia
t
0
π π+ m 2π 3π
is
m
+Ia π+ m
π+ m+ m t
0 m π 2π 3π
- Ia
io
Ia Load current
0 t
Fig. 16.4 Sinusoidal pulse-width modulation control.

8.6 Filters
It is known that the output voltage waveform of a single phase full wave diode
(uncontrolled) bridge converter (rectifier) fed from f = 50 Hz (fundamental) supply,
contains harmonics of 2f = 100 Hz. So, it is necessary to filter out this and other harmonics
from the output voltage to obtain dc component only. The harmonic frequency present in
the output voltage waveforms of three-phase half-wave and full wave (bridge) diode
converters, are 150 Hz (3f) and 300 Hz (6f) respectively. The higher the harmonic
frequency, it is easier to filter it. For phase-controlled thyristor converters, the harmonic
frequency remains same, but magnitudes vary, as the firing angle delay, is changed. It
may also be noted that the harmonics present in the output current waveforms of the
converters with resistive (R) load, remain same. .
For simple filter, a capacitor (C) is connected in parallel across the output of the diode
converters with resistive (R) load. The reactance of the capacitor should be low, such that
harmonics currents pass through it. So, the harmonics in the output voltage decrease. The
value of the capacitor chosen varies with the predominant harmonic frequency present.
Thus, the capacitor of higher value is needed to filter lower harmonic frequency, say 100
Hz, whereas a lower value of C could be chosen for say, three phase converters. The
function of the capacitor may also be explained in the following way. The voltage across
the capacitor changes as per the input voltage, which is the output voltage of the
converter, fed to it, and the capacitor voltage tries to stabilize at the overage value of the
output voltage, as the capacitor voltage decreases, load resistance being connected across
it.
Same is the case with the filter used to reduce the harmonic content of the output
current waveform for the above converters with resistive (R) load. Instead of a capacitor
in parallel, an inductor (L) is connected in series with the load. The reactance of the
inductor increases, thus reducing the harmonic component in the current waveform.
Here, a smaller value of the inductor is needed to filter higher harmonics, for example a
three- phase bridge converter. These are all simple cases, known to those, who have
studied the circuit (network) theory. Also, by Faraday’s laws, induced voltage (emf)
appears across the inductor, L, when the current through it changes, and the sign of it
opposes the cause, thus opposing the changes in current. So, the current is not allowed to
change much, as an inductor is placed in series with the load. In actual practice, a
combination of L, C & R is needed to get an optimum filter needed to reduce or eliminate
the harmonics in both output voltage and current waveforms.

8.7 Low Pass (L-C) Filter

A passive low pass filter is the ideal choice. But two problems arise; one is the voltage
level, the other is the power or current level. All the elements used, L C or R must be
properly rated for the voltage or current level as needed. A single stage filter (L-C) is used
to reduce the harmonic components in both voltage and current waveforms of a single
phase full wave diode bridge converter with resistive (RL) load as shown in Fig. 16.5(a). It
may be noted that, for the lowest harmonic frequency of 100 Hz, the value of the inductor
needed is high, needing an iron-cored coil. The size also may be large, if the power or
th
current level is high. As stated earlier, such that n harmonic ripple content passes
through the filter capacitor (C), the impedance of the series path must be much greater
than that of the capacitance, i.e.,
2 2 1
Z R n L
L L n C
The condition to be satisfied is
10
Z
L n C or ZL 10 1 n C
and the effect of load is negligible. As shown, the capacitive reactance chosen is total load
impedance divided by a factor of 10
The advantages are small ripple factor with just a single stage (L-C) used, with higher
dc output voltage. The main advantage is poor voltage regulation, also resulting in higher
peak anode current and peak inverse voltage rating.
 iL
+ A D

L
D1 D2
1- +
Suppl L
y
G O
(50Hz
) C A RL
- is
H D

D4 D3

- B

(a)

A
+ E
R RL, L
L
O
C1 A
C2
D

-
B
(b)

Fig. 16.5 (a) Low pass (L-C) filter, (b) Two-stage filter

8.8 Two Stage Filter

A two-stage filter (Fig. 16.5(b)) may be used, instead of a single stage one given
earlier. In this case, the first one is only capacitive (C1) to reduce the harmonic content in
voltage waveform, followed by second stage (R-C), instead of L-C. The size may be
reduced as the size of R is smaller than that of L, as given earlier. This circuit offers
satisfactory operation at light loads, but considerably poor voltage regulation due to drop
in R, resulting in higher ripple content, at heavy load.
If a single capacitor (C1) is used as a single stage one, the ripple factor (RF) is
RF 1 2 4fR L C1 1
For a chosen ripple factor, the value of C1 may be computed, if the values of rated output
voltage and current for the converter are known or given.
These filters may also be used at the output of the dc-dc converter circuits described in
module 3 (lessons $3.1-3.2). Only a single stage (L-C) filter may be used, as the frequency
in the output voltage in thus case is much higher than the harmonic frequency (100 Hz) for
the single phase full wave ac-dc converter (rectifier) circuit described here.

8.9 Harmonic Reduction

The harmonic reduction schemes are presented in brief. The important point to be
noted is that, recently due to increasing use of power electronic units, utility or
electricity supply agencies (boards), have restricted that the power is drawn by the
consumers, so as to decrease the harmonic content in the input current, or make it
sinusoidal, and at the same time, improved load power factor is achieved. Two schemes
– (a) passive (filter) circuits and (b) Active shaping of input line current, are presented,
in brief.

2 mark question with answers

1. What is meant by inverter?
A device that converts dc power into ac power at desired output voltage and
frequency is called an inverter.
2. What are the applications of an inverter?
2.1. Adjustable speed drives
2.2. Induction heating
2.3. Stand-by aircraft power supplies
2.4. UPS
2.5. HVDC transmission
3. What are the main classification of inverter?
3.1. Voltage Source Inverter
3.2. Current Source Inverter
4. Why thyristors are not preferred for inverters?
Thyristors require extra commutation circuits for turn off which results in
uncreased complexity of the circuit. For these reasons thyristors are not
preferred for inverters.
5. How output frequency is varied in case of a thyristor?
The output frequency is varied by varying the turn off time of the thyristors in the
inverter circuit, i.e. the delay angle of the thyristors is varied.
6. Give two advantages of CSI.
6.1. CSI does not require any feedback diodes.
6.2. Commutation circuit is simple as it involves only thyristors.
7. What is the main drawback of a single phase half bridge inverter?
It require a 3-wire dc supply.
8. 61. Why diodes should be connected in antiparallel with thethyristors in inverter circuits?
For RL loads, load current will not be in phase with load voltage and the diodes
8.1. connected in antiparallel will allow the current to flow when the main
thyristors are turned off. These diodes are called feedback diodes.
9. What types of inverters require feedback
diodes?
VSI with RL load.

10. What is meant a series inverter?

An inverter in which the commutating elements are connected in series with the
 load is called a series inverter.
11. What is the condition to be satisfied in the selection of L and C in a series
inverter?
2
R < 4L
C
12. What is meant a parallel inverter?
12.1.1.1. An inverter in which the commutating elements are connected in
parallel with the load is called a parallel inverter.
13. What are the applications of a series inverter?
The thyristorised series inverter produces an approximately sinusoidal waveform at
a high output frequency, ranging from 200 Hz to 100kHz. It is commonly used for
fixed output applications such as
Ultrasonic generator.
Induction heating.
Sonar Transmitter
Fluorescent lighting.

14. How is the inverter circuit classified based on commutation circuitry?

14.1. Line commutated inverters.
14.2. Load commutated inverters.
14.3. Self commutated inverters.
14.4. Forced commutated inverters.

15. What is meant by McMurray inverter?

It is an impulse commutated inverter which relies on LC circuit and an auxiliary
thyristor for commutation in the load circuit.

16. What are the applications of a CSI?

16.1. Induction heating
16.2. Lagging VAR compensation
16.3. Speed control of ac motors
16.4. Synchronous motor starting.

17. What is meant by PWM control?

In this method, a fixed dc input voltage is given to the inverter and a controlled ac
output voltage is obtained by adjusting the on and off periods of the inverter
components. This is the most popular method of controlling the output voltage
and this method is termed as PWM control.

18. What are the advantages of PWM control?

18.1. The output voltage can be obtained without any additional components.
18.2. Lower order harmonics can be eliminated or minimized along with its
output voltage control. As the higher order harmonics can be filtered easily,
the filtering requirements are minimized.
19. What are the disadvantages of the harmonics present in the inverter system?
19.1. Harmonic currents will lead to excessive heating in the induction motors.
This will reduce the load carrying capacity of the motor.
 19.2. If the control and the regulating circuits are not properly shielded, harmonics
from power ride can affect their operation and malfunctioning can result.
19.3. Harmonic currents cause losses in the ac system and can even some time
produce resonance in the system. Under resonant conditions, the
instrumentation and metering can be affected.
19.4. On critical loads, torque pulsation produced by the harmonic current
can be useful.
20. What are the methods of reduction of harmonic content?
20.1. Transformer connections
20.2. Sinusoidal PWM
20.3. Multiple commutation in each cycle
20.4. Stepped wave inverters

21.Compare CSI and VSI.

S. No. VSI CSI

1. Input voltage is maintained
constant
2. The output voltage does not
depend on the load
3. The magnitude of the output
current and its waveform
depends on the nature of the
load impedance
4. It requires feedback diodes
Input current is constant but
adjustable
The output current does not depend
on the load
The magnitude of the output voltage
and its waveform depends on the
nature of the load impedance
It does not requires feedback diodes

5. Commutation circuit is Commutation circuit is simple i.e. it

complicated i.e. it contains contains only capacitors.
capacitors and inductors.
22. What are the disadvantages of PWM control?
SCRs are expensive as they must possess low turn-on and turn-
off times.
23. What does ac voltage controller mean?
It is device which converts fixed alternating voltage into a variable
voltage without change in frequency.
24. What are the applications of ac voltage controllers?
a. Domestic and industrial heating
b. Lighting control
c. Speed control of single phase and three phase ac motors
d. Transformer tap changing
25What are the advantages of ac voltage controllers?
e. High efficiency
f. Flexibility in control
g. Less maintenance
26What are the disadvantages of ac voltage controllers?
The main draw back is the introduction of harmonics in the supply current and
 the load voltage waveforms particularly at low output voltages

12 mark question
1.Describe the operation of series inverter with aid of diagrams. Describe an
expression for output frequency, current and voltages. What are the
disadvantages of basic series inverter?
Ans:
series inverter circuit
Current & voltage waveforms
Operation
Expression for output frequency, VL, VC

2.State different methods of voltage control inverters. Describe about PWM

control in inverter.
Ans:
External control of ac output voltage
External control of dc input voltage
Internal control of Inverter
PWM inverter
Single pulse modulation
Multiple pulse modulation
Sinusoidal pulse modulation
0
3.Explain the operation of 3

bridge inverter for 180 degree mode of operation
with aid of relevant phase and line voltage waveforms.
Ans:
Inverter circuit
operation- equivalent circuits
Waveforms of phase and line voltage
 0
4. Explain the operation of 3

bridge inverter for 120 degree mode of operation with
aid of relevant phase and line voltage waveforms.
Ans:
Inverter circuit
operation- equivalent circuits
Waveforms of phase and line voltage

5.Draw the circuit diagram of 1

auto sequential commutated current source
inverter and explain its operation with equivalent circuits for different modes
and necessary waveforms.
Ans:
Inverter circuit
Modes of operation- equivalent circuits
Waveforms of ic, vc , io
Expression for tc, vc, vL

6.Draw the circuit diagram of 1

capacitor commutated current source inverter
and explain its operation with equivalent circuits for different modes and
necessary waveforms.
Ans:
Inverter circuit
Modes of operation- equivalent circuits
Waveforms of ic, vo , io, iT1, iT2, vT1,
Expression for vc, vL vT2 , vo , io, tc

7.Explain the operation of multistage control of AC voltage controllers with neat

diagram.
Ans:
Circuit diagram
Operation