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FEBFAN7631 - L17U120A: User Guide For
FEBFAN7631 - L17U120A: User Guide For
FEBFAN7631 - L17U120A: User Guide For
FEBFAN7631_L17U120A
Fairchild Semiconductor.com
1. Introduction
This document describes a proposed solution for a 120 W LED driver consisting of an
AC-DC converter for flyback bias regulation, a boost converter for Power-Factor-
Correction (PFC), an LLC resonant converter for a single LED channel with constant
current and voltage or individual boost converters for two LED channels with constant
current and dimming control. The input voltage range is 85 VRMS – 300 VRMS and there
are DC outputs with a constant current of 2.4 A at 50 VMAX for a single LED channel or
with constant current and dimming of 1.2 V at 100 V for two LED channels.
The power supply mainly utilizes:
FSL117MRIN – Green Mode Fairchild Power Switch (FPS™)
FL7930B – CRM PFC Controller
FAN7631 – Half-Bridge LLC Controller
FAN73402 – Single-Channel Boost Controller (for each controller)
FCPF190N60E and FCPF600N60Z – Fairchild SuperFET® Technology
FDPF14N30 – Fairchild UniFET® Technology N-Channel MOSFET
FFPF08H60S – Fairchild Hyperfast Rectifier
MBR20200CT – Fairchild Schottky Rectifier
RURD620CCS9A – Fairchild Ultra-Fast Recovery Rectifier (for discrete)
This document contains important information (e.g. schematic, bill of materials, printed
circuit board layout, transformer design documentation), and the typical operating
characteristics supporting this evaluation board.
ICH
Vburst
0.35V / 0.50V
Soft Burst VREF
VCC Good 7.5V / 12V
Random
VCC VREF
OSC
2.0µA 90µA Soft-Start
IDELAY IFB S Q
PWM
Gate
FB 3 Driver
R Q
3R
R LEB (300ns)
tON<tOSP(1.0μs)
LPF 1 GND
VAOCP
VOSP
TSD S Q
VSD
7.0V
VCC Good R Q
VCC
VOVP
VINH / VINL
24.5V
4
VIN FSL1117MRIN
1.2.1. Features
Additional PFC-Ready Function
Input-Voltage-Absent-Detection Circuit
Maximum Switching Frequency Limitation.
Internal Soft-Start with Overshoot Prevention
Internal Total harmonic Distortion (THD) Optimizer
Precise Adjustable Output Over-Voltage Protection (OVP)
Open-Feedback Protection and Disable Function
Zero Current Detector (ZDC)
150 μs Internal Startup Timer
MOSFET Over-Current Protection (OCP)
Under-Voltage Lockout with 3.5 V Hysteresis (UVLO)
Low Startup (40 μA) and Operating Current (1.5 mA)
Totem-Pole Output with High State Clamp
+500 / -800 mA Peak Gate Drive Current
SOP-8 Package
circuit 8.5 12
ZCD 5 -
VCC
+ restart
timer gate
VTH(ZCD)
driver
7 OUT
fMAX
limit VO(MAX)
6.5V
THD optimized S Q
1V
sawtooth +
generator
R Q
-
Startup
40kW
without
Overshoot
+ 4 CS
8pF
-
INV 1 - VCS_LIM
VREF VREF
stair +
6 GND
step
clamp
circuit
reset VIN-Absent
Detection
COMP 3
disable
disable thermal
shutdown
- 0.35 0.45
2.5 2.675
+
RDY 2 INV_open
VBIAS
OVP
UVLO
1.60 2.24
RT 2 R Q
50% Duty Cycle
14
-
Frequency
CTR
Divider < 600kHz
VSS_END
OCP
4 DT
+
VSS_ATART CS
OVP A/R
Low-Side
/ VSS_END -
Protection
Gate Driver
11 LO
DT
S Q
OLP
ISS1 30µA Block OLP
ISS2 R Q CS
OCP
Current VSS_START +
VOCP
Steering +
-0.56V
Block -
9 CS
SS 3 -
AOCP
IOLP
+
VAOCP
30µA -1.1V
-
Latch
LINE Good LVcc Good SKIP
Protection
PG 10 +
10µA Q S TSD
ILINE 0.6 V/ 0.4 V +
Q R
+
7
-
SG VRT
- LVCC < 5V 4V
- VFI
3V
8 1 6
LS CON FI
Figure 3. Block Diagram of FAN7631
1.4.1. Features
Single-Channel Boost LED Switch
Internal Power MOSFET for PWM Dimming:
RDS(ON)=1.0 Ω at VGS=10 V, BVDSS=200 V
Current-Mode PWM Control
Internal Programmable Slope Compensation
Wide Supply Voltage Range: 10 V to 35 V
LED Current Regulation: ±1%
Programmable Switching Frequency
Analog and PWM Dimming
Wide Dimming Ratio: On Time=10 µs to DC
Cycle-by-Cycle Current Limiting
Thermal Shutdown: 150°C
Open-LED Protection (OLP)
Over-Voltage Protection (OVP)
Over-Current Protection (OCP)
Error Flag Generation (for External Load Switch)
Internal Soft-Start
16-Lead SOIC Package
20μs Delay
3V -
OVP
+
OVP 100mV
FAULT
OLP
TSD
1μs
+ Delay
ADIM*4
S Q
1.4~4V - OCP
R
POR
Current 640µs at 200kHz
Auto-Restart
Sense
PWM
-
gm 1/4
-
ADIM
+
R Dim off
0.3~3V + DRV
Q
S
Gate
PWM Driver
CMP
Slope
100mV 5k Compensation
- CS
Burst
0.5V
+ Operation
CLK+LEB
4V
+
Switch Off
16 Steps -
0.5V
Internal Soft-Start 3ms at 200kHz
Oscillator RT
GND
45µA
Drain
-
UVLO 9V PWM
VCC +
OLPi Dim off
Hys. 1.0V
1.22V -
ENA + BDIM
Hys. 70mV OLP
Current
Sense
BDIM
Figure 4. Block Diagram of FAN73402
All data of the evaluation board measured with the board enclosed in a case and external
temperature around 25°C.
232 mm
114 mm
Figure 7. Top Pattern
G
I O
2
PS_ON CS813
10uF/35V
RS857
15k
RS858
10k
RS805 RS804 QS854
100k/3216 100k/3216 KST2222A CN805
VPFC TS801 DS801 RS855 5.2V 2
EPC1717 ES1D 10k 5.2V
RS806 CS802 1 10 1
30k/3216 RS821 2.2n/3216 GND
30k/3216 2 CON3
CS803
3 9 47uF/35V
RS822 CS804 RS824
30k/3216 DS802 4 8 470uF/10V 390/3216 5.2V
RS1M DS803
5 7 SB560
RS823 RS808 RS825
30k/3216 6 1k 390/3216
5
1 7 RS809
Vstr
0R/3216 1
RS810
8 1.5k
DRAIN
PCS801A CS805
DS804 FOD817B NC
3 6 1N4003
Vf b DRAIN 2
4
PCS801B
FOD817B 4 2
Vin Vcc CS809 RS811 CS806
100n CY 806 12k 82n
CS807 RS812 ICS802 4,7n
100n 0R0 FSL117MRIN ICS803
3 CS808 KA431SMF2TF RS813 RS814
10uF/50V NC 4.7k
RS818
ICS804 20k PS_ON
KA78L15 QS801
1
1 3 KSPT2907A
VCC
G
O I PCS802A RS815
CS810 RS816 FOD817B 1k
2
100n 20k
CS814
10uF/50V QS802
RS817 2 KST2222AMTF
20k
4 RS819
PCS802B 20k QS803 SW1
FOD817B KST2222AMTF CS815 PS_ON
RS820 FO 100n
CS811 20k
100n
CS812
3
100n
+
DP802
DX801
D15XB60
~
2
FFPF08H60S
LP801
-
PFC3819QM
RP801
CP803
680n/630V 4.3M
6
CP801
LX801 330uF/250V
CV630055 RP815 LL4148
3.3 DP804
CY 801
470p
RP804 CP802
QP802 4.3M 330uF/250V
FCPF190N60E
CX801 CY 802 VCC RP803
470nF 470p 10
RP806 RP805
47k 10K
DP803 RP807
LX802 ES1D 4.3M
CV630055
CX802
470nF 8 7
VCC OUT
FL7930C
RX801 RX802 RX803 RP811
1M/3216 1M/3216 1M/3216 150 RP809
5 4 4.3M
ZCD CS
RT1 ZDP801 3 1
RT2 3D15 NC COMP INV
3D15 RP812 CP807 RP813
t t 10k 200n
6 2
91K
ZNR801 CP806 GND READY
10D561K CP805 100n CP808 CP809
10uF/35V 1u ICP801 1n RP816
FL7930C 4.7K
RP817
NC
FS801 RP814 CP811
250VAC, T6.3AH 0.1/5W 1n
PFC OK
1
CN801
INLET
Figure 11.
RTN
4 9 CM802 CM804 RM802
680uF/63V 680uF/63V 0.2/1W
5 8 CM824
RM805 1 16 1 47n/3216
1M CON HVCC 7 2 ISEN RM803
4
RM806 CM806 3 27k/F
PCM801B 1.1K 220n DM803 TM801
15
FOD817B LL4148 SRX43EM DM802 RM814
2 15 MBR20200CT RM807 5.6k
RM808 RT HO QM801 24k/F
2.2M RM812 FCPF600N60Z CY 803
3 3.3R RM809 4.7n 15V
RM811 10k RM810
4.7K 3 14 2.7k/F
SS CTR
RM841
RM813 CM807 DM804 39k
2.2M 10n CM808 UF4004
470n 4 13 CM817
DT NC 8.2n
RM817
10/3216 CM823
DM810 VCC TSM103W 5.6n
ICM803
5 12 ES1D RM830 RM828 CM818 RM829
RM820 NC LVcc 12k 15k 8 1 20k
100n VCC OUT1
RM827 24k
39k CM810 CM809 CM812 7 2
FAN7631
FI LO FCPF600N60Z INV2 Non_INV1_ref
5 4
CM811 RM822 RM823 PCM801A Non_INV2 VEE
100n 3.3R 10k FOD817B
7 10 RM839
RM821 SG PG 10k
100K 2 JPM801
RM825 CM814 JUMPER DM809
DM806 1K/3216 10p LL4148 RM840
8 9 LL4148 2.2k/F RM837
LS CS 10k/F
JPM802 CM820 RM832
ICM801 RM826 DM807 CM816 JUMPER 8.2nF ISEN 5.1k
PFC OK FAN7631 1K LL4148 3.9nF/630V
RM836
22k
RM838
5.1k
※ RM830 should be NC in case of 50 V/2.4 A output and use 16 k value in case of 100 V/1.2 A output.
LL801 DL801
50V/1.2A 68uH/SPI-SDH1360-680 RURD620
100V/600mA
VLED+ VLED1
RL801
150k RL803
3R3 CL801 CL802
QL801 RL804
RL802 FDPF14N30 RL807 47uF/160V 47uF/160V 150K
150k 0R
ENA
CL803 RL808
1.2n RL810 LL4148 150K
9.1k DL805 DL803
LL4148 RL812 ICL802 BDIM1
PS_ON 10K FAN73402 RL813
RL818 150K
10k
1 16 REF1
15V-1 VCC BDIM OVP1
DL806 CL807 CL809 RL820
FAN73402
ES1D CL806 100n 1.2n 12k
10uF/50V RL822 2 15 ADIM
7.5K DRV ADIM
RL817 RL816 3 14
0.2R/3216 GND CMP
0.2R/3216
RL828
4 13 OVP1 15k
CS OVP CL812
CL811 6.8n
10p CL815
REF1 5 12 100n
REF ENA ENA
CL817
RL832 NC RL830
75k NC
FO 6
FAULT
ADIM1
RL834
1.8k 7 10
RT DRAIN
RL835
150k
RV801 CL819 8 9 RTN1
50k RL838 SENSE DRAIN
39k 10n
RL837
2R/2W
JPM803
NC
RL847
BDIM1 CN803
VLED+
2
1K RL848 VLED1
100K CL820 1
1n RTN1
RTN1
CON3
BDIM1
DIM1+
GND
※ JPM805 should be opened in case of 50 V/2.4 A output and shorted in case of 100 V/1.2 A output.
FAN73402
RL823 1.2n 12k
CL808 7.5K 2 15 ADIM2
CL821 DRV ADIM
0.1u
10uF/50V
RL825 3 14
RL826 GND CMP
0.2R/3216
0.2R/3216
RL829
4 13 OVP2 15k
CS OVP CL814
CL813 6.8n
10p CL816
5 12 ENA 100n
REF ENA
CL818 RL831
RL841 NC NC
75k FO 6
FAULT
ADIM2
7 10
RL839 RT DRAIN
1.8k RL836
150K
CL822 8 9 RTN2
RV802 10n SENSE DRAIN
50k
RL842
39k RL840
2R/2W
JPM804
NC
RL850
1K
CN804
BDIM2 VLED+
2
VLED1
CL823 1
RL849 1n RTN1
RTN1
100K CON3
BDIM2
DIM2+
GND
ECP1717
5 2 NS2(3 à4)
NP1
NP1(10à9)
6 NS1
2mm NP2(6 à7)
NP2
1 Barrier
7
NS1 (1 à2) 2mm
9 4
Barrier
NA NS2
NP1(5 à6)
10 3
PFC3819QM
4
5 1
NS(7à6)
6 NP 2
NA
7 3
NP (1 à3)
8
SRX43EM
7
2
NS1
NP 10
9
4 NS2
12
NP (4à2) NS2(12à9)
NS1(10à7)
Table 11 shows stand-by power consumption of 85 VAC~ 140 VAC [low line, 60 Hz] and
180 ~ 300 VAC [high line, 50 Hz] input voltage ranges. The results are measured when the
PS-ON switch is turned off.
Min. Max.
Input Voltage CV CC
VOUT [V] IOUT [mA] VOUT [V] IOUT [mA]
85 VAC / 60 Hz 49.60 2552 49.70 2560 ±0.03% ±0.04%
469 ms 340 ms
Figure 23 and Figure 24 show the startup and stop performance for the PS-ON switch
operation; including boost, LLC resonant converter, and single-channel boost converter.
The output load current starts flowing about 59 ms after the PS-ON switch was turned on
and is disconnected when the PS-ON switch was turned off in standby status; CH1: VDD-
PFC (10 V / div), CH2: VPS-ON (2 V / div), CH3: VLED (50 V / div), CH4: ILED (0.5 A / div).
59 ms
395 ms 297 ms
Figure 27 and Figure 28 show the startup and stop performance for the flyback converter
according to PS-ON switch operation. Each output voltage is raised at the same time
when the PS-ON switch is turned on and VDD-FAN73402 drops under UVLO after 100 ms
since PS-ON switch was turned off in standby status; CH1: VDD-PFC (10 V / div), CH2:
VPS-ON (2 V / div), CH3: V5V (2 V / div), CH4: VDD-FAN73402 (10 V / div), Time Scale:
200 ms / div.
429 ms 339 ms
Figure 31and Figure 32 show the startup and stop performance for the boost converter
according to PS-ON switch operation at rated output load. The PFC output voltage is
raised rapidly when the PS-ON switch is turned on and VDD-PFC drops below UVLO and
PFC output starts discharging PFC output capacitors when PS-ON switch was turned off
in standby status; CH1: VDD-PFC (10 V / div), CH2: VPS-ON (2 V / div), CH3: VOUT-PFC
(200 V / div), CH4: VRDY (2 V / div).
Figure 31. PS-ON, [200 ms/div] Figure 32. PS-OFF, [500 ms/div]
455 ms 337 ms
Figure 35 and Figure 36 show the startup and stop performance for the LLC converter
according to the PS-ON switch operation at rated output load. The LLC output current is
raised up to the rated voltage within 50 ms after the PS-ON switch is turned on and the
output current drops to zero quickly when the PS-ON switch is turned off in standby
status; CH1: VDD-LLC (10 V / div), CH2: VPS-ON (2 V / div), CH3: VOUT_LLC (20 V / div),
CH4: IOUT_LLC (2 A / div), Time Scale: 200 ms / div.
Figure 37. VIN = 85 VAC / 60 Hz, 100% Dim Figure 38. VIN = 300 VAC / 50 Hz, 100% Dim
Figure 39 and Figure 40 show AC input and output waveforms at 85 VAC and 300 VAC
line voltage and 50% output load condition, respectively; CH1: VIN (2 A / div), CH2: VIN
(200 V / div), CH3: VOUT (50 V / div), CH4: ILED (0.5 A / div), Time Scale: 5 ms / div.
Figure 39. VIN = 85 VAC / 60 Hz, 50% Dim Figure 40. VIN = 300 VAC / 50 Hz, 50% Dim
Figure 41. VIN = 85 VAC / 60 Hz, 10% Dim Figure 42. VIN = 300 VAC / 50 Hz, 10% Dim
53 kHz
53 kHz
Figure 45. VIN = 85 VAC / 60 Hz, [5 ms/div] Figure 46. VIN = 85 VAC / 60 Hz, [5 µs/div]
Figure 47 and Figure 48 show key waveforms of PFC stage at 85 VAC line voltage and
no-load condition; CH1: IDS_QP802 (0.5 A / div), CH2: VDS_QP802 (200 V / div), CH3:
VAK_DP802 (200 V / div), CH4: IAK_DP802 (0.5 A / div).
179 kHz
Figure 47. VIN = 85 VAC / 60 Hz, [5 ms/div] Figure 48. VIN = 85 VAC / 60 Hz, [2 µs/div]
62 kHz
Figure 49. VIN = 300 VAC / 50 Hz, [2 ms/div] Figure 50. VIN = 300 VAC / 50 Hz, [5 µs/div]
Figure 51 and Figure 52 show key waveforms of the PFC stage at 300 VAC line voltage
and no-load condition; CH1: IDS_QP802 (0.5 A / div), CH2: VDS_QP802 (200 V / div), CH3:
VAK_DP802 (200 V / div), CH4: IAK_DP802 (0.5 A / div).
Burst
Figure 51. VIN = 300 VAC / 50 Hz, [5 ms/div] Figure 52. VIN = 300 VAC / 50 Hz, [2 µs/div]
212 kHz
Figure 53. Rated Load [5 ms/div] Figure 54. Rated Load [2 µs/div]
Figure 55 and Figure 56 show key waveforms in the secondary side of the LLC converter
at rated output load condition; CH1: I_Secondary (2.0 A / div), CH2: VAK_DM802 (100 V / div),
CH3: VAK_DM802 (100 V / div).
Figure 55. Rated Load [5 ms/div] Figure 56. Rated Load [2 µs/div]
Figure 59 and Figure 60 show key waveforms in the secondary side of the LLC converter
at no-load condition; CH1: I_Secondary (0.5 A / div), CH2: VAK_DM802 (100 V / div), CH3:
VAK_DM802 (100 V / div).
133 kHz
Figure 61. Rated Load [2 ms/div] Figure 62. Rated Load [2 us/div]
Figure 63 and Figure 64 show key waveforms of a single-channel boost converter at 10%
load condition; CH1: IDS_QL802 (2.0 A / div), CH2: VDS_QL802 (100 V / div), CH3: VAK_DL802
(100 V / div), CH4: IAK_DL802 (2.0 A / div).
132 kHz
Figure 63. 10% Load [2 ms/div] Figure 64. 10% Load [2 µs/div]
Figure 65. 10% ADIM [2 ms/div] Figure 66. 10% ADIM [2 µs/div]
Figure 67 and Figure 68 show key waveforms for PWM dimming performance of a
single-channel boost converter at 100% ADIM (VADIM: 1.2 V) and 1% BDIM; CH1: ILED
(0.5 A / div), CH2: VGATE-QL802 (5.0 V / div), CH3: VBDIM (5.0 V / div), CH4: VADIM
(0.5 V / div).
200 Hz
700
600
500
ILED [mA]
400
ADIM
300
200
100
0
0.1 0.3 0.5 0.7 0.9 1.1 1.3
ADIM Voltage [V]
700
600
500
400
ILED [mA]
BDIM
300
200
100
0
0 20 40 60 80 100
LED Short
Figure 71. LED Short Figure 72. Recover from LED Short
Figure 73 and Figure 74 show waveforms for output voltage and current when an LED is
opened and recovered in one of the LED channels [100 V/0.6 A]; CH1: ILED (0.5 A / div),
CH2: VLED (50 V / div), CH3: VGATE-QL802 (5 V / div), Time Scale: 100 ms / div.
LED Open
Figure 73. LED Open Figure 74. Recover from LED Open
Primary Secondary
Transformer:
72.6 ºC
Boost MOSFET:
PFC MOSFET: 61.8 ºC
65.2 ºC
LLC MOSFET:
Bridge Diode:
59.4 ºC
64.2 ºC LLC Rectifier:
67.5 ºC
Figure 76 shows temperatures measured for the primary [top] and secondary [bottom]
active components at 300 VAC line voltage and rated output load [two LED channels:
100 V/1.2 A].
Primary Bottom
ICL802_FAN73402:
82.1 ºC
The Evaluation board (or kit) is for demonstration purposes only and neither the Board nor this User’s Guide constitute a sales contract or create any
kind of warranty, whether express or implied, as to the applications or products involved. Fairchild warrantees that its products meet Fairchild’s
published specifications, but does not guarantee that its products work in any specific application. Fairchild reserves the right to make changes without
notice to any products described herein to improve reliability, function, or design. Either the applicable sales contract signed by Fairchild and Buyer or,
if no contract exists, Fairchild’s standard Terms and Conditions on the back of Fairchild invoices, govern the terms of sale of the products described
herein.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR
USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR
THE RIGHTS OF OTHERS.
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems which, (a) are 2. A critical component is any component of a life support device or
intended for surgical implant into the body, or (b) support or sustain system whose failure to perform can be reasonably expected to
life, or (c) whose failure to perform when properly used in accordance cause the failure of the life support device or system, or to affect its
with instructions for use provided in the labeling, can be reasonably safety or effectiveness.
expected to result in significant injury to the user.
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