Available online at www.sciencedirect.

com

Solar Energy 87 (2013) 229–245

www.elsevier.com/locate/solener

FPGA based multilevel cascaded inverters with SVPWM algorithm

for photovoltaic system
M. Valan Rajkumar a,1, P.S. Manoharan b,⇑
a
Department of Electrical and Electronics Engineering, Anna University of Technology, Madurai, India
b
Department of Electrical and Electronics Engineering, Thiagarajar College of Engineering, Madurai 625 015, India

Received 18 May 2012; received in revised form 2 November 2012; accepted 4 November 2012
Available online 6 December 2012

Communicated by: Associate Editor Nicola Romeo

Abstract

This paper presents the control for three-phase multilevel cascaded H-bridge inverter for photovoltaic (PV) system. The maximum
power point tracking (MPPT) is capable of extracting maximum power from the PV array connected to each DC link voltage level.
The MPPT algorithm is solved by perturbation and observation method (P&O). Space vector pulse width modulation (SVPWM) algo-
rithm uses a simple mapping to generate gate signals for the inverter. The location of the reference vector and time are easily determined.
The adjustments of modulation index and phase angles are synthesized onto field programmable gate array (FPGA) by means of hard-
ware description language (VHDL). A digital design of the generator SVPWM using VHDL is proposed and implemented on FPGA.
This is done to achieve high dynamic performance with low total harmonic distortion (THD). Simulation and experimental results are
given to verify the implemented SVPWM control for PV system in terms of THD.
Ó 2012 Elsevier Ltd. All rights reserved.

Keywords: Photovoltaic (PV) system; Cascaded H-bridge multilevel inverter; Space vector pulse width modulation (SVPWM); Field programmable gate
array (FPGA); Total harmonic distortion (THD)

1. Introduction energy in low irradiation conditions (ii) the amount of elec-

Recently, the installation of PV generation systems is
rapidly growing due to concerns related to environment,
global warming, energy security, technology improvements
and decreasing costs. PV generation system is considered as
a clean and environmental-friendly source of energy. The
main applications of PV systems are in either standalone
or grid connected configurations. Standalone PV genera-
tion systems are attractive as they are indispensable elec-
tricity source for remote areas. However, PV generation
systems have two major problems: (i) low conversion
⇑ Corresponding author. Tel.: +91 9486019204; fax: +91 452 2483427.
E-mail addresses: valanrajkumar@gmail.com (M. Valan Rajkumar),
psmeee@tce.edu (P.S. Manoharan).
1
Research Scholar.
tric power generated by PV arrays varies continuously with
weather conditions. Therefore, how to increase the effi-
ciency of the energy produced from PV arrays are discussed
(Richard et al., 2005; Marcelo et al., 2009).
Many MPPT algorithms have been proposed in the lit-
erature, such as incremental conductance (INC), constant
voltage (CV) and perturbation and observation (P&O).
The P&O method has been widely used because of its sim-
ple feedback structure and fewer measured parameters, as
described in (Hajizadeh and Golkar, 2008). The implemen-
tation of the low power consumption MPPT controller
using a pulse frequency modulation dc-dc boost converter
was developed (Lopez-Lapena et al., 2010). Different types
of multilevel inverter topologies are presented in the litera-
ture (Jose et al., 2002; Tolbert et al., 1999; Hammond,
1997). Many methods of pulse width modulation (PWM)

0038-092X/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved.
http://dx.doi.org/10.1016/j.solener.2012.11.003
230 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245
techniques are used to control the inverter have been dis-
cussed (Colak et al., 2011). SVPWM directly uses the con-
trol variable given by the control system, and identifies
each switching vector as a point in complex (a, b) space
has been discussed in detail (Massoud et al., 2003).
SVPWM is suitable for digital signal processing implemen-
tation and optimization of switching patterns as explained
(Celanovic and Boroyevich, 2001).
Simple ON-time calculation is done due to the use of a
two-level geometry based ON-time equations. The ON-
time calculation equations for different modulation mode
do not change with the position of reference vector like
the traditional approach in (Mondal et al., 2003, 2002).
The optimal switching sequence and the discontinuous
modulation can be applied to multilevel inverters using
zero sequence offset voltages derived from two-level inver-
ter space vector concepts are discussed (McGrath et al.,
2003). The multilevel ON-time calculation problem is con-
verted to a simple two-level ON-time calculation problem.
This method is described in detail in (Gupta et al., 2004).
The implementation of PWM by digital signal processor
(DSP) and microcontroller has been discussed (Tzou
et al., 1996; Vadivel et al., 1991).
An attractive idea is to implement the PWM via an
application-specific integrated circuit (ASIC). The FPGA
is a sub-class of ASIC controllers which provides charac-
teristics such as fast prototyping, simple hardware and soft-
ware design and higher switching frequency are discussed
(Puyal et al., 2006; Tzou and Hsu, 1997). The FPGA-based
PW modulators for multilevel three-phase three-wire volt-
age source inverters were developed (Zhou et al., 2004;
Tonelli et al., 2001). A generic digital VHDL module for
the multilevel multiphase SVPWM algorithm has been dis-
cussed (Alvarez et al., 2011).
A single phase cascaded H-bridge multilevel inverter can
be controlled using phase shifted PWM as a feasible multi-
string topology for PV applications are discussed (Villanu-
eva et al., 2009). In a PV system, proportional controller
current control scheme is used to maintain the output cur-
rent sinusoidal and to get high dynamic performance from
the different atmospheric conditions are discussed (Selvaraj
and Rahim, 2009). The scheme is (Cecati et al., 2010) pro-
posed for a single-phase multilevel cascaded H-bridge
inverter for PV applications with fuzzy logic control and
system-on-chip approach.
The leakage current in three-phase transformer-less PV
systems connected to the grid was discussed (Cavalcanti
et al., 2010). A fundamental-frequency-modulated diode
clamped multilevel inverter fed by PV modules for stand-
alone application has been discussed (Ozdemir et al.,
2009). A novel power conversion scheme for the grid con-
nection of a PV generation system has been analysed and
implemented in DSP was discussed (Grandi et al., 2009).
The elimination of harmonics in multilevel inverters
using particle swarm optimization was explained (Al-oth-
man and Tamer Abdelhamid, 2009). The THD minimiza-
tion on output voltage of the multilevel inverters was
discussed (Yousefpoor et al., 2012). Real time algorithm
for minimizing THD in multilevel inverters with unequal
or varying voltage steps under staircase modulation was
proposed (Liu et al., 2009a). Real time calculation of
switching angles minimizing THD for multilevel inverters
with step modulation was discussed (Liu et al., 2009b).
Harmonic optimization of voltage balancing control for
multilevel converter system was discussed (Pan and Peng,
2006).
This paper proposes a system consisting of a PV array
connected to the three phase multilevel cascaded H-bridge
inverter through DC bus which is connected to the three
phase load as shown in Fig. 1.
The control structure of the PV system is composed of
two structure control.
1. The MPPT control, whose main property is to extract
the maximum power from the PV generator,
2. The inverter control is applied
i. To control DC bus voltage.
ii. To convert DC input to AC output at the same wave-
forms as the three phase lines.
iii. To ensure high quality of the output power.
2. PV array modeling and simulation
The PV array used in the proposed system is KC200GT
and it is simulated using a model based on (Ravi et al.,
2011; Xiao et al., 2004; Sera et al., 2007). In this model,
a PV cell is represented by a current source in parallel with
diode and a series resistance as shown in Fig. 2. In this PV
array, mathematical model can be expressed as
   
q
I ¼ I Photo  I RSat exp ðV þ IRse Þ  1
AD K B T
V þ Rse I
 ð1Þ
Rp
Eq. (1) shows that the non linear output characteristics of
solar cell. It is affected by temperature, radiation of solar
and condition of load, where IPhoto is the photo current,
IRSat is the reverse saturation current, q is the electron
charge (1.6021747  1019 C), RSe is the series resistance
and Rp is the parallel resistance. Photocurrent IPhoto is di-
rectly proportional to the solar irradiation (Gira). In Eq.
(1) AD is dimensionless factor, KB is the Boltzmann con-
stant (1.38  1023 J/K) and T is the temperature.
 
Gira
I Photo ðGira Þ ¼ I sc ð2Þ
Giras
where ISC short circuit current depends linearly on cell tem-
perature and Giras is the standard irradiation (1000 W/m2).
I sc ðT Þ ¼ I scsat ½1 þ DI sc ðT  T st Þ ð3Þ
where DIsc is the temperature coefficient and TSt is the stan-
dard temperature (298 K). IPhoto and IRSat depend on the
 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245 231

Fig. 1. General diagram of three phase load connected photovoltaic system.

Fig. 2. Equivalent circuit of a PV cell physical model.

cell temperature and solar irradiation and these can be mum power point tracking are the P&O and INC
mathematically expressed as methods. The INC method offers good performance under
  rapidly changing atmospheric conditions. The INC method
Gira
I Photo ðGira ; T Þ ¼ I scsat ½1 þ DI sc ðT  T st Þ ð4Þ uses two voltage sensors and two current sensors to sense
Giras
the output voltage and current of the PV array. If the sen-
I Photo ðGira ; T Þ sors require more conversion time, then the MPPT process
I RSat ðGira ; T Þ ¼ ð5Þ
eð V t Þ  1
V oc
will take longer to track the maximum power point. During
tracking time, the PV output is less than its maximum
In Eq. (5), Vt is thermal voltage. The parameters of solar
power. This means that longer the conversion time, larger
array KC200GT at nominal operating conditions is shown
the power loss (Hajizadeh and Golkar, 2008).
in the Table 1.
On the contrary, if the execution speed of the P&O
method increases, then the system loss will decrease. More-
3. MPPT control over, this method only requires two sensors, which results
in a reduction of hardware requirements and cost. There-
Many MPPT algorithms have been proposed in the lit- fore, P&O method is used to control the MPPT process.
erature. The two algorithms often used to achieve maxi- In order to achieve maximum power, two different
Table 1 applied control methods that are often chosen are volt-
Parameters of the adjusted model of the KC200GT solar age-feedback control and power-feedback control (Hua
array at nominal operating conditions. et al., 1998). Voltage-feedback uses the solar-array terminal
Imp 7.61 A voltage to control and keep the array operating near its
Vmp 26.3 V maximum power point by regulating the array’s voltage
Pmax,m 200.143 W and matching the voltage of the array to a desired voltage.
Isc 8.21 A
The drawback of the voltage-feedback control is its neglect
Voc 32.9 V
Io,n 9.825  108 A of the effect of irradiation and cell temperature. Therefore,
IPhoto 8.214 A the power-feedback control is used to achieve maximum
A 1.3 power.
Rp 415.405 X The P&O MPPT algorithm with a power-feedback con-
Rse 0.221 X
trol (Hua et al., 1998; Koutroulism and Kaalitzakis, 2001)
232 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245

is shown in Fig. 3. The power is calculated by using deter-
mination of PV voltage and PV current. At the maximum
power point dv/dt is zero. The maximum power point can
be achieved by changing the reference voltage by the
amount of DVref.
In order to implement the MPPT algorithm, a buck-
boost dc-dc converter is used. The parameters L and C in
the buck-boost converter must satisfy the following condi-
tions (Mohan et al., 2003).
L > Rð1  DÞ2 =2f
C > D=Rf ðDV =V out Þ
In Eqs. (6) and (7), D is the duty cycle and f is the switching
frequency. The buck-boost converter consists of one
switching device that enables it to turn ON and OFF
depending on the applied gate signal D. The gate signal
for the switching device can be obtained by comparing
the saw-tooth waveform with the control voltage (Haji-
zadeh and Golkar, 2008). The change of reference voltage
DVref obtained by MPPT algorithm becomes the input of
the pulse width modulation (PWM). The PWM gate signal
to control the buck-boost converter and, thus, maximum
power is tracked and delivered to the inverter.
4. Five-level cascaded H-bridge inverter topology
The multilevel inverter is best suited for the application
which demands the finest quality of the ac supply wave-
forms. This work presents a SVPWM control scheme,
which pertains fully to cascaded multilevel inverters. The
comparison of diode clamped and cascaded inverters are
ð6Þ
shown in Table 2. When compared to diode clamped
ð7Þ inverters, cascaded inverter requires the least number of
components to achieve the same number of voltage levels.
A cascaded multilevel inverter consists of a series of H-
bridge (single-phase, full-bridge (FB)) inverter units. The
general function of this multilevel inverter is to synthesize
a desired voltage from several separate dc sources (SDCSs),
which may be obtained from batteries, fuel cells, or solar
cells. A three phase five-level cascaded H-bridge circuit dia-
gram is shown in Fig. 4. Each SDCS is connected to H-
bridge inverter. The ac terminal voltages of different level
inverters are connected in series. An m-level cascaded H-

Fig. 3. Flow chart of the P&O MPPT.

 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245 233

Table 2
Comparison of diode clamped and cascaded multilevel inverter topologies.
S. No. Topology Diode clamped Cascaded
1 Power semiconductor switches 2(m  1) 2(m  1)
2 Clamping diodes per phase (m  1)(m  2) 0
3 DC bus capacitors (m  1) (m  1)/2
4 Balancing capacitors per phase 0 0
5 Voltage unbalancing Average Small
6 Applications Motor drive system STATCOM Motor drive system, PV, fuel cells, battery system

Fig. 4. Five-level cascaded inverter topology.

bridge inverter typically consists of 2(m  1) main switch-
ing devices, 2(m  1) main diodes and (m  1)/2 capacitors
on the DC bus. Unlike the diode-clamp inverter, the cas-
caded inverter does not require any voltage-clamping
diodes.
The phase output voltage is synthesized by the sum of
four inverter output voltages Van = Va1 + Va2 + Va3 + Va4.
Each inverter level can generate three different voltage out-
puts, +Vdc, 0 and Vdc, by connecting the dc source to the
ac output side by different combinations of the four
switches, Sp1, Sp2, Sn1, and Sn2. When the switches Sp1
and Sp2, are turned ON, it gives Va4 = +Vdc. When the
switches Sn2 and Sn1, turned ON, it gives Va4 = Vdc.
When the all switches are turned OFF, it gives Va4 = 0.
Similarly, the ac output voltage at each level can be
obtained in the same manner. If NS is the number of dc
sources, the output phase voltage level is m = NS + 1.
Controlling the conduction angles at different inverter
levels can minimize the harmonic distortion of the output
voltage. If the phase current ia, is sinusoidal and leads or
lags the phase voltage Van by 90°, the average charge to
each dc capacitor is equal to zero over one cycle. Therefore,
all SDCS capacitor voltages can be balanced. Each H-
bridge unit generates a quasi-square waveform by phase
shifting its positive and negative phase-leg-switching tim-
ings. Table 3 shows the relationship between the output
voltage levels and switching states for the five-level topol-
ogy is shown in Fig. 5. Switches Spx and Snx
(x = 1, 2, 3, 4) are arranged in pairs and operate in a com-
plementary mode where Spx as positive switches and Snx as
negative switches. State condition ‘1’ means the switch is
ON and ‘0’ means the switch is OFF.
5. SVPWM algorithm
Different PWM techniques are applied for controlling
the active devices in a multilevel inverter (Colak et al.,
2011). In this paper, SVPWM technique is used to generate
PWM control signals to the inverter. Fig. 6 shows the space
234 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245

Table 3
Relationship between output level and switching states (1 indicates ON-states and 0 indicates OFF-states).
Output level Switching states
Sp1 Sp2 Sp3 Sp4 Sn4 Sn3 Sn2 Sn1
2Vdc 0 0 0 0 1 1 1 1
Vdc 1 0 0 0 1 1 1 0
0 0 0 1 0 1 1 1
0 0 1 0 1 0 1 1
0 1 0 0 1 1 0 1
0 1 1 0 0 1 1 0 0
0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0
1 0 0 1 0 1 1 0
0 1 0 1 0 1 0 1
0 1 1 0 1 0 0 1
+Vdc 1 1 1 0 1 0 0 0
0 1 1 1 0 0 0 1
1 0 1 1 0 0 1 0
1 1 0 1 0 1 0 0
+2Vdc 1 1 1 1 0 0 0 0

Fig. 6. Space vector diagram for two-level inverter.

Six = (2/p)(n  1)Vdc, where Vdc is the dc link voltage.

Fig. 5. One-leg circuit of five-level cascaded inverter.
For a NPC topology VP1Six = (2/p)(Vdc), this is same as
two-level inverter. The SVM is used to compensate the re-
quired volt-seconds using discrete switching states and their
ON-times produced by inverter.
In a two level inverter, ON-time calculation is based on
the location of reference vector within a sector Si, i = 1,
2 . . . , 6 for a two-level inverter, volt-second equation is,

V zT s ¼ V X T a þ V Y T b ð9Þ
vector diagram for two-level inverter. Modulation index
(MI) is defined as in Eq. (8) The volt-seconds in terms of components VZ, VX and VY of
V P1 along a – b axis are,
MI ¼ ð8Þ
V P 1Six
V Za T s ¼ T a þ 0:5T b ð10Þ
In Eq. (8), VP1 is the peak value of fundamental voltage V Z
¼ hT b ð11Þ
bT s
and VP1Six is the peak value of fundamental voltage at
six step operation. For a n-level cascaded topology VP1- Ts ¼ Ta þ Tb þ T0 ð12Þ
 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245 235

Solving Eqs. (10)–(12), obtain for the calculation of ON- In each sector, triangle can be classified into two types.
times, Type 1 triangle has its base side at the bottom. Type 2 tri-
" !# angle has its base side at the top. The triangle number Dj
V Zb T s
Ta ¼ Ts V a Z
ð13Þ can be determined in terms of two integer variables I1
2h and I2, which are dependent on the position of reference
" # vector (Va, Vb).
V Zb
Tb ¼ Ts ð14Þ  
h Vb
I 1 ¼ int V a þ pffiffiffi ð18Þ
3
T0 ¼ Ts  Ta  Tb ð15Þ  
Vb
In Eqs. (13) andp(14), I 2 ¼ int ð19Þ
ffiffiffi h is height of the triangle of sector h
S i fh ¼ 0:866 or ð 3=2Þg, assuming that the sides of the
equilateral triangle are unity. In Eqs. (13)–(15), TS = 1/ Eq. p(18) signifies
ffiffiffi p ffiffiffi part ofpffiffithe
ffi sector
pffiffiffi between the lines
(2fS), fS is the switching frequency. Fig. 7 shows the sector y þ 3 ¼ 3I 1 and y þ 3x ¼ 3ðI 1 þ 1Þ. This forms
1 for two-level inverter. one region. Eq. (19) signifies part of the sector between
Each sector can be split into (n  1) triangles, where n the lines y = hI1 and y = h(I1 + 1). This forms another re-
indicates level of the inverter. For any given reference vec- gion. The tip of reference vector is situated at the intersec-
tor, the sector of operation and its angle within the sector is tion of these two regions inclined at 120° and forms
determined by using Eqs. (16) and (17), respectively. triangle or rhombus.
  This rhombus is made of two triangles. Let (VaS, VbS)
h are the co-ordinates of the reference vector with respect
S i ¼ int þ1 ð16Þ
60 to the origin of the rhombus.
 
h
c ¼ rem ð17Þ V aS ¼ V a  I 1 þ 0:5I 2 ð20Þ
60
V bS ¼ V b  I 2 h ð21Þ
In Eqs. (16) and (17), h(0° 6 h 6 360°)is the angle of the ref-
erence vector with respect to a axis, cð0  c  60 Þ is the In Eqs. (20) and (21), (VaS/VbS) is the slope of the line be-
angle within the sector and Si(1 6 Si 6 6) is its sector oper- tween the origin of the rhombus and the reference vector
ation, int and rem is standard math function of integer and and it is compared
pffiffiffi with slope of the diagonal of the rhom-
reminder. The space vector diagram of a three phase voltage bus which is 3.
source inverter is a hexagon, consisting of six sectors. The pslope
ffiffiffi comparison is done by evaluating inequality
SVPWM algorithm is to identify the triangle in which ðV bS 6 3V aS Þ and to determine the small p vector
ffiffiffi VZ and
the tip of the reference vector is located. Each triangle the exact triangle number Dj. If the ðV bS 6 3V aS Þ, which
can be treated as a vector of a two level inverter. The indicates triangle of type 1 and these triangles are similar
ON-time can be calculated using small vector analogy to sector 1 of two-level inverter. The triangle number Dj
ON-time equation of the two-level inverter. Fig. 8 shows is obtained as
the space vector diagram for five-level inverter. Dj ¼ I 21 þ 2I 2 ð22Þ
pffiffiffi
If ðV bS > 3V aS Þ , which indicates the triangle of type 2
and these triangles are similar to sector 2 of two-level.
The triangle number Dj is obtained as
Dj ¼ I 21 þ 2I 2 þ 1 ð23Þ
In Eqs. (22) and (23), D indicates the triangle and j is the
triangle number and hence Dj is an integer and signifies
jth triangle in the sector. Using Eqs. (22) and (23), to iden-
tify triangle in a sector and the on times are calculated
using Eqs. (13)–(15). The Dj is formulated to provide a sim-
ple way of arranging the triangle, leading to ease of identi-
fication and extension to any level and it greatly simplifies
the PWM process as switching state can be easily mapped
with respect to Dj. The sector and switching states mapping
is shown in Table 4.

6. Inverter control

The inverter control circuit has the function to control

Fig. 7. Sector 1 for two-level inverter. the active and reactive power. In the decoupled d-axis
236 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245

Fig. 8. Space vector diagram for five-level inverter.

Table 4 The design used Xilinx development tools, namely

Sector and switching states mapping. works view, and is realized in a single FPGA chip with
Sector Phase A Phase B Phase C no external memory. The whole system is implemented in
S1 Sa Sb Sc only a single chip and more reliable, faster design, verifica-
S2 Sb Sc Sa tion time, and high performance. A standard FPGA design
S3 Sc Sa Sb flow should include circuit design and entry, functional
S4 Sa Sb Sc simulation, synthesize, post synthesize simulation, place-
S5 Sb Sc Sa
S6 Sc Sa Sb
and-route, post place-and-route simulation, board level
simulation and download and debug. The block diagram
for FPGA implementation of SVM control strategy is
shown in Fig. 9. The SVM generator based on finite state
and q-axis current control loops, two PI controllers are machine (FSM) is to implement the SVM algorithm. The
employed to eliminate current errors. The outputs of PI FSM consists of six states, which are waiting, a – b trans-
controllers are inductor filter voltage references V Ld and formation, sector selection, triangle determination, switch
V Lq that are superimposed by Vgd and Vgq to generate the states judgment, and dwell time configuration.
inverter output voltage references V d and V q for SVPWM. In this programming, FPGA using VHDL and coding
The current references id and iq are provided by the output are used to generate the SVPWM for the inverter circuit.
of PV array. Simulation steps are as follows.
At the end Vref is obtained, these are passed to inverter
control which gives outputs of pulses to drive the multilevel 1. Initialize system parameters using FPGA.
inverter switches. As there is dc-dc buck-boost converter 2. Perform VHDL coding to:
between the PV generator and the inverter, to get the i. Determine sector.
MPPT function. ii. Determine time duration Ta, Tb, T0.
iii. Determine the switching time of each sector.
7. FPGA implementation iv. Generate the inverter output voltage.
3. View the SVPWM waveforms through Xilinx.
FPGA is a silicon chip containing an array of logic con-
figurable blocks, consists of configurable logic block
(CLB), digital clock manager (DCM), and hardware multi-
pliers. The FPGA used in this project is Xilinx Spartan 3A, 8. Simulation results
which has 1.8 Million gates device. An ASIC can perform a
single function for the lifetime of the chip whereas FPGA Simulations are performed by using MATLAB/simulink
can be reprogrammed to perform different function in a for the proposed system. The SVPWM switching strategy is
matter of microseconds. used in this paper. The SVPWM output is generated from
 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245 237

Fig. 9. Block diagram for FPGA implementation SVM control with finite state machine.

Fig. 10. Switching instant of a SVPWM pulse waveform.

this simulink module. This involves determining the posi-
tion of reference vector according to fundamental fre-
quency f = 50 Hz, sampling frequency fs = 10 kHz and
time. According to sector wherein the reference vector is,
determine the switching sequence and to calculate the time
for different switching states. The switching instant of a
SVPWM pulse waveform is shown in Fig. 10. The modula-
tion index determines the shape of the output voltage of the
inverter. The simulation block diagram for proposed sys-
tem is shown in Fig. 11.
The MPPT using P&O tracks the operating point
quickly and accurately in irradiance level. The simulation
result of P&O MPPT tracking is shown in Fig. 12. Simula-
tion result for the two-level inverter is shown in Fig. 13.
Simulation result for the three-level inverter is shown in
Fig. 14. Simulation result for the proposed five-level inver-
ter is shown in Fig. 15. This shows that the generated line-
to-line voltage is much improved with the level of inverter.
The decoupling of the voltage loops V d and V q is good,
since the V q remains constant under variations which
shows high dynamic performance of the controllers. The
performance of the P&O with the three phase five-level cas-
caded H-bridge inverter also shows that output of the PV
follows its reference.
The THD levels of three phase two-level, three-level and
five-level are compared in Table 5. This proves that the
proposed scheme can reduce the THD which is indispens-
able condition for PV system. The results from five-level
SVPWM inverter are compared with those from two-level
SVPWM and three-level SVPWM inverter in terms of
THD. The THD measurement for the two-level inverter
is shown in Fig. 16. The THD measurement for the
238 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245

Fig. 11. Simulation block diagram for the proposed system.

three-level inverter is shown in Fig. 17. The THD measure- as the level of inverter, increases. From the results it is
ment for the proposed five-level inverter is shown in observed that the generated voltage spectrum is very much
Fig. 18. These shows the THD, which is highly reduced increased with the level of inverter. The THD measurement
 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245 239

Fig. 12. Simulation result of P&O MPPT tracking algorithm.

Fig. 13. Line-to-line voltage (Vab) two-level inverter.

Fig. 14. Line-to-line voltage (Vab) three-level inverter.

of the two-level inverter is 16.10% and three-level inverter
is 9.08%. The THD measurement of the proposed five-level
inverter is 5.68%.
The THD values of the proposed inverter are lower than
that of the five-level diode clamped multilevel inverter
(DCMLI) using sinusoidal PWM (SPWM) technique (Ravi
et al., 2011). The THD measurement of three-level DCMLI
is 35.27% and five-level DCMLI is 13.11% (Ravi et al.,
2011) as shown in Table 6. The fundamental component
of the output voltage is increased with the level of inverter.
This proves that the proposed scheme can reduce the THD
which is necessary criterion for PV system.
9. Experimental results
The simulation results are verified experimentally using
a FPGA Spartan 3A kit. The proposed two-level and
three-level inverter is tested with a PV array and the ratings
240 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245

Fig. 15. Line-to-line voltage (Vab) for proposed five-level inverter.

Table 5 VHDL code is developed to examine the switching pat-

Total harmonic distortion for the proposed system.
No of levels THD (%)
2 16.10
3 9.08
5 5.68
of PV module are shown in Table 1. The 1200 V, 25 A,
IGBT is used in cascaded H-bridge inverter. The 415 V,
1.8 A, 50 Hz, 1440 rpm, 1 HP three phase induction motor
is used as load. Prototypes two-level and three-level voltage
source inverter, to validate the simulation results are built.
terns of SVPWM method. This code is synthesized using
Xilinx ISE. The FPGA based generalized SVPW modula-
tor is applied to control these voltage source inverter to
track the given reference. The generation of SVPWM pulse
waveform for two-level inverter through Xilinx show in
Fig. 19. The generation of SVPWM pulse waveform for
three-level inverter through Xilinx show in Fig. 20.
The proposed system is tested in laboratory during
stand-alone operations. The block diagram for the control
system is shown in Fig. 21. The photograph of the experi-
mental setup that includes the FPGA is shown in Fig. 22.

Fig. 16. THD measurement for two-level inverter.

Fig. 17. THD measurement for three-level inverter.

 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245 241

Fig. 18. THD measurement for proposed five-level inverter.

Table 6 The solar panel is not shown in photograph. The voltage

Comparison between THD for proposed system with SPWM.
signals are scaled down to match the FPGA analog input
No of levels SPWM (%) Proposed SVPWM (%) level. These oscilloscope graphs demonstrate the good
3 35.27 9.68 quality of the obtained voltage waveforms, confirming sim-
5 13.11 5.68 ulation results. The triggered signals generated by the

Fig. 19. Generation of SVPWM pulse wave for two-level inverter.

Fig. 20. Generation of SVPWM pulse wave for three-level inverter.

242 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245

Fig. 21. Basic structure of the experimental setup.

Fig. 22. Photograph of experimental setup.

FPGA control the transistors of the multilevel inverter.
The two-level and three-level three phase cascaded inverter
with different switching states, are used in the experiments.
The switching frequency is 10 kHz. The THD levels of two-
level and three-level inverter are compared in Table 5. The
experimental system configuration is the same as that in
simulations.
The experimental result of controlling a two-level inver-
ter is shown in Fig. 23. The experimental result of control-
ling a three-level inverter is shown in Fig. 24. The
experimental results show that the FPGA based PV system
having output line-to-line voltage with lower THD. Better
performance can be obtained when the modulation index is
increased. Therefore, the overall efficiency of PV system
depends on the multilevel conversion with SVPWM con-
trol, P&O MPPT and DC-DC conversion. The use of
FPGA allows very high speed control loops, resulting in
significantly enhanced performance. In the output, wave-
forms have limited harmonic content; therefore, a small
and light output filter is sufficient for fulfilling electromag-
netic interference rules, thus reducing size and cost.
10. Conclusion
This paper presents FPGA based multilevel cascaded
inverters with SVPWM algorithm for photovoltaic system.
The configuration for the proposed system is designed and
simulated using MATLAB/simulink and implementation
in FPGA. The acceptable results for the proposed multi-
level cascaded inverter are summarized as follows.
 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245 243

Fig. 23. Line-to-line voltage (Vab) of two-level inverter.

Fig. 24. Line-to-Line voltage (Vab) of three-level inverter.

(1) The proposed system produces less dv/dt voltage
stress imposed on the switching devices and the
capacity to operate at a lower switching frequency.
(2) The P&O MPPT algorithm does not require any
additional hardware components. The PV system loss
decreases, execution speed increases, and requires less
conversion time.
(3) The SVPWM can provide proper selecting switching
states of the inverter, optimization of switching pat-
terns, and improving dc link voltage utilization. It is
more efficient than any other conventional PWM
methods.
(4) Embedding SVPWM in an FPGA creates the
increased controller bandwidth, high speed input out-
put response enables a precise switching, the flexible
adjustment of dead time, resulting in the reduction
of voltage harmonics which is very beneficial for the
output voltage quality.
(5) The FPGA can be more efficient than the conven-
tional controller due to fast prototyping, software
design and simple hardware design.
(6) It is seen from the simulation results that the gener-
ated voltage spectrum is very much improved with
increase in the level of the inverter for PV system.
The THD is highly reduced as the level of inverter
increases (5.68%). It is quite low as compared with
the conventional two-level inverter (16.10%) and
three-level inverter (9.08%). Hence, the optimum
power is transferred to drive a 1 HP three phase
induction motor.
244 M. Valan Rajkumar, P.S. Manoharan / Solar Energy 87 (2013) 229–245
(7) The THD value of the five-level DCMLI with SPWM
(13.11%) is higher than the THD value of the pro-
posed five-level with SVPWM (5.68%).
(8) The results obtained are full of promise to use the
multilevel cascaded H-bridge inverter with SVPWM
strategy are gained importance in high voltage, high
power, and high performance applications such as
PV generation system. The proposed system solves
commutation loss, electromagnetic interference, har-
monics and high frequency switching problems.
(9) The level of the inverter increases, the harmonic con-
tent of the output voltage waveform decreases. Thus,
the output voltage quality increases. It can be easily
extended to the n-number of levels.
Acknowledgment
One of the authors of this paper (P.S. Manoharan)
acknowledges University Grant Commission (UGC), India
for sanctioning the funding under major research project,
vide reference F.No. 40-468/2011 (SR).
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