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VLSI
VLSI
(ELECTRONICS) SEMESTER VI
(ELX -603)
VLSI Design
(ELXL-603)
Term-Work : 25 marks
Practical/Oral : 25 marks
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Course Objectives
Silicon IC Technology
Bipolar MOS
2 input
NAND gate
array
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Prepared by YP Sir (VESIT)
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Prepared by YP Sir (VESIT)
Figure :- Structural Decomposition of 4 bit Adder
May-15 (10M)
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Prepared by YP Sir (VESIT)
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Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
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Q. Explain the effect on drain current due to channel length
modulation and velocity saturation May-15/ (5M)
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Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Prepared by YP Sir (VESIT)
Parameter Name SPICE Unit
Name
Threshold Voltage Vto V
Transconductance Kp A/V2
Substrate-Bias Coefficient GAMMA V1/2
Surface Potential PHI V
Channel Length Modulation LAMBDA 1/V
Coefficient
Drain resistance RD Ώ
Source resistance RS Ώ