Low Power DC-DC Converter

WELCOME TO
ISSCC 2014
SESSION 23
ENERGY
HARVESTING
A 0.15-V Input Energy Harvesting Charge
Pump with Switching Body Biasing and
Adaptive Dead-Time for Efficiency
Improvement
Jungmoon Kim1,2, Philip K. T. Mok1, and Chulwoo Kim2
1Hong Kong University of Science and

Technology, Hong Kong
2Korea University, Korea
Outline
• Motivation
• Proposed Architecture
– Switching body biasing (SBB)
– Adaptive dead-time (AD)
– Switch-conductance (SW-G) enhancement
• Measurement Results
• Conclusions
© 2014 IEEE 23.1: A 0.15-V Input Energy Harvesting Charge Pump with Switching Body Biasing
International Solid-State Circuits Conference and Adaptive Dead-Time for Efficiency Improvement 2 of 34
Small-Scale Energy Harvesting
• Energy Harvesting (EH)
– Low voltage and low power condition
– An example of thermoelectric EH*
• Low-input-voltage (VIN) up-converters

– Inductive type vs. Capacitive type
* MPG-D751, Micropelt, Germany.
Inductive DC-DC for Low-VIN
• Inductive DC-DC Converters
– External battery* : VIN,MIN = 20mV
– External mechanical switch** : VIN,MIN = 35mV
– Post-fabrication process*** : VIN,MIN = 95mV
– Transformer† : VIN,MIN = 40mV
– LC-tank oscillator†† : VIN,MIN = 50mV
• Challenges
* Carlson, VLSI 2009
– Electrical start-up ** Y. K. Ramadass, ISSCC 2010
– Bulky components *** P-H Chen, ISSCC 2011
† J.-P. Im, ISSCC 2012
†† H.-Y. Tang, VLSI 2012
Capacitive DC-DC for Low-VIN
• Capacitive DC-DC Converters
– No bulky inductor
– Not start-up issue, just min. VDD issue
• Challenges
– Voltage conversion efficiency (VCE)
– Power conversion efficiency (PCE)
– Low-VIN operation
• Meindl limit
• Conduction loss (RON drop)
• Dead-time (TD) limitations
Meindl Limit*
• Fundamental limit on signal transfer
for binary switching transition
kT SS
Min. VDD = 2ln 2 ≅ 52mV ⋅ ln 1+ at 300°K
q 60mV
– Min. VDD depends on subthreshold swing (SS)**
– SS = 60mV/dec. ~ 100mV/dec.
– Min. VDD = 36mV ~ 50mV
• Capacitive converter limit = Meindl limit
* J. D. Meindl and A. J. Davis, JSSC 2000, pp 1515-1516.
** Bo Zhai et al., TVLSI 2005, pp 1239-1252.
Conventional Doublers (1)
• CP-cross w/ cross-coupled load switches*
* Y. Nakagome et al., JSSC 1991, pp 465-472.

Conventional Doublers (2)
• CP-LS w/ load switches driven by level
shifter (LS)*
* P. Favrat et al., JSSC 1998, pp 410-416.

Conductance Comparison
• Conductance degradation @ low VIN
Bulk Switching (BS)
• BS* : Poor VCE and PCE at low VIN
MN1, MN2
Low ION
ON
Reverse bias
Low leakage
OFF
Reverse bias
MP1, MP2
Normal ION
ON
No body effect
Normal leakage
OFF
No body effect
* P. Favrat et al., JSSC 1998, pp 410-416.

Forward Body Biasing (FBB)
• FBB* : Good VCE but poor PCE
MN1, MN2
High ION
ON
Forward bias
High leakage
OFF
Forward bias
MP1, MP2
High ION
ON
Forward bias
High leakage
OFF
Forward bias
* P.-H. Chen et al., CICC 2010, pp 239-242.

Switching Body Biasing (SBB)
• Proposed SBB : How to control?
MN1, MN2
High ION
ON
Forward bias
Low leakage
OFF
Reverse bias
MP1, MP2
High ION
ON
Forward bias
Low leakage
OFF
Reverse bias
Proposed CP Architecture
• Low VIN operation and PCE improvement
by three simple & cost-effective solutions
CLK / CLKB / N / NB
E / EB
• CLK / CLKB
 overlapped
• N / NB / E / EB
 non-overlapped
Unit CP
• SBB to maximize PCE
• SW-conductance enhancement for low VIN
SBB : CLK = High, E = Low
• MN1 off ← RBB, MN2 on ← FBB
SBB : CLK = Low, E = High
• MN1 on ← FBB, MN2 off ← RBB
Fixed Dead-time Circuit
• In EH CP, VIN is low and not fixed → TD variation
– Power throughput, PCE, and reliability issues
• Fixed dead-time circuit is not effective @ low VIN
• How to control TD for low-power and low-voltage

charge pump?
1. Supplying more current @ low VIN for faster
transition of delay cells
2. Multiplexing : long TD @ high VIN, short TD @
low VIN  Parallelism
– Where should MUX be inserted?
Adaptive Dead-time (AD) Circuit
• Binary selection
for dead-times
Dead-time Circuits
Short
Dead-time
(τS)
Long
Dead-time
(τL)
Dead-time vs. VIN
• As VIN increases, τS causes reverse current.
• As VIN decreases, τL is prohibitively increased.
• tpHL α/(VDD – VTH,N – VDSATn/2)
IN BD
Low-VIN Detector
• As VIN increases, SEL = L  H
• VIN < VBD : SEL=L, VIN > VBD : SEL=H
Temp. & Process Variations
• VIN = VIN,X : τL @ 60°C  τS @ 10°C
• VBD is shifted from VBD,X (= 0) to VBD,Y
Temp. [°C]
Corner
VTH
VTH
Normalized IIN
Normalized IIN
Switch-Conductance Enhancer
• E and EB for SBB and SW-G enhancement
Chip Microphotograph
• 0.13μm CMOS technology w/ triple well
• 10nF off-chip pumping capacitors
 low-frequency and low-voltage CP
Measurement Results (Unit-CP)
• Pumped CLKs and VOUT @ VIN = 0.3V
Measurement Results (Nega-CP)
• CN should be optimized for better PCE
Dead-time Measurement
• SBB and SW-G techniques are applied
• VBD was up-shifted from simulated value
L
IN
Efficiency at Low-VIN
PCE Comparison of CPs
Power Throughput Improvement
Efficiency at High-VIN
Maximum Ripple Voltage
Performance Comparison
CICC 2010 ASP-DAC 2012 TCAS-II 2011 This work
Process 65nm CMOS 65nm CMOS 0.13μm CMOS 0.13μm CMOS
CP Type 3-stg doubler 10-stg CP 3-stg CP 3-stg doubler
Clock Freq. 10MHz 1MHz, 20MHz 800kHz 250kHz
Min. VIN 0.18V 0.12V 0.27V 0.15V
VOUT 0.6V 0.77V 1.3V 0.619V
@ No load @ VIN = 0.18V @ VIN = 0.12V @ VIN = 0.35V @ VIN = 0.18V
34%
38.8% 56% @ VIN = 0.18V,
Max. PCE N/A
@ VIN = 0.12V @ VIN = 0.45V 72.5%
@ VIN = 0.45V
7μA
IOUT 8.75μA 5μA 21μA
@ VIN = 0.12V
@ VOUT = 0.5V @ VIN = 0.18V @ VIN = 0.45V @ VIN = 0.18V
(by extrapolation)
Conclusions
• SBB improves PCE at low VIN
• AD circuit and SW-G enhancer push
VIN of CP to lower value
• PCE is improved by 17% at VIN=0.2V
by turning on AD circuit
• Also, the proposed CP works at
VIN,MIN = 0.15V
A 1.1nW Energy Harvesting System
with 544pW Quiescent Power for
Next-Generation Implants
Saurav Bandyopadhyay1,*, Patrick P. Mercier1,2,
Andrew C. Lysaght3, Konstantina M. Stankovic3,4 and
Anantha P. Chandrakasan1
1Massachusetts
Institute of Technology, Cambridge MA,
2University of California, San Diego, La Jolla, CA,
3Massachusetts Eye and Ear Infirmary, Boston, MA,
4Massachusetts General Hospital, Harvard University, Boston, MA
*now with Texas Instruments, Dallas, TX
© 2014 IEEE
International Solid-State Circuits Conference 23.2: A 1.1nW Energy Harvesting System with 544pW Quiescent Power for Next Generation Implants 1 of 32
Motivation for Energy Harvesting
Electronic Sensors Emerging Biomedical
Circuits and Systems
Wearable ECG Patch (IMEC, 2008) Bionic Lens (Univ. Washington, 2008)
Automotive Applications Flexible circuits (Univ. Illinois, 2012)
© 2014 IEEE
PMU Challenges in Energy Harvesting
Maximum Low quiescent Power Converter

Power current in always on End-to-End
Extraction circuits Efficiency
© 2014 IEEE
Recent Advancement in Harvesting Bio-Potentials
Reference:- P.P. Mercier, A.C. Lysaght, S. Bandyopadhyay, K.M. Stankovic and

A.P. Chandrakasan, “Energy Extraction from the biologic battery in the inner
ear”, Nature Biotechnology, Dec 2012
© 2014 IEEE
nW Power Management Unit
Maximum Extractable Efficient Boost Converter

Power is 1.1-6.25nW for 30-55mV to 1V
With VIN 30-55mV conversion at nW levels
10-100’s of pW Quiescent
Power of Controller for
sustainability
© 2014 IEEE
Outline
 Details of the nW Power Management Unit
• Boost Converter- Design Considerations and Losses
• Charge Pump for Leakage Reduction
• pW Control Circuits
 Measured Results
• Boost Converter Efficiency
• Quiescent Power of Controller
• Transient Measurements
 Comparison with state-of-art and Conclusions
© 2014 IEEE
nW Boost Converter Operation
Single Power Conversion Stage for increased efficiency

© 2014 IEEE
nW Boost Converter Operation
Long idle time compared to Φ1

and Φ2 durations in DCM
© 2014 IEEE
Boost Converter Traditional Losses
Conduction Loss = IN,RMS2 RDS,N + IP,RMS2 RDS,P + IIN,RMS2 RESR
Switching Loss = CG,NVGATE2 fs+ CG,PVGATE2 fs + 0.5CPARVDD2 fs
From Power FETs From Parasitics

© 2014 IEEE
Additional Considerations for nW Operation
fs of 1KHz, VDD of 1V CPAR typically ~5pF

Switching Loss of 2.5nW
Loss due to Power FET Low Leakage Output

leakage of 243pW in typical Capacitor
and >1nW in the fast corner
© 2014 IEEE
Boost Converter Efficiency Optimization
Overall Loss = Switching Losses (∝CV2fs ) +
Conduction Losses (Irms2 R ) + Leakage Losses
Optimization w.r.t fs, WN and WP under ZIN constraint

with leakage considerations
© 2014 IEEE
Boost Converter Frequency Optimization
Optimum Switching Frequency under ZIN constraint

© 2014 IEEE
Leakage Paths
Loss due to Leakage from Loss due to Leakage from

Input of 40mV: 20pW Output of 0.9V: 223pW
Power Loss due to Leakage from Output Path more than

from Input Path
© 2014 IEEE
Reducing Leakage Losses
Output Leakage governed

by PMOS sub-threshold
conduction
© 2014 IEEE
Reducing Leakage Losses
PMOS leakage reduced by

VPUMP (~1.6V) generated
using a Voltage Doubler
© 2014 IEEE
Charge Pump
 VDD (~0.9V) converted to VPUMP (1.6-1.7V) with 77% efficiency

 All capacitors- CPUMP and CDECAP integrated
© 2014 IEEE
Charge Pump Operation
Phase 1 Operation
© 2014 IEEE
Charge Pump Operation
Phase 2 Operation
© 2014 IEEE
pW Charge Pump Benefit
Charge Pump Leakage

Output Power 30pW Reduction by
223pW
Effective Power
Savings of 188pW,
17% of power budget
Effective Savings
950pW at the fast
Charge Pump Input Power ~40pW @ 77% efficiency corner
© 2014 IEEE
Φ1 Pulse Generation
All-digital Implementations
minimize quiescent power
© 2014 IEEE
Φ2 Pulse Generation
All-digital Implementations
minimize quiescent power
© 2014 IEEE
Ultra-low power Timer
Voltage divider generating Relaxation Oscillator with Clock
VREF1 and VREF2 Divider and Constant gm-Current
Reference for ICHG1 and ICHG2
© 2014 IEEE
Die Micrograph
Sensor Implemented in a 0.18μm CMOS Process

© 2014 IEEE
Sensor PCB
Φ1Gen. Boost
Clk. Φ2Gen.
Div
VPUMP Decoupling
Voltage
pW Voltage Doubler
Osc. Ref.
Current
Reference
© 2014 IEEE
Outline
 Details of the nW Power Management Unit
• Boost Converter- Design Considerations and Losses
• Charge Pump for Leakage Reduction
• pW Control Circuits
 Measured Results
• Boost Converter Efficiency
• Quiescent Power of Controller
• Transient Measurements
 Comparison with state-of-art and Conclusions
© 2014 IEEE
Boost Converter Output Power
© 2014 IEEE
Boost Converter Efficiency
© 2014 IEEE
Effect of Smaller Boost Converter Inductance
© 2014 IEEE
Quiescent Power and Design Summary
PMU Design Summary
0.18μm
Technology
CMOS
Φ1Gen. Boost Input Voltage 20-70mV

Clk. Φ2Gen.
Div
VPUMP Decoupling
Output Voltage 0.8-1.1V
Voltage
pW Voltage Doubler Peak Efficiency 56%
Osc. Ref.
Current Quiescent Power

Reference of Controller and 544pW
Auxiliary Circuits
© 2014 IEEE
Transient Results
© 2014 IEEE
Comparison with State-of-Art
ISSCC 2012 TPS62736 ISSCC 2011 This Work
Switched
Capacitor Boost with Voltage
Topology Boost Buck
Charge Pump Doubler
(Boost)
Inductive Boost:-
20-70mV boosted to
80mV-2.5V 2-5.5V step 450mV
Voltage 0.8-1.1V
boosted to 3- down to 1.3- boosted to
Conversion Charge Pump:-
5V 5V 3.6V
0.8-1.1V boosted to
1.5-1.9V
Converter 2.5μW- 10nW to
1μW-30mW 544pW-4nW
Output Power 125mW 160nW
Converter
Efficiency at 55% at 53% at 1.2nW
20% at 1μW 35% at 10nW
Ultra-Low 2.5μW (1.1nW in PMU)
Power
Quiescent
9.9nW 760nW 7.3nW 544pW
Power
© 2014 IEEE
Conclusions
 Power Management Unit of a sensor with an overall power

budget of 1.1nW
 Ultra-low power boost converter with peak 56% efficiency for

ultra-low energy harvesters
 pW Charge Pump for leakage reduction in boost converter
 Always on Circuits (Control and Bias) with 544pW quiescent

power for system sustainability
Acknowledgements:-
This work is funded by the C2S2, IFC, US National Institutes of Health
grants K08 DC010419 and T32 DC00038 and the Bertarelli Foundation.
© 2014 IEEE
A 3nW Fully Integrated Energy Harvester
Based on Self-Oscillating Switched-
Capacitor DC-DC Converter
Wanyeong Jung, Sechang Oh, Suyoung Bang,

Yoonmyung Lee, Dennis Sylvester, David Blaauw
University of Michigan, Ann Arbor, MI
© 2014 IEEE 23.3: A 3nW Fully Integrated Energy Harvester Based on Self-Oscillating Switched-Capacitor DC-DC Converter
International Solid-State Circuits Conference 1 of 79
Motivation
• Powering small wireless systems
– Limited battery capacity due to
small size
– Harvested power is also limited
by small form factor
1 mm3 Die-Stacked Sensing system
[ Y. Lee et al., JSSC 2013 ]
• Efficient DC-DC up-conversion at low power

level is required
– Boost converters require a large inductor
– Switched-capacitor DC-DC converters can be
made small
Conventional Voltage Doubler
• Clock generator + Level shifter + SCN
VOUT
ΦHIGH
CLS VIN CFLY

En ΦLOW
Φ
Clock Generator Switched Capacitor

Level shifter
& Switch driver Network
• Clock makes flying caps oscillate between
VIN - VSS and VOUT – VIN
VOUT
VOUT
ΦHIGH VIN
CLS VIN CFLY
En VSS VIN
Φ ΦLOW
VSS

Level shifter
• Clock makes flying caps oscillate between
VIN - VSS and VOUT - VIN
VOUT
VIN
ΦHIGH 2VINVOUT
CLS VIN CFLY
En VIN VSS
Φ ΦLOW
VIN

Level shifter
• Extra power overhead for
clock generation and level shifting
VOUT
ΦHIGH
CLS VIN CFLY

En ΦLOW
Φ

Level shifter
Proposed Voltage Doubler
• To reduce power overhead,
clock generator and level shifter are removed
• How to make SCN operate by itself?
VOUT
VIN CFLY
Switched Capacitor
Network
– Add another SCN stage to drive the next
VOUT VOUT
VIN CFLY VIN CFLY
– Add another SCN stage to drive the next
VOUT VOUT VOUT
VIN CFLY VIN CFLY VIN CFLY
– The first stage is driven by the last
– SCNs oscillate by themselves
VOUT VOUT VOUT
VIN CFLY VIN CFLY VIN CFLY
Self-Oscillating Voltage Doubler
• N stages (N is odd, ≥ 3)
• 3 Power terminals - VLOW, VMED, VHIGH
VHIGH
+
C1 C2 CN
VMED
VOUT
+
VIN
- -
VLOW
N stages
• Bottom ring oscillator operates between
VMED and VLOW
VHIGH
+
C1 C2 CN
VMED
VOUT
+
VIN
- -
VLOW
N stages
• Top ring oscillator operates between
VHIGH and VMED
VHIGH
+
C1 C2 CN
VMED
VOUT
+
VIN
- -
VLOW
N stages
• Top and bottom oscillations are coupled
through flying caps
• Two oscillations become matched in clock amplitude
as well as frequency
VHIGH
+
C1 C2 CN
VMED
VOUT
+
VIN
- -
VLOW
N stages
Operation Example (N = 3)
• Simplified operation snapshot
– Cap connections not shown
– C1, C3 are at the higher rail
C 3P VOUT
– C2 is at the lower rail C 3M VIN
VSS
VOUT
VOUT 2VIN - Δ C2P VIN
C1P C3P C2M VSS
C1 C3
C1P VOUT
C2P C1M VIN

VIN
VSS
C1M C3M
C2 2VIN
Δ
VOUT
C2M
VSS
Time
• C1 is driven low and charged
C3P VOUT
C3M VIN
C1: VDD – Δ VDD VSS

(C1 is charged) VOUT
C3P C2M VSS
C3
C1P VOUT
C1M VIN
VIN C1P C2P
VSS
C3M
C1 C2 2VIN
Δ
VOUT
C1M C2M
VSS
Time
• C2 is driven high and discharged,
dumping charge Δ∙C2 to VOUT
C3P VOUT
C3M VIN
C2: VDD VDD – Δ VSS

(C2 is discharged) VOUT
Δ C2 is dumped to output VOUT 2VIN - Δ C2P VIN
C2P C3P C2M VSS
C2 C3
C1P VOUT
C1M VIN
VIN C1P
VSS
C2M C3M
C1 2VIN
Δ
VOUT
C1M
VSS
Time
• C3 is driven low and charged
C3P VOUT
C3M VIN
C3: VDD – Δ VDD VSS

(C3 is charged) VOUT
C2P C2M VSS
C2
C1P VOUT
C1M VIN
VIN C1P C3P
VSS
C2M
C1 C3 2VIN
Δ
VOUT
C1M C3M
VSS
Time
• C1 is driven high and discharged,
dumping charge Δ∙C1 to VOUT
C3P VOUT
C3M VIN
C1: VDD VDD – Δ VSS

(C1 is discharged) VOUT
Δ C1 is dumped to output VOUT 2VIN - Δ C2P VIN
C1P C2P C2M VSS
C1 C2
C1P VOUT
C1M VIN
VIN C3P
VSS
C1M C2M
C3 2VIN
Δ
VOUT
C3M
VSS
Time
• No overhead for clock and level shifting
• Negligible efficiency loss from
phase mismatch and contention loss
• Naturally multi-phased C
C
3P VOUT
VIN
3M
 Low VOUT ripple VSS
• Capable of self-startup C 2P
VOUT
VIN
C2M VSS
C1P VOUT
C1M VIN
VSS
2VIN
Δ
VOUT
Time
Doubler Efficiency Optimization
• Efficiency = 1 – (PLOSS / PIN)
• Analyze PLOSS / PIN in terms of Δ / VIN
– Δ is voltage drop at VOUT (VOUT = 2VIN – Δ)
– Multi-phase operation makes VOUT and Δ near DC
PLOSS / PIN
Δ / Vin
• Total loss ≈ Conduction loss + Switching loss
• Loss from leakage is usually negligible
PLOSS / PIN
Leakage – Usually negligible
Δ / Vin
• Conduction loss comes from VOUT drop
– PLOSS_CONDUCTION / PIN ∝ Δ / VIN
PLOSS / PIN
Conduction Loss
Δ / Vin
Δ / Vin
• Switching loss comes from dynamic power
– Larger Δ increases transferred energy per clock
– PLOSS_SWITCHING / PIN ∝ VIN / Δ PLOSS / PIN
Conduction Loss
Δ / Vin
Switching Loss
Vin / Δ
Δ / Vin
• At minimum loss point, Δ / VIN is at fixed point
– Independent of VIN, Frequency, Load current
Total Loss
PLOSS / PIN
PLOSS / PIN
Conduction Loss
Δ / Vin
Minimum loss point

Switching Loss
Vin / Δ
Δ / Vin = (Constant) Δ / Vin

Frequency Modulation for Optimum Δ
• For desired Δ / VIN, VOUT is compared to VIN
Δ = 2VIN – VOUT,
VIN = VOUT / (2 – Δ / VIN) = VOUT / R_DIV
• Feedback control of oscillation frequency to keep

VDIV = VOUT / R_DIV at the same level as VIN
VDIV f
VOUT ÷R_DIV VOUT Adjusted to
achieve target Δ
f
VIN
VHIGH
+
VMED
VOUT
+
VIN
- -
VLOW
Self-oscillating doubler
• VDIV = VOUT / R_DIV ( R_DIV ≡ 2 – Δ / VIN )
VHIGH
Voltage VDIV
+
Divider
VMED
VOUT
+
VIN
- -
VLOW
• VDIV is periodically compared to VIN
VHIGH
Voltage VDIV
+
Divider
VMED VMED
VOUT
+ ClkOUT
÷M
VIN
- -
VLOW
• VDIV is periodically compared to VIN to adjust VCTR
VHIGH
Voltage VDIV
+
Divider
Charge
VMED VMED
VOUT
Pump
+ ClkOUT
÷M
VIN
- -
VLOW VCTR
• VDIV is periodically compared to VIN to adjust VCTR
• Feedback control of stage delay through VCTR
VHIGH
Voltage VDIV
+
Divider
Charge
VMED VMED
Delay
Delay
Delay
VOUT
Pump
+ ClkOUT
÷M
VIN
- -
VLOW VCTR
• Oscillator operates regardless of initial VCTR value
– Capable of self-startup
• VCTR goes to minimum when input power unavailable
– Low idle power consumption at output
VHIGH
Voltage VDIV
+
Divider
Charge
VMED VMED
Delay
Delay
Delay
VOUT
Pump
+ ClkOUT
÷M
VIN
- -
VLOW VCTR
Self-oscillating doubler Frequency controller

Blocks for Frequency Modulation
VHIGH
Voltage VDIV
+
Divider
Charge
VMED VMED
Delay
Delay
Delay
VOUT
Pump
+ ClkOUT
÷M
VIN
- -
VLOW VCTR

• Voltage divider
– Slow diode stack for DC division VHIGH
– Fast capacitive voltage division
VDIV
VHIGH
Voltage VDIV
+
Divider
Charge
VMED VMED VLOW
Delay
Delay
Delay
VOUT
Pump
+ ClkOUT
÷M
VIN
- - Voltage divider
VLOW VCTR

• Charge pump
– CSTEP determines the CSTEP
amount of charge flow Output

isolation
per cycle
VCON
– Output is isolated Pull up Pull down
when idle to sustain

COUT
CSTEP
VCTR for long period

Charge pump
VHIGH
Voltage VDIV
+
Divider
Charge
VMED VMED
Delay
Delay
Delay
VOUT
Pump
+ ClkOUT
÷M
VIN
- -
VLOW VCTR

• Voltage controlled synchronized delay
• Leakage-based delay element provides long delay
with low energy consumption
[G. Chen, ISSCC 2010]
In Out Out In
VHIGH
Voltage VDIV
+ Leakage-based delay element
Divider
Charge
VMED VMED
Delay
Delay
Delay
VOUT
Pump
+ ClkOUT
÷M
VIN
- -
VLOW VCTR

• Isolation transistors are turned off
to operate it as a 2-way thyristor, 1 0 0 1 1 0 0 1
providing long, sharp delay

VHIGH
Voltage VDIV
+ 1 0 Transition
Divider
Charge
VMED VMED
Delay
Delay
Delay
VOUT
Pump
+ ClkOUT
÷M
VIN
- -
VLOW VCTR

• Isolation transistors are turned off
to operate it as a 2-way thyristor, 0 1 1 0 0 1 1 0
providing long, sharp delay

VHIGH
Voltage VDIV
+ 0 1 Transition
Divider
Charge
VMED VMED
Delay
Delay
Delay
VOUT
Pump
+ ClkOUT
÷M
VIN
- -
VLOW VCTR

– Leakage-based delay element provides long delay
• Pass transistor controlled by VCTR provides
additional leakage path to output, controlling delay
Delay element
VMED
VHIGH
Voltage VDIV
+ LK' LK+1 LK+1'
Divider
VMED VMED
Charge VLOW
Delay
Delay
Delay
VOUT
Pump
+ ClkOUT
÷M
VIN
- - TP
Additional
VLOW VCTR
leakage path
VCTR
– Delay is controlled by VCTR
• Top oscillation is also delayed
VHIGH
HK' HK+1 HK+1'
CK+1
VMED
VHIGH
Voltage VDIV
+ LK' LK+1 LK+1'
Divider
VMED VMED
Charge VLOW
Delay
Delay
Delay
VOUT
Pump
+ ClkOUT
÷M
VIN
- - TP
VLOW VCTR

VCTR
– Delay is controlled by VCTR
• Delayed output nodes are coupled to synchronize
delays of two oscillations V HIGH
HK' HK+1 HK+1'
CK+1 CK+1'
VMED
VHIGH
Voltage VDIV
+ LK' LK+1 LK+1'
Divider
VMED VMED
Charge VLOW
Delay
Delay
Delay
VOUT
Pump
+ ClkOUT
÷M
VIN
- - TP
VLOW VCTR

VCTR
Achieving Higher Conversion Ratios
• Cascading voltage doublers
– Each doubler oscillates in its own clock domain to
maintain optimum efficiency
– Base conversion ratio: 2N
Achieving higher ratios
• Cascading voltage doublers
– Each doubler oscillates in its own clock domain to
maintain optimum efficiency
– Base conversion ratio: 2N
– Example: 4 stages – 24 = 16X base ratio
2X 4X 8X
16X
VIN VOUT
X2 X2 X2 X2
VSS VSS VSS VSS

• Bottom voltage modulation
– Modifying bottom voltage changes VOUT
2X 4X 8X
16X
VIN VOUT
X2 X2 X2 X2
VSS VSS VSS VSS

– Example: VSS  VIN at Final stage
2X 4X 8X
16X
VIN VOUT
X2 X2 X2 X2
7X
VSS VSS VSS VIN : 1X
– Example: VSS  VIN at Final stage  15X (-1X)
– VOUT = VBOT + 2(VIN – VBOT) = 2VIN – VBOT
2X 4X 8X 7X
15X (-1X)
VIN VOUT
X2 X2 X2 X2
7X
– Earlier stage has greater effect on ratio
2X 4X 8X
15X
VIN VOUT
X2 X2 X2 X2

– Example: VSS  VIN at 2nd stage
2X 4X 8X
15X
VIN VOUT
X2 X2 X2 X2
VSS VIN : 1X VSS VIN : 1X

2X 3X (-1X) 8X
15X
VIN VOUT
X2 X2 X2 X2

2X 3X (-1X) 6X (-2X)
15X
VIN VOUT
X2 X2 X2 X2

– Example: VSS  VIN at 2nd stage  11X (-4X)
2X 3X (-1X) 6X (-2X)
11X (-4X)
VIN VOUT
X2 X2 X2 X2

– Example: VSS  VIN at 2nd stage  11X
– All changes are linearly combined
– Arbitrary integer ratio can be achieved
2X 3X 6X
11X
VIN VOUT
X2 X2 X2 X2

Harvester System Architecture
• Up-conversion from low voltage
harvesting source to battery
– VIN ≈ 0.3V (for solar cell), VOUT ≈ 4V (for battery)
VOUT 4V
Power VIN 0.3V Around 10X ~ 20X

source Upconversion is
required
• 4 cascaded voltage doublers – base 16X ratio
VOUT
VHIGH
Power VIN VMED
X2 X2 X2 X2
source
VLOW
VHIGH
VMED
Delay
Delay
Delay
Frequency
Control
VLOW
Single Voltage Doubler Stage
• Operating voltage is different at each stage
– Bootstrapped lower VTH drivers at 1st stage
– Thick-oxide IO devices at the final stage
VOUT
Power VIN
X2 X2 X2 X2
source
Bootstrapped
lower VTH driver
High VTH Thck
oxide device
• Conversion ratio modulation for optimum VIN level
• Bottom voltage is selected from VIN, GND, VNEG
– VNEG is generated using same doubler structure
• 16X – 23X ratios
VOUT
Power VIN
X2 X2 X2 X2
source
VLOW
VHIGH selector
VMED
X2
VLOW
VNEG -VIN
Bootstrapped
Negative Voltage
Generator lower VTH driver
High VTH Thck
oxide device
• Conversion ratio modulation for optimum VIN level
• Bypass 1st stage for lower ratios (9X – 15X)
• 9X – 23X ratios
VOUT
Power VIN 1
X2 X2 X2 X2
source 0
X2
VNEG
Bootstrapped
lower VTH driver
High VTH Thck
oxide device
• Ratio controller operates between VIN and VNEG
for better self-startup capability
VOUT
Power VIN 1
X2 X2 X2 X2
source 0
X2
Bypass
VNEG
VDD VSS Bootstrapped
Ratio Switch lower VTH driver
container mapping
High VTH Thck
Conversion Ratio Controller oxide device
• Whole system is fully integrated on chip
• No external devices are needed
• Capable of self-startup with low VIN (140mV,
measured)
VOUT
Power VIN 1
X2 X2 X2 X2
source 0
X2
Bypass
VNEG On Chip
VDD VSS Bootstrapped
Ratio Switch lower VTH driver
container mapping
High VTH Thck
Conversion Ratio Controller oxide device
Die Micrograph
• 0.18µm CMOS test chip
• Standalone voltage doubler: 0.069mm2, 54pF total
flying cap
• Harvester: 0.86mm2, 600pF total flying cap
Negative Standalone
Doubler
Voltage 0.069mm2
Generator
0.81mm
2nd stage
Doubler
Switches
1st stage
4th stage
Doubler
3rd stage
Doubler Doubler
1.06mm
Test Setup
• Test with voltage / current source
• Test with silicon solar cell chip
– 0.84mm2 130nm CMOS (~10nW under room light)
VOUT = 4.066V
92Lux
1mm
0.84mm
Solar
Cell
Test Chip Solar Cell
(0.84mm2)
MEASURED RESULTS
Standalone Voltage Doubler
• VIN = 1.2V, R_DIV = 1.73 (for Δ to be 0.27 VIN)
• Near maximum efficiency over >105 range
• Idle power consumption: 170pW @ 1.2V VIN
2.4 1.0 100M 2.2

VIN = 1.2V VIN = 1.2V 2.0
2.3 0.9
Max. Efficiency = 75% 10M
Conversion Efficiency
0.8 1.8
Output Voltage (V)
2.2
Frequency (Hz)
0.7 1M 1.6
2.1
1.4
0.6 100k
2.0 1.2
V CTR
0.5
1.9 10k 1.0
0.4
0.8
1.8 1k
0.3
0.6
1.7
Output Voltage 0.2 Frequency 0.4
100
1.6 Conversion Efficiency 0.1 VCTR 0.2
10
1.5 0.0 0.0
1n 10n 100n 1µ 10µ 100µ 1m 1n 10n 100n 1µ 10µ 100µ 1m
Load Current (A) Load Current (A)
Standalone Voltage Doubler
• VIN = 1.2V, R_DIV = 1.73 (for Δ to be 0.27 VIN)
• Near maximum efficiency over >105 range
• Idle power consumption: 170pW @ 1.2V VIN
2.4 1.0 100M 2.2

VIN = 1.2V VIN = 1.2V 2.0
2.3 0.9
Max. Efficiency = 75% 10M
0.8 1.8
Output Voltage (V)
2.2
Frequency (Hz)
0.7 1M 1.6
2.1
1.4
0.6 100k
2.0 1.2
V CTR
0.5
1.9 10k 1.0
0.4
0.8
1.8 1k
0.3
0.6
1.7
Output Voltage 0.2 Frequency 0.4
100
1.6 Conversion Efficiency 0.1 VCTR 0.2
10
1.5 0.0 0.0
1n 10n 100n 1µ 10µ 100µ 1m 1n 10n 100n 1µ 10µ 100µ 1m
Comparison of Voltage Doubler
This work
JSSC 2010 [5] VLSI 2010 [6] VLSI 2009 [7]
(Doubler)
45nm SOI CMOS
Technology 32nm CMOS 0.13μm CMOS 0.18μm CMOS
w/ trench cap
Multi-phase 1:2 step-up/down Multi-phase Self-oscillating
Architecture
voltage doubler converter voltage doubler voltage doubler
Conversion
1:2 2 : 1, 1 : 2 1:2 1:2
ratio
Tested input
1V-1.2V 1V 1V-1.2V 1.2V
voltage
Frequency 250MHz-2GHz 1 100MHz N/R 70Hz-19MHz
Peak efficiency 64% 90% 82% 75%
0.4mA-9mA 0.5mA-5mA 0.15mA-2.2mA 1nA-0.35mA

Load range
w/ η > 40% 1 w/ η > 80% 1 w/ η > 70% 1 w/ η > 70%
Area 0.0067mm2 0.0012mm2 2.25mm2 0.069mm2
N/R: Not reported

1 : Estimated number from the paper
This work
JSSC 2010 [5] VLSI 2010 [6] VLSI 2009 [7]
(Doubler)
45nm SOI CMOS
w/ trench cap
Architecture
Conversion
1:2 2 : 1, 1 : 2 1:2 1:2
ratio
Tested input
1V-1.2V 1V 1V-1.2V 1.2V
voltage

Load range
w/ η > 40% 1 w/ η > 80% 1 w/ η > 70% 1 w/ η > 70%
Area 0.0067mm2 0.0012mm2 2.25mm2 0.069mm2
N/R: Not reported

This work
JSSC 2010 [5] VLSI 2010 [6] VLSI 2009 [7]
(Doubler)
45nm SOI CMOS
w/ trench cap
Architecture
Conversion
1:2 2 : 1, 1 : 2 1:2 1:2
ratio
Tested input
1V-1.2V 1V 1V-1.2V 1.2V
voltage

Load range
w/ η > 40% 1 w/ η > 80% 1 w/ η > 70% 1 w/ η > 70%
Area 0.0067mm2 0.0012mm2 2.25mm2 0.069mm2
N/R: Not reported

Harvester
• Conversion ratio control
– VOUT of 2.2V to 5.2V from 0.35V VIN
0.5
5
3 stages 0.4
Harvester Efficiency
4
Harvester VOUT (V)
4 stages 0.3
3
2 0.2
VIN = 0.35V VIN = 0.35V
Load current = 10nA Load current = 10nA
1 0.1
0 0.0
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Conversion Ratio Conversion Ratio
Harvester
• Result for VIN = 0.25V, 0.35V, and 0.45V
– Conversion ratio controlled to keep VOUT flat
– Idle power consumption: <3nW
0.5
5
Output Voltage (V)
0.4
4
3 0.3
5nW-5μW Output power
2 0.2
VIN = 0.25V VIN = 0.25V
1 VIN = 0.35V 0.1 VIN = 0.35V
VIN = 0.45V VIN = 0.45V
0 0.0
100p 1n 10n 100n 1µ 100p 1n 10n 100n 1µ
Harvester
• Result for VIN = 0.25V, 0.35V, and 0.45V
– Conversion ratio controlled to keep VOUT flat
– Idle power consumption: <3nW
0.5
5
Output Voltage (V)
0.4
4
3 0.3
5nW-5μW Output power
2 0.2
VIN = 0.25V VIN = 0.25V
1 VIN = 0.35V 0.1 VIN = 0.35V
VIN = 0.45V VIN = 0.45V
0 0.0
100p 1n 10n 100n 1µ 100p 1n 10n 100n 1µ
Harvester with Solar Cell
• 0.86mm2 harvester with Illuminance (Lux)
100 1k 10k 100k
0.84mm CMOS solar cell
2
V = 4V OUT
1.0
• Operates properly
under room light to 0.8
Room light Daylight
daylight condition
Efficiency
0.6 >35% Overall Measurement from actual light
from 7nW
• Conversion ratio 0.4
modulation can bring 0.2

Solar cell efficiency 1
2
Harvester efficiency
VIN near optimum level Overall efficiency
>30% Overall
from 4.5nW
3
0.0
• Able to cold start from 10n 100n 1µ 10µ
Solar cell short circuit current (A)
100µ
dim light of <200lux 1. Solar cell efficiency

= Harvester input / Max. Solar cell power
(~6nW from solar cell) 2. Harvester efficiency
= Harvester output / Harvester input
3. Overall efficiency
= Harvester output / Max. Solar cell power
Comparison of Harvester
ISSCC 2012 [2] ASP-DAC 2012 [4] ISSCC 2009 [8] This work (Harvester)
Technology 0.13μm CMOS 65nm CMOS 0.35μm CMOS 0.18μm CMOS
Transformer Integrated Integrated Cascade of
Architecture
self-startup charge pump charge pump voltage doublers
Fully integrated No (transformer) Yes Yes Yes
Self-startup Yes (min. 40mV) Yes (min. 120mV) N/R Yes (min. 140mV)
Input voltage 40mV-300mV 0.12V-0.16V 0.6V-4V 0.14V-0.5V
2.2V-5.2V
Output voltage 2V 1V, 1.8V, 3V N/R
(0.35V VIN, 10nA ILOAD)
Peak efficiency 61% @ 0.3V VIN 38.8% @ 0.12V VIN 70% @ 2V VIN 50% @ 0.45V VIN
Output power 1μW-10μW 1μW-1mW 5nW-5μW

N/R
range w/ η > 15% 1 (Efficiency N/R) w/ η > 40%
Idle power 2μW @ 100μW input

N/R N/R <3nW
consumption 7μW @ 1mW input
Minimum 6nW for self-startup
N/R N/R N/R
input power 1.7nW while harvesting
Area 0.093mm2 0.78mm2 59mm2 0.86mm2
N/R: Not reported

Architecture
2.2V-5.2V

N/R

N/R N/R <3nW
N/R N/R N/R
Area 0.093mm2 0.78mm2 59mm2 0.86mm2
N/R: Not reported

Architecture
2.2V-5.2V

N/R

N/R N/R <3nW
N/R N/R N/R
Area 0.093mm2 0.78mm2 59mm2 0.86mm2
N/R: Not reported

Architecture
2.2V-5.2V

N/R

N/R N/R <3nW
N/R N/R N/R
Area 0.093mm2 0.78mm2 59mm2 0.86mm2
N/R: Not reported

Architecture
2.2V-5.2V

N/R

N/R N/R <3nW
N/R N/R N/R
Area 0.093mm2 0.78mm2 59mm2 0.86mm2
N/R: Not reported

Architecture
2.2V-5.2V

N/R

N/R N/R <3nW
N/R N/R N/R
Area 0.093mm2 0.78mm2 59mm2 0.86mm2
N/R: Not reported

Conclusions
• Self-oscillating voltage doubler is proposed
– Reduced overhead for clock generation and level shifting
– Small output ripple by multi-phased operation
– Frequency is automatically modulated to maximize
efficiency
– Test chip shows >105 load range and 170pW idle power
consumption
• Low power energy harvester is implemented

– Cascading self-oscillating voltage doublers
– Conversion ratio is modulated by changing bottom voltages
– Capable of self-startup from 6nW input power
ISSCC 2014 / SESSION 23 /
ENERGY HARVESTING / 23.4
Dual-Source Single-Inductor
0.18µm CMOS Charger-Supply
with Nested Hysteretic
and Adaptive On-Time PWM Control
Suhwan Kim and Gabriel A. Rincón-Mora

Georgia Tech Analog, Power, and Energy IC Research
Georgia Institute of Technology, Atlanta, GA
© 2014 IEEE 23.4: Dual-Source Single-Inductor 0.18µm CMOS Charger-Supply

International Solid-State Circuits Conference with Nested Hysteretic and Adaptive On-Time PWM Control 1 of 33
Outline
 Motivation / Challenges
 Hybrid Energy Sources / Power Conditioners
 Proposed Charger-Supply IC
 Load-dependent Control
 Light Mode: Hysteretic, Duty-cycled Operation
 Heavy Mode: PWM Operation
 IC Prototype Results
 Voltage Regulation
 Efficiency, Reduction in of Required Sources
 Conclusions
Motivation
Wireless sensors’ wide application areas …
Data Browsing/
Processing
Enemy Zone Sensor Base Station

Home Zone
Enemy Vehicle
Environment
Sensor Monitoring
Command
Center
Military Sink node
Reconnaissance
 $14.6B by 2019 Reportlinker
Smart Grids
“Wireless sensors can make
Human Access to Important Information
Much Easier, Safer, and Cheaper.”
Challenges
(1) Operational Life
Integration Bottleneck..
= Energy
(2) Functionality
= Power
Sensor’s Load Profile
(3) In Limited Space :
Major Challenge:
Operational Life + Various Functionalities in Limited Space
Selection of Energy Sources
Ragone plot:
Energy and Power capabilities of energy sources
1000
200
10 200
Major Challenge:
Hard to find an Ideal Single Source
with ↑ Energy and ↑ Power Densities
Hybrid Energy Sources
To Achieve Optimum Volume for given Load’s Targets:
Solutions Capability for unit volume Required volume
Sensor load’s Target
 Energy-dense Oversize x 4
Source only E for Power
 Power-dense Oversize x 4
Source only for Energy
 Energy-dense  No
Source + Power- Oversizing
dense Source Required
Hybrid Energy Sources …

Can meet Power and Lifetime demands with smaller volume.
Power Conditioners for Hybrid Sources
Linear Regulator Switched Capacitor  Switched Inductor
 ↑η for specific  Flexible voltage in

 VOUT < VIN VOUT from topology MIMO Converters
 ↑ Conduction
 Requires many  Single ↑Q inductor
losses  ↓η
switches in MIMO  Compact and ↑η
Inductor-based Switching Converters :
↑η Voltage Conversion for wide voltage ranges
© 2014 IEEE
 Suitable for MIMO Converters
23.4: Dual-Source Single-Inductor 0.18µm CMOS Charger-Supply
Power Conditioners for Hybrid Sources
Control Intelligence Needed:
Let Energy-dense Source to Supply Light Load
Let Power-dense Source to Supply High, Peak Load
Power Source
Energy Source
High Peak-to-Average Load
Load-dependent Source-Selecting Control :

Can AVOID Oversizing Energy Source for Power Demand,
Power Source for Lifetime Demand.
Proposed PWM-Hysteretic Charger-supply
 Dual Input
 vED : Energy-
dense Source
 vPD : Power-
dense Source
 Dual Output
 vO : Load
 vPD : When
recharged
 Single Inductor

Energy Flow: (1) When pO < PED  Light Mode
 Draw Const. PED

from vED
 Supply Load
 Recharge vPD
(if remnant PED)
 Hysteretic CPLT :
 Regulate vO in
Light Mode

Energy Flow: (2) When pO > PED  Heavy Mode
 To supply pO:
 Const. PED
from vED
 Var. Power
from vPD (PWM)
 PWM regulates vO
in Heavy Mode

Mode Control:
 Hysteretic CPM
senses vO
(∆VHYST > CPLT)
 LightHeavy :
vO ↓ < VTH.L
 HeavyLight :
vO ↑ > VTH.H
 ↓ Complexity
than Sensing iO

Light Mode: (1) Energize from vED
Sequence 1: Energize from VED
 Starts from the rising edge of fCLK (40kHz)

 Energize for the fixed τEN to draw PED
 PED from the optimum/max power of the energy source
Light Mode : (2) Supply vO / Recharge vPD
Sequence 2: De-Energize to vO or vPD
 At the end of τEN: Check vO’s level (Hysteretic CPLT )

 If vLT ↓: Turn on SO to supply vO
 If vLT ↑: Turn on SPCHG to recharge vPD
 De-energize until iL = zero (detected by CPIOZ or CPIPZ)
Output Comparator CPLT
τD
 ∆VHYST by Latched TRs

 Duty-cycled to Save Power
 ON at the end of τEN
 vEN shifted by τD to
cover the moment
Decision Point
23.4: Dual-Source Single-Inductor 0.18µm CMOS Charger-Supply
© 2014 IEEE
Zero-iL-detect Comparator CPIOZ

 ON during SO is on
 CPIOZ turns off when it
detects zero iL
 Output deglitched when
Enable.
Zero-iL-detect Comparator CPIPZ
 Common-gate Input Pairs

 Intentional Offset to detect
faster
 ON during SPCHG is on
 CPIPZ turns off when it
© 2014 IEEE detects zero iL. 23.4: Dual-Source Single-Inductor 0.18µm CMOS Charger-Supply
with Nested Hysteretic and Adaptive On-Time PWM Control 17 of 33
International Solid-State Circuits Conference
Heavy Mode: (1) Energize from vED
Sequence 1: Energize from VED
 Heavy Mode : PO > Energy sources’ power PED

 Same sequence as Light Mode :
 Starts from ↑ edge of fCLK (40kHz)
 Energize for the fixed τEN to draw PED
Heavy Mode: (2) Supply vO
Sequence 2: De-Energize into vO
 De-energize to vO only:
 Because Load is heavy, no recharge power for vPD
 After VED’s cycle, vO is still ↓
 The power source VPD is needed!
Heavy Mode: (3) Energize from vPD
Sequence 3: Energize from VPD
 To supply ↑ power to vO with vPD’s power

 Controlled by PWM  ↕ Power
 Start energizing from vPD after VED’s energy cycle
 End when CPHV’s output VHV ↑
Heavy Mode (4) Supply vO
Sequence 4: De-Energize into vO
 Turn on SDE to discharge LO into vO

 All switches kept OFF until the next fCLK ↑
Pulse Width Modulation in Heavy Mode
PWM Operation for VPD’s ↕ Power
 Comparator CPHV  vG VS vSAW

 vSAW starts after vED’s energy cycle
 Compensated vG from Error amplifier GHV
 When vHV ↑  Turns off SPE, resets vSAW
Transconductance PWM Amplifier GHV
 Folded-cascode structure, Gm= 2.5 µS

 Overall loop gain AOL│0 ≈ 43 dB
 Compensation:
 System’s Dominant Pole at vG
 Insert a zero to cancel the second pole at vO
 PM ≈ 90 degrees, stable.
Die Photo and PCB Prototype
0.18-µm BiCMOS
Power Source :
8x8x12-mm3 1-F
super capacitor
PCB
840x840 µm2
1 µF
CO
Die Photo
50 µH
Inductor
*Zinc-air Cell: Hearing-Aids
 Fuel Cell-like Battery Energy Source :
 Use Air as fuel 11x11x5-mm3, 600-mAh
 As a test vehicle *Zinc-air Cell
Regulation Performance in Light Mode
100 µA 200 µA 200 µA 100 µA
To vO
± 2.5mV
To vPD To vPD
 Regulation within Light Mode

 < 0.2% DC variations @ iO = 100 µA ↔ 200 µA
Regulation Performance in Heavy Mode
4 mA 8 mA 8 mA 4 mA
± 25mV
From vPD
 Regulation within Heavy Mode

 < 2.5% DC variations @ iO = 4 mA ↔ 8 mA
 ∆vO = ±25 mV  Due to ↑ energy packet from vPD
Mode Transitions
100 µA 8 mA 8 mA 100 µA
~200µs
+5mV
-25mV ~210µs
 Seamless Mode Transitions @ iO = 0.1 ↔ 8 mA

 Indirect iO sensing from vO (Hysteretic CPM)
tHL, tLH = f(CO, iO)  Slow, but ↓ complexity
Efficiency Performance
100
Simulation
90 Measurement
Efficiency [%]
80
70
60
50
0.1 0.5 2.0 8.0
 Measured Efficiency … IO [mA]
 Peaked at 83% @ iO = 4 mA
 ↓ η @ iO = 1 mA , due to ↑ Gate-drive losses
 Simulation VS Measurement :
↓ IBIAS  ↑τEN  ↑ iL(PK)  ↑ Conduction losses
Load-dependent Source-selection Control
Power
Source
Without Load-Dependent
Source-Selection control,
 VED Oversized for PO.PEAK,
Or
Energy  VPD Oversized for t1-MONTH
Load
Source
With Load-Dependent
Source-Selection control,
 VED for t1-MONTH
 VPD for PO.PEAK
Energy Load  Optimum Use of Sources!

Source
Example Load Profile
To estimate the required Sources’ Volume / Weight
Functions Power Duty

Sense / Actuate 1200 µW 1%
Process 1000 µW 1%
Transmit / Receive 4000 µW 1%
Idle 10 µW 97 %
Average 72 µW 100%
*Halgamuge, Progress in Electromagnetics Research B 2009
Calculation of Required Sources
DMFC for pO.AVE, 1-MONTH This image cannot currently be display ed.
(Total Energy)
WFC =
(Energy Density)FC
PO(AVG)t1−MONTH
=
ηC(AVG)EDFC
Li Ion for pO.PEAK

(Peak Power)
WLI =
(Power Density)LI
PO(PEAK)
=
ηC(PEAK)PDLI
WTOT = WFC + WLI << WFC.ONLY or WLI.ONLY

Performance Comparison Table
Huang, Qiu, Chew, Kim,
This work
JSSC 09 ISSCC 11 ISSCC 13 AICSP 12
η0.1mW 80% 83% 83% 4% 70%
/ ηPEAK / 93% / 87% / 83% / 32% / 83%
*LD/SS
x x x o o
Control
Sources
430-mg 460-mg 482-mg 1.3-g
required
DMFC DMFC DMFC DMFC 74.5-mg DMFC
to supply
Or Or Or + 63-mg + 24-mg Li Ion
the load
326-mg 314-mg 314-mg Li Ion = = 98.6 mg
Li Ion Li Ion Li Ion 1363 mg < 32% of SoAs
* Load-dependent Source-Selecting Control

Conclusions
 This IC Selectively draws power from hybrid sources
 pO.AVE from Energy-dense source
 pO.PEAK from Power-dense source
 To optimize sources’ volume for ↑ pO.PEAK / pO.AVE
 Peak η of 83% in 0.1-8mA’s iO

 Reduction in sources’ weight:
< 32% for a ↑ pO.PEAK / pO.AVE sensor load

ISSCC 2014
Session 23.5
An Energy Pile-up Resonance Circuit

Extracting Maximum 422% Energy from
Piezoelectric Material in a Dual-Source
Energy-Harvesting Interface
Young-Sub Yuk, Seungchul Jung, Hui-Dong Gwon, Sukhwan Choi, Si

Duk Sung, Tae-Hwang Kong, Sung-Wan Hong, Jun-Han Choi, Min-Yong
Jeong, Jong-Pil Im, Seung-Tak Ryu, Gyu-Hyeong Cho
KAIST, Republic of Korea
EECS, KAIST
Circuit Design & System Application Laboratory
Contents
 Introduction about the Piezoelectric Transducer (PZT)

 The Previous works for Energy Extraction from PZT
 A Proposed Energy Pile-up Resonance Circuit
 Chip Implementation
 Measurement Results
 Conclusion
© 2014 IEEE 23.5: An Energy Pile-up Resonance Circuit Extracting Maximum 422% Energy from
International Solid-State Circuits Conference Piezoelectric Material in a Dual-Source Energy-Harvesting Interface 2 of 50
Contents

 A Proposed Energy Pile-up Resonance Technique
 Conclusion
Electrical Modeling of the PZT
PZT cantilever
Mechanical domain Electrical domain
RM LM CM 1:X
vPZT Cz +
Mechanical
vibration Vz
-
Mechanical to electrical model Mechanical resonance
Ideal Resonance Technique for PZT
1
L ext =
(2πfr ) 2
⋅ Cz
 The Cz is 220 nF and mechanical resonance fr is 100 Hz

 The required external inductor is 11.5 H
 Too much large inductor is required!
Contents

 Conclusion
Previous work [1]
An Efficient Piezoelectric Energy Harvesting Interface Circuit

Using A Bias Flip Rectifier and Shared Inductor, ISSCC 2009
280%
100%
[FBR] [Type 1]
Previous work [2]
A Single-Inductor AC-DC Piezoelectric Energy-Harvester/

Battery-Charger IC Converting 0.35 to 1.2V, ISSCC 2010
180%
FBR: Full Bridge Rectifier

[Type 2]
Previous work [3]
A Single-Inductor 0.35um CMOS Energy-Investing
Piezoelectric Harvester, ISSCC 2013
247%
[Type 3]
Contents

 Conclusion
A Proposed Energy Pile-up Resonance Technique
CMOS Process Breakdown

PZT Material
iPZT Vz at Proposed
Resonance
Rz
iPZT (t)
Cz
Vz
- Vz + Time
M1
Inductor
2tR1 tL2
M3
tR2
iL
CLoad
How can the Energy Piles-up in the Capacitor ?
PZT Material
iPZT
Rz
iPZT (t)
Cz
Vz
- Vz + Time
Vzo
M1
Inductor
M3
iL
CLoad
PZT Material
iPZT
Rz
iPZT (t)
Cz
Vz
- Vz + Time
Vzo
M1
Inductor
M3
iL
CLoad
PZT Material
iPZT
Rz
iPZT (t)
Cz
Vz
- Vz + Time
Vzo
M1
Inductor
M3
iL
CLoad
PZT Material
iPZT
Rz
iPZT (t)
Cz
Vz
- Vz + Time
Vzo
M1
Inductor
M3
iL
CLoad
PZT Material
iPZT
Rz
iPZT (t)
Cz
Vz
- Vz + Time
Vzo
M1
Inductor
M3
iL
CLoad
CMOS Breakdwon Voltage
PZT Material
iPZT
Rz
iPZT (t)
Cz
Vz
- Vz + Time
Vzo
M1
Inductor
M3
iL
CLoad
How can the Energy be transferred to the Load ?
PZT Material
iPZT
Rz
iPZT (t)
Cz
Vz
- Vz + Time
Vzo
M1
Inductor
M3
iL
CLoad
PZT Material
iPZT
Rz
iPZT (t)
Cz
Vz
- Vz + Time
Vzo
M1
Inductor
M3
iL
CLoad
VLimit
PZT Material
iPZT
Rz
iPZT (t)
Cz
Vz
- Vz + Time
Vzo
M1
Inductor
M3
tR2
iL
CLoad
VLimit
PZT Material
iPZT
Rz
iPZT (t)
Cz
Vz
- Vz + Time
Vzo
M1
Inductor
tL2
M3
tR2
iL
CLoad
VLimit
PZT Material
iPZT
Rz
iPZT (t)
Cz
Vz
- Vz + Time
Vzo
M1
Inductor
tL2
M3
tR2
iL
CLoad
VLimit
PZT Material
iPZT
Rz
iPZT (t)
Cz
Vz
- Vz + Time
Vzo
M1
Inductor
tL2
M3
tR2
iL
CLoad
VLimit
PZT Material
iPZT
Rz
iPZT (t)
Cz
Vz
- Vz + Time
Vzo
M1
Inductor
tL2
M3
tR2
iL
CLoad
VLimit
PZT Material
iPZT
Rz
iPZT (t)
Cz
Vz
- Vz + Time
Vzo
M1
Inductor
tL2
M3
tR2
iL
CLoad
A Proposed Energy Pile-up Resonance Technique
Limited by CMOS Process Breakdown
1 2 1 2 VLimit
E L = ⋅ C z ⋅ Vmax - - ⋅ C z ⋅ VLimit
2 2 Vz at Proposed
Resonance
Vz at Conventional
Resonance
iPZT (t) Vzo: Vz at no Resonance iPZT (t)
Vz Time
Time
ETM
EPM
EPM: Energy Pile-up Mode
ETM: Energy Transferring Mode
Vmax-
tR1 2tR1 tL2
tL1
tR2
iL
© 2014 IEEE
[Type 2] [Proposed]
23.5: An Energy Pile-up Resonance Circuit Extracting Maximum 422% Energy from
Contents

 Conclusion
0.35um BCDMOS Energy Pile-up Resonance Circuit for PZT
PZT Material PZT Resonance Controller
Vplimit+
iPZT Vzs Peak Value M
Vplimit- Checker
Rz
Rz: 4MΩ
Cz: 220nF Cz- Vz + Sampling
Attenuator
Φp
&Peak
Detector Φn Vzs Resonance
Interceptor
Vlimit
(VLimit)
Full Inversion RI M:0 EPM
Detector
M1 * M1 Gate Driver M:1 ETM
Body_Switc
II RS
Q S
h
RI INT
INT
Q R
Inductor
Body_Switc
TEG RS FB
h
iL M3
VLoad III
RTEG I RS
Body_Switc
TEG FB
M3
h
controller
VTEG CIN Gate
M2 Driver
CP
+
-
PZT Resonance Controller
Vplimit+
Vz Vzs Peak Value M
Vplimit- Checker
Sampling Φp
Attenuator
&Peak
Interceptor
Vlimit
(VLimit)
Detector * M1 Gate Driver M:1 ETM
M1 RS
Q S
RI INT
INT
Q R
Vplimit+
Vz Vzs Peak Value M
Vplimit- Checker
Sampling Φp
Attenuator
&Peak
Interceptor
Vlimit
(VLimit)
M1 RS
Q S
RI INT
INT
Q R
Sampling Attenuator & Peak Detector
 Sensing the Vz and make a Vzs for resonance control

 DC voltage of the Vzs can be defined by C3 and C4 (C41+C42)
Sampling Attenuator & Peak Detector

Switch-Cap Resistor
Vp ΦY Φ0 Vp
Φ2 Φ1 Cp C43
+
-
CP
Φp
P.G
Sampling VDD Vzs
Attenuator Φ1 Φ0 P.G:
Vz
C1 Vzs Φ2 C3 Pulse
Generator
C2 Φ1 C41 Φ0 Vn
P.G
Φn
Φp Φn
CP Φ2 Φ1 Cn C42
+
-
Switch-Cap Resistor Vn Φx Timing of Φp, Φn and Waveform of the Vzs, Vp, Vn

VDD is same with VLoad
Vplimit+
Vz Vzs Peak Value M
Vplimit- Checker
Sampling Φp
Attenuator
&Peak
Interceptor
Vlimit
(VLimit)
M1 RS
Q S
RI INT
INT
Q R
Vplimit+
Vz Vzs Peak Value M
Vplimit- Checker
Sampling Φp
Attenuator
&Peak
Interceptor
Vlimit
(VLimit)
M1 RS
Q S
RI INT
INT
Q R
Full Inversion Detector and Resonance Interceptor
PZT Material
iPZT Mi off
Vz VLimit
Rz
-V + Vci
Cz z
Full Inversion Detector
- Vci +
Ci Mi on
Ri2 Ri1
Mi M1
EPM ETM
+
-
CP
MUX INT iL
P.G RI
INT
RI
© 2014 IEEE
iL 23.5: An Energy Pile-up Resonance Circuit Extracting Maximum 422% Energy from
34 of 50
International Solid-State Circuits Conference Piezoelectric Material in a Dual-Source Energy-Harvesting Interface
Vplimit+
Vz Vzs Peak Value M
Vplimit- Checker
Sampling Φp
Attenuator
&Peak
Interceptor
Vlimit
(VLimit)
M1 RS
Q S
RI INT
INT
Q R
Mi off
Resonance Vz VLimit VLimit
Interceptor
Vzs Vlimit Vci
(VLimit) Vci
+
Mi on
RI P.G
Energy to the
EPM load
ETM
M MUX
iL iL
Roff tL2
RI
Roff
PZT Material
iPZT Resonance
Vzs Interceptor
Rz Vlimit
Vzs
Sampling
Cz Vz Attenuato
Φp (VLimit)
-
Full Inversion Detector
r &Peak
Detector Φn
- Vci + RI
P.G
Ci
Ri2 Ri1 M1
Mi RS Q S M MUX
INT Q
+
-
CP R
INT
MUX Vzs : Attenuated signal of Vz
RI
P.G P.G : Pulse Generator
TEG VIN
RS FB
RTEG CIN M3 VLoad

iL RS
Body_Switch
TEG FB
controller
VTEG M2
CP
+
-
Vplimit+
Vz Vzs Peak Value M
Vplimit- Checker
Sampling Φp
Attenuator
&Peak
Interceptor
Vlimit
(VLimit)
M1 RS
Q S
RI INT
INT
Q R
Gate Driver for M1 switch
VB (supply voltage for M1 Gate Driver)

Vz M1 Gate Driver
M.O.S
Body_Switch
H.M.O.S
Cz MMO1
Gate
Level RS
Driver
MG1 MMO2 Shifter
Body_Switch
L.M.O.S
M1
Body_Switch
OUT Gate IN
+
Selector CP
Driver -
MG2
Vz
inductor VD
H.M.O.S: High Side Main Off Switch
L.M.O.S: Low Side Main Off Switch
Core Gate Driver in M1 Gate Driver
Core Gate Driver for preventing the short circuit
VB VB
IN
MP4 MP2 IN
MP1
CMN
MP3 V1 DELAY1
OUT Body_Switch
V1 DELAY1
V2 DELAY2
DELAY2
Body_Switch
V2 MN2
Body_Switch
OUT
MN4 MN1
-VB
Timing diagram of IN, V1, V2 and OUT
MN3
Contents

 Conclusion
Boosting Vz by the Proposed Technique
Waveforms of the Energy Transferring Mode
Full Inversion of the Vz at EPM and ETM
Load Charging with Energy Pile-up Resonance Technique
Performance Analysis
EL =
1
2
{
⋅ C z ⋅ ( Vmax - + VIN ) 2 - (VLimit - VIN ) 2 }
 Theoretical output energy VS Real measured output energy

 Theoretical energy: 1.1913 uJ Measured energy: 0.98 uJ
 Real extracted energy is 82.2% of the expected energy
OPIR according to the amplitude of Vz
450%
400%
PZT Output Power Increasing Rate
350%
300%
250%
200%
150%
100%
50%
0%
1.3 2.6 4.0 5.0 6.0 7.0 7.6
FBR: Full Bridge Rectifier Vz (Vpp)

23.5: An Energy Pile-up Resonance Circuit Extracting Maximum 422% Energy from
© 2014 IEEE
Performance Summary
Conclusion
 Vz is boosted until 7 Vpp using original swing 1.3 Vpp.

 With the Vz of 7 Vpp, the EHI charges the load from 2V to
4V.
 When the Vz is 7 Vpp, the 422% energy is extracted
compared to the conventional technique (full bridge).
 Real extracted energy is 82.2% of the expected energy
extraction and the amount of extracted energy is maximum
1 uJ
Thank you
Thank You
A 43V 400mW-to-21W Global-Search-
Based Photovoltaic Energy Harvester
with 350μs Transient Time, 99.9% MPPT
Efficiency, and 94% Power Efficiency
Sandip Uprety, Hoi Lee
Integrated Power Laboratory

The University of Texas at Dallas, USA
© 2014 IEEE 23.6: A 43V 400mW-to-21W Global-Search-Based Photovoltaic Energy Harvester with 350μs Transient Time,
International Solid-State Circuits Conference 99.9% MPPT Efficiency, and 94% Power Efficiency 1 of 48
Outline
 Background and Motivation
 Proposed Energy Harvester Architecture and
Algorithm
 Irradiance Aware Adaptive Frequency Power
Controller (IAAFPC) and Gate Driver
 Pulse-Integration Based Maximum Power
Point Tracker (PI-MPPT)
 Conclusion
Solar Energy Harvesting
 Photovoltaic cells have the highest energy density.

 Many standalone systems can be solar-powered.
Solar Panel Characteristics
SP I-V Characteristic Curve
0.4
0.3
IPV(A)
0.2
0.1
Lumped electrical model of a PV cell 0.0

0 20 40
VPV (V)
SP P-V Characteristic Curve

12
Peak Power
10
8
Power (W) 6
4
2 VMPP
0
0 20 40
VPV (V)
PV modules forming a Solar Panel Maximum Power Point Tracking (MPPT)
Variation of SP Output during the Day
 High MPPT efficiency and high power efficiency across wide

input-power range are indispensable.
Source: www.vernier.com/innovate/the-effect-of-sky-conditions-on-solar-panel-power-output/
Effect of Partial Shading on PV Modules
PV PV
Module Module
PV PV
Module Module
PV PV
Module Module
Partially
Shaded
 For a large size SP, Partial Shading Conditions (PSC) can occur due
to birds, trees, buildings and other objects.
 Multiple local maxima are present during PSC.
Design Challenges due to PSC
Multiple Local Maxima during PSC
8
6.68 W
7
6
4.68 W
Power (W)
Measured SP 5
characteristic 4
curve during PSC 3
2
>30% Power Savings if Global
1
MPP is tracked
0
2 strings in parallel 0 10 20 30 40
2/8 modules of one string Solar
SolarPanel TerminalVoltage
Panel Terminal Voltage(V)(V)
shaded for PSC test
 P&O and hill-climbing algorithms get stuck at the lower local

maximum.
 The state-of-the-art integrated EHs cannot perform Global
MPPT (GMPPT).
Outline
 Proposed Energy Harvester Architecture
and Algorithm
 Conclusion
Proposed Energy Harvester Architecture
Global Search Algorithm (GSA)
 GSA provides extended search window.

 GSA enables instantaneous power computation in GMPPT mode.
 Ripple-based IAAFPC, low CIN and high-operation-frequency EH
allows VPV to ramp down quickly.
Global Search Algorithm (1)
 After startup and in

periodic normal
operation, system
enters GMPPT mode.
 A closed-loop feedback
controls VPV using VREF.
 Instantaneous SP
output power is
calculated using VPV
and IPV information.
 After the GMPPT mode,

VREF = VMPP.
 The power stage settles

and transitions to the
steady-state operation.
 The EH extracts power

from the SP at its GMPP.
 The duration of steady-

state is programmable.
 After the steady-state
timer expires, MPPT is
triggered.
 VPV is charged to VOC

during Buck Converter
Disabled (BCD) mode.
 EH then goes to
GMPPT mode unless
SP UVLO or VBATT over-
voltage protection is
triggered.
VREF Generation during BCD Mode
 In Buck Converter
Disabled (BCD) mode:
ØBCD = 1 and ØMPPT = 0.
R F2
 V RAMP = V PV
R F1 + R F 2
 ØSS = 0, and VREF = VRAMP.
 VREF is updated to Solar

Panel’s open cell voltage.
VREF Generation during GMPPT mode
 In GMPPT mode:
ØSS = 0, and VREF = VRAMP.
 ØBCD = 0 and ØMPPT = 1.
 CRAMP is discharged by a
constant current source.
 PI-MPPT calculates
instantaneous Solar
Panel output power.
VREF during Steady-State Operation
 In steady state:
ØSS = 1, and VREF = VMPP.
 ØBCD = 0 and ØMPPT = 0.
 IAAFPC uses VREF to

operate Solar Panel its
global peak power.
Outline
Algorithm
 Irradiance Aware Adaptive Frequency
Power Controller (IAAFPC) and Gate Driver
 Conclusion
Irradiance Aware Adaptive Frequency Power Controller Operation
IAAFPC Operation: High Irradiance
 EH operates in CCM with constant on-time of switch MP1.

 m1VPV is compared with VREF to determine tOFF of buck converter:
 VPV ηP 
t OFF =  − 1 TON ≈ constant.
 VBATT 
IAAFPC Operation: Low Irradiance
 (VPV - VBATT ) TON  1

 Constant on-time and t OFF =  − 1 TON ∝
 2 L IPV  IPV
Adaptive Frequency in DCM
2 L IPV
fsw = ∝ IPV
(VPV − VBATT ) TON
 Reduced fSW helps to maintain high power efficiency even
when Solar Panel output power is much lower.
High Voltage Gate Driver and Level Shifter
 VGS for MP1 has to be <5V to prevent device breakdown.

 Gate-drive logic for MP1 is shifted up to a high DC voltage.
 Level-shifter requires low-static current and low transition time.
High Voltage Capacitively Coupled Level Shifter
*
 HVCCLS exhibits zero static current and sub-ns level-shifting.
* Zhidong Liu and Hoi Lee, "A 100V gate driver with sub-nanosecond-delay capacitive-coupled level shifting and dynamic timing
control for ZVS-based synchronous power converters," Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, USA, Sept. 2013.
HV Gate Driver and Current Sensor
VPV
M1 M2 M3 M4
M11 M24
M12 M13
VX
M10 Mps Mx
MP1
M23
VG_MP1 999 : 1
VGp
M9
VDDL
M14 M15 VDDL
R1 VX IMP1
C1 VDDL IMP1 999 M22
C2
Inv M5 M6 M16 M17 M21

Vsensep
VDDL EN
VLS_MP1 R2 C3
M7 M8
MP1 Control Driver M18 M19 M20
D1
High Voltage PMOS Driver with Capacitively High-voltage High-side PMOS Current Sensor
Coupled Level Shifter for Peak Current Limiting
 HVCCLS also provides switching signals to operate high-voltage

current-sensor for peak-current-limiting of MP1.
Outline
Algorithm
 Conclusion
Pulse Integration based MPPT (PI-MPPT)
 500 kS/s MPPT clock

A P ∝ m 1 VPV = c 1 m 1 VPV
 135 instantaneous power samples
computed in a 270µs GMPPT time t P ∝ m 2 R IPV = c 2 m 2 R IPV
Power Comparison and Update

MPP Update
Global Maximum
Power Point
Outline
Algorithm
 Conclusion
Chip Micrograph
 Implemented in 0.35µm 50V CMOS with a total chip area of 8.1mm2

 Power Transistors: MP1, MN1 and MN2
 Irradiance Aware Adaptive Frequency Power Controller (IAAFPC)
 Global Search Algorithm (GSA)
 Pulse-Integration based MPPT (PI-MPPT)
Measurement Setup
Test PCB Outdoor Measurement Setup for PSC

Startup during Partial Shading Condition
 EH tracks Global Maximum voltage VMPP in 270µs and sets VREF = VMPP.
Normal Operation during PSC
 Total transient time (GMPPT + settling) of 350µs with VPV = 23V.

High Input Power Un-shaded Condition
 PI-MPPT tracks single local maximum voltage VMPP.

Low Input Power Un-shaded Condition
 Proposed EH in DCM achieves 510µs total transient time.

Low Input Power Un-shaded Condition
 Proposed EH operates with reduced fSW of 625kHz in DCM with

zero current detector.
Power and MPPT Efficiency Measurements
 VOUT is a 15V Li-Po battery.

 VIN is 40V with (ISC, RS) ranging from (20mA, 500Ω) to (800mA, 12Ω).
Comparisons with State-of-the-Art Designs
[5] [4] [3] [2]
ISSCC 13 LT3652 ISSCC 12 ISSCC 13 This work
0.35µm HV 0.35µm HV
Process TSMC 0.35µm N.A. 0.5µm CMOS
CMOS CMOS
Harvester Power Throughput 36 (off-chip
~0.04 – 0.5 7 – 28.8 0.55 – 2.6 0.4 – 21.1
(W) power stage)
VIN (V) 0.5 – 2 5 – 32 3.4 – 5.5 4 7 – 43
89% 88% 94% 94.2%
Peak Power Efficiency (ηP) N.A.
(fSW = 500kHz) (fSW = 1MHz) (fSW = 100kHz) (fSW = 1MHz)
POUT Range (W) for ηP > 85% ~0.12 – 0.34 N.A. N.A. 0.55 – 2.2 0.988 – 21.1
Power Density (mW/mm2)
~158 N.A. N.A. 168 1022
@ Peak ηP
Peak Tracking Efficiency N.A.
N.A. > 99% 99.9% 99.9%
(w/o PSC) (fixed VREF)
POUT Range (W) for Tracking N.A. (~2 –
N.A. N.A. 0.55 – 2.6 0.4 – 21.1
Efficiency (ηT) > 95% 37.7 PIN)
Global MPPT in PSC (ηT) No No No No Yes (99%)
~1.6ms (470µs
Transient Time 350µs (under
for 50% PMAX
(Total Time for MPPT and N.A. N.A. N.A. multiple local
settling in one
Settling to reach PMAX) maxima)
local maxima)
Conclusion
 A 43V 21W Solar Energy Harvester with a Global
Search Algorithm is presented.
 GSA implemented with PI-MPPT can track GMPP in

presence of multiple local maxima. 99% GMPPT
efficiency and total transient time of 350µs are reported.
 IAAFPC enables the EH to have >80% power efficiency

across entire 400mW - 21W power throughput. Peak
power efficiency of 94% is achieved at fSW of 1 MHz.
 1022 mW/mm2 power density of this EH improves state-

of-the-art EHs’ performance by 6×.
Self-Powered 30μW to 10mW Piezoelectric
Energy Harvesting System with 9.09ms/V
Maximum Power Point Tracking Time
Minseob Shim, Jungmoon Kim, Junwon Jung,

and Chulwoo Kim
Korea University, Korea
© 2014 IEEE 23.7: Self-Powered 30μW to 10mW Piezoelectric Energy Harvesting System
International Solid-State Circuits Conference with 9.09ms/V Maximum Power Point Tracking Time 1 of 24
Introduction
Electrical
P P P Energy
Piezoelectric
Energy Source Harvester
• Generate electrical power from kinetic energy

• Improve battery lifetime or batteryless
Motivation (1)
• Maximum power point (MPP)
PE Transducer PE RECT
P P P
O
VRECT = ½ VOC
(@MPP)
RECT
• The MPP is sensitive to changes of the environment
• Frequency
• Amplitude
Motivation (2)
• Conventional MPP tracking (MPPT) methods
• Perturb & Observe
(Hill-climbing)
– Sensing V & I
• Fractional VOC
– Sensing V
• Tens to hundreds of cycles for tracking
One-cycle MPP Sensing
• Use small size sensing capacitor

• Short MPPT time
• Extracts more power from transducer
Top Block Diagram
PH1 PH4
PE Transducer VBIAS
& Rectifier ZCS VIN VX VOUT
VRECT
SW1 CIN
COUT
One-cycle Peak Charge Sharing ½ VOC
Detector Block
SW1 C2 PH2 PH3
ZCS
VBIAS VPK
Buck-Boost Controller
SW1 PH1 PH2 PH3 PH4

Open Circuit Time VOUT
Controller SW1 Reverse Current & BD Remover VX VIN
VS1 VS2 VBD

VIN VDDC
Deadtime
Proposed VOUT
&
½ VOC Ramp Gen.
SW Controller VRAMP
One-cycle Sensing Blocks
PH1 PH4
PE Transducer VBIAS
VRECT
SW1 CIN
COUT
Detector Block
SW1 C2 PH2 PH3
ZCS
VBIAS VPK
SW1 PH1 PH2 PH3 PH4

VS1 VS2 VBD

VIN VDDC
Deadtime
Proposed VOUT
&
½ VOC Ramp Gen.
SW Controller VRAMP
Sensing Cap. Size Selection
RECT OC
1 RECT
t
OC
RECT
RECT
2 3
• Large cap (C1) : small ripple & long tracking time

• Small cap (C2) : large ripple & short tracking time
One-cycle Peak Detector
OC
RECT
P
BIAS PK
• VRECT : input and supply voltages of peak detector

• VBIAS : common mode voltage
Open Circuit Time Controller
• ZCS signal charges COT every cycle

• SW1 opens the rectifier output for one cycle
Charge Sharing Block
2 3
MPP1 MPP2
RECT
2 OC1 OC2 2
RECT RECT
MPP1
½ VOC
MPP2
t t
SW2 SW3
• VMPP2 becomes the half of VOC
PH1 PH4
PE Transducer VBIAS
VRECT
SW1 CIN
COUT
Detector Block
SW1 C2 PH2 PH3
ZCS
VBIAS VPK
SW1 PH1 PH2 PH3 PH4

VDD MUX
VS1 VS2 VBD
VIN VDDC
Deadtime
Proposed VOUT
&
½ VOC Ramp Gen.
SW Controller VRAMP
Ramp Generator (1)
• Deciding frequency and duty of switching signals of

buck-boost converter
• Ramp generator with VDD independence
– Constant frequency and amplitude
– Low power consumption and small area
Ramp Generator (2)
RG Cell
DDC
OUT1 OUT2
IN1 R1 R2 IN2
CR1, R2 : Small or parasitic

capacitors
Reverse Current & BD Remover (1)
IL = 0 before the end of one cycle
Reverse current from VOUT to GND

(VOUT > VX)
Buck-boost is turned off

(VIN < ½ VOC), but IL remains
BD effect with large VDS drop

(VOUT > VX)
• Reverse current and BD effect cause large losses
Reverse Current & BD Remover (2)
Turn off M2 and M4

VOUT > VX to prevent the
reverse current
Keep on M2 and M4
VIN < ½ VOC, VOUT < VX to prevent the body
diode effect
Conventional Voltage MUX
IN
OUT
CO2
CO1
CONT
• Small bias current for low-power VDD MUX

– Comparator delay
– Voltage spikes occur at overlapped regions
* T. Y. Man et al., JSSC, vol. 43, pp. 2306–2346, Sep. 2008.
Proposed Voltage MUX
IN
OUT
CO2
CO1
DDC
• Rising-edge detector and S-R latch

• Selects a front edge of comparator output
– No voltage spike
Chip Photograph
• 0.35μm BCDMOS process
Measurement Results (1)
• Sensing ½ VOC in one cycle

• Fast tracking
• Tracking time : 20ms/(3.4V1.2V) = 9.09ms/V

• When VDDC is changed from 1.2V to 6.5V

– Frequency = 89.5~92.3kHz : changed by 3%
• Vref = 418~419mV
– Constant Duty = 0.5
Comparisons
ISSCC 2013* TPEL 2012** This work
Process 0.25μm BCD Off-chip 0.35μm BCD
Input voltage 5 – 60V 3 – 25V 1 – 7V
Output voltage 2–5V 3V – 1 – 8V
Input power 25μW – 1.6mW N/A 33μW – 10mW
Converter type Buck Buck-Boost Buck-Boost
Max. PCE 88.9% 76% 80%
Variable step-size
MPPT algorithm P&O Fractional VOC
P&O
Max. MPPT
99.9% 97% 99.9%
efficiency
MPPT time 80ms/V 7.83s/V 9.09ms/V
* S. Stanzione et al., ISSCC, pp. 74–75, Feb. 2013.

** N. Kong et al., TPEL, vol. 27, pp. 2298–2308, May 2012.
Conclusions
• One-cycle MPP sensing method is
proposed
• MPPT time : 9x faster
• Low-power control blocks :
– Ramp generator with VDD independence
– Voltage MUX without voltage spikes
• Prevent BD effect & reverse current
A 34V Charge Pump in 65nm
Bulk CMOS Technology
Yousr Ismail1, Haechang Lee2, Sudhakar

Pamarti1 and Chih-Kong Ken Yang1
1University of California, Los Angeles, CA
2Altera, San Jose, CA
High Performance Mixed-Mode Circuits Group

© 2014 IEEE
International Solid-State Circuits Conference 23.8: A 34V Charge Pump in 65nm Bulk CMOS Technology 1 of 20
Outline
• Motivation
• Technology Limitations
• Charge Pump Design
• Measurement Results
• Conclusion
© 2014 IEEE
MEMS Resonator System
This image cannot currently be display ed.
HV DC
DC-DC Bias
Chip Vout
Converter
Supply
(Vdd)
Actuate Sense
idrive
2
inoise   f0 2  Area ⋅ V ⋅ V 2
(∆f) = 2  1+    idriveα drive bias
2 idrive   2Q ⋅ ∆f   (gap) 4
• Cellular and GPS applications demand excellent

phase noise performance
• Power conversion efficiency is critical for portable
applications
© 2014 IEEE
Bulk CMOS Technology Limitations
6 40
Well Breakdown Voltage (V)

0.5um 0.5um
Supply Voltage (V)
5 SOI
30
4
0.35um
0.35um CMOS
0.18um
3 20
0.18um 0.25um 45nm
0.25um 90nm
2 0.13um 22nm
90nm 45nm 22nm 10 65nm 28nm
1 0.13um BCD-like
65nm 28nm
0 0
0.5 0.1 0.02 0.5 0.1 0.02
Technology Node (um) Technology Node (um)
• Transistor voltage ratings shrink as technology

scales down
• Technology maximum voltage handling is limited
to the well diodes breakdown
© 2014 IEEE
Voltage Tolerance in Bulk CMOS
Symbol VBD Description
VNP 8V n+/pwell diode
VNW 12V nwell/psub diode
VDNW 12V dnwell/psub diode
Approximate values for 65nm
Vmax= min(VNW, VDNW) CMOS technology
NMOS PMOS DNWELL NMOS

Vmax=VNP Vmax=VNW Vmax=VDNW
© 2014 IEEE
Extended CMOS Voltage Tolerance (1/2)
VNP 8V n+/pwell diode
VNW 12V nwell/psub diode
VDNW 12V dnwell/psub diode
CMOS technology
Proposed deep-nwell bias
Vmax= VDNW+VNP=20V
• An all-NMOS CP is proposed
• Backgate bias reduces efficiency
© 2014 IEEE
Extended CMOS Voltage Tolerance (2/2)
Vout
Vmid P Li N VNP 8V n+/pwell diode
p poly i n poly VNW 12V nwell/psub diode
p+ STI
n+ p-well n+ VBD VDNW 12V dnwell/psub diode
deep n-well VFOX 88V STI capacitor
p substrate
Polysilicon Diodes CMOS technology
Vmax= VDNW+VFOX=100V Vin Vout
VFOX
• Only diodes can be used φ1
VDNW
Vdd
• Diode drop reduces efficiency
Vmid
© 2014 IEEE
Charge Pump Architecture
ηmax=68% ηmax=42% ηmax=29%
4 stages 5 stages 8 stages Vout

Vdd CMOS CP All-NMOS CP Dickson CP
Vmax = 12 V Vmax = 20 V Vmax = 88 V
clk1 clk2 clk3 clk4 clk1 clk2 clk3 clk4 clk1 clk2
clk1 clk2 clk3 clk4

Deep NWELL
Clock
Generation
clk
© 2014 IEEE
Sub-pump Design
Separate caps
for gate drive Isc
Isc
Isc
Isc
Two-phase Voltage
Doubler (TPVD) Improved TPVD
© 2014 IEEE
Sub-pump I Design
Vdd tov
φ2 V φ2
C2
φ1
φ4 V t
dd
V φ3 tnov
Vin C4 Vout
C3
φ4
φ3 Vdd t
Deep 0<tov<tnov
NWELL C1 NWELL Clock timing guarantees
φ1 break-before-make switching
Vdd
Vout=f(αVdd, Iload) α=1/(1+Cp/C)

• CMOS four phase voltage doubler (FPVD)
• 4 cascaded stages/ 2.5V thick oxide devices
© 2014 IEEE
Sub-pump II Design
-tnov<tov<tnov
Clock timing guarantees
break-before-make switching
Vout=f(αVdd-Vth, Iload) Vth=g(Vout-Vmid)
• All-NMOS four phase voltage doubler (FPVD)
• 5 cascaded stages/ 2.5V thick-oxide devices
© 2014 IEEE
Sub-pump III Design
2 1
in out
V φ2 tov
1 2
φ1
Vout=f(αVdd-VD, Iload) t
• Dickson charge pump using polysilicon

diodes
• Sub-pump consists of 8 stages
© 2014 IEEE
Polysilicon Diodes
Salicide Block
Vss Vdd P Li N Vdd Vss
PP Intrinsic NP
PP NP PP STI PP NP PP
STI
P- N- N- P-
Well Well Well Well
P-Well
Deep NWell
P-Sub
Vss
Vdd
Vdd
0.35< Li (um)<0.45
Li
W P I N
© 2014 IEEE
Clock Generation and Drive
Non overlapping phases
clk3 C3
clk
φ3 CP
C4
clk4 φ4 V CP
DD
Overlapping phases n1 C1
clk1 n2 φ1 CP
n1 n2 n1
Delay
V φ2 tov clk2 n2 C2
n1 φ2 CP
φ1 VDD
t
V φ3 tnov Buffering + Tristate switching
Cuts parasitic capacitance

φ4
t losses by <50%
© 2014 IEEE
Capacitor Design for Reliability (1/2)
• Time-dependent dielectric breakdown (TDDB)
• Reliability criterion is 0.01% failure over 10 years at 85˚C
1. Weibull statistics CDF=1-exp[(t/τ)β]
2. Accelerated sqrt-E model τ α exp[γ(√Vst- √Vop)]
3. Arrhenius temp. Relation τ α exp[(Ea/K)(1/Top-1/Tst)]
4. Poisson area scaling τ α (Ast/Aop)β
80
Voltage Tolerance (V)
60
40
20
Cunit= 3.6pF cap
0
1 1.5 2 2.5 3 3.5 4
Finger spacing normalized to min. spacing
© 2014 IEEE
Capacitor Design for Reliability (2/2)
~100nm ~150nm ~200nm
M4
~170nm ~170nm ~170nm
M3
M2
VP
VP
VP
VN
VN
VN
1st sub-pump 2nd sub-pump 3rd sub-pump
1x spacing (10V) 1.5x spacing (21 V) 2x spacing (33V)
1.4 fF/um2 0.93 fF/um2 0.6 fF/um2
Cp/C=3.6% Cp/C=5.2% Cp/C=8.8%
© 2014 IEEE
Measurement Results (1/3)
40
Pump I
35 Pump II
34 V
Output Voltage (V)
30 Pump III
Voxide
25
20 20 V
15 VNP
12 V
10
5
VDNW All pumps cascaded
Fpump=8MHz
0
1.5 1.75 2 2.25 2.5 2.75 3 No load condition
Supply Voltage (V)
1st sub-pump 2nd sub-pump 3rd sub-pump Total

0.028mm2 0.053mm2 0.071mm2 0.152mm2
© 2014 IEEE
100
3rd sub-pump
Output Voltage (V)
80
Vmid=0V
60
40
20
Device failure
0 micrograph
0 20 40 60 80
Input voltage (V)
• Clock amplitude and frequency are fixed

• Input voltage is manually ramped
© 2014 IEEE
35 Vdd=2.25V
0.4 Vdd=2.25V
Output Voltage (V)
30 Vdd=2.5V Vdd=2.5V
25 Vdd=2.75V 0.3 Vdd=2.75V
Efficeincy
Measurements
20
15
0.2 @ fpump=8MHz
10
0.1
5
0 20 40 60 80 100 0 20 40 60 80 100
Load Current (uA) Load Current (uA)
1000
(Kohm)
750
Measurement
500 @ Vdd=2.5V
out
250
R
0 5 10 15 20 25 30 35 40 45
Pumping Frequency (MHz)
© 2014 IEEE
Conclusion
• A 34V charge pump in 65nm Bulk CMOS
represents a 3x improvement in max. voltage
– Stacking substrate diodes + All-NMOS CP cell
– Polysilicon diodes
• A hybrid architecture enables improved
power efficiencies
• Device and component reliability carefully
preserved
Tech. # of Vclk Voltage Eff. Rout @ Area
stages range f = 8MHz
[3] 0.25um 4 10V >43V -- ~ 150KΩ ~0.6mm2
This work 65nm 17 2.5V >34V 38% 370KΩ 0.15mm2
© 2014 IEEE

Low Power DC-DC Converter

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Low Power DC-DC Converter

Uploaded by

Copyright:

Available Formats

WELCOME TO

Jungmoon Kim1,2, Philip K. T. Mok1, and Chulwoo Kim2

1Hong Kong University of Science and

• Low-input-voltage (VIN) up-converters

* Y. Nakagome et al., JSSC 1991, pp 465-472.

* P. Favrat et al., JSSC 1998, pp 410-416.

* P. Favrat et al., JSSC 1998, pp 410-416.

* P.-H. Chen et al., CICC 2010, pp 239-242.

• Fixed dead-time circuit is not effective @ low VIN

• How to control TD for low-power and low-voltage

3Massachusetts Eye and Ear Infirmary, Boston, MA,

4Massachusetts General Hospital, Harvard University, Boston, MA

*now with Texas Instruments, Dallas, TX

Automotive Applications Flexible circuits (Univ. Illinois, 2012)

Maximum Low quiescent Power Converter

Reference:- P.P. Mercier, A.C. Lysaght, S. Bandyopadhyay, K.M. Stankovic and

Maximum Extractable Efficient Boost Converter

 Comparison with state-of-art and Conclusions

Single Power Conversion Stage for increased efficiency

Long idle time compared to Φ1

Conduction Loss = IN,RMS2 RDS,N + IP,RMS2 RDS,P + IIN,RMS2 RESR

Switching Loss = CG,NVGATE2 fs+ CG,PVGATE2 fs + 0.5CPARVDD2 fs

From Power FETs From Parasitics

fs of 1KHz, VDD of 1V CPAR typically ~5pF

Loss due to Power FET Low Leakage Output

Overall Loss = Switching Losses (∝CV2fs ) +

Conduction Losses (Irms2 R ) + Leakage Losses

Optimization w.r.t fs, WN and WP under ZIN constraint

Optimum Switching Frequency under ZIN constraint

Loss due to Leakage from Loss due to Leakage from

Power Loss due to Leakage from Output Path more than

Output Leakage governed

PMOS leakage reduced by

 VDD (~0.9V) converted to VPUMP (1.6-1.7V) with 77% efficiency

Charge Pump Leakage

Sensor Implemented in a 0.18μm CMOS Process

 Comparison with state-of-art and Conclusions

PMU Design Summary

Φ1Gen. Boost Input Voltage 20-70mV

Current Quiescent Power

 Power Management Unit of a sensor with an overall power

 Ultra-low power boost converter with peak 56% efficiency for

 pW Charge Pump for leakage reduction in boost converter

 Always on Circuits (Control and Bias) with 544pW quiescent

Wanyeong Jung, Sechang Oh, Suyoung Bang,

University of Michigan, Ann Arbor, MI

• Efficient DC-DC up-conversion at low power

CLS VIN CFLY

Clock Generator Switched Capacitor

Clock Generator Switched Capacitor

Clock Generator Switched Capacitor

CLS VIN CFLY

Clock Generator Switched Capacitor

VIN CFLY VIN CFLY

VOUT VOUT VOUT

VIN CFLY VIN CFLY VIN CFLY

VIN CFLY VIN CFLY VIN CFLY

C2P C1M VIN

C1: VDD – Δ VDD VSS

C2: VDD VDD – Δ VSS

C3: VDD – Δ VDD VSS

C1: VDD VDD – Δ VSS

Leakage – Usually negligible