05 SingleCycleCPU PDF

Single Cycle CPU
Jason Mars
Tuesday, February 5, 13
The Big Picture: The Performance Perspective
Execute an
entire instruction
• Processor design (datapath and control) will determine:

• Clock cycle time
• Clock cycles per instruction
Execute an
entire instruction

• Starting today:
• Single cycle processor:
• Advantage: One clock cycle per instruction
• Disadvantage: long cycle time
Execute an
entire instruction

• Starting today:
• Single cycle processor:
• Advantage: One clock cycle per instruction
• Disadvantage: long cycle time
• ET = Insts * CPI * Cyc Time
Execute an
entire instruction
Processor Datapath and Control
• We're ready to look at an implementation of the MIPS simplified to contain

only:
• memory-reference instructions: lw, sw
• arithmetic-logical instructions: add, sub, and, or, slt
• control flow instructions: beq

only:
• Generic Implementation:
• use the program counter (PC) to supply instruction address
• get the instruction from memory
• read registers
• use the instruction to decide exactly what to do

only:
• Generic Implementation:
• use the program counter (PC) to supply instruction address
• get the instruction from memory
• read registers
• use the instruction to decide exactly what to do
• All instructions use the ALU after reading the registers
• memory-reference? arithmetic? control flow?
Review: MIPS Instruction Formats
• All instructions 32-bits long
• 3 Formats:
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

shift
R-Type opcode rs rt rd amount
funct
6 bits 5 bits 5 bits 16 bits
I-Type opcode rs rt immediate / offset
6 bits 26 bits
J-Type opcode target
The MIPS Subset

shift
opcode rs rt rd amount
funct
opcode rs rt immediate / offset
The MIPS Subset
• R-Type
• add rd, rs, rt opcode rs rt rd shift
funct
amount
• sub, and, or, slt
The MIPS Subset
• R-Type
funct
amount
• LOAD and STORE 6 bits 5 bits 5 bits 16 bits
• lw rt, rs, imm16 opcode rs rt immediate / offset

• sw rt, rs, imm16
The MIPS Subset
• R-Type
funct
amount
• LOAD and STORE 6 bits 5 bits 5 bits 16 bits
• lw rt, rs, imm16 opcode rs rt immediate / offset

• sw rt, rs, imm16
• BRANCH: 6 bits 5 bits 5 bits 16 bits
• beq rs, rt, imm16 opcode rs rt immediate / offset
Basic Steps of Execution
• Instruction Fetch
• Where is the instruction?
• Decode
• What’s the incoming instruction?
• Where are the operands in an instruction?
• Decode
• Execution: ALU
• What is the function that ALU should perform?
• Decode
• Execution: ALU
• Memory access
• Where is my data?
• Decode
• Execution: ALU
• Memory access
• Write back results to registers
• Where to write?
• Decode
• Execution: ALU
• Memory access
• Where to write?
• Determine the next PC
• Instruction Fetch Instruction memory

• Where is the instruction? address: PC
• Decode
• Execution: ALU
• Memory access
• Where to write?

• Decode
• What’s the incoming instruction? register file
• Execution: ALU
• Memory access
• Where to write?

• Decode
• Execution: ALU
ALU
• Memory access
• Where to write?

• Decode
• Execution: ALU
ALU
• Memory access Data memory
• Where is my data? address: effective address
• Where to write?

• Decode
• Execution: ALU
ALU
• Where to write? register file

• Decode
• Execution: ALU
ALU
• Where to write? register file
• Determine the next PC program counter
Where We’re Going...
Instruction memory
address: PC
Instruction memory register file

address: PC

address: PC ALU

address: PC ALU
Data memory
address: effective address

address: PC ALU
program counter
Data memory
address: effective address
Review: Two Type of Logical Components
A
Combinational
Logic
C = f(A,B)
B
A
Combinational
Logic
C = f(A,B)
B
A
State C = f(A,B,state)
Element
B
clk
Clocking Methodology
Clk
Setup Hold Setup Hold
Don t Care
. . . .
. . . .
. . . .
• All storage elements are clocked by the same clock edge
Storage Element: The Register
• Register Write Enable
• Similar to the D Flip Flop except Data In Data Out
• N-bit input and output N N
• Write Enable input

Clk
• Write Enable:
• 0: Data Out will not change
• 1: Data Out will become Data In (on the clock edge)
Storage Element: Register File
RegWrite
Read Data 1
Write Data 32 32-bit 32
32 Registers
RR1 Read Data 2
5 32
RR2
WR 5
5
Clk
• Register File consists of (32) registers:

RegWrite
Read Data 1
32 Registers
RR1 Read Data 2
5 32
RR2
WR 5
5
Clk

• Two 32-bit output buses RegWrite
Read Data 1
32 Registers
RR1 Read Data 2
5 32
RR2
WR 5
5
Clk

• One 32-bit input bus Read Data 1

32 Registers
RR1 Read Data 2
5 32
RR2
WR 5
5
Clk


• Register is selected by: Write Data 32 32-bit 32
32 Registers
RR1 Read Data 2
5 32
RR2
WR 5
5
Clk


32 Registers
• RR1 selects the register to put on RR1 Read Data 2
bus “Read Data 1” 32
5
RR2
WR 5
5
Clk


32 Registers
5
RR2
• RR2 selects the register to put on
bus “Read Data 2” WR 5
5
Clk


32 Registers
5
RR2
5
• WR selects the register to be Clk
written


32 Registers
5
RR2
5
written
• via WriteData when RegWrite is 1


32 Registers
5
RR2
5
written
• via WriteData when RegWrite is 1
• Clock input (CLK)
data Write
Inside the Register File

FIGURE C.8.7 A register file with two read ports and one write port has five inputs and
two outputs. The control input Write is shown in color.
Read register
number 1
Register 0
Register 1
M
... u Read data 1
x
Register n – 2
Register n – 1
Read register
number 2
M
u Read data 2
x
FIGURE C.8.8 The implementation of two read ports for a register file with n registers
• The implementation of two read ports register file
can be done with a pair of n-to-1 multiplexors, each 32 bits wide. The register read number
signal is used as the multiplexor selector signal. Figure C.8.9 shows how the write port is implemented.
• n registers
• done with a pair of n-to-1 multiplexors, each 32 bits wide.
AppendixC-9780123747501.indd 55 26/07/11 6:29 PM
Storage Element: Memory
MemWrite Address
Write Data Read Data

32 32
Clk
MemRead
• Memory
MemWrite Address

32 32
Clk
MemRead
• Memory
• Two input buses: WriteData, Address
MemWrite Address

32 32
Clk
MemRead
• Memory
• One output bus: ReadData
MemWrite Address

32 32
Clk
MemRead
• Memory
• Memory word is selected by: MemWrite Address

32 32
Clk
MemRead
• Memory
• Address selects the word to put on ReadData
bus
32 32
Clk
MemRead
• Memory
bus
• If MemWrite = 1: address selects the memory
32 32
word to be written via the WriteData bus Clk
MemRead
• Memory
bus
32 32
MemRead
• Memory
bus
32 32
• The CLK input is a factor ONLY during write MemRead
operation
• Memory
bus
32 32
operation
• During read operation, behaves as a
combinational logic block:
• Memory
bus
32 32
operation
• During read operation, behaves as a
combinational logic block:
• Address valid => ReadData valid after
“access time.”
RTL: Register Transfer Language
• Describes the movement and manipulation of data between storage

elements:
R[3] <- R[5] + R[7]

PC <- PC + 4 + R[5]
R[rd] <- R[rs] + R[rt]
R[rt] <- Mem[R[rs] + immed]
Instruction Fetch and Program Counter
Management
Overview of the Instruction Fetch Unit
• The common RTL operations

• Fetch the Instruction: inst <- mem[PC]
• Update the program counter:
• Sequential Code: PC <- PC + 4
• Branch and Jump PC <- “something else”
Datapath for Register-Register Operations

shift
funct
• R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt

shift
funct

• RR1, RR2, and WR comes from instruction’s rs, rt, and rd fields

shift
funct

• RR1, RR2, and WR comes from instruction’s rs, rt, and rd fields
• ALUoperation and RegWrite: control logic after decoding instruction

shift
funct
Control Logic??
288 Chapter 5 The Processor: Datapath and Control
Branch
M
u
x
Add M
Add
u
x
ALU operation
Data
MemWrite
Register #
PC Address Instruction Registers ALU Address
Register # M Zero
u Data
Instruction
x memory
memory Register # RegWrite
Data
MemRead
Control
Tuesday, February 5, 13 FIGURE 5.2 The basic implementation of the MIPS subset including the necessary multiplexors and control
Control Logic??
Branch
M
u
x
Add M
Add
u
x
ALU operation
Data
MemWrite
Register #
Register # M Zero
u Data
Instruction
x memory
Data
MemRead
Control
Datapath for Load Operations
• R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16









Datapath for Store Operations
• Mem[R[rs] + SignExt[imm16]] <- R[rt] Example: sw rt, rs, imm16







Datapath for Branch Operations
• Z <- (rs == rt); if Z, PC = PC+4+imm16; else PC = PC+4

• beq rs, rt, imm16












Control Logic??
Branch
M
u
x
Add M
Add
u
x
ALU operation
Data
MemWrite
Register #
Register # M Zero
u Data
Instruction
x memory
Data
MemRead
Control
Control Logic??
Branch
M
u
x
Add M
Add
u
x
ALU operation
Data
MemWrite
Register #
Register # M Zero
u Data
Instruction
x memory
Data
MemRead
Control
Binary Arithmetic for the Next Address
• In theory, the PC is a 32-bit byte address into the instruction memory:

• Sequential operation: PC<31:0> = PC<31:0> + 4
• Branch operation: PC<31:0> = PC<31:0> + 4 + SignExt[Imm16] * 4

• The magic number “4” always comes up because:
• The 32-bit PC is a byte address
• And all our instructions are 4 bytes (32 bits) long
• The 2 LSBs of the 32-bit PC are always zeros
• There is no reason to have hardware to keep the 2 LSBs

• The magic number “4” always comes up because:
• The 32-bit PC is a byte address
• And all our instructions are 4 bytes (32 bits) long
• The 2 LSBs of the 32-bit PC are always zeros
• There is no reason to have hardware to keep the 2 LSBs
• In practice, we can simplify the hardware by using a 30-bit PC<31:2>:
• Branch operation: PC<31:2> = PC<31:2> + 1 + SignExt[Imm16]
• In either case: Instruction Memory Address = PC<31:2> concat “00”
Putting it All Together: A Single Cycle Datapath
• We have everything except control signals
GAME: GUESS THE FUNCTION!!
The R-Format (e.g. add) Datapath
The Load Datapath
The Load Datapath
The Load Datapath
The Load Datapath
The Load Datapath
The Load Datapath
The Load Datapath
The Load Datapath
The Load Datapath
The Load Datapath
The Load Datapath
The Store Datapath
The Store Datapath
The Store Datapath
The Store Datapath
The Store Datapath
The Store Datapath
The Store Datapath
The Store Datapath
The Store Datapath
The Branch (beq) Datapath
GAME: GUESS THE FUNCTION!! (Review)
Key Points
Key Points
• CPU is just a collection of state and combinational logic
Key Points
• We just designed a very rich processor, at least in terms of functionality
Key Points
• We just designed a very rich processor, at least in terms of functionality
• ET = IC * CPI * Cycle Time
• where does the single-cycle machine fit in?
The Control Unit
ALU Control Bits
• 5-Function ALU
ALU control input Function Operations
000 And and
001 Or or
010 Add add, lw, sw
110 Subtract sub, beq
111 Slt slt
• Note: book also has NOR, not used - and a forth bit, not used
Full ALU
what signals accomplish:

Binvert CIn Oper
add?
sub?
and?
or?
beq?
slt?
C.5 Constructing a Basic A
ALU operation
Zero
ALU Result
Overflow
CarryOut
FIGURE C.5.14 The symbol commonly used to represent an ALU,

C.5.12. This symbol is also used to represent an adder, so it is normally labeled eit
Full ALU

Binvert CIn Oper
add? 0 0 10
sub?
and?
or?
beq?
slt?
ALU operation
Zero
ALU Result
Overflow
CarryOut

Full ALU

Binvert CIn Oper
add? 0 0 10
sub? 1 1 10
and?
or?
beq?
slt?
ALU operation
Zero
ALU Result
Overflow
CarryOut

Full ALU

Binvert CIn Oper
add? 0 0 10
sub? 1 1 10
and? 0 0 00
or?
beq?
slt?
ALU operation
Zero
ALU Result
Overflow
CarryOut

Full ALU

Binvert CIn Oper
add? 0 0 10
sub? 1 1 10
and? 0 0 00
or? 0 0 01
beq?
slt?
ALU operation
Zero
ALU Result
Overflow
CarryOut

Full ALU

Binvert CIn Oper
add? 0 0 10
sub? 1 1 10
and? 0 0 00
or? 0 0 01
beq? 1 1 10
slt?
ALU operation
Zero
ALU Result
Overflow
CarryOut

Full ALU

Binvert CIn Oper
add? 0 0 10
sub? 1 1 10
and? 0 0 00
or? 0 0 01
beq? 1 1 10
slt? 1 1 11
ALU operation
Zero
ALU Result
Overflow
CarryOut

ALU Control Bits
• 5-Function ALU
ALU control input Function Operations
000 And and
001 Or or
010 Add add, lw, sw
110 Subtract sub, beq
111 Slt slt
• Based on opcode (bits 31-26) and function code (bits 5-0) from instruction
• ALU doesn’t need to know all opcodes--we will summarize opcode with
ALUOp (2 bits):
00 - lw,sw 01 - beq 10 - R-format
func
op Main 6 ALU ALUctr
6 ALUop Control 3
Control
2
Generating ALU Control
Instruction ALUOp Instruction Function Desired ALU
opcode operation code ALU control
action input
lw 00 load word xxxxxx add 010
sw 00 store word xxxxxx add 010
beq 01 branch eq xxxxxx subtract 110
R-type 10 add 100000 add 010
R-type 10 subtract 100010 subtract 110
R-type 10 AND 100100 and 000
R-type 10 OR 100101 or 001
R-type 10 slt 101010 slt 111
ALU
Control
Logic
Controlling the CPU
Mem to- Reg Mem Mem

Instruction RegDst ALUSrc Reg Write Read Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 1 0
lw 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 1 0
lw 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0
lw 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 1 0
lw 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 1 0
lw 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 1 0
lw 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 X 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 X 0 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 X 0 0 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 X 0 0 0 0 1
Controlling the CPU
Mem to- Reg Mem Mem

R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 X 0 0 0 1 0 1
Control Truth Table
R-format lw sw beq
Opcode 000000 100011 101011 000100
RegDst 1 0 x x
ALUSrc 0 1 1 0
MemtoReg 0 1 x x
RegWrite 1 1 0 0
Outputs MemRead 0 1 0 0
MemWrite 0 0 1 0
Branch 0 0 0 1
ALUOp1 1 0 0 0
ALUOp0 0 0 0 1
Control
• Simple Combinational Logic (truth tables)
Inputs
Op5
Op4
ALUOp
Op3
ALU control block
Op2
ALUOp0 Op1
ALUOp1 Op0
Operation2
F3 Outputs
Operation R-format Iw sw beq
F2 Operation1 RegDst
F (5– 0)
ALUSrc
F1
Operation0 MemtoReg
F0 RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOpO
Single Cycle CPU Summary
• Easy, particularly the control
• Which instruction takes the longest? By how much? Why is that a problem?
• ET = IC * CPI * CT
• What else can we do?
• When does a multi-cycle implementation make sense?
• e.g., 70% of instructions take 75 ns, 30% take 200 ns?
• suppose 20% overhead for extra latches
• When does a multi-cycle implementation make sense?
• e.g., 70% of instructions take 75 ns, 30% take 200 ns?
• suppose 20% overhead for extra latches
• Real machines have much more variable instruction latencies than this.

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Single Cycle CPU

• Processor design (datapath and control) will determine:

• Processor design (datapath and control) will determine:

• Processor design (datapath and control) will determine:

• ET = Insts * CPI * Cyc Time

• We're ready to look at an implementation of the MIPS simplified to contain

• We're ready to look at an implementation of the MIPS simplified to contain

• We're ready to look at an implementation of the MIPS simplified to contain

• All instructions 32-bits long

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

6 bits 5 bits 5 bits 16 bits

I-Type opcode rs rt immediate / offset

J-Type opcode target

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

6 bits 5 bits 5 bits 16 bits

opcode rs rt immediate / offset

6 bits 5 bits 5 bits 16 bits

opcode rs rt immediate / offset

6 bits 5 bits 5 bits 16 bits

opcode rs rt immediate / offset

6 bits 5 bits 5 bits 16 bits

opcode rs rt immediate / offset

• LOAD and STORE 6 bits 5 bits 5 bits 16 bits

• lw rt, rs, imm16 opcode rs rt immediate / offset

6 bits 5 bits 5 bits 16 bits

opcode rs rt immediate / offset

• LOAD and STORE 6 bits 5 bits 5 bits 16 bits

• lw rt, rs, imm16 opcode rs rt immediate / offset

• BRANCH: 6 bits 5 bits 5 bits 16 bits

• beq rs, rt, imm16 opcode rs rt immediate / offset

• Instruction Fetch Instruction memory

• Instruction Fetch Instruction memory

• Instruction Fetch Instruction memory

• Instruction Fetch Instruction memory

• Instruction Fetch Instruction memory

• Instruction Fetch Instruction memory

Instruction memory register file

Instruction memory register file

Instruction memory register file

Instruction memory register file

• All storage elements are clocked by the same clock edge

• Register Write Enable

• Similar to the D Flip Flop except Data In Data Out

• N-bit input and output N N

• Write Enable input

• 0: Data Out will not change

• 1: Data Out will become Data In (on the clock edge)

• Register File consists of (32) registers:

• Register File consists of (32) registers:

• Register File consists of (32) registers:

• One 32-bit input bus Read Data 1

• Register File consists of (32) registers:

• One 32-bit input bus Read Data 1

• Register File consists of (32) registers:

• One 32-bit input bus Read Data 1

• Register File consists of (32) registers:

• One 32-bit input bus Read Data 1

• Register File consists of (32) registers:

• One 32-bit input bus Read Data 1

• Register File consists of (32) registers:

• One 32-bit input bus Read Data 1

• Register File consists of (32) registers:

• One 32-bit input bus Read Data 1