library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity BPtoRGB is
port ( iCLK : in std_logic;
iRST : in std_logic;
next_row : in std_logic_vector (7 downto 0);
current_row : in std_logic_vector (7 downto 0);
previuos_row : in std_logic_vector (7 downto 0);
sel : in std_logic_vector(1 downto 0);--sel
r : out unsigned (7 downto 0);
g : out unsigned (7 downto 0);
b : out unsigned (7 downto 0)
);
end BPtoRGB;

architecture Behavioral of BPtoRGB is

signal c1 : unsigned(7 downto 0) := ( others => '0');
signal c2 : unsigned(7 downto 0) := ( others => '0');
signal n1 : unsigned(7 downto 0) := ( others => '0');
signal p1 : unsigned(7 downto 0) := ( others => '0');
signal c3 : unsigned(7 downto 0) := ( others => '0');
signal d1 : unsigned(7 downto 0) := ( others => '0');
signal d2 : unsigned(7 downto 0) := ( others => '0');
signal p2 : unsigned(7 downto 0) := ( others => '0');
signal p3 : unsigned(7 downto 0) := ( others => '0');
signal d3 : unsigned(7 downto 0) := ( others => '0');
signal d4 : unsigned(7 downto 0) := ( others => '0');

--signal sel : std_logic_vector(1 downto 0) := ( others => '0');

begin

--process (iCLK)
--begin
-- if rising_edge(iCLK) then
-- if(bayer_phase = "00") then--RG-GB
-- if(position = "00") then
-- sel <= "10";
-- else if(position = "01") then
-- sel <= "00";
-- else if(position = "10") then
-- sel <= "01";
-- else if(position = "11") then
-- sel <= "11";
-- end if;
-- end if;
-- end if;
-- end if;

-- else if(bayer_phase = "01") then--GR-BG

-- if(position = "00") then
-- sel <= "00";
-- else if(position = "01") then
-- sel <= "10";
-- else if(position = "10") then
-- sel <= "11";
-- else if(position = "11") then
-- sel <= "01";
-- end if;
-- end if;
-- end if;
-- end if;

-- else if(bayer_phase = "10") then--BG-GR

-- if(position = "00") then
-- sel <= "11";
-- else if(position = "01") then
-- sel <= "01";
-- else if(position = "10") then
-- sel <= "00";
-- else if(position = "11") then
-- sel <= "10";
-- end if;
-- end if;
-- end if;
-- end if;

-- else if(bayer_phase = "11") then--GB-RG

-- if(position = "00") then
-- sel <= "01";
-- else if(position = "01") then
-- sel <= "11";
-- else if(position = "10") then
-- sel <= "10";
-- else if(position = "11") then
-- sel <= "00";
-- end if;
-- end if;
-- end if;
-- end if;
-- end if;
-- end if;
-- end if;
-- end if;
-- end if;
--end process;

process (iCLK)
begin
if rising_edge(iCLK) then
if (iRST='0') then
c1 <= "00000000";
c2 <= "00000000";
n1 <= "00000000";
p1 <= "00000000";
c3 <= "00000000";
d1 <= "00000000";
d2 <= "00000000";
p2 <= "00000000";
 p3 <= "00000000";
d3 <= "00000000";
d4 <= "00000000";
else
n1 <= unsigned(next_row);
c1 <= unsigned(current_row);
p1 <= unsigned(previuos_row);
c2 <= c1;
c3 <= c2;
d1 <= shift_right(unsigned(c1+c3),1);
d2 <= shift_right(unsigned(p1+n1),1);
p2 <= d2;
p3 <= p2;
d3 <= shift_right(unsigned(d1+p2),1);
d4 <= shift_right(unsigned(p3+d2),1);

end if;
end if;
end process;

proces_mux_r: process (d1,p2,c2,d4,sel)

begin
case sel is
when "00" => r <= d1;
when "01" => r <= p2;
when "10" => r <= c2;
when others => r <= d4;
end case;
end process;

proces_mux_g: process (d3,c2,sel(1))

begin
case sel(1) is
when '0' => g <= c2;
when others => g <= d3;
end case;
end process;

proces_mux_b: process (d1,p2,c2,d4,sel)

begin
case sel is
when "00" => b <= p2;
when "01" => b <= d1;
when "10" => b <= d4;
when others => b <= c2;
end case;
end process;

end Behavioral;