MP PPT 2016 171

MICROPROCESSORS
Subject code:15EC42
Dept. of ECE, ATMECE, MYSURU 1

Features
 It is a 16-bit μp.
 8086 has a 20 bit address bus can access up to 220
memory locations (1 MB).
 It can support up to 64K I/O ports.
 It provides 14, 16 -bit registers.
 Word size is 16 bits.
 It has multiplexed address and data bus AD0-
AD15 and A16 – A19.
 It requires single phase clock with 33% duty cycle
to provide internal timing.
 8086 is designed to operate in two modes, Minimum
and Maximum.
 It can prefetches up to 6 instruction bytes from

memory and queues them in order to speed up
instruction execution.
 It requires +5V power supply.
 A 40 pin dual in line package.
 Address ranges from 00000H to FFFFFH
 Memory is byte addressable - Every byte has a

separate address.
Intel 8086 Internal Architecture

Internal architecture of 8086
• 8086 has two blocks BIU and EU.
• The BIU handles all transactions of data and addresses
on the buses for EU.
• The BIU performs all bus operations such as instruction
fetching, reading and writing operands for memory and
calculating the addresses of the memory operands. The
instruction bytes are transferred to the instruction
queue.
• EU executes instructions from the instruction system
byte queue.

• Both units operate asynchronously to give the
8086 an overlapping instruction fetch and
execution mechanism which is called as
Pipelining. This results in efficient use of the
system bus and system performance.
• BIU contains Instruction queue, Segment
registers, Instruction pointer, Address adder.
• EU contains Control circuitry, Instruction
decoder, ALU, Pointer and Index register, Flag
register.

EXECUTION UNIT
• Decodes instructions fetched by the BIU

• Generate control signals,
• Executes instructions.
The main parts are:

• Control Circuitry
• Instruction decoder
• ALU

EXECUTION UNIT – General Purpose Registers
16 bits
8 bits 8 bits
AH AL Accumulator
AX
BX
BH BL Base
CX CH CL Count
DX DH DL
Data
SP Stack Pointer
Pointer
BP Base Pointer
SI Source Index
Index
DI Destination Index
EXECUTION UNIT – General Purpose Registers
Register Purpose
AX Word multiply, word divide, word I /O
AL Byte multiply, byte divide, byte I/O, decimal arithmetic
AH Byte multiply, byte divide
BX Store address information
CX String operation, loops
CL Variable shift and rotate
DX Word multiply, word divide, indirect I/O

(Used to hold I/O address during I/O instructions. If the result is more than
16-bits, the lower order 16-bits are stored in accumulator and higher order
16-bits are stored inofDX
Dept. ECE,register)
ATMECE, MYSURU 9
Pointer And Index Registers
• used to keep offset addresses.
• Used in various forms of memory addressing.
• In the case of SP and BP the default reference to form a
physical address is the Stack Segment (SS-will be discussed
under the BIU)
• The index registers (SI & DI) and the BX generally default to
the Data segment register (DS).
SP: Stack pointer
– Used with SS to access the stack segment
BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments

• SI: Source Index register
– is required for some string operations
– When string operations are performed, the SI
register points to memory locations in the data
segment which is addressed by the DS register.
Thus, SI is associated with the DS in string operations.
• DI: Destination Index register

– is also required for some string operations.
– When string operations are performed, the DI
register points to memory locations in the data
segment which is addressed by the ES register.
Thus, DI is associated with the ES in string operations.
• The SI and the DI registers may also be used to access

data stored in arraysDept. of ECE, ATMECE, MYSURU 11
EXECUTION UNIT – Flag Register
• A flag is a flip flop which indicates some conditions

produced by the execution of an instruction or
controls certain operations of the EU .
• In 8086 The EU contains
– a 16 bit flag register
– 9 of the 16 are active flags and remaining 7 are undefined.
– 6 flags indicates some conditions- status flags
– 3 flags –control Flags
U U U U OF DF IF TF SF ZF U AF U PF U CF
Sign Auxiliary Carry

Interrupt Trap Zero Parity
Over flow Direction
U - Unused
EXECUTION UNIT – Flag Register
Flag Purpose
Carry (CF) Holds the carry after addition or the borrow after subtraction.
Also indicates some error conditions, as dictated by some
programs and procedures .
Parity (PF) PF=0;odd parity, PF=1;even parity.
Auxiliary (AF) Holds the carry (half – carry) after addition or borrow after
subtraction between bit positions 3 and 4 of the result
(for example, in BCD addition or subtraction.)
Zero (ZF) Shows the result of the arithmetic or logic operation.
Z=1; result is zero. Z=0; The result is 0
Sign (SF) Holds the signDept.
of ofthe result after an arithmetic/logic instruction
ECE, ATMECE, MYSURU 13
Flag Purpose
A control flag.
Trap (TF) Enables the trapping through an on-chip debugging
feature.
A control flag.
Interrupt (IF) Controls the operation of the INTR (interrupt request)
I=0; INTR pin disabled. I=1; INTR pin enabled.
A control flag.
Direction (DF) It selects either the increment or decrement mode for DI
and /or SI registers during the string instructions.
Overflow occurs when signed numbers are added or
Overflow (OF) subtracted. An overflow indicates the result has exceeded
the capacity of the Machine

Execution unit – Flag Register
• Six of the flags are status indicators reflecting properties
of the last arithmetic or logical instruction.
• For example, if register AL = 7Fh and the instruction ADD
AL,1 is executed then the following happen
AL = 80h
CF = 0; there is no carry out of bit 7
PF = 0; 80h has an odd number of ones
AF = 1; there is a carry out of bit 3 into bit 4
ZF = 0; the result is not zero
SF = 1; bit seven is one
OF = 1; the sign bit has changed
BUS INTERFACE UNIT (BIU)
Contains
• 6-byte Instruction Queue (Q)
• The Segment Registers (CS, DS, ES, SS).
• The Instruction Pointer (IP).
• The Address Summing block (Σ)

THE QUEUE (Q)
• The BIU uses a mechanism known as an instruction
stream queue to implement a pipeline architecture.
• This queue permits pre-fetch of up to 6 bytes of

instruction code. Whenever the queue of the BIU is not
full, it has room for at least two more bytes and at the
same time the EU is not requesting it to read or write
operands from memory, the BIU is free to look ahead in
the program by pre-fetching the next sequential
instruction.

• These pre-fetching instructions are held in its FIFO
queue. With its 16 bit data bus, the BIU fetches two
instruction bytes in a single memory cycle.
• After a byte is loaded at the input end of the queue, it

automatically shifts up through the FIFO to the empty
location nearest the output.
• The EU accesses the queue from the output end. It

reads one instruction byte after the other from the
output of the queue.
• The intervals of no bus activity, which may occur

between bus cycles are known as Idle state.
Segmented Physical Memory
Memory 00000
The memory in an 8086/88 based
system is organized as segmented
memory.
Code segment (64KB)
The CPU 8086 is able to address

Data segment (64KB)
1 MB
1Mbyte of memory.
Extra segment (64KB)
The Complete physically available
memory may be divided into a Stack segment (64KB)
number of logical segments.
FFFFF

• The size of each segment is 64 KB
• A segment is an area that begins at any location which is
divisible by 16.
• A segment may be located any where in the memory
• Each of these segments can be used for a specific
function.
– Code segment is used for storing the instructions.

– The stack segment is used as a stack and it is used to store
the return addresses.
– The data and extra segments are used for storing data byte.
* In the assembly language programming, more than one

data/ code/ stack segments can be defined. But only one
segment of each type can be accessed at any time.
• The 4 segments are Code, Data, Extra and Stack
segments.
• A Segment is a 64kbyte block of memory.
• The 16 bit contents of the segment registers in the
BIU actually point to the starting location of a
particular segment.
• Segments may be overlapped or non-overlapped
Advantages of Segmented memory Scheme

• Allows the memory capacity to be 1Mb although the actual addresses to be
handled are of 16 bit size.
• Allows the placing of code, data and stack portions of the same program in different
parts (segments) of the m/y, for data and code protection.
• Permits a program and/or its data to be put into different areas of memory each
time program is executed, i.e. provision for relocation may be done .
• The segment registers are used to allow the instruction, data or stack portion of a
program to be more than 64Kbytes long. The above can be achieved by using more
than one code, data or stack segments.
Segment registers
• In 8086/88 the processors have 4 segments registers
• Code Segment register (CS), Data Segment register (DS),
Extra Segment register (ES) and Stack Segment (SS)
register.
• All are 16 bit registers.
• Each of the Segment registers store the upper 16 bit
address of the starting address of the corresponding
segments.

MEMORY
00000
BIU
Segment Registers 34BA0
CODE (64k)
44B9F
CSR 34BA
44EB0
DATA (64K)
1 MB
DSR 44EB 54EAF
54EB0
ESR 54EB EXTRA (64K)
64EAF
SSR 695E 695E0
STACK (64K)
795DF
Each segment register store the upper

16 bit of the starting address of the
segments Dept. of ECE, ATMECE, MYSURU 24
Instruction pointer & summing block
• The instruction pointer register contains a 16-bit offset
address of instruction that is to be executed next.
• The IP always references the Code segment register (CS).
• The value contained in the instruction pointer is called as
an offset because this value must be added to the base
address of the code segment, which is available in the CS
register to find the 20-bit physical address.
• The value of the instruction pointer is incremented after
executing every instruction.
• To form a 20bit address of the next instruction, the 16 bit
address of the IP is added (by the address summing block)
to the address contained in the CS , which has been
shifted four bits to the left.

• The following examples shows the CS:IP scheme
of address formation:
CS 34BA IP 8AB4 Code segment
34BA0
Inserting a hexadecimal 0H (0000B)
with the CSR or shifting the CSR 8AB4 (offset)
four binary digits left
3D645
34BA0(CS)+
8AB4(IP)
3 D 6 5 4 (next address)
44B9F

• Example For Address Calculation (segment:
offset)
• If the data segment starts at location 1000h and

a data reference contains the address 29h where
is the actual data?
Offset 0000 0000 0010 1001
Segment Address
0001 0000 0000 0000 0000
Required Address 0001 0000 0000 0010 1001

Segment and Address register
combination
• CS:IP
• SS:SP SS:BP
• DS:BX DS:SI
• DS:DI (for other than string operations)
• ES:DI (for string operations)

Summary of Registers & Pipeline of 8086 µP
EU BIU
AX AH AL
IP
BX BH BL
Fetch &
CX CH CL D
store code CS DS ES SS
E
DX DH DL C
bytes in
C
O PIPELINE C
O PIPELINE O IP BX DI SP
D
SP D E (or) D DI BP
E O QUEUE E
BP I SI
R U
SI T N
DI
Default Assignment
Timing
FLAGS ALU control

Addressing Modes of 8086
• The different ways in which a processor can access data are
called addressing modes
• 8086 accesses code bytes using contents of CS & IP register
• 8086 accesses stack using contents of SS & SP register
• 8086 assembly language instructions can be used to illustrate
the addressing modes
• Format of MOV instruction
MOV destination, source

• Source of data can be
– Immediate data
– A specified register
– A memory location specified in 1 of 24
different ways
• Destination of data can be
– A specified register
– A memory location specified in 1 of 24
different ways

Classification of Addressing Modes
1. Register addressing mode
2. Immediate addressing mode
3. Memory addressing mode
4. Port addressing mode
5. Relative addressing mode
6. Implied addressing mode

• Source/destination can be one of the 8086
registers
• MOV AX, BX ; 16-bit data transfer
• MOV AL, BL ; 8-bit data transfer

• 8 or 16-bit data can be specified as part
of the instruction
• E.g. MOV AL, 45H
MOV BX, 5062H
• One of the operands is in memory
• 8086 must use
– a segment register
– A 16-bit offset (effective address)
• By default, DS register is used for accessing
data from memory
• 16-bit offset can be specified in many ways

Different ways of specifying
offset
• Direct memory addressing
• Register Indirect addressing
• Based addresSing
• Indexed addressing
• Based Indexed addressing
• String addressing

a. Direct Memory addressing
• Effective address is specified directly in the
instruction
• E.g. MOV BX, [5062]
• 20-bit physical address of memory location is
calculated using DS and offset value 5062
Segment register
+ = 20-bit physical address

of operand
16-bit offset

b. Register indirect addressing
• The effective address of memory operand

is present in one of the base or index
registers [BX, BP, SI, DI]
• E.g. MOV CX, [BX]
• If DS = 2000H, BX = 0004H
• THEN contents of memory location 20004H
are copied to register CX

c. Based addressing
• Effective address is sum of
– 16-bit offset given in instruction
– Contents of base register BX or BP
• Segment register is DS or SS
• E.g. MOV AX, 4[BX]
• E.G. PUSH CX

d. Indexed addressing

– Contents of index register SI or DI
• Segment register is DS
• E.g. MOV AX, 4[SI]

e. Based Indexed addressing
– Contents of index register SI or DI
– Contents of base register BX or BP
• Segment register is DS
• E.g. MOV AX, 4[BX][SI]

f. String addressing
• Used when string related instructions are

executed
• Uses index registers
• SI register points to the first byte or word of
the source string
• DI register points to the first byte or word of
the destination

Classification of Addressing Modes
4. Port addressing mode

4. Port addressing
• Two I/O port addressing modes can be used
–Direct (e.g. IN AL, 02H)
–Indirect (e.g. IN AL, DXH)

• Specifies the operand as a 8-bit signed
displacement relative to PC
• E.g. JNC 08H
• IF carry = 0, THEN PC is loaded with current PC
contents + 8-bit signed value

• No operands are specified
• E.g. CLC
• Means clear carry flag

8086 INSTRUCTION FORMATS
The 8086 instruction sizes vary from one to six bytes. Depending on
the type of coding, an instruction may have more than one Hexcode,
(not unique as in 8085)
The OP code field occupies 6-bits.It defines the operation to be

carried out by the instruction.
Register Direct bit (D) occupies one bit. It defines whether the
register operand in byte 2 is the source or destination operand.
D=1 Specifies that the register operand is the destination operand.
D=0 indicates that the register is a source operand.
Data size bit (W) defines whether the operation to be performed is an
8 bit or 16 bit data

• This byte contains 3 fields. These are the mode (MOD) field, the register
(REG) field and the
• Register/Memory (R/M) field.
• Register field occupies 3 bits. It defines the register for the first operand
which is specified as source or destination by the D bit.

Register Codes:
The R/M field occupies 3 bits. The R/M field along with the MOD field defines the
second operand as shown below.
MOD 11

In the above, encoding of the R/M field depends on how the mode field is set. If MOD=11
(register to register mode), this R/M identifies the second register operand.
MOD selects memory mode, then R/M indicates how the effective address of the memory
operand is to be calculated. Bytes 3 through 6 of an instruction are optional fields that
normally contain the displacement value of a memory operand and / or the actual value
of an immediate constant operand.
Obtain the opcodes for the following instructions.
Example 1 : Code for MOV CH, BL

This instruction transfers 8 bit content of BL into CH
The 6 bit Opcode for this instruction is 1000102 D bit indicates whether the register
specified by the REG field of byte 2 is a source or destination operand.
D=0 indicates BL is a source operand.

W=0 byte operation
In byte 2, since the second operand is a register MOD field is 112.
The R/M field = 101 (CH)
Register (REG) field = 011 (BL)
Hence the machine code for MOV CH, BL is

10001000 11 011 101
Byte 1 Byte2
= 88DDH

Example 2: Code for SUB BX, (DI)
This instruction subtracts the 16 bit content of memory location addressed by DI and DS
from Bx.
The 6 bit Opcode for SUB is 0010102.
D=1 so that REG field of byte 2 is the destination operand. W=1 indicates 16 bit operation.
MOD = 00
REG = 011
R/M = 101
The machine code is 0010 1011 0001 1101
2B1Dh
Example 3 :Code for MOV 1234 (BP), DX

Here we have specify DX using REG field, the D bit must be 0, indicating the DX is the
source register. The REG field must be 010 to indicate DX register. The W bit must be 1 to
indicate it is a word operation. 1234 [BP] is specified using MOD value of 10 and R/M
value of 110 and a displacement of 1234H.
The 4 byte code for this instruction would be 89 96 34 12H

Example 4 :Code for MOV DS : 2345 [BP], DX
Here we have to specify DX using REG field. The D bit must be 0, indicating that Dx is the
source register. The REG field must be 010 to indicate DX register. The w bit must be 1 to
indicate it is a word operation. 2345 [BP] is specified with MOD=10 and R/M = 110 and
displacement = 2345 H.
Whenever BP is used to generate the Effective Address (EA), the default segment would
be SS. In this example, we want the segment register to be DS, we have to provide the
segment override prefix byte (SOP byte) to start with. The SOP byte is 001 xx 110, where
SR value is provided as per table shown below.
To specify DS register, the SOP byte would be 001 11 110 = 3E H. Thus the 5 byte code
for this instruction would be 3E 89 96 45 23 H.
Suppose we want to code MOV SS : 2345 (BP), DX. This generates only a 4 byte code,
without SOP byte, as SS is already the default segment register in this case.
Example 5:
Give the instruction template and generate code for the instruction ADD 0FABE [BX]
[DI], DX (code for ADD instruction is 000000)
ADD 0FABE [BX] [DI], DX
Here we have to specify DX using REG field. The bit D is 0, indicating that DX is the
source register. The REG field must be 010 to indicate DX register. The w must be 1 to
indicate it is a word operation. FABE (BX + DI) is specified using MOD value of 10 and
R/M value of 001 (from the summary table). The 4 byte code for this instruction would be
Example 6 :
Give the instruction template and generate the code for the instruction MOV AX, [BX]
(Code for MOV instruction is 100010)
AX destination register with D=1 and code for AX is 000 [BX] is specified using 00 Mode
and R/M value 111. It is a word operation

INPUT/OUTPUT INSTRUCTIONS:
IN acc, port : In transfers a byte or a word from input port to the AL register or the AX
register respectively. The port number my be specified either with an immediate byte
constant, allowing access to ports numbered 0 through 255 or with a number previously
placed in the DX register allowing variable access (by changing the value in DX) to
ports numbered from 0 through 65,535.
OUT port, acc : Out transfers a byte or a word from the AL register or the AX register
respectively to an output port. The port numbers may be specified either with an immediate
byte or with a number previously placed in the register DX allowing variable access.

I/O mode (direct) :
Port number is an 8 bit immediate operand.
Example : OUT 05 H, AL
Outputs [AL] to 8 bit port 05 H
I/O mode (indirect):
The port number is taken from DX.
Example 1 : INAL, DX
If [DX] = 5040
8 bit content by port 5040 is moved into AL.
Example 2 : IN AX, DX
Inputs 8 bit content of ports 5040 and 5041 into AL and AH respectively.

Introduction to 8086 Assembly Language
Program Statements
Mnemonic operand(destination), operand(source)
;comment
Operation is a predefined or reserved word

mnemonic - symbolic operation code
directive - pseudo-operation code
Space or tab separates initial fields
Comments begin with semicolon
Most assemblers are not case sensitive

Program Data and Storage
• Pseudo-ops to define • These directives require
data or reserve storage one or more operands
– DB - byte(s) – define memory contents
– DW - word(s) – specify amount of
– DD - doubleword(s) storage to reserve for
– DQ - quadword(s) run-time data
– DT - tenbyte(s)

Defining Data
• Numeric data values • A list of values may be
– 100 - decimal used - the following
– 100B - binary creates 4 consecutive
– 100H - hexadecimal words
– '100' - ASCII DW 40CH,10B,-13,0
– "100" - ASCII • A ? represents an
• Use the appropriate uninitialized storage
DEFINE directive (byte, location
word, etc.) DB 255,?,-128,'X'

Naming Storage Locations
• Names can be • ANum refers to a byte
associated with storage storage location,
locations initialized to FCh
ANum DB -4 • The next word has no
DW 17 associated name
ONE
UNO DW 1
• ONE and UNO refer to
X DD ? the same word
• These names are called • X is an unitialized
variables doubleword

Arrays
• Any consecutive storage locations of the same
size can be called an array
X DW 40CH,10B,-13,0
Y DB 'This is an array'
Z DD -109236, FFFFFFFFH, -1, 100B
• Components of X are at X, X+2, X+4, X+8
• Components of Y are at Y, Y+1, …, Y+15
• Components of Z are at Z, Z+4, Z+8, Z+12

DUP
• Allows a sequence of storage locations to be
defined or reserved
• Only used as an operand of a define directive
DB 40 DUP (?)
DW 10h DUP (0)
DB 3 dup ("ABC")
db 4 dup(3 dup (0,1), 2 dup('$'))

Word Storage
• Word, doubleword, and quadword data are

stored in reverse byte order (in memory)
Directive Bytes in Storage
DW 256 00 01
DD 1234567H 67 45 23 01
DQ 10 0A 00 00 00 00 00 00 00
X DW 35DAh DA 35
Low byte of X is at X, high byte of X is at X+1

Named Constants
• Symbolic names associated with storage locations
represent addresses
• Named constants are symbols created to represent
specific values determined by an expression
• Named constants can be numeric or string
• Some named constants can be redefined
• No storage is allocated for these values

Equal Sign Directive
• name = expression
– expression must be numeric
– these symbols may be redefined at any time
maxint = 7FFFh
count = 1
DW count
count = count * 2
DW count

EQU Directive
• name EQU expression
– expression can be string or numeric
– Use < and > to specify a string EQU
– these symbols cannot be redefined later in the
program
sample EQU 7Fh
aString EQU <1.234>
message EQU <This is a message>

Data Transfer Instructions
• MOV target, source • reg can be any non-
– reg, reg segment register except
– mem, reg IP cannot be the target
– reg, mem register
– mem, immed • MOV's between a
– reg, immed segment register and
• Sizes of both operands memory or a 16-bit
must be the same register are possible

Sample MOV Instructions
b db 4Fh
w dw 2048 • When a variable is created with a
define directive, it is assigned a
mov bl,dh default size attribute (byte, word,
mov ax,w etc)
mov ch,b • You can assign a size attribute
mov al,255 using LABEL
mov w,-100 LoByte LABEL BYTE
mov b,0 aWord DW 97F2h

Addresses with Displacements
b db 4Fh, 20h, 3Ch • The assembler
w dw 2048, -100, 0 computes an address
based on the expression
mov bx, w+2 • NOTE: These are address
mov b+1, ah computations done at
mov ah, b+5 assembly time
MOV ax, b-1
mov dx, w-3
will not subtract 1 from the
• Type checking is still in value stored at b
effect

eXCHanGe
• XCHG target, source • This provides an
– reg, reg efficient means to swap
– reg, mem the operands
– mem, reg – No temporary storage is
needed
• MOV and XCHG cannot
perform memory to – Sorting often requires
this type of operation
memory moves
– This works only with the
general registers

Arithmetic Instructions
ADD dest, source • source can be a general
SUB dest, source register, memory
INC dest location, or constant
DEC dest • dest can be a register or
memory location
NEG dest
– except operands cannot
• Operands must be of both be memory
the same size

Program Segment Structure
• Data Segments • Stack Segment
– Storage for variables – used to set aside storage
– Variable addresses are for the stack
computed as offsets – Stack addresses are
from start of this computed as offsets into
segment this segment
• Code Segment • Segment directives
– contains executable .data
instructions .code
.stack size

Memory Models
• .Model memory_model
– tiny: code+data <= 64K (.com program)
– small: code<=64K, data<=64K, one of each
– medium: data<=64K, one data segment
– compact: code<=64K, one code segment
– large: multiple code and data segments
– huge: allows individual arrays to exceed 64K
– flat: no segments, 32-bit addresses, protected
mode only (80386 and higher)

Program Skeleton
.model small
.stack 100H • Select a memory model
.data • Define the stack size
;declarations • Declare variables
.code • Write code
main proc – organize into procedures
;code • Mark the end of the
main endp source file
;other procs – optionally, define the
end main entry point

Instruction Set of 8086
• An instruction is a binary pattern designed
inside a microprocessor to perform a specific
function.
• The entire group of instructions that a
microprocessor supports is called Instruction
Set.
• 8086 has more than 20,000 instructions.

Classification of Instruction Set
• Data Transfer Instructions
• Arithmetic Instructions
• Bit Manipulation Instructions
• Program Execution Transfer Instructions
• String Instructions
• Processor Control Instructions
• These instructions are used to transfer data
from source to destination.
• The operand can be a constant, memory
location, register or I/O port address.

 MOV Des, Src:
 Src operand can be register, memory location or immediate
operand.
 Des can be register or memory operand.
 Both Src and Des cannot be memory location at the same
time.
 E.g.:
 MOV CX, 037A H
 MOV AL, BL
 MOV BX, [0301 H]

 PUSH Operand:
 It pushes the operand into top of stack.
 E.g.: PUSH BX
 POP Des:
 It pops the operand from top of stack to Des.
 Des can be a general purpose register, segment register
(except CS) or memory location.
 E.g.: POP AX
• XCHG Des, Src:
– This instruction exchanges Src with Des.
– It cannot exchange two memory locations directly.
– E.g.: XCHG DX, AX

• IN Accumulator, Port Address:
– It transfers the operand from specified port to accumulator
register.
– E.g.: IN AX, 0028 H
• OUT Port Address, Accumulator:

– It transfers the operand from accumulator to specified port.
– E.g.: OUT 0028 H, AX

• LEA Register, Src:
– It loads a 16-bit register with the offset
address of the data specified by the Src.
– E.g.: LEA BX, [DI]
• This instruction loads the contents of DI (offset)
into the BX register.

• LDS Des, Src:
– It loads 32-bit pointer from memory source to
destination register and DS.
– The offset is placed in the destination register and the
segment is placed in DS.
– To use this instruction the word at the lower memory
address must contain the offset and the word at the
higher address must contain the segment.
– E.g.: LDS BX, [0301 H]
• LES Des, Src:
– It loads 32-bit pointer from memory source to
destination register and ES.
– The offset is placed in the destination register and
the segment is placed in ES.
– This instruction is very similar to LDS except that it
initializes ES instead of DS.
– E.g.: LES BX, [0301 H]
• LAHF:
– It copies the lower byte of flag register to AH.
• SAHF:
– It copies the contents of AH to lower byte of flag register.
• PUSHF:
– Pushes flag register to top of stack.
• POPF:
– Pops the stack top to flag register.

• ADD Des, Src:
– It adds a byte to byte or a word to word.
– It effects AF, CF, OF, PF, SF, ZF flags.
– E.g.:
• ADD AL, 74H
• ADD DX, AX
• ADD AX, [BX]

• ADC Des, Src:
– It adds the two operands with CF.
– E.g.:
• ADC AL, 74H
• ADC DX, AX
• ADC AX, [BX]

• SUB Des, Src:
– It subtracts a byte from byte or a word from word.
– For subtraction, CF acts as borrow flag.
– E.g.:
• SUB AL, 74H
• SUB DX, AX
• SUB AX, [BX]
• SBB Des, Src:
– It subtracts the two operands and also the borrow
from the result.
– E.g.:
• SBB AL, 74H
• SBB DX, AX
• SBB AX, [BX]
• INC Src:
– It increments the byte or word by one.
– The operand can be a register or memory
location.
– It effects AF, OF, PF, SF, ZF flags.
– CF is not effected.
– E.g.: INC AX
• DEC Src:
– It decrements the byte or word by one.
location.
– It effects AF, OF, PF, SF, ZF flags.
– CF is not effected.
– E.g.: DEC AX
• AAA (ASCII Adjust after Addition):
– The data entered from the terminal is in ASCII format.
– In ASCII, 0 – 9 are represented by 30H – 39H.
– This instruction allows us to add the ASCII codes.
– This instruction does not have any operand.
• Other ASCII Instructions:
– AAS (ASCII Adjust after Subtraction)
– AAM (ASCII Adjust after Multiplication)
– AAD (ASCII Adjust Before Division)

• DAA (Decimal Adjust after Addition)
– It is used to make sure that the result of adding two
BCD numbers is adjusted to be a correct BCD number.
– It only works on AL register.
• DAS (Decimal Adjust after Subtraction)
– It is used to make sure that the result of subtracting
two BCD numbers is adjusted to be a correct BCD
number.
– It only works on AL register.
• NEG Src:
– It creates 2’s complement of a given
number.
– That means, it changes the sign of a
number.

• CMP Des, Src:
– It compares two specified bytes or words.
– The Src and Des can be a constant, register or memory
location.
– Both operands cannot be a memory location at the
same time.
– The comparison is done simply by internally
subtracting the source from destination.
– The value of source and destination does not change,
but the flags are modified to indicate the result.
• MUL Src:
– It is an unsigned multiplication instruction.
– It multiplies two bytes to produce a word or two words to
produce a double word.
– AX = AL * Src
– DX : AX = AX * Src
– This instruction assumes one of the operand in AL or AX.
– Src can be a register or memory location.
• IMUL Src:
– It is a signed multiplication instruction.
• DIV Src:
– It is an unsigned division instruction.
– It divides word by byte or double word by word.
– The operand is stored in AX, divisor is Src and the
result is stored as:
• AH = remainder AL = quotient
• IDIV Src:
– It is a signed division instruction.

• CBW (Convert Byte to Word):
– This instruction converts byte in AL to word in AX.
– The conversion is done by extending the sign bit of AL
throughout AH.
• CWD (Convert Word to Double Word):
– This instruction converts word in AX to double word in
DX : AX.
– The conversion is done by extending the sign bit of AX
throughout DX.
Bit Manipulation Instructions
• These instructions are used at the bit level.
• These instructions can be used for:
– Testing a zero bit
– Set or reset a bit
– Shift bits across registers

• NOT Src:
– It complements each bit of Src to produce 1’s
complement of the specified operand.
location.

• AND Des, Src:
– It performs AND operation of Des and Src.
– Src can be immediate number, register or memory
location.
– Des can be register or memory location.
– Both operands cannot be memory locations at the
same time.
– CF and OF become zero after the operation.
– PF, SF and ZF are updated.
• OR Des, Src:
– It performs OR operation of Des and Src.
location.
same time.
• XOR Des, Src:
– It performs XOR operation of Des and Src.
location.
same time.
• SHL Des, Count:
– It shift bits of byte or word left, by count.
– It puts zero(s) in LSBs.
– MSB is shifted into carry flag.
– If the number of bits desired to be shifted is 1, then
the immediate number 1 can be written in Count.
– However, if the number of bits to be shifted is more
than 1, then the count is put in CL register.
• SHR Des, Count:
– It shift bits of byte or word right, by count.
– It puts zero(s) in MSBs.
– LSB is shifted into carry flag.
– If the number of bits desired to be shifted is 1, then
the immediate number 1 can be written in Count.
– However, if the number of bits to be shifted is more
than 1, then the count is put in CL register.
• ROL Des, Count:
– It rotates bits of byte or word left, by count.
– MSB is transferred to LSB and also to CF.
– If the number of bits desired to be shifted is 1,
then the immediate number 1 can be written in
Count.
– However, if the number of bits to be shifted is
more than 1, then the count is put in CL register.
• ROR Des, Count:
– It rotates bits of byte or word right, by count.
– LSB is transferred to MSB and also to CF.
– If the number of bits desired to be shifted is 1,
then the immediate number 1 can be written in
Count.
– However, if the number of bits to be shifted is
more than 1, then the count is put in CL register.
Program Execution Transfer Instructions
• These instructions cause change in the
sequence of the execution of instruction.
• This change can be through a condition or
sometimes unconditional.
• The conditions are represented by flags.

• CALL Des:
– This instruction is used to call a subroutine or function
or procedure.
– The address of next instruction after CALL is saved
onto stack.
• RET:
– It returns the control from procedure to calling
program.
– Every CALL instruction should have a RET.
• JMP Des:
– This instruction is used for unconditional jump
from one place to another.
• Jxx Des (Conditional Jump):

– All the conditional jumps follow some conditional
statements or any instruction that affects the flag.

Conditional Jump Table
Mnemonic Meaning Jump Condition
JA Jump if Above CF = 0 and ZF = 0
JAE Jump if Above or Equal CF = 0
JB Jump if Below CF = 1
JBE Jump if Below or Equal CF = 1 or ZF = 1
JC Jump if Carry CF = 1
JE Jump if Equal ZF = 1
JNC Jump if Not Carry CF = 0
JNE Jump if Not Equal ZF = 0
JNZ Jump if Not Zero ZF = 0
JPE Jump if Parity Even PF = 1
JPO Jump if Parity Odd PF = 0
JZ Jump if Zero ZF = 1
• Loop Des:
– This is a looping instruction.
– The number of times looping is required is placed
in the CX register.
– With each iteration, the contents of CX are
decremented.
– ZF is checked whether to loop again or not.

String Instructions
• String in assembly language is just a
sequentially stored bytes or words.
• There are very strong set of string instructions
in 8086.
• By using these string instructions, the size of
the program is considerably reduced.

String Instructions
• CMPS Des, Src:
– It compares the string bytes or words.
• SCAS String:
– It scans a string.
– It compares the String with byte in AL or with
word in AX.
String Instructions
• MOVS / MOVSB / MOVSW:
– It causes moving of byte or word from one string
to another.
– In this instruction, the source string is in Data
Segment and destination string is in Extra
Segment.
– SI and DI store the offset values for source and
destination index.

String Instructions
• REP (Repeat):
– This is an instruction prefix.
– It causes the repetition of the instruction until CX
becomes zero.
– E.g.: REP MOVSB STR1, STR2
• It copies byte by byte contents.
• REP repeats the operation MOVSB until CX becomes
zero.
Processor Control Instructions
• These instructions control the processor itself.
• 8086 allows to control certain control flags
that:
– causes the processing in a certain direction
– processor synchronization if more than one
microprocessor attached.

• STC:
– It sets the carry flag to 1.
• CLC:
– It clears the carry flag to 0.
• CMC:
– It complements the carry flag.
• STD:
– It sets the direction flag to 1.
– If it is set, string bytes are accessed from higher
memory address to lower memory address.
• CLD:
– It clears the direction flag to 0.
– If it is reset, the string bytes are accessed from lower
memory address to higher memory address.
Stack and Subroutines
The Stack
• The stack is an area of memory identified by the programmer
for temporary storage of information.
• The stack is a LIFO structure.
• – Last In First Out.
• The stack normally grows backwards into memory.
– In other words, the programmer defines the
bottom of the stack and the stack grows up
into reducing address range.

• Given that the stack grows backwards into memory, it is customary to
place the bottom of the stack at the end of memory to keep it as far
away from user programs as possible.
• In the 8085, the stack is defined by setting the SP (Stack Pointer)
register.
• LXI SP, FFFFH
• This sets the Stack Pointer to location FFFFH (end of memory for the
8085).
• The Size of the stack is limited only by the available memory
Saving Information on the Stack

• Information is saved on the stack by PUSHing it on.
– It is retrieved from the stack by POPing it off.
• The 8085 provides two instructions: PUSH and POP for storing
information on the stack and retrieving it back.
– Both PUSH and POP work with register pairs ONLY.
The PUSH Instruction
• PUSH B (1 Byte Instruction)
– Decrement SP
– Copy the contents of register B to the memory location pointed to by
SP
– Decrement SP
– Copy the contents of register C to the memory location pointed to by
SP
B C
12 F3
FFFB
FFFC
FFFD F3
FFFE
12
FFFF SP

The POP Instruction
• POP D (1 Byte Instruction)
– Copy the contents of the memory location
pointed to by the SP to register E
– Increment SP
pointed to by the SP to register D
– Increment SP
D E
12 F3
FFFB
FFFC
FFFD F3 SP
FFFE
FFFF
12

Operation of the Stack
• During pushing, the stack operates in a “decrement then store”
style.
– The stack pointer is decremented first, then the information is
placed on the stack.
• During poping, the stack operates in a “use then increment” style.

– The information is retrieved from the top of the the stack and then the
pointer is incremented.
• The SP pointer always points to “the top of the stack”.
LIFO
• The order of PUSHs and POPs must be opposite of each other in order to retrieve
information back into its original location.
PUSH B
PUSH D
... • Reversing the order of the POP instructions will result in
POP D the exchange of the contents of BC and DE.
POP B
The PSW Register Pair
• The 8085 recognizes one additional register pair
called the PSW (Program Status Word).
– This register pair is made up of the Accumulator
and the Flags registers.
• It is possible to push the PSW onto the stack, do

whatever operations are needed, then POP it off
of the stack.
– The result is that the contents of the
Accumulator and the status of the Flags are
returned to what they were before the
operations were executed.

PUSH PSW Register Pair
• PUSH PSW (1 Byte Instruction)
– Decrement SP
– Copy the contents of register A to the memory
location pointed to by SP
– Decrement SP
– Copy the contents of Flag register to the
memory location pointed to by SP
A Flag
12 80
FFFB
FFFC
FFFD 80
FFFE
12
FFFF SP

Pop PSW Register Pair
• POP PSW (1 Byte Instruction)
pointed to by the SP to Flag register
– Increment SP
pointed to by the SP to register A
– Increment SP
A Flag
12 80
FFFB
FFFC
FFFD 80 SP
FFFE
FFFF
12

Modify Flag Content using PUSH/POP
• Let, We want to Reset the Zero Flag
• 7 6 5 4 3 21 0
• 8085 Flag : S | Z | X |AC|X |P |X |Cy
• Program:
– LXI SP FFFF
– PUSH PSW
– POP H
– MOV A L
– ANI BFH (BFH= 1011 1111) * Masking
– MOV L A
– PUSH H
– POP PSW

Subroutines
• A subroutine is a group of instructions that will be used
repeatedly in different locations of the program.
– Rather than repeat the same instructions several times, they
can be grouped into a subroutine that is called from the different
locations.
• In Assembly language, a subroutine can exist anywhere in the
code.
– However, it is customary to place subroutines separately from
the main program.
• The 8085 has two instructions for dealing with subroutines.
– The CALL instruction is used to redirect program execution to
the subroutine.
– The RET insutruction is used to return the execution to
the calling routine.

The CALL Instruction
• CALL 4000H (3 byte instruction)
– When CALL instruction is fetched, the MP
knows that the next two Memory location
contains 16bit subroutine address in the
memory.
2000 CALL 4000
2003
4 0 00 [W] [Z]Register
PC 2 0 03
FFFB
FFFC
FFFD 03
FFFE
FFFF
20 SP

The CALL Instruction
– MP Reads the subroutine address from the next
two memory location and stores the higher order
8bit of the address in the W register and stores
the lower order 8bit of the address in the Z
register
– Pushe the address of the instruction
immediately following the CALL onto the stack
[Return address]
– Loads the program counter with the 16-bit
address supplied with the CALL instruction from
WZ register.

The RET Instruction
• RET (1 byte instruction)
– Retrieve the return address from the top of
the stack
– Load the program counter with the return
address.
PC 2 0 03
FFFB
4014 ... FFFC
4015 RET FFFD 03 SP
FFFE
FFFF
20

Things to be considered in Subroutine
• The CALL instruction places the return address at the two memory
locations immediately before where the Stack Pointer is pointing.
– You must set the SP correctly BEFORE using the CALL instruction.
• The RET instruction takes the contents of the two memory locations at
the top of the stack and uses these as the return address.
– Do not modify the stack pointer in a subroutine.
You will loose the return address.
• Number of PUSH and POP instruction used in the subroutine must be

same, otherwise, RET instruction will pick wrong value of the return
address from the stack and program will fail.

Passing Data to a Subroutine
• Data is passed to a subroutine through registers.
– Call by Reference:
• The data is stored in one of the registers by the calling program and the
subroutine uses the value from the register. The register values get modified within
the subroutine. Then these modifications will be transferred back to the calling
program upon returning from a subroutine
– Call by Value:
• The data is stored in one of the registers, but the subroutine first PUSHES register
values in the stack and after using the registers, it POPS the previous values of the
registers from the stack while exiting the subroutine.
i.e. the original values are restored before execution returns to the calling
program.
• The other possibility is to use agreed upon memory locations.
– The calling program stores the data in the memory location and the subroutine
retrieves the data from the location and uses it.

Cautions with PUSH and POP
• PUSH and POP should be used in opposite
order.
• There has to be as many POP‟s as there are

PUSH‟s.
– If not, the RET statement will pick up the wrong
information from the top of the stack and the
program will fail.
• It is not advisable to place PUSH or POP inside a

loop.

Conditional CALL and RET Instructions
• The 8085 supports conditional CALL and
conditional RET instructions.
– The same conditions used with conditional
JUMP instructions can be used.
– CC, call subroutine if Carry flag is set.

– CNC, call subroutine if Carry flag is not set
– RC, return from subroutine if Carry flag is set
– RNC, return from subroutine if Carry flag is not
set
– Etc.

A Proper Subroutine
• According to Software Engineering practices, a
proper subroutine:
– Is only entered with a CALL and exited with an
RTE
– Has a single entry point
• Do not use a CALL statement to jump into different points
of the same subroutine.
– Has a single exit point
• There should be one return statement from any
subroutine.

Writing Subroutines
• Write a Program that will display FF and 11 repeatedly on
the seven segment display. Write a „delay‟ subroutine and
Call it as necessary.
C000: LXISP FFFF

Program Transfer
C003: MVIA FF
C005: OUT 00
C007: CALL 14 20
C00A: MVIA 11
C00C: OUT 00
C00E: CALL 14 20
C011: JMP 03 C0
DELAY: C014: MVIB FF
C016: MVIC FF
C018: DCR C
C019: JNZ 18 C0
C01C: DCR B
C01D: JNZ 16 C0
C020: RET

8086 Microprocessor Interrupts
 When your phone rings during a lecture, what will happen?
 When you are studying then your cell phone rings – what will you do?
When you finish talking on the phone then you will continue with
your study
 Now your phone rings again and someone also knocking at your door
then what will you do?
When being interrupted, you will perform some pre-defined action
Interrupt has priority – some interrupt is more important than the

others. For example, asking your phone is more important than opening
the door Dept. of ECE, ATMECE, MYSURU 140
Introduction
 An interrupt is used to cause a temporary halt in the execution of
program.
 The meaning of ‘interrupts’ is to break the sequence of operation.
 While the Microprocessor is executing a program, an ‘interrupt’

breaks the normal sequence of execution of instructions, diverts
its execution to some other program called Interrupt Service
Routine (ISR).
After executing ISR, IRET returns the control back again to the
main program. Interrupt processing is an alternative to polling.
Need for Interrupt:
 Interrupts are particularly useful when interfacing
I/O devices, that provide or require data at
relatively low data transfer rate.
Sources of Interrupts:
Three types of interrupts sources are there:
1. An external signal applied to NMI or INTR input pin( hardware
interrupt)
2. Execution of Interrupt instruction( software interrupt)
3. Interrupt raised due to some error condition produced in 8086
instruction execution process. ( divide by zero, overflow errors
etc) Dept. of ECE, ATMECE, MYSURU 142
Use of interrupt
How to get key typed in the keyboard or a keypad?
 Polling :-
The CPU executes a program that check for the available of
data If a key is pressed then read the data, otherwise keep waiting
or looping!!!
 Interrupt:-
The CPU executes other program, as soon as a key is pressed,
the Keyboard generates an interrupt. The CPU will response to the
interrupt – read the data. After that returns to the original program.
So by proper use of interrupt, the CPU can serve many devices at the
“same time”
Polling Vs Interrupt
The keyboard controller can hold only a single keystroke.
Therefore, the keyboard controller must be freed before the next
keystroke arrives.
The keystroke is passed to the CPU by putting it in the
keyboard buffer. So, the keyboard controller keeps on passing the
keystroke input to the CPU,
but how does the CPU attend to it?

The CPU is not at the disposal of the keyboard controller; it is
usually busy doing several other operations. So, we need
some mechanism to indicate to the CPU that a keystroke has
arrived. How is this done? There are two approaches to making
sure that the CPU pays attention:
Polling-based
Interrupt-based
Example: Polling Vs Interrupt
Keystroke causes interrupt

Polling
Figure 2: Polling-based interrupt handling
 The CPU executes a program that check for the

available of data If a key is pressed then read the data,
otherwise keep waiting or
Dept. of ECE, looping!!!
ATMECE, MYSURU 146
Keystroke passed to the CPU
No Dept.
keystroke for CPU
of ECE, ATMECE, MYSURU 147
Interrupt-based systems
Interrupt-based approach
 The CPU executes other program, as soon as a key is
pressed, the Keyboard generates an interrupt. The CPU
will response to the interrupt – read the data. After
that returns to the original program. So by proper use
of interrupt, the CPU can serve many devices at the
“same time” Dept. of ECE, ATMECE, MYSURU 148
Example of interrupt
 How to control a robot that has sensors to detect

obstacles and makes a turn
Controlling a robot by using Polling & Interrupt

 Polling
 Move forward in a pre-defined unit
 Check sensor reading
 Do nothing if no obstacle or turn if obstacle detected
 Loop back and move forward again
 Interrupt
 Keeping moving until interrupted by the sensor
 Interrupt received then do pre-defined operation
 After finishing the interrupt service return to normal
operation i.e keep moving forward again

Polling Vs Interrupt Control of a robot
Move forward
Move forward
Check sensor
Y
Stop or turn interrupt

INTERRUPT VECTOR TABLE

8086 INTERRUPT TYPES
256 INTERRUPTS OF 8086 ARE DIVIDED IN TO 3 GROUPS
1. TYPE 0 TO TYPE 4 INTERRUPTS-

These Are Used For Fixed Operations And Hence Are Called
Dedicated Interrupts
2. TYPE 5 TO TYPE 31 INTERRUPTS

Not Used By 8086,reserved For Higher Processors Like 80286
80386 Etc
3. TYPE 32 TO 255 INTERRUPTS

Available For User, called User Defined Interrupts These Can
Be H/W Interrupts And Activated Through Intr Line Or Can Be
S/W Interrupts. Dept. of ECE, ATMECE, MYSURU 195
Type – 0 Divide Error Interrupt
Quotient Is Large Cant Be Fit In Al/Ax Or Divide By Zero
Type –1 Single Step Interrupt
Used For Executing The Program In Single Step Mode By Setting Trap Flag
To Set Trap Flag PUSHF
MOV BP,SP
OR [BP+0],0100H;SET BIT8
POPF
Type – 2 Non Maskable Interrupt
This Interrupt Is Used For Executing Isr Of Nmi Pin (Positive Egde Signal). Nmi
Cant Be Masked By S/W
Type – 3 Break Point Interrupt
Used For Providing Break Points In The Program
Type – 4 Over Flow Interrupt
Used To Handle Any Overflow Error After Signed Arithmetic
PRIORITY OF INTERRUPTS
Interrupt Type Priority
INT0, INT3-INT 255, Highest
NMI(INT2)
INTR
SINGLE STEP Lowest

DOS interrupts
INT 21h is provided by DOS. When MS-DOS is loaded into the
computer, INT 21H can be invoked to perform some extremely useful
functions. These functions are commonly referred to as DOS INT 21H
function calls. Data input and output through the keyboard and
monitor are the most commonly used functions. Below are two
examples that use DOS interrupts.
1. Display the message defined with variable DATA_ASC DB ‘the

earth is but one country’,’$’
MOV AH,09 ;option 9 to display string of data
MOV DX, OFFSET DATA_ASC ;DX= offset address of data
INT 21H ; invoke the interrupt
2. Inputting a single character, with echo.
MOV AH, 01 ;option 01 to input one character
INT 21H ;invoke the interrupt
DOS (Disk Operating System) Interrupts
1. Function Call 01: Read The Key Board
Input Parameter Ah = 01 Read A Character From Keyboard.
Echo It On CRO Screen and Return The ASCII Code Of The Key
Pressed in Al Output Parameter: Al = ASCII Code Of Character
2. Function Call 02h: Display On CRT Screen
Input Parameter: Ah = 02
Dl = ASCII Character To Be Displayed On CRT Screen
3. Function Call 03: Read Character From Com1
Input Parameter: Ah = 03h
Function: Reads Data From Com Port
Output Parameter: Al = ASCII Code Of Character
4. Function Call 04: Write Character To Com1
Input Parameter: Ah = 04h Dl = ASCII Code Of Character To
Be Transmitted
Function: Writes DataDept.To Com
of ECE, Port
ATMECE, MYSURU 200
DOS INTERRUPTS
5. Function Call 05: Write To Lpt1
Input Parameter: Al = 05H
Dl = Ascii Code Of Character To Be Printted
Function: Print The Character Available In Dl On Printer Attached To Lpt1
6. Function Call 09: Display A Character String

Input Parameter: Ah = 09,ds:dx= Address Of Character String
Function: Displays The Characters Available In The String To Crt Till A $
7. Function Call 0ah: Buffered Key Board Input

Input Parameter: Ah = 0ah
Ds:dx = Address Of Keyboard Input Buffer
Function: The ASCII Codes Of The Characters Received From Keyboard

Are Stored In Keyboard Buffer From 3rd Byte. 1st Byte Of Buffer =
Size Of Buffer Upto 255. It Receives The Characters Till
Specified No.Of Characters Are Received Or Enter Key
Is Presses Which Ever Is Earlier
BIOS interrupt
INT 10H subroutines are burned into the ROM BIOS of the
8086 based and compatibles and are used to communicate with the
computer user screen video. Much of the manipulation of screen text
or graphics is done through INT 10H. Among them are changing the
color of characters or background, clearing screen, and changing the
locations of cursor. Below are two examples that use BIOS interrupts.
1. Clearing the screen:
MOV AX, 0600H ;scroll entire screen
MOV BH, 07 ;normal attribute
MOV CX, 0000 ;start at 00,00
MOV DX, 184FH ;end at 18, 4F
INT 10H ;invoke the interrupt
BIOS (Basic Input/output System) INTERRUPTS
INT 10h:Video Service Interrupt
It Controls The Video Display
(a) Function Call 00: Select Video Mode
Input Parameter: Al = Mode Number
Ah = 00h
Function: It Changes The Display Mode And Clears The Screen
Al = 00 40 X 25 Black And White
Al = 04 320 X 200 Color
Al = 10h 640 X 350 X 16 Color
(b) FUNCTION CALL 03: READ CURSOR POSITION
Input Parameter: Ah = 03
Bh = Page Number
Function: Reads Cursor Position On Screen
Output Parameters: Ch = Starting Line
Cl = Ending Line
Dh = Current Row
Dl = Current Column
BIOS INTERRUPTS
( C) Function Call 0E:Write Character On CRT Screen And Advance Cursor

Input Parameter:Ah = 0eh
Al = ASCII Code Of The Character
Bh = Page(text Mode)
Bl = Color(graphics)
Function: Display Character Available In Al On Screen
INT 11h: Determine The Type Of Equipment Installed. Register Ax Should Contain
FFFFh And Instruction INT 11h To Be Executed. On Return, Register Ax Will
Indicate The Equipments Attached To Computer
INT14h: Control The Serial Communication Port Attached To The Computer. Ah
Should Contain The Function Call
(a) Function Call 00:initialize The Com Port
(b) Function Call 01: Send A Character
(c) Function Call 02:receive A Character
INT 16h: Keyboard Interrupt
Ah Should Contain The Function Call
(a) Function Call 00: Read Keyboard Character, It Will Return Ascii Code Of The
Character
(b) Function Call 01: Get Key Board Status
Strings, Procedures and Macros
Objective

Outline
• The 8086 String instructions
• Moving a String
• Using compare string byte to check password
• Writing and using procedures
• The CALL and RET instructions
• The 8086 Stack
• Using PUSH and POP
• Passing parameters to and from procedures
• Writing and debugging program containing procedures
• Reentrant and Recursive procedures
• Writing and Calling Far procedures
• Accessing a procedure
• Writing and using Assembler Macros
• Comparison Macros and Procedures
• Defining and calling a Macro without parameters
• Passing parameters to Macros
The 8086 String instructions
• A string is the series of bytes stored in

successive memory locations.
• Word processor or text editor programs can
be used to create strings.
• These programs have facility to search
through the text.

Moving a String(contd.)
• Definition:
• You have a string of ASCII characters in successive
memory locations in data segment, and you want to
move the string to some new location in the data
segment.
• Basic pseudo code:
REPEAT
MOVE BYTE FROM SOURCE STRING
TO DESTINATION STRING
UNTIL ALL BYTES MOVED
Moving a String(contd.)
• The basic pseudo code doesn’t help much in understanding
how the algorithm will be implemented.
• Expanded code:
INITIALIZE SOURCE POINTER, SI
INITIALIZE DESTINATION POINTER, DI
INITIALIZE COUNTER, CX
REPEAT
COPY BYTE FROM SOURCE TO DESTINATION
INCREMENT SOURCE POINTER
INCREMENT DESTINATION POINTER
DECREMENT COUNTER
UNTIL COUNTER=0
Using compare string byte to check
password(contd.)
• Definition:
– We want to compare a user entered password to
the correct password stored in the memory. If the
passwords do not match we want to sound an
alarm and If the passwords matches we will allow
access to computer for that user.
• Need:
– REPEAT-UNTIL
– Compare String instruction CMPS

Using
compare
string byte
to check
password-
flowchart


Using compare string byte to check
password - Code
• Code:
INITIALIZE PORT DEVICE FOR OUTPUT
INTIALIZE SOURCE POINTER-SI
INITALIZE DESTINATION POINTER-DI
INITIALIZE COUNTER-CX
REPEAT
COMPARE SOURCE BYTE WITH DESTINATION BYTE
INCREMENT SOURCE POINTER
INCREMENT DESTINATION POINTER
DECREMENT COUNTER
UNTIL (STRING BYTES NOT EQUAL) OR (CX=0)
IF STRING BYTES NOT EQUAL THEN
SOUND ALARM
STOP
ELSE DO NEXT MAINLINE INSTRUCTION
Writing and using procedures
• Avoid writing the same sequence of

instruction again and again.
• Write it in a separate subprogram and call that

subprogram whenever necessary.
• For that CALL instruction is used.

The CALL and RET instructions(contd.)
The CALL Instruction:
• Stores the address of the next instruction to
be executed after the CALL instruction to
stack. This address is called as the return
address.
• Then it changes the content of the instruction
pointer register and in some cases the content
of the code segment register to contain the
starting address of the procedure.

Chart for CALL

and RET
instruction 

Types of CALL instructions:
• DIRECT WITHIN-SEGMENT NEAR CALL: produce the starting address
of the procedure by adding a 16-bit signed displacement to the
contents of the instruction pointer.
• INDIRECT WITHIN-SEGMENT NEAR CALL: the instruction pointer is
replaced with the 16-bit value stored in the register or memory
location.
• THE DIRECT INTERSEGMENT FAR CALL: used when the called
procedure is in different segment. The new value of the instruction
pointer is written as bytes 2 and 3 of the instruction code. The low
byte of the new IP value is written before the high byte.
• THE INDIRECT INTERSEGMENT FAR CALL: replaces the instruction
pointer and the contents of the segment register with the two 16-
bit values from the memory.

The CALL and RET instructions
The 8086 RET instruction:
• When 8086 does near call it saves the
instruction pointer value after the CALL
instruction on to the stack.
• RET at the end of the procedure copies this
value from stack back to the instruction
pointer (IP).

The 8086 Stack
• Section of memory you
set aside for storing
return addresses.
• Also used to store the
contents of the
registers for the calling
program while a
procedure executes.
• Hold data or address
that will be acted upon
by procedures.

Using PUSH and POP
• The PUSH register/memory instruction decrements the
stack pointer by 2 and copies he contents of the
specified 16-bit register or memory location to
memory at the new top-of-stack location.
• The POP register/memory instruction copies the word
on the top-of-stack to the specified 16-bit register or
memory location and increments the stack pointer by
2.

Passing parameters to and from
procedures
Major ways of passing parameters to and from a
procedure:
• In register
• In dedicated memory locations accessed by
name
• With pointers passed in registers
• With the stack

Writing and debugging programs
containing procedures
• Carefully workout the overall structure of the
program and break it down into modules which
can easily be written as procedures.
• Simulate each procedure with few instructions
which simply pass test values to the mainline
program. This is called as dummy or stubs.
• Check that number of PUSH and POP operations
are same.
• Use breakpoints before CALL, RET and start of the
program or any key points in the program.
Reentrant and Recursive procedures
• Reentrant procedures: The procedure which

can be interrupted, used and “reentered”
without losing or writing over anything.
• Recursive procedure: It is the procedure

which call itself.

Writing and Calling Far procedures
• It is the procedure that is located in a segment
which has different name from the segment
containing the CALL instruction.

Accessing Procedure
Accessing a procedure in another segment
• Put mainline program in one segment and all the
procedures in different segment.
• Using FAR calls the procedures can accessed as discuss
above.
Accessing procedure and data in separate assembly module
• Divide the program in the series of module.
• The object code files of each module can be linked
together.
• In the module where variables or procedures are declared,
you must use PUBLIC directive to let the linker know that it
can be accessed from other modules.
• In a module which calls procedure or accesses a variable in
another module, you must use the EXTERN directive.

Writing and using Assembler Macros

Comparison Macros and Procedures
• A big advantage of using procedures is that the
machine codes for the group of instruction in the
procedures needs to be loaded in to main memory
only once.
• Disadvantage using the procedures is the need for the
stack.
• A macro is the group of instruction we bracket and give
a name to at the start of the program.
• Using macro avoids the overhead time involved in
calling and returning from a procedures.
• Disadvantage is that this will make the program take up
more memory than using a procedure.

Defining and calling a Macro without
parameters

Passing parameters to Macros
• The words
NUMBER, SOURCE
and DESTINATION
are called as the
dummy variables.
When we call the
macro, values from
the calling
statements will be
put in the
instruction in place
of the dummies.

Time Delay programs of 8086
Writing Time Delay Programs
Every instruction in the 8086 requires a definite number of
clock cycles for its execution. The amount of time for
execution of an instruction is obtained by multiplying the
number of clock cycles required for the execution the
instruction, with the clock period at which the 8086 is
running.

The steps for writing a time delay program are as follows:
(i) Find the exact time delay (td) required for the given application.
(ii) Select the instructions to be included in the time delay program. While selecting the instructions and
registers to be used in the delay program, care must be taken that the execution of these instructions
does-not affect the main program execution. That is, any memory location or register used by the main
program must not be altered by time delay program. If a register used in the main program is needed in
the delay program, the content of that register is pushed into a stack before executing the time delay
program. At the end of the execution of the time program, its original value will be popped from the
stack and then control will be transferred to the main program.
(iii) Find the period of the clock at which the microprocessor is running by taking the reciprocal of the
8086‟s clock frequency. T is the duration of one clock period of clock state.
(iv) Find the number of clock states required for execution of each of the instructions in the time-delay
program. Then find the number of clock states (m) needed to execute the loop in the delay program
once, by adding the clock states required for each instruction in the delay program.
(v) Find the number of times (i.e., count n) the loop in the delay program has to be executed by dividing
the required time delay (td) by the time taken to execute the loop once, which is m X T
Count (n) = td/ (m X T)
The time delay obtained using this method is sufficiently accurate to be used in many problems. When
more accurate delays are required, the programmable timer IC 8253 or the 8254 can be used.

Example: Write a time delay program to generate a delay of
120ms in an 8086 – based system that runs on a 10Mhz
frequency clock.
Solution:
The time delay program is as follows:
Instruction T-states for execution

MOV BX, Count 4
L1: DEC BX 2
NOP 3
JNZ L1 16
RET 8
In this program, the instructions DEC BX, NOP, and JNZ L1 form the loop
as they are executed repeatedly until BX becomes zero. Once BX
becomes zero, the 8086 returns to the main program.

120ms in an 8086 – based system that runs on a 10Mhz frequency
clock.
Solution (continued):
Number of clock cycles for execution of the loop once
(m) = 2 + 3 + 16 = 21
Time required for the execution of loop once = m X T =
21 X 1/(10 X 10^6)
= 2.1 µs
Count = td/(m X T) = 120 X 10^-3 /(2.1 X 10^-6)
= 57143 = DF37h
By loading DF37h in BX, the time taken to execute the delay program is
approximately 120ms. The NOP included in the delay program is to
increase the execution time of the loop. To get more delay, the number of
NOP instructions in the delay loop can be increased. The exact delay
obtained using this time delay subroutine can be calculated as shown in
the next slide.

120ms in an 8086 – based system that runs on a 10Mhz frequency
clock.
Solution (continued):
The MOV BX, Count
& RET instructions in the delay program are executed only once. The JNZ
instruction takes 16 T-states when the condition is satisfied (i.e. Z = 0)
and four T – states when the condition is not satisfied, which occurs only
once.
Exact delay = [4 x 0.1 + (2+3) x 57143 x 0.1 + 16 x 57142 x0.1 + 4 X

0.1 + 8 X 0.1 ] µs
= 0.4 + 28571.5 + 91427.2 + 0.4 + 0.8

= 120000.3 µs = 120.0003 ms
The error in the previous calculation is very less as the exact delay is also
very close to 120ms. When 16-bit count register is used in the delay
program, the maximum count value that can be loaded in it is FFFFh. This
may put a limitation on the maximum time delay that can be generated
using the above delay subroutine.

Example: Write a delay program to create a time delay of 240ms.
Assume that 5Mhz clock is used with 8086. Following is given:
Instruction No. of T-states

MOV BX, Immediate 4
DEC Register 2
NOP 3
JNZ Label 16
RET 8
Solution: td = 240 X 10^-3 seconds

One T-state time period = 1/(5 X 10^-6) sec
= 0.2 µs
No. of T-states in one loop , m = 21
No. of times to run the loop, Count =
(240 X 10^-3)/ (0.2 X 10^-6 X 21) = 57143D
= DF37h

Example: Write a delay program to create a time delay of
240ms. Assume that 5Mhz clock is used with 8086. Following
is given:
Solution(continued):
;Description ;No of T-states
MOV BX, DF37h 4
NEXT DEC BX 2
NOP 3
JNZ NEXT 16
RET 8
The exact delay = (Generated Delay) + (4+8 –

12)*0.2µs = approximately the same !

Self Practice Problem: Write a delay program to create a time
delay of five minutes. Assume that a 10 Mhz clock is used with
8086. Given that
Instruction No. of T-states
MOV BX, Immediate 4
DEC Register 2
NOP 3
JNZ Label 16
RET 8

Assembler Directives
• An assembler is a program that is used to convert an assembly language program
into an equivalent machine language program.
• The assembler finds the address of each label and substitutes the value of each
constant and variable in the assembly language program during the assembly
process, to generate the machine language code.
• While performing these operations, the assembler may find syntax errors. They
are reported to the programmer at the end of the assembly process. The logical
and other programming errors are not found by the assembler.
• For completing these tasks the assembler needs some commands from the
programmer – the required storage class for a particular constant or a variable
such as byte, word, or double word, the logical name of the segments such as
CODE, STACK, or DATA, the type of procedures or routines such as FAR,
NEAR, PUBLIC, or EXTRN, the end of a segment etc.
• These types of commands are given to the assembler using a predefined
alphabetical strings called Assembler directives.
• Assembler directives are directions for the assembler, and not the instructions for
the 8086.
Assembler Directives for variable and Constant
Definition
The Assembler directives for variable and constant definition are as follows:
(i) DB, DW, DD, DQ, and DT: the directives DB (define byte), DW(define word),
DD(define double word), DQ (define quad word), and DT (define ten bytes) are used to
reserve one byte, one word (i.e. 2 bytes), one double word(i.e. 2 words), one quad
word(i.e. 4 words) and ten bytes in memory, respectively for storing constants,
variables, or strings.
DATA 1 DB 20h ; Reserve one byte for storing
; DATA1 and assign the value 20h
; to it.
ARRAY DB 10h, 20h, 30h ; Reserve three bytes for storing ARRAY1 and
initialize it with the values
; 10h, 20h and 30h
CITY DB “NARELA” ;Store the ASCII code of the characters
; specified within double quotes in the
; array or a list named CITY
DATA2 DW 1020h ; Reserve one word for storing ;DATA2 and Assign
the value 1020 ;to it.
Definition
The directive DUP (duplicate) is used to reserve a series of bytes, words, double words, or ten
bytes and is used with DB, DW, DD and DT, respectively. The reserved area can be either filled
with a specific value or left uninitialized.
Example:
Array DB 20 DUP(0) ;Reserve 20 bytes in the memory
; for the array named ARRAY and
; initialize all the elements of the
; array to 0 (due to presence of 0
; within the bracket near the DUP
; directive
ARRAY1 DB 25 DUP (?) ; Reserve 25 bytes in the memory
; for the array named ARRAY1 and
; keep all the elements of the array
; uninitialized (due to the question
; mark present within the bracket near the DUP
directive)
ARRAY2 DB 50 DUP (64h) ; Reserves 50 bytes in the memory
; for the array named ARRAY2 and
; initializes all the elements of the
; array to 64h
Definition
(ii) EQU: The directive EQU(equivalent) is used to assign a
value to a data name.
Example:
NUMBER EQU 50h ; Assign the value 50h to NUMBER.

NAME EQU “RAMESH” ; Assign the string “RAMESH” to NAME.

Assembler Directives Related to
Code(Program) Location
The Assembler directives related to Code location:
(i) ORG: The ORG (origin) directive directs the assembler to start the memory allocation
for a particular segment (data, code, or stack) form the declared offset address in the
ORG statement. While starting the assembly process for a memory segment, the
assembler initializes a location counter (LC) to keep track of the allotted offset addresses
for the segment. When the ORG directive is not mentioned , LC is initialized with the
offset address 0000h. When the ORG directive is mentioned at the beginning of the
statement, LC is initialized with the offset address specified in the ORG directive.
Example:
ORG 100h
When this directive is placed at the beginning of the code segment, the location counter is
initialized with 0100h and the first instruction is stored from the offset address 0100h within
the code segment. If it is placed in the data segment, the next data storage starts from the
offset address 0100h within the data segment.

(ii) EVEN: The EVEN directive updates the location counter to next even address,
if the current location counter content is not an even number.
Example:
ARRAY2 DW 20 DUP (0)
These statements in a segment declare an array named ARRAY2 having 20
words, starting at an even address. The advantage of storing an array of words
starting at an even address is that the 8086 takes just one memory read/write cycle
to read/write the entire word, if the word is stored starting at an even address.
Otherwise, the 8086 takes two memory read/write cycles to read/write to read/write
the word.
Example: on next slide ..

Example:
EVEN
RESULT PROC NEAR
….. ; Instructions in the
;RESULT Procedure
RESULT ENDP
Here the procedure RESULT, which is of type NEAR, is stored

starting at an even address in the code segment. The ENDP
directive indicates the end of the RESULT procedure.

(iii) LENGTH: This directive is used to determine the length of
an array or string in bytes.
Example:
MOV CX, LENGTH ARRAY
CX is loaded with the number of bytes in the ARRAY.
(iv) OFFSET: This operator is used to determine the offset of

a data item in a segment containing it.
Example:
MOV BX, OFFSET TABLE
If the data item named TABLE is present in the data segment,
this statement places the offset address of TABLE, in the BX
register.
(v) LABEL: The LABEL directive is used to assign a name to the
current value in the location counter. It is used to specify the
destination of the branch-related instructions such as jump and
call. When LABEL is used to specify the destination, it is
necessary to specify whether it is NEAR or FAR. When the
destination is in the same segment, the label is specified as
NEAR and when the destination is in another segment, it is
specified as FAR.
Example:
REPEAT LABEL NEAR

CALCULATE LABEL FAR

8086 Microprocessor

LABEL can also be used to specify a data item. When it is used to specify a data item,
the type of data item must be specified. The data may have the type byte or word.
Example:
A stack segment having 100 words of data is defined using the following statements:
STACK SEGMENT
DW 100 DUP (0) ; Reserve 100 words for
; Stack
STACK_TOP LABEL WORD
STACK ENDS
The second statement reserves 100 words in the stack segment and fills them with 0. The third statement assigns
the name STACK_TOP to the location present just after the hundredth word. The offset address of this label can
then be assigned to the stack pointer in the code segment using the following statement:
MOV SP, OFFSET STACK_TOP

Assembler Directives for Segment
Declaration
The Assembler directives for segment declaration
(i) SEGMENT and ENDS: The SEGMENT and ENDS directives
indicate the start and end of a segment, respectively. In
some cases, the segment may be assigned a type such as
PUBLIC (i.e. , it can be used by other modules of the
program while linking) or GLOBAL (i.e. it can be accessed
by any other module). Example:
CODE 1 SEGMENT
…… ; Instructions of CODE 1 segment
CODE 1 ENDS
This example indicates the declaration of a code segment
named CODE 1.

Declaration
(ii) ASSUME: The ASSUME directive is used to inform the
assembler, the name of the logical segments to be assumed for
different segments used in the program.
ASSUME CS : CODE 1, DS: DATA1
This statement informs the assembler that the segment

address where the logical segments CODE1 and DATA1 are
loaded in memory during execution is to be stored in CS and
DS registers, respectively.

Declaration
(iii) GROUP: This directive is used to form a logical group of segments with a similar
purpose. The Assembler passes information to the linker/loader to form the code, such
that the group declared segments or operands lie within a 64 Kb memory segment. All
such segments can be addressed using the same segment address. Example:
PROGRAM1 GROUP CODE1, DATA1, STACK1
This statement directs the loader/linker to prepare an executable file (.exe) such that the
CODE1, DATA1, and STACK1 segments lie within a 64KB memory segment that is
named PROGRAM1.

Declaration
(iv) SEG: This segment operator is used to decide the segment address of the label,
variable, or procedure and substitute the segment address in place of the SEG label.
Example:
MOV AX, SEG ARRAY1 ; Load the segment address in which ARRAY1
is present, in AX
MOV DS, AX ; Move the contents of AX to DS.

Assembler Directives for declaring
procedures
The Assembler directives for declaring procedures:
(i) PROC : The PROC directive indicates the start of a named procedure. The NEAR
and FAR directive specify the type of the procedure: Example:
SQUARE_ROOT PROC NEAR

This statement indicates the beginning of a procedure named SQUARE_ROOT, which
is to be called by a program located in the same segment. The FAR directive is used for
procedures to be called by the programs present in code segments other than the one in
which this procedure is present. For example, SALARY PROC FAR indicates the
beginning of a FAR type procedure named SALARY.

procedures
(ii) ENDP: The ENDP directive is used to indicate the end of a procedure. To mark the end
of a particular procedure, the name of the procedure may appear as prefix with the directive
ENDP. Example:
SALARY PROC NEAR

…… ; Code of SALARY ;Procedure
SALARY ENDP

procedures
(iii) EXTRN and PUBLIC: The directive EXTRN (external) informs the assembler that the
procedures, label/labels, and names declared after this directive has/have already been defined in
some other segments and in the segments where they actually appear, they must be declared in
public, using the PUBLIC directive. Example:
MODULE1 SEGMENT
PUBLIC SQURE_ROOT
SQUARE_ROOT PROC FAR
…. ; CODE OF SQUARE_ROOT
PROCEDURE
SQUARE_ROOT ENDP
MODULE1 ENDS
; Code continued on next

; slide

procedures
(iii) EXTRN and PUBLIC (continued):
MODULE2 SEGMENT
EXTRN SQUARE_ROOT FAR
…… ; CODE OF MODULE2
CALL SQUARE_ROOT
……
MODULE 2 ENDS
NOTE: If one wants to call the procedure named SQUARE_ROOT appearing in MODULE1 from
MODULE2, it must be declared using the statement PUBLIC SQUARE_ROOT in MODULE1 and it must be
declared external using the statement EXTRN SQUARE_ROOT in MODULE2. If a jump or a call address is
external, it must be represented as NEAR or FAR. If data are defined as external, their size must be
represented as BYTE, WORD, or DWORD.

procedures
(iii) EXTRN and PUBLIC (continued):
MODULE2 SEGMENT
EXTRN SQUARE_ROOT FAR
…… ; CODE OF MODULE2
CALL SQUARE_ROOT
……
MODULE 2 ENDS
NOTE: If one wants to call the procedure named SQUARE_ROOT appearing in MODULE1
from MODULE2, it must be declared using the statement PUBLIC SQUARE_ROOT in MODULE1
and it must be declared external using the statement EXTRN SQUARE_ROOT in MODULE2. If a
jump or a call address is external, it must be represented as NEAR or FAR. If data are defined
as external, their size must be represented as BYTE,
Dept. of ECE, ATMECE, WORD, or DWORD.
MYSURU 255
Other Assembler Directives
PTR The PTR(pointer) operator is used to declare the type of label,
variable, or memory operand.
Examples: INC BYTE PTR[SI]
;Increment the byte contents of the memory location addressed
by SI
INC WORD PTR [BX]
;Increment the word contents of the memory location addressed
by BX
GLOBAL The labels, variables, constants, or procedures declared GLOBAL
may be used by other modules of the program.
Example: GLOBAL DATA1, DATA2, ARRAY1
; above statement declares the variables DATA1,
; DATA2, and ARRAY1 as GLOBAL variables
LOCAL The label, variables, constants, or procedures declared LOCAL in a
module are to be used only by that particular module.
Example: LOCAL DATA1, DATA2, ARRAY1, A1, A2
Other Assembler Directives
NAME The NAME directive is used to assign a name to an assembly
language program module. The module may now be referred to by
its declared name. The names, if selected properly, may indicate
the function of the different modules, and hence help in good
documentation.
SHORT The SHORT operator indicates to the assembler the only one byte
is required to code the displacement for a jump (i.e. the
displacement is within -128 to +127 bytes from the address of the
byte present next to the JMP instruction)
TYPE The TYPE operator directs the assembler to decide the data type
of the specified label and replaces the TYPE label with the decided
data type. For the word type variable, the data type is 2. For the
double word type, its 4, and for the byte type its 1.

MACRO and ENDM
Suppose a number of instructions occur repeatedly in the main program, the program listing
becomes lengthy. In such a situation, a macro definition, i.e. a label, is assigned with the
repeatedly appearing string of instructions. The process of assigning a label or macro name to
the repeatedly appearing string of instructions is called macro definition. The macro name is
then used throughout the main program to refer to that string of instructions.
; Defining a MACRO
CALCULATE MACRO
MOV AX, [BX]
ADD AX, [BX + 2]
MOV [SI], AX
ENDM
; CALCULATE is the macro name and the macro is used to add two successive data in the
memory, whose offset address is present in BX and the result is stored in the memory at
the offset address in SI.

Passing parameters to a MACRO
Using parameters in macro definition, the programmer specifies the parameters of the macro
that are likely to be changed each time the macro is called. The macro given before
(CALCULATE) can be modified to calculate the result for the different sets of data and store it
in a different memory locations as follows:
CALCULATE MACRO OPERAND, RESULT

MOV BX, OFFSET OPERAND
MOV AX, [BX]
ADD AX, [BX + 2]
MOV SI, OFFSET RESULT
MOV [SI], AX
ENDM

Example Programs (using Directives)
1. Program to find the average of 10 byte-type data stored in an array in data
segment.
ASSUME CS: CODE1, DS: DATA1

DATA1 SEGMENT ;data segment
; starts
ARRAY DB 12h, 23h, 44h, 56h, 0ABh, 73h, ; 10 bytes are
44h, 0ABh, 0EEh, 0Ah ; stored
COUNT EQU 10 ; Count is the
; number of bytes
; in the array
AVERAGE DB 01 DUP(0) ;Reserve one byte
; to store the result
DATA1 ENDS ; data segment
; ends

segment (continued).
CODE1 SEGMENT ; Code segment

; starts
START: MOV AX, DATA1 ; Segment address of
DATA1 is moved to AX
MOV DS, AX ; MOV AX contents to DS
MOV SI, OFFSET ARRAY ; Move offset
; address of ARRAY to SI
XOR AX, AX ; Clear AX and Carry
; Flag
MOV BX, 0000h ; Clear BX
MOV CX, COUNT ; Move COUNT to CX

8086 Microprocessor

segment (continued).
NEXT: MOV BL, [SI] ; Move one byte

; from array into BL
ADD AX, BX ; Add AX and BX
INC SI ; Increment SI to point to
next byte
LOOP NEXT ; Repeat Loop
; NEXT CX times
MOV DH, COUNT ; MOV Count to DH
DIV DH ;Divide AX by CH
MOV AVERAGE, AL ; Store AL contents
; in AVERAGE
CODE1 ENDS ;Code Segment ends
Memory Organization of 8086 Microprocessors
• In 8086 there is 20 bit address bus,so it can address
1,048,576 address.
• At each address we can store 8 bit address (1-byte)but if

want to write a word(16-bit)into a memory segment to
store data in byte form then we write the data in two
consecutive memory address which are even(low) and
odd(high) memory.
• The 8086 memory address space can be viewed as a

sequence of one million bytes in which any byte may
contain an 8 bit data element and any two consecutive
bytes may contain a 16 bit data element.
Memory Organization (continued..)
• The other bank is connected to the upper half of
the data bus (D8-D15) and contains odd address
bytes.
• When A0 is high and BHE (Bus High Enable) is

low, the odd bank is selected.
• A specific byte within each bank is selected by

address lines A1-A19


• The memory address space of the 8086-based
microcomputers has different logical and physical
organizations
– Logically, memory is implemented as a single 1M × 8

memory chunk. The byte-wide storage locations are
assigned consecutive addresses over the range from
0000016 through FFFFF16.
– Physically, memory is implemented as two independent
512Kbyte banks: the low (even) bank and the high (odd)
bank.
• Data bytes associated with an even address (0000016, 0000216,
etc.) reside in the low bank, and those with odd addresses
(0000116, 0000316, etc.) reside in the high bank.


Segment Registers
– Additional registers called segment registers
generate memory address when combined with
other in the microprocessor. In 8086 microprocessor,
memory is divided into 4 segments as follow:

Segment Registers
• Code Segment (CS): The CS register is used for
addressing a memory location in the Code Segment
of the memory, where the executable program is
stored.
• Data Segment (DS): The DS contains most data used
by program. Data are accessed in the Data Segment
by an offset address or the content of other register
that holds the offset address.
• Stack Segment (SS): SS defined the area of memory
used for the stack.
• Extra Segment (ES): ES is additional data segment
that is used by some of the string to hold the
destination data.
18/10/14
Even and Odd Memory Banks of

8086 Microprocessors
DEEPAK.P
271
Memory Organization
• The address space is physically connected to a
16 -bit data bus by dividing the address space
into two 8 bit banks of up to 512K bytes each.
• One bank is connected to the lower half of the
16 bit data bus (D0-D7 ) and contains even
address bytes.
• When A0 bit is low, the bank is selected.

Memory Organization
• Data can be accessed from the memory in four
different ways.
• They are:
• 8 -bit data from Lower (Even) address Bank.
• 8-bit data from Higher (Odd) address Bank.
• 16-bit data starting from Even Address.
• 16-bit data starting from Odd Address

Memory Organization

Memory Organization

Memory Organization

Minimum and Maximum Modes For 8086
Microprocessor
General Bus Operation
 The 8086 has a combined address and data bus commonly referred as a time
multiplexed address and data bus.
 The main reason behind multiplexing address and data over the same pins is
the maximum utilization of processor pins and it facilitates the use of 40 pin
standard DIP package.
 The bus can be demultiplexed using a few latches and
transreceivers, when ever required.
 Basically, all the processor bus cycles consist of at least four clock cycles.
These are referred to as T1, T2, T3, T4. The address is transmitted by the
processor during T1. It is present on the bus only for one cycle.
 The negative edge of this ALE pulse is used to separate the address and
the data or status information. In maximum mode, the status lines S0, S1
and S2 are used to indicate the type of operation.
 Status bits S3 to S7 are multiplexed with higher order address bits and the
BHE signal.
 Address is valid during T1 while status bits S3 to S7 are valid during T2
through T4.
General Bus Cycle For 8086
278
Dept. of ECE, ATMECE, MYSURU
Minimum Mode 8086 System
 The microprocessor 8086 is operated in minimum mode by
strapping its MN/MX pin to logic 1.
 In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in
the minimum mode system.
 The remaining components in the system are latches,
transreceivers, clock generator, memory and I/O devices.
 Latches are generally buffered output D-type flip-flops like

74LS373 or 8282. They are used for separating the valid address
from the multiplexed address/data signals and are controlled by
the ALE signal generated by 8086.

Minimum Mode Configuration
For 8086

 Transreceivers are the bidirectional buffers and some times they are
called as data amplifiers. They are required to separate the valid data
from the time multiplexed address/data signals. They are controlled by
two signals namely, DEN and DT/R.
 The DEN signal indicates the direction of data, i.e. from or to the
processor.
 The system contains memory for the monitor and users program
storage. Usually, EPROM are used for monitor storage, while RAM for
users program storage. A system may contain I/O devices.
 The opcode fetch and read cycles are similar. Hence the timing diagram
can be categorized in two parts, the first is the timing diagram for read
cycle and the second is the timing diagram for write cycle.
 The read cycle begins in T1 with the assertion of address latch enable
(ALE) signal and also M / IO signal. During the negative going edge of
this signal, the valid address is latched on the local bus.

281
 The BHE and A0 signals address low, high or both bytes. From
T1 to T4 , the M/IO signal indicates a memory or I/O
operation.
 At T2, the address is removed from the local bus and is sent to
the output. The bus is then tristated. The read (RD) control
signal is also activated in T2.
 The read (RD) signal causes the address device to enable its data
bus drivers. After RD goes low, the valid data is available on the
data bus.
 The addressed device will drive the READY line high. When the
processor returns the read signal to high level, the addressed
device will again tristate its bus drivers.

282
 A write cycle also begins with the assertion of ALE and the
emission of the address.
 The M/IO signal is again asserted to indicate a memory or I/O

operation. In T2, after sending the address in T1, the processor
sends the data to be written to the addressed location.
 The data remains on the bus until middle of T4 state. The WR

becomes active at the beginning of T2 (unlike RD is somewhat
delayed in T2 to provide time for floating).
 The BHE and A0 signals are used to select the proper byte or
bytes of memory or I/O word to be read or write.
 The M/IO, RD and WR signals indicate the type of data transfer

as specified in table below.

284
Hold Response sequence:
 The HOLD pin is checked at leading edge of each clock pulse.
If it is received active by the processor before T4 of the previous
cycle or during T1 state of the current cycle, the CPU activates
HLDA in the next clock cycle and for succeeding bus cycles, the
bus will be given to another requesting master.
 The control of the bus is not regained by the processor until the
requesting master does not drop the HOLD pin low.
 When the request is dropped by the requesting master, the

HLDA is dropped by the processor at the trailing edge of the
next clock.

285
Hold Response Timing Cycle

286
Maximum Mode 8086 System
 In the maximum mode, the 8086 is operated by strapping the
MN/MX pin to ground.
 In this mode, the processor derives the status signal S2, S1, S0.
Another chip called bus controller derives the control signal using
this status information .
 In the maximum mode, there may be more than one

microprocessor in the system configuration. The components in
the system are same as in the minimum mode system.
 The basic function of the bus controller chip IC8288, is to derive

control signals like RD and WR ( for memory and I/O devices),
DEN, DT/R, ALE etc. using the information by the processor on the
status lines.

287
 The bus controller chip has input lines S2, S1, S0 and CLK.
These inputs to 8288 are driven by CPU.
 It derives the outputs ALE, DEN, DT/R, MRDC, MWTC,

AMWC, IORC, IOWC and AIOWC. The AEN, IOB and CEN
pins are specially useful for multiprocessor systems.
 AEN and IOB are generally grounded. CEN pin is usually tied to
+5V. The significance of the MCE/PDEN output depends upon
the statusof the IOB pin.
 INTA pin used to issue two interrupt acknowledge pulses to the

interrupt controller or to an interrupting device.

 IORC, IOWC are I/O read command and I/O write command
signals respectively . These signals enable an IO interface to read
or write the data from or to the address port.
 The MRDC, MWTC are memory read command and memory

write command signals respectively and may be used as
memory read or write signals.
 All these command signals instructs the memory to accept or

send data from or to the bus.
 Here the only difference between in timing diagram between

minimum mode and maximum mode is the status signals used
and the available control and advanced command signals.

289
Maximum Mode Configuration For
8086

290
 R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will
output a pulse as on the ALE and apply a required signal to its DT / R
pin during T1.
 In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input
it will activate MRDC or IORC. These signals are activated until T4.
 For an output, the AMWC or AIOWC is activated from T2 to T4 and

MWTC or IOWC is activated from T3 to T4.
 The status bit S0 to S2 remains active until T3 and become passive

during T3 and T4.
 If reader input is not activated before T3, wait state will be inserted
between T3 and T4.

291
Basic Peripherals and their Interfacing with 8086
We have four common types of memory:
• Read only memory (ROM)
• Flash memory (EEPROM)
• Static Random access memory (SARAM)
• Dynamic Random access memory (DRAM).
• Pin connections common to all memory devices are: The address input, data
output or input/outputs, selection input and control input used to select a read or
write operation.
• Address connections: All memory devices have address inputs that select a
memory location within the memory device. Address inputs are labeled from A0 to
An.
• Data connections: All memory devices have a set of data outputs or input/outputs.
Today many of them have bi-directional common I/O pins.
• Selection connections: Each memory device has an input, that selects or enables
the memory device. This kind of input is most often called a chip select (CS
), chip enable (CE
) or simply select (S
) input.

MEMORY COMPONENT ILLUSTRATING THE ADDRESS, DATA AND CONTROL
CONNECTIONS

• RAM memory generally has at least one CS or S input and ROM at least one CE
• If the CE, CS, S input is active the memory device perform the read or write.
• If it is inactive the memory device cannot perform read or write operation.
• If more than one CS
connection is present, all most be active to perform read or write data.
• Control connections: A ROM usually has only one control input, while a RAM often
has one or two control inputs.
• The control input most often found on the ROM is the output enable (OE
) or gate (G
), this allows data to flow out of the output data pins of the ROM.
• If OE and the selected input are both active, then the output is enable, if OE is
inactive, the output is disabled at its high-impedance state.
• The OE
connection enables and disables a set of three-state buffer located within the memory
device and must be active to read data.
• A RAM memory device has either one or two control inputs. If there is one control
input it is often called R/W
• This pin selects a read operation or a write operation only if the device is selected by
the selection input (CS).
• If the RAM has two control inputs, they are usually labeled WE or W and OE or G.
• (WE) write enable must be active to perform a memory write operation and OE must
be active to perform a memory read operation.
• When these two controls WE and OE are present, they must never be active at the
same time.
• The ROM read only memory permanently stores programs and data and data was
always present, even when power is disconnected.
• It is also called as nonvolatile memory.
• EPROM (erasable programmable read only memory) is also erasable if exposed to high
intensity ultraviolet light for about 20 minutes or less, depending upon the type of
EPROM.
• We have PROM (programmable read only memory)
• RMM (read mostly memory) is also called the flash memory.
• The flash memory is also called as an EEPROM (electrically erasable programmable
ROM), EAROM (electrically alterable ROM), or a NOVROM (nonvolatile ROM).
• These memory devices are electrically erasable in the system, but require more time to
erase than a normal RAM.
• EPROM contains the series of 27XXX contains the following part numbers : 2704(512 *
8), 2708(1K * 8), 2716(2K * 8), 2732(4K * 8), 2764(8K * 8), 27128(16K * 8) etc.
• Each of these parts contains address pins, eight data connections, one or more chip
selection inputs (CE) and an output enable pin (OE).
• This device contains 11 address inputs and 8 data outputs.
• If both the pin connection CE and OE are at logic 0, data will appear on the output
connection . If both the pins are not at logic 0, the data output connections remains at
their high impedance or off state.
• To read data from the EPROM Vpp pin must be placed at a logic 1.
• Static RAM memory device retain data for as long as DC power is applied.
Because no special action is required to retain stored data, these devices
are called as static memory. They are also called volatile memory because
they will not retain data without power.
• The main difference between a ROM and RAM is that a RAM is written
under normal operation, while ROM is programmed outside the computer
and is only normally read.
• The SRAM stores temporary data and is used when the size of read/write
memory is relatively small.

• The control inputs of this RAM are slightly
different from those presented earlier. The
OE pin is labeled G, the CS pin S and the WE
pin . W
• This 4016 SRAM device has 11 address
inputs and 8 data input/output
connections.
Static RAM Interfacing
• The semiconductor RAM is broadly two types – Static RAM and Dynamic RAM.
• The semiconductor memories are organised as two dimensional arrays of memory
locations.
• For example 4K * 8 or 4K byte memory contains 4096 locations, where each locations
contains 8-bit data and only one of the 4096 locations can be selected at a time. Once a
location is selected all the bits in it are accessible using a group of conductors called
Data bus.
• For addressing the 4K bytes of memory, 12 address lines are required.
• In general to address a memory location out of N memory locations, we will require at
least n bits of address, i.e. n address lines where n = Log2 N.
• Thus if the microprocessor has n address lines, then it is able to address at the most N
locations of memory, where 2n=N. If out of N locations only P memory locations are to
be interfaced, then the least significant p address lines out of the available n lines can
be directly connected from the microprocessor to the memory chip while the remaining
(n-p) higher order address lines may be used for address decoding as inputs to the chip
selection logic.
• The memory address depends upon the hardware circuit used for decoding the chip
select (CS). The output of the decoding circuit is connected with the CS pin of the
memory chip.

• The general procedure of static memory interfacing with 8086 is briefly described as
follows:
1. Arrange the available memory chip so as to obtain 16- bit data bus width. The upper
8-bit bank is called as odd address memory bank and the lower 8-bit bank is called as
even address memory bank.
2. Connect available memory address lines of memory chip with those of the
microprocessor and also connect the memory RD
and WR
inputs to the corresponding processor control signals. Connect the 16-bit data bus of
the memory bank with that of the microprocessor 8086.
3. The remaining address lines of the microprocessor, BHE and A0 are used for decoding
the required chip select signals for the odd and even memory banks. The CS
of memory is derived from the o/p of the decoding circuit.
• As a good and efficient interfacing practice, the address map of the system should be
continuous as far as possible, i.e. there should not be no windows in the map and no
fold back space should be allowed.
• A memory location should have a single address corresponding to it, i.e. absolute
decoding should be preferred and minimum hardware should be used for decoding.

PIO 8255
• The parallel input-output port chip 8255 is also called as
programmable peripheral input-output port. The Intel‟s
8255 is designed for use with Intel‟s 8-bit, 16-bit and
higher capability microprocessors. It has 24 input/output
lines which may be individually programmed in two
groups of twelve lines each, or three groups of eight lines.
The two groups of I/O pins are named as Group A and
Group B. Each of these two groups contains a subgroup
of eight I/O lines called as 8-bit port and another
subgroup of four lines or a 4-bit port. Thus Group A
contains an 8-bit port A along with a 4-bit port. C upper.

303
PIO 8255 (cont..)
• The port A lines are identified by symbols PA0-PA7 while
the port C lines are identified as PC4-PC7. Similarly,
Group B contains an 8-bit port B, containing lines PB0-
PB7 and a 4-bit port C with lower bits PC0- PC3. The port
C upper and port C lower can be used in combination as
an 8-bit port C.
• Both the port C are assigned the same address. Thus one
may have either three 8-bit I/O ports or two 8-bit and two
4-bit ports from 8255. All of these ports can function
independently either as input or as output ports. This can
be achieved by programming the bits of an internal
register of 8255 called as control word register ( CWR ).

PIO 8255 (cont..)
• The internal block diagram and the pin configuration

of 8255 are shown in fig.
• The 8-bit data bus buffer is controlled by the read/write
control logic. The read/write control logic manages all of
the internal and external transfers of both data and
control words.
• RD, WR, A1, A0 and RESET are the inputs provided by
the microprocessor to the READ/ WRITE control logic of
8255. The 8-bit, 3-state bidirectional buffer is used to
interface the 8255 internal data bus with the external
system data bus.

PIO 8255 (cont..)
• This buffer receives or transmits data upon the execution

of input or output instructions by the microprocessor. The
control words or status information is also transferred
through the buffer.
• The signal description of 8255 are briefly presented
as follows :
• PA7-PA0: These are eight port A lines that acts as either
latched output or buffered input lines depending upon
the control word loaded into the control word register.
• PC7-PC4 : Upper nibble of port C lines. They may act as
either output latches or input buffers lines.
306
PIO 8255 (cont..)
• This port also can be used for generation of handshake

lines in mode 1 or mode 2.
• PC3-PC0 : These are the lower port C lines, other details
are the same as PC7-PC4 lines.
• PB0-PB7 : These are the eight port B lines which are used
as latched output lines or buffered input lines in the same
way as port A.
• RD : This is the input line driven by the
microprocessor and should be low to indicate read
operation to 8255.
• WR : This is an input line driven by the microprocessor. A
low on this line indicates write operation.
PIO 8255 (cont..)
• CS : This is a chip select line. If this line goes low, it

enables the 8255 to respond to RD and WR signals,
otherwise RD and WR signal are neglected.
• A1-A0 : These are the address input lines and are driven
by the microprocessor. These lines A1-A0 with RD, WR
and CS from the following operations for 8255. These
address lines are used for addressing any one of the four
registers,
i.e. three ports and a control word register as given in
table below.
• In case of 8086 systems, if the 8255 is to be interfaced
with lower order data bus, the A0 and A1 pins of 8255 are
connected with A1 and A2 respectively.

RD WR CS A1 A0 Input (Read) cycle
0 1 0 0 0 Port A to Data bus
0 1 0 0 1 Port B to Data bus
0 1 0 1 0 Port C to Data bus
0 1 0 1 1 CWR to Data bus
RD WR CS A1 A0 Output (Write) cycle

1 0 0 0 0 Data bus to Port A
1 0 0 0 1 Data bus to Port B
1 0 0 1 0 Data bus to Port C
1 0 0 1 1 Data bus to CWR
RD WR CS A1 A0 Function
X X 1 X X Data bus tristated
1 1 0 X X Data bus tristated
Control Word Register

309
PIO 8255.
• D0-D7 : These are the data bus lines those carry data or
control word to/from the microprocessor.
• RESET : A logic high on this line clears the control word
register of 8255. All ports are set as input ports by default
after reset.

310
Block Diagram of 8255 (Architecture)
( cont..)
• It has a 40 pins of 4 groups.
1. Data bus buffer
2. Read Write control logic
3. Group A and Group B controls
4. Port A, B and C
• Data bus buffer: This is a tristate bidirectional buffer
used to interface the 8255 to system databus. Data is
transmitted or received by the buffer on execution of
input or output instruction by the CPU.
• Control word and status information are also
transferred through this unit.
Dept. of ECE, ATMECE, 3

MYSURU 1
1
( cont..)
• Read/Write control logic: This unit accepts control
signals ( RD, WR ) and also inputs from address bus
issues
and commands to individual group of control
blocks ( Group A, Group B).
•It has the following pins. a)
CS – Chipselect : A low on this PIN enables the
communication between CPU and 8255.
b) RD (Read) – A low on this pin enables the CPU to read
the data in the ports or the status word through data
bus buffer.

312
( cont..)
c) WR ( Write ) : A low on this pin, the CPU can write
data on to the ports or on to the control register
through the data bus buffer.
d) RESET: A high on this pin clears the control register
and all ports are set to the input mode
e) A0 and A1 ( Address pins ): These pins in conjunction
with RD and WR pins control the selection of one of
the 3 ports.
• Group A and Group B controls : These block receive
control from the CPU and issues commands to their
respective ports.

( cont..)
• Group A - PA and PCU ( PC7 –PC4)
• Group B - PCL ( PC3 – PC0)
• Control word register can only be written into no
read operation of the CW register is allowed.
• a) Port A: This has an 8 bit latched/buffered O/P and 8 bit
input latch. It can be programmed in 3 modes – mode 0,
mode 1, mode 2.
b) Port B: This has an 8 bit latched / buffered O/P and
8 bit input latch. It can be programmed in mode 0,
mode1.

Block Diagram of 8255 (Architecture).
c) Port C : This has an 8 bit latched input buffer and 8

bit out put latched/buffer. This port can be divided into
two 4 bit ports and can be used as control signals for port
A and port B. it can be programmed in mode 0.

Modes of Operation of 8255 (cont..)
• These are two basic modes of operation of 8255. I/O

mode and Bit Set-Reset mode (BSR).
• In I/O mode, the 8255 ports work as programmable I/O
ports, while in BSR mode only port C (PC0-PC7) can
be used to set or reset its individual port bits.
• Under the I/O mode of operation, further there are
three modes of operation of 8255, so as to support
different types of applications, mode 0, mode 1 and
mode 2.

• BSR Mode: In this mode any of the 8-bits of port C can

be set or reset depending on D0 of the control word. The
bit to be set or reset is selected by bit select flags D3, D2
and D1 of the CWR as given in table.
• I/O Modes :
a)Mode 0 ( Basic I/O mode ): This mode is also called as
basic input/output mode. This mode provides simple input
and output capabilities using each of the three ports. Data
can be simply read from and written to the input and
output ports respectively, after appropriate initialisation.

317
• The control word register has two formats. The first
format is valid for I/O modes of operation, i.e. modes 0,
mode 1 and mode 2 while the second format is valid for
bit set/reset (BSR) mode of operation. These formats are
shown in following fig.

321
322
324
b) Mode 1: ( Strobed input/output mode ) In this mode the

handshaking control the input and output action of the
specified port. Port C lines PC0-PC2, provide strobe or
handshake lines for port B. This group which includes
port B and PC0-PC2 is called as group B for Strobed data
input/output. Port C lines PC3-PC5 provide strobe lines for
port A. This group including port A and PC3-PC5 from
group A. Thus port C is utilized for generating handshake
signals. The salient features of mode 1 are listed as
follows:

1. Two groups – group A and group B are available for

strobed data transfer.
2. Each group contains one 8-bit data I/O port and one 4-
bit control/data port.
3. The 8-bit data port can be either used as input and
output port. The inputs and outputs both are latched.
4. Out of 8-bit port C, PC0-PC2 are used to generate control
signals for port B and PC3-PC5 are used to generate
control signals for port A. the lines PC6, PC7 may be
used as independent data lines.
326
• The control signals for both the groups in input and

output modes are explained as follows:
Input control signal definitions (mode 1 ):
• STB( Strobe input ) – If this lines falls to logic low
level, the data available at 8-bit input port is loaded into
input latches.
• IBF ( Input buffer full ) – If this signal rises to logic 1, it
indicates that data has been loaded into latches, i.e. it
works as an acknowledgement. IBF is set by a low on
STB and is reset by the rising edge of RD input.

• INTR ( Interrupt request ) – This active high output signal

can be used to interrupt the CPU whenever an input
device requests the service. INTR
is set by a high STB pin and a
high at IBF pin. INTE is an internal flag that can be
controlled by the bit set/reset mode of either PC4(INTEA)
or PC2(INTEB) as shown in fig.
• INTR is reset by a falling edge of RD input. Thus an
external input device can be request the service of the
processor by putting the data on the bus and sending
the strobe signal.
Output control signal definitions (mode 1) :

• OBF (Output buffer full ) – This status signal, whenever
falls to low, indicates that CPU has written data to the
specified output port. The OBF flip-flop will be set by a
rising edge of WR signal and reset by a low going edge
at the ACK input.
• ACK ( Acknowledge input ) – ACK signal acts as an
acknowledgement to be given by an output device. ACK
signal, whenever low, informs the CPU that the data
transferred by the CPU to the output device through the
port is received by the output device.

• INTR ( Interrupt request ) – Thus an output signal that can

be used to interrupt the CPU when an output device
acknowledges the data received from the CPU. INTR is
set when ACK, OBF and INTE are 1. It is reset by a
falling edge on WR input. The INTEA and INTEB flags
are controlled by the bit set-reset mode of PC6 and PC2
respectively.

331
332
• Mode 2 ( Strobed bidirectional I/O ): This mode of

operation of 8255 is also called as strobed bidirectional
I/O. This mode of operation provides 8255 with an
additional features for communicating with a peripheral
device on an 8-bit data bus. Handshaking signals are
provided to maintain proper data flow and
synchronization between the data transmitter and
receiver. The interrupt generation and other functions are
similar to mode 1.
• In this mode, 8255 is a bidirectional 8-bit port with
handshake signals. The RD and WR signals decide
whether the 8255 is going to operate as an input port
or output port.
• The Salient features of Mode 2 of 8255 are listed

as follows:
1. The single 8-bit port in group A is available.
2. The 8-bit port is bidirectional and additionally a 5-
bit control port is available.
3. Three I/O lines are available at port C.( PC2 – PC0 )
4. Inputs and outputs are both latched.
5. The 5-bit control port C (PC3-PC7) is used for
generating / accepting handshake signals for the 8-
bit data transfer on port A.

• Control signal definitions in mode 2:

• INTR – (Interrupt request) As in mode 1, this control
signal is active high and is used to interrupt the
microprocessor to ask for transfer of the next data byte
to/from it. This signal is used for input ( read ) as well
as output ( write ) operations.
• Control Signals for Output operations:
• OBF ( Output buffer full ) – This signal, when falls to
low level, indicates that the CPU has written data to port
A.

• ACK ( Acknowledge ) This control input, when falls to

logic low level, acknowledges that the previous data byte
is received by the destination and next byte may be sent
by the processor. This signal enables the internal tristate
buffers to send the next data byte on port A.
• INTE1 ( A flag associated with OBF ) This can be
controlled by bit set/reset mode with PC6.
• Control signals for input operations :
• STB (Strobe input ) A low on this line is used to strobe in
the data into the input latches of 8255.
338
• IBF ( Input buffer full ) When the data is loaded into

input buffer, this signal rises to logic „1‟. This can be
used as an acknowledge that the data has been received
by the receiver.
• The waveforms in fig show the operation in Mode 2
for output as well as input port.
• Note: WR must occur before ACK and STB must be
activated before RD.

• The following fig shows a schematic diagram containing

an 8-bit bidirectional port, 5-bit control port and the
relation of INTR with the control pins. Port B can either be
set to Mode 0 or 1 with port A( Group A ) is in Mode 2.
• Mode 2 is not available for port B. The following fig
shows the control word.
• The INTR goes high only if either IBF, INTE2, STB and
RD go high or OBF, INTE1, ACK and WR go high. The
port C can be read to know the status of the peripheral
device, in terms of the control signals, using the normal
I/O instructions.
341
342
343
Interfacing a Microprocessor To
Keyboard
• When you press a key on your computer, you are
activating a switch. There are many different ways of
making these switches. An overview of the
construction and operation of some of the most
common types.
1. Mechanical key switches: In mechanical-switch keys,
two pieces of metal are pushed together when you press
the key. The actual switch elements are often made of a
phosphor-bronze alloy with gold platting on the contact
areas. The key switch usually contains a spring to
return the key to the nonpressed position and perhaps a
small piece of foam to help damp out bouncing.
Keyboard (cont..)
• Some mechanical key switches now consist of a molded
silicon dome with a small piece of conductive rubber
foam short two trace on the printed-circuit board to
produce the key pressed signal.
• Mechanical switches are relatively inexpensive but they
have several disadvantages. First, they suffer from
contact bounce. A pressed key may make and break
contact several times before it makes solid contact.
• Second, the contacts may become oxidized or dirty
with age so they no longer make a dependable
connection.
345
Keyboard (cont..)
• Higher-quality mechanical switches typically have a
rated life time of about 1 million keystrokes. The
silicone dome type typically last 25 million
keystrokes.
2. Membrane key switches: These switches are really a
special type of mechanical switches. They consist of
a three-layer plastic or rubber sandwich.
• The top layer has a conductive line of silver ink
running under each key position. The bottom layer has
a conductive line of silver ink running under each
column of keys.
346
Keyboard (cont..)
• When u press a key, you push the top ink line
through the hole to contact the bottom ink line.
• The advantages of membrane keyboards is that they
can be made as very thin, sealed units.
• They are often used on cash registers in fast food
restaurants. The lifetime of membrane keyboards
varies over a wide range.
3. Capacitive key switches: A capacitive keyswitch has
two small metal plates on the printed circuit board and
another metal plate on the bottom of a piece of foam.

Keyboard (cont..)
• When u press the key, the movable plate is pushed
closer to fixed plate. This changes the capacitance
between the fixed plates. Sense amplifier circuitry
detects this change in capacitance and produce a logic
level signal that indicates a key has been pressed.
• The big advantages of a capacitive switch is that it has
no mechanical contacts to become oxidized or dirty.
• A small disadvantage is the specified circuitry needed
to detect the change in capacitance.
• Capacitive keyswitches typically have a rated lifetime
of about 20 million keystrokes.
348
Keyboard (cont..)
4. Hall effect keyswitches: This is another type of switch
which has no mechanical contact. It takes advantage
of the deflection of a moving charge by a magnetic
field.
• A reference current is passed through a semiconductor
crystal between two opposing faces. When a key is
pressed, the crystal is moved through a magnetic field
which has its flux lines perpendicular to the direction
of current flow in the crystal.
• Moving the crystal through the magnetic field causes a
small voltage to be developed between two of the
other opposing faces of the crystal.
Keyboard (cont..)
• This voltage is amplified and used to indicate that a key
has been pressed. Hall effect sensors are also used to
detect motion in many electrically controlled machines.
• Hall effect keyboards are more expensive because of the
more complex switch mechanism, but they are very
dependable and have typically rated lifetime of 100
million or more keystrokes.
350
Keyboard Circuit Connections and
Interfacing (cont..)
• In most keyboards, the keyswitches are connecting in
a matrix of rows and columns, as shown in fig.
• We will use simple mechanical switches for our
examples, but the principle is same for other type
of switches.
• Getting meaningful data from a keyboard, it requires
the following three major tasks:
1. Detect a keypress.
2. Debounce the keypress.
3. Encode the keypress

• Three tasks can be done with hardware, software, or
a combination of two, depending on the application.
1. Software Keyboard Interfacing:
• Circuit connection and algorithm : The following fig
(a)shows how a hexadecimal keypad can be connected
to a couple of microcomputer ports so the three
interfacing tasks can be done as part of a program.
• The rows of the matrix are connected to four output
port lines. The column lines of matrix are connected to
four input-port lines. To make the program simpler, the
row lines are also connected to four input lines.

• When no keys are pressed, the column lines are held high
by the pull-up resistor connected to +5V. Pressing a key
connects a row to a column. If a low is output on a row
and a key in that row is pressed, then the low will appear
on the column which contains that key and can be
detected on the input port.
• If you know the row and column of the pressed key, you
then know which key was pressed, and you can convert
this information into any code you want to represent
that key.

• The following flow chart for a procedure to detect,
debounce and produce the hex code for a pressed key.
• An easy way to detect if any key in the matrix is pressed
is to output 0‟s to all rows and then check the column to
see if a pressed key has connected a low to a column.
• In the algorithm we first output lows to all the rows and
check the columns over and over until the column are
all high. This is done before the previous key has been
released before looking for the next one. In the standard
keyboard terminology, this is called two-key lockout.

• Once the columns are found to be all high, the program
enters another loop, which waits until a low appears on
one of the columns, indicating that a key has been
pressed. This second loop does the detect task for us. A
simple 20- ms delay procedure then does the debounce
task.
• After the debounce time, another check is made to see if
the key is still pressed. If the columns are now all high,
then no key is pressed and the initial detection was caused
by a noise pulse or a light brushing past a key. If any of
the columns are still low, then the assumption is made that
it was a valid keypress.

• The final task is to determine the row and column of the
pressed key and convert this row and column information
to the hex code for the pressed key. To get the row and
column information, a low is output to one row and the
column are read. If none of the columns is low, the
pressed key is not in that row. So the low is rotated to the
next row and the column are checked again. The process
is repeated until a low on a row produces a low on one of
the column.
• The pressed key then is in the row which is low at
that time.
• The connection fig shows the byte read in from the input
port will contain a 4-bit code which represents the row
of the pressed key and a 4-bit code which represent the
column of the pressed key.
• Error trapping: The concept of detecting some error
condition such as “ no match found” is called error
trapping. Error trapping is a very important part of real
programs. Even in simple programs, think what might
happen with no error trap if two keys in the same row
were pressed at exactly at the same time and a column
code with two lows in it was produced.

• This code would not match any of the row-column codes
in the table, so after all the values in the table were
checked, assigned register in program would be
decremented from 0000H to FFFFH. The compare
decrement cycle would continue through 65,536 memory
locations until, by change the value in a memory location
matched the row-column code. The contents of the lower
byte register at hat point would be passed back to the
calling routine. The changes are 1 in 256 that would be the
correct value for one of the pressed keys. You should keep
an error trap in a program whenever there is a chance for
it.
2. Keyboard Interfacing with Hardware: For the
system where the CPU is too busy to be bothered
doing these tasks in software, an external device is
used to do them.
• One of a MOS device which can be do this is the
General Instruments AY5-2376 which can be connected
to the rows and columns of a keyboard switch matrix.
• The AY5-2376 independently detects a keypress by
cycling a low down through the rows and checking
the columns. When it finds a key pressed, it waits a
debounce time.
• If the key is still pressed after the debounce time, the AY5-
2376 produces the 8-bit code for the pressed key and send
it out to microcomputer port on 8 parallel lines. The
microcomputer knows that a valid ASCII code is on the
data lines, the AY5-2376 outputs a strobe pulse.
• The microcomputer can detect this strobe pulse and read
in ASCII code on a polled basis or it can detect the strobe
pulse on an interrupt basis.
• With the interrupt method the microcomputer doesn‟t
have to pay any attention to the keyboard until it receives
an interrupt signal.
• So this method uses very little of the microcomputer time.
The AY5-2376 has a feature called two-key rollover. This
means that if two keys are pressed at nearly the same
time, each key will be detected, debounced and converted
to ASCII.
• The ASCII code for the first key and a strobe signal for it
will be sent out then the ASCII code for the second key
and a strobe signal for it will be sent out and compare
this with two-key lockout.

Example
• Interface a 4 * 4 keyboard with 8086 using 8255 an write
an ALP for detecting a key closure and return the key code
in AL. The debounce period for a key is 10ms. Use
software debouncing technique. DEBOUNCE is
an available 10ms delay routine.
• Solution: Port A is used as output port for selecting a row
of keys while Port B is used as an input port for sensing a
closed key. Thus the keyboard lines are selected one by
one through port A and the port B lines are polled
continuously till a key closure is sensed. The routine
DEBOUNCE is called for key debouncing. The key code
is depending upon the selected row and a low sensed
column.

Example (cont..)
• The higher order lines of port A and port B are left unused.
The address of port A and port B will respectively 8000H
and 8002H while address of CWR will be 8006H. The
flow chart of the complete program is as given. The
control word for this problem will be 82H. Code segment
CS is used for storing the program code.
• Key Debounce : Whenever a mechanical push-button
is pressed or released once, the mechanical
components of the key do not change the position
smoothly, rather it generates a transient response .

Example (cont..)
• These transient variations may be interpreted as the

multiple key pressure and responded accordingly by
the microprocessor system.
• To avoid this problem, two schemes are suggested: the
first one utilizes a bistable multivibrator at the output of
the key to debounce .
• The other scheme suggests that the microprocessor
should be made to wait for the transient period ( usually
10ms ), so that the transient response settles down and
reaches a steady state.

Example
• A logic „0‟ will be read by the microprocessor when the

key is pressed.
• In a number of high precision applications, a designer
may have two options- the first is to have more than one
8-bit port, read (write) the port one by one and then from
the multibyte data, the second option allows forming 16-
bit ports using two 8-bit ports and use 16-bit read or write
operations.

Interfacing Analog to Digital Data
Converters
• In most of the cases, the PIO 8255 is used for
interfacing the analog to digital converters with
microprocessor.
• We have already studied 8255 interfacing with 8086 as an
I/O port, in previous section. This section we will only
emphasize the interfacing techniques of analog to digital
converters with 8255.
• The analog to digital converters is treaded as an input
device by the microprocessor, that sends an initialising
signal to the ADC to start the analogy to digital data
conversation process. The start of conversation signal is
a pulse of a specific duration.

Converters (cont..)
• The process of analog to digital conversion is a slow
process, and the microprocessor has to wait for the digital
data till the conversion is over. After the conversion is
over, the ADC sends end of conversion EOC signal to
inform the microprocessor that the conversion is over and
the result is ready at the output buffer of the ADC. These
tasks of issuing an SOC pulse to ADC, reading EOC
signal from the ADC and reading the digital output of the
ADC are carried out by the CPU using 8255 I/O ports.

Converters (cont..)
• The time taken by the ADC from the active edge of
SOC pulse till the active edge of EOC signal is called
as the conversion delay of the ADC.
• It may range any where from a few microseconds in case
of fast ADC to even a few hundred milliseconds in case
of slow ADCs.
• The available ADC in the market use different conversion
techniques for conversion of analog signal to digitals.
Successive approximation techniques and dual slope
integration techniques are the most popular techniques
used in the integrated ADC chip.

Converters (cont..)
• General algorithm for ADC interfacing contains the
following steps:
1. Ensure the stability of analog input, applied to the ADC.
2. Issue start of conversion pulse to ADC
3. Read end of conversion signal to mark the end
of conversion processes.
4. Read digital data output of the ADC as equivalent
digital output.

Converters (cont..)
• Analog input voltage must be constant at the input of the
ADC right from the start of conversion till the end of the
conversion to get correct results. This may be ensured by
a sample and hold circuit which samples the analog
signal and holds it constant for a specific time duration.
The microprocessor may issue a hold signal to the sample
and hold circuit.
• If the applied input changes before the complete
conversion process is over, the digital equivalent of the
analog input calculated by the ADC may not be correct.

Converters (cont..)
ADC 0808/0809 :
• The analog to digital converter chips 0808 and 0809 are
8- bit CMOS, successive approximation converters. This
technique is one of the fast techniques for analog to
digital conversion. The conversion delay is 100µs at a
clock frequency of 640 KHz, which is quite low as
compared to other converters. These converters do not
need any external zero or full scale adjustments as they
are already taken care of by internal circuits. These
converters internally have a 3:8 analog multiplexer so
that at a time eight different analog conversion by using
address lines -
Converters (cont..)
ADD A, ADD B, ADD C. Using these address inputs,
multichannel data acquisition system can be designed
using a single ADC. The CPU may drive these lines
using output port lines in case of multichannel
applications. In case of single input applications, these
may be hardwired to select the proper input.
• There are unipolar analog to digital converters, i.e. they
are able to convert only positive analog input voltage to
their digital equivalent. These chips do no contain any
internal sample and hold circuit.

Analog Address lines
I/P
selected C B A
I / P0 0 0 0
I / P1 0 0 1
I / P2 0 1 0
I / P3 0 1 1
I / P4 1 0 0
I / P5 1 0 1
I / P6 1 1 0
I / P7 1 1 1

Converters (cont..)
• If one needs a sample and hold circuit for the conversion
of fast signal into equivalent digital quantities, it has to
be externally connected at each of the analog inputs.
• Vcc Supply pins +5V

• GND GND
• Vref + Reference voltage positive +5 Volts
maximum.
• Vref _ Reference voltage negative 0Volts
minimum.

Converters (cont..)
• I/P0 –I/P7 Analog inputs
• ADD A,B,C Address lines for selecting
analog inputs.
• O7 – O0 Digital 8-bit output with O7 MSB and
O0 LSB
• SOC Start of conversion signal pin
• EOC End of conversion signal pin
• OE Output latch enable pin, if high
enables output
• CLK Clock input for ADC

382
CLOCK
START
ALE
EOC
OE
O /P
Timing Diagram of ADC 0808

Converters (cont..)
• Example: Interfacing ADC 0808 with 8086 using 8255
ports. Use port A of 8255 for transferring digital data
output of ADC to the CPU and port C for control
signals. Assume that an analog input is present at I/P2 of
the ADC and a clock input of suitable frequency is
available for ADC.
• Solution: The analog input I/P2 is used and therefore
address pins A,B,C should be 0,1,0 respectively to select
I/P2. The OE and ALE pins are already kept at +5V to
select the ADC and enable the outputs. Port C upper acts
as the input port to receive the EOC signal while port C
lower acts as the output port to send SOC to the ADC.

Converters (cont..)
• Port A acts as a 8-bit input data port to receive the digital
data output from the ADC. The 8255 control word is
written as follows:
D7 D6 D5 D4 D3 D2 D1 D0
10011000
• The required ALP is as follows:
MOV AL, 98h ;initialise 8255 as
OUT CWR, AL ;discussed above.
MOV AL, 02h ;Select I/P2 as analog
OUT Port B, AL ;input.

Converters (cont..)
MOV AL, 00h ;Give start of conversion
OUT Port C, AL ; pulse to the ADC
MOV AL, 01h
OUT Port C, AL
MOV AL, 00h
OUT Port C, AL
WAIT: IN AL, Port C ;Check for EOC by
RCR ; reading port C upper and
JNC WAIT ;rotating through carry.
IN AL, Port A ;If EOC, read digital equivalent
;in AL
HLT ;Stop.

Vref +
Vref +
CS + 5V
+ 5V Vcc Clock up
D0 – D7 PA7 – PA0 O7 – O0
Analog
PC7 EOC ADC I/P
A2
PC0 SOC
0808 Voltage
A1
OE GND
Reset 8255 +5V
ALE
A B C
IORD PB0
PB1
IOWR PB2
Interfacing 0808 with 8086

Interfacing Digital To Analog
Converters (cont..)
INTERFACING DIGITAL TO ANALOG CONVERTERS: The
digital to analog converters convert binary number into
their equivalent voltages. The DAC find applications in
areas like digitally controlled gains, motors speed
controls, programmable gain amplifiers etc.
AD 7523 8-bit Multiplying DAC : This is a 16 pin DIP,
multiplying digital to analog converter, containing R-2R
ladder for D-A conversion along with single pole double
thrown NMOS switches to connect the digital inputs to
the ladder.

OUT 1 1 16 RFB
OUT 2 2 15 Vref in
GND 3 14 V+
MSB B1 4 13 NC
AD 7523
B2 5 12 NC
B3 6 11 B8 LSB
B4 7 10 B7
B5 8 9 B6
Pin Diagram of AD 7523

Interfacing Digital to Analog Data
Converters (cont..) +5V
(MSB)
LSB
D0 D1 D2 D3
R1 R3 R5 R7
2R 2R 2R 2R 2R
2R
-
V0
R2 R4 R6 R8 +

Converters (cont..)
• The pin diagram of AD7523 is shown in fig the supply
range is from +5V to +15V, while Vref may be any where
between -10V to +10V. The maximum analog output
voltage will be any where between -10V to +10V, when all
the digital inputs are at logic high state.
• Usually a zener is connected between OUT1 and OUT2
to save the DAC from negative transients. An operational
amplifier is used as a current to voltage converter at the
output of AD to convert the current out put of AD to a
proportional output voltage.

Converters (cont..)
• It also offers additional drive capability to the DAC
output. An external feedback resistor acts to control the
gain. One may not connect any external feedback resistor,
if no gain control is required.
• EXAMPLE: Interfacing DAC AD7523 with an 8086
CPU running at 8MHZ and write an assembly language
program to generate a sawtooth waveform of period 1ms
with Vmax 5V.
• Solution: Fig shows the interfacing circuit of AD 74523
with 8086 using 8255. program gives an ALP to generate a
sawtooth waveform using circuit.

Example (cont..)

+5V +10V
15 14
16
RFB
PA7 MSB 4
OUT1 1 -
8255A VZ V0
LSB 2 +
PA 0 11 OUT2
AD7523
CS
GND
3
Fig: Interfacing of AD7523

Interfacing Digital to Analog Data
Converters (cont..)
• In the above program, port A is initialized as the output
port for sending the digital data as input to DAC. The
ramp starts from the 0V (analog), hence AL starts with
00H. To increment the ramp, the content of AL is
increased during each execution of loop till it reaches
F2H.
• After that the saw tooth wave again starts from 00H, i.e.
0V(analog) and the procedure is repeated. The ramp
period given by this program is precisely 1.000625 ms.
Here the count F2H has been calculated by dividing the
required delay of 1ms by the time required for the
execution of the loop once. The ramp slope can be
controlled by calling a controllable delay after the OUT
instruction. 395

Programmable Timer 8254
396
8254 Programming

8254 Programming
Each counter may be programmed with a count of 1 to

FFFFH.
Minimum count is 1 all modes except 2 and 3 with minimum count of
2.
Each counter has a program control word used to select the
way the counter operates.
If two bytes are programmed, then the first byte (LSB) stops the
count, and the second byte (MSB) starts the counter with the new
count.

8254 Read Back Command
 8254 Read Back Command
1 1 COUNT STATUS CNT2 CNT1 CNT0 0
 8254 status word format
NULL
OUTPUT COUNT RW1 RW0 M2 M1 M0 BCD
NULL COUNT: goes low when the new count written to a counter is
actually loaded into the counter

8254 Modes
Mode 0: An events counter enabled with G.
The output becomes a logic 0 when the control word is written and
remains there until N plus the number of programmed counts.
Mode 1: One-shot mode.

The G input triggers the counter to output a 0 pulse for `count'
clocks.
Counter reloaded if G is pulsed again.

8254 Modes
Mode 2: Counter generates a series of pulses 1 clock pulse wide.
The seperation between pulses is determined by the count.
The cycle is repeated until reprogrammed or G pin set to 0.
Mode 3: Generates a continuous square-wave with G set to 1.

If count is even, 50% duty cycle otherwise OUT is high 1 cycle longer.

8254 Modes
Mode 4: Software triggered one-shot
(G must be 1).
Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.

Overview
 Intel 8088 facts
 20 bit address bus allow accessing VDD (5V)
1 M memory locations
 16-bit internal data bus and 8-bit
external data bus. Thus, it need 20-bit
8-bit data
two read (or write) operations to address
read (or write) a 16-bit datum control 8088 control

 Byte addressable and byte-swapping signals

signals
To 8088 from 8088
Word: 5A2F
CLK
18001 5A High byte of word
GND
18000 2F Low byte of word
8088 signal classification
Memory locations
403
Dept. of ECE, ATMECE,
MYSURU
Organization of 8088
Address bus (20 bits)
AH AL General purpose
BH BL register 
CH CL
Execution Unit DH DL
(EU) Data bus
SP CS (16 bits)
Segment
BP register DS
SI SS
DI ALU Data bus ES
(16 bits)
IP
Bus
control
ALU Instruction Queue External bus
EU
control
Flag register
Bus Interface Unit (BIU)
404
General Purpose Registers
15 8 7 0
AX AH AL Accumulator
BX BH BL Base
Data Group
CX CH CL Counter
DX DH DL Data
SP Stack Pointer
BP Base Pointer
Pointer and
Index Group
SI Source Index
DI Destination Index
405
Arithmetic Logic Unit (ALU)
A B F Y
n bits n bits
0 0 0 A+B
Carry 0 0 1 A -B
0 1 0 A -1
Y= 0 ? F 0 1 1 A and B
1 0 0 A or B
A>B?
1 0 1 not A
     
Y
 Signal F control which function will be conducted by ALU.
 Signal F is generated according to the current instruction.
 Basic arithmetic operations: addition, subtraction, 

 Basic logic operations: and, or, xor, shifting,
406
Flag Register
 Flag register contains information reflecting the current status of a
microprocessor. It also contains information which controls the
operation of the microprocessor.
15 0
   OF DF IF TF SF ZF  AF  PF  CF
 Control Flags  Status Flags
IF: Interrupt enable flag CF: Carry flag

DF: Direction flag PF: Parity flag
TF: Trap flag AF: Auxiliary carry flag
ZF: Zero flag
SF: Sign flag
OF: Overflow flag
407
Instruction Machine Codes
 Instruction machine codes are binary numbers
 For Example:
1000100011000011 MOV AL, BL

Register
MOV
mode
 Machine code structure
Opcode Mode Operand1 Operand2
 Some instructions do not have operands, or have only one operand

 Opcode tells what operation is to be performed.
(EU control logic generates ALU control signals according to Opcode)
 Mode indicates the type of a instruction: Register type, or Memory type
 Operands tell what data should be used in the operation. Operands can
be addresses telling where to get data (or where to store results)
408
EU Operation
1. Fetch an instruction from instruction

queue AH AL General purpose
BH BL register
2. According to the instruction, EU control CH CL
logic generates control signals. DH DL
(This process is also referred to as instruction SP
BP
decoding) SI
DI ALU Data bus
3. Depending on the control signal, (16 bits)
EU performs one of the following
operations:
 An arithmetic operation ALU
EU
 A logic operation control instruction
Flag register 1011000101001010
 Storing a datum into a register
 Moving a datum from a register
 Changing flag register

Generating Memory Addresses
 How can a 16-bit microprocessor generate 20-bit memory addresses?
Left shift 4 bits

FFFFF
16-bit register 0000 Addr1 + 0FFFF

Segment
+ 16-bit register Offset Offset (64K)
Addr1
20-bit memory address Segment

address
00000
Intel 80x86 memory address generation 1M memory space
410
Memory Segmentation
 A segment is a 64KB block of memory starting from any 16-byte
boundary
 For example: 00000, 00010, 00020, 20000, 8CE90, and E0840 are all valid
segment addresses
 The requirement of starting from 16-byte boundary is due to the 4-bit
left shifting
 Segment registers in BIU

15 0
CS Code Segment
DS Data Segment
SS Stack Segment
ES Extra Segment
411
Memory Address Calculation
 Segment addresses must be stored 0000

Segment
in segment registers address
 Offset is derived from the combination + Offset
of pointer registers, the Instruction

Memory address
Pointer (IP), and immediate values
 Examples
CS 3 4 8 A 0 SS 5 0 0 0 0
IP + 4 2 1 4 SP + F F E 0
Instruction address 3 8 A B 4 Stack address 5 F F E 0
DS 1 2 3 4 0
DI + 0 0 2 2
Data address 1 2 3 6 2
412
Fetching Instructions
 Where to fetch the next instruction?
8088 Memory
CS 1 2 3 4
IP 0012 12352 MOV AL, 0
12352
 Update IP
— After an instruction is fetched, Register IP is updated as follows:
IP = IP + Length of the fetched instruction
— For Example: the length of MOV AL, 0 is 2 bytes. After fetching this instruction,
the IP is updated to 0014

Accessing Data Memory
 There is a number of methods to generate the memory address when
accessing data memory. These methods are referred to as
Addressing Modes
 Examples:
— Direct addressing: MOV AL, [0300H]
DS 1 2 3 4 0 (assume DS=1234H)
0 3 0 0
Memory address 1 2 6 4 0
— Register indirect addressing: MOV AL, [SI]
DS 1 2 3 4 0 (assume DS=1234H)
0 3 1 0 (assume SI=0310H)
Memory address 1 2 6 5 0

Reserved Memory Locations
 Some memory locations are reserved for special purposes.
Programs should not be loaded in these areas
FFFFF
 Locations from FFFF0H to FFFFFH Reset FFFF0
are used for system reset code instruction
area
 Locations from 00000H to 003FFH

Interrupt
are used for the interrupt pointer table
pointer
 It has 256 table entries table
 Each table entry is 4 bytes
003FF
256  4 = 1024 = memory addressing space
From 00000H to 003FFH 00000

Interrupts
 An interrupt is an event that occurs while the processor is executing a program
 The interrupt temporarily suspends execution of the program and switch the
processor to executing a special routine (interrupt service routine)
 When the execution of interrupt service routine is complete, the processor
resumes the execution of the original program
 Interrupt classification
Hardware Interrupts Software Interrupts
 Caused by activating the processor‟s  Caused by the execution of an INT

interrupt control signals (NMI, instruction
INTR)  Caused by an event which is
generated
by the execution of a program, such
as division by zero
 8088 can have 256 interrupts

Minimum and Maximum Operation modes
 Intel 8088 (8086) has two operation modes:

Architecture of NDP 8087-Overview
 Each processor in the 80x86 family has a

corresponding coprocessor with which it is compatible
 Math Coprocessor is known as
NPX,NDP,FUP. Numeric processor extension
(NPX),
Numeric data processor (NDP),
Floating point unit (FUP).

Compatible Processor and Coprocessor
Processors Coprocessors
1. 8086 & 8088 1. 8087
2. 80286 2. 80287,80287XL
3. 80386DX 3. 80287,80387DX
4. 80386SX 4. 80387SX
5. 80486DX 5. It is Inbuilt
6. 80486SX 6. 80487SX

Architecture of 8087
 Control Unit
 Execution Unit

Block Diagram of 8087
+5V
Vcc TAG
CLK 79 0 TAG
0 register
INT 8-register stack, each has 80 bits to
BHE/S7 TAG 7
Bus
tracking Floating point arithmetic module
AD15 - AD0 control
logic, Status Register 16 bit
A19/S6 A16/S3 instruction
queue Control Register
QS1-QS0
16 LBS of instruction address
RQ/GT0 4MSB inst address 0 11 LSB of op code
16 LSB of operand address
RQ/GT1
Busy 4 MSB of operand address 0
Ready vss
Reset Dept. of ECE, ATMECE, MYSURU 422
Block Diagram of 8087
Control Unit Numeric execution unit
Control word Exponent bus Fraction bus
Programm
Status word
able shifter
Exponent
Module interface
16
Data
Micro control 68 Arithmetic
buffer unit module
Data
16 64
Operand temporary
queue 16 register
7
Status Tag
Addressing 8 Register Stack
word
bus tracking
Exception 80 Bits
Address pointer 0
Control Unit
 Control unit: To synchronize the operation of the

coprocessor and the processor.
 This unit has a Control word and Status word and
Data Buffer
 If instruction is an ESCape (coprocessor) instruction,
the coprocessor executes it, if not the microprocessor
executes.

Status Register (cont..)
15 0
B C3 ST C2 C1 C0 ES PE UE OE ZE DE IE
• C3-C0 Condition code bits

• TOP Top-of-stack (ST)
• ES Error summary
• PE Precision error
• UE Under flow error
• OE Overflow error
• ZE Zero error
• DE Denormalized error
• IE Invalid error
• B Busy bit
 Status register reflects the over all operation of
the coprocessor.
 B-Busy bit indicates that coprocessor is busy executing a
task. Busy can be tested by examining the status or by
using the FWAIT instruction. Newer coprocessor
automatically synchronize with the microprocessor, so
busy flag need not be tested before performing
additional coprocessor tasks.
 C3-C0 Condition code bits indicates conditions about
the coprocessor.

 TOP- Top of the stack (ST) bit indicates the current
register address as the top of the stack.
 ES-Error summary bit is set if any unmasked error bit
(PE, UE, OE, ZE, DE, or IE) is set. In the 8087 the error
summary is also caused a coprocessor interrupt.
 PE- Precision error indicates that the result or
operand executes selected precision.
 UE-Under flow error indicates the result is too large to be
represent with the current precision selected by the
control word.

Status Register (contd..)
 OE-Over flow error indicates a result that is too large to

be represented. If this error is masked, the coprocessor
generates infinity for an overflow error.
 ZE-A Zero error indicates the divisor was zero while
the dividend is a non-infinity or non-zero number.
 DE-Denormalized error indicates at least one of
the operand is denormalized.
 IE-Invalid error indicates a stack overflow or underflow,
indeterminate from (0/0,0,-0, etc) or the use of a NAN
as an operand. This flag indicates error such as those
produced by taking the square root of a negative number.

Control Register
 Control register selects precision, rounding

control, infinity control.
 It also masks an unmasks the exception bits that
correspond to the rightmost Six bits of status register.
 Instruction FLDCW is used to load the value into the
control register.

15
Control Register
0
IC RC PC PM UM OM ZM DM IM
• IC Infinity control
• RC Rounding control
• PC Precision control
• PM Precision control
• UM Underflow mask
• OM Overflow mask
• ZM Division by zero mask
• DM Denormalized operand
• IM mask Invalid operand mask
Control Register (cont..)
 IC –Infinity control selects INFINITY CONTROL
either affine or projective
infinity. Affine allows 0 = Projective
positive and negative 1 = Affine
infinity, while projective
assumes infinity
is unsigned. ROUNDING CONTROL
 RC –Rounding control 00=Round to nearest or even
determines the type of 01=Round down towards minus infinity
rounding. 10=Round up towards plus infinity
11=Chop or truncate towards zero

MYSURU 1
Control Register
 PC- Precision control sets
the precision of he result as PRECISION CONTROL
define in table
 Exception Masks – It 00=Single precision (short)
Determines whether the error
01=Reserved
indicated by the exception
affects the error bit in the 10=Double precision (long)
status register. If a logic1 is 11=Extended precision
placed in one of the (temporary)
exception control bits,
corresponding status register
bit is masked off.

MYSURU 2
Numeric Execution Unit
 This performs all operations that access and manipulate

the numeric data in the coprocessor‟s registers.
 Numeric registers in NUE are 80 bits wide.
 NUE is able to perform arithmetic, logical and
transcendental operations as well as supply a small number
of mathematical constants from its on-chip ROM.
 Numeric data is routed into two parts ways
a 64 bit mantissa bus and
a 16 bit sign/exponent bus.

MYSURU 3
Circuit Connection for 8086 –
8087 (cont.)
INTR
8259A INT
8086 CPU
PIC CLK Multi
8086
RQ/GT1 master
Multi BUS System
IRn
QS0 QS1 TEST master INTER- bus
FACING
local
COMPO-
8284A
bus NENTS
QS 0 QS 1 BUSY
CLICK
RQ/GT0
GENERATOR
CLK
CLK 8087
INT RQ/GT 1

MYSURU 4
8087 (cont.)
 Multiplexed address-data bus lines are connected directly
from the 8086 to 8087.
 The status lines and the queue status lines connected
directly from 8086 to 8087.
 The Request/Grant signal RQ/GT0 of 8087 is connected to
RQ/GT1 of 8086.
 BUSY signal 8087 is connected to TEST pin of 8086.
 Interrupt output INT of the 8087 to NMI input of 8086.
This intimates an error condition.
MYSURU 5
8087 (cont.)
 The main purpose of the circuitry between the INT output
of 8087 and the NMI input is to make sure that an NMI
signal is not present upon reset, to make it possible to
mask NMI input and to make it possible for other
devices to
cause an NMI interrupt.
 BHE pin is connected to the system BHE line to enable
the upper bank of memory.
 The RQ/GT1 input is available so that another
coprocessor such as 8089 I/O processor can be connected
and function in parallel with the 8087.

MYSURU 6
8087 (cont.)
 One type of Cooperation between the two processors that
you need to know about it is how the 8087 transfers data
between memory and its internal registers.
 When 8086 reads an 8087 instruction that needs data from
memory or wants to send data to memory, the 8086 sends out
the memory address code in the instruction and sends out the
appropriate memory read or memory write signal to transfer a
word of data.

MYSURU 7
8087 (cont.)
 In the case of memory read, the addressed word will be
kept on the data bus by the memory. The 8087 then
simply reads the word of data bus. The 8086 ignores this
word .If the 8087 only needs this one word of data, it
can then go on and executes its instruction.
 Some 8087 instructions need to read in or write out up
to 80-bit word. For these cases
8086 outputs the address of the first data word on the
address bus and outputs the appropriate control signal.

MYSURU 8
8087 (cont.)
 The 8087 reads the data word on the data bus by memory or
writes a data word to memory on the data bus. The 8087 grabs
the 20-bit physical address that was output by the 8086.To
transfer additional words it needs to/from memory, the 8087
then takes over the buses from 8086.
 To take over the bus, the 8087 sends out a low-going pulse on
RQ/GT0 pin. The 8086 responds to this by sending another low
going pulse back to the RQ/GT0 pin of 8087 and by floating

its buses.

MYSURU 9
8087 (cont.)
 The 8087 then increments the address it grabbed during the
first transfer and outputs the incremented address on the
address bus. When the 8087 output a memory read or memory
write signal, another data word will be transferred to or from
the 8087.
 The 8087 continues the process until it has transferred all
the data words required by the instruction to/from memory.

MYSURU 0
8087 (cont.)
 When the 8087 is using the buses for its data transfer, it
sends another low-going pulse out on its RQ/ GT0 pin

to 8086 to know it can have the buses back again.
The next type of the synchronization between the host
processor and the coprocessor is that required to make sure the
8086 hast does not attempt to execute the next instruction before
the 8087 has completed an instruction.

MYSURU 1
8087 (cont.)
 Taking one situation, in the case where the 8086 needs the
data produced by the execution of an 8087 instruction to carry
out its next instruction.
 In the instruction sequence for example the 8087 must
complete the FSTSW STATUS instruction before the 8086
will have the data it needs to execute the
MOV AX , STATUS instruction.
 Without some mechanism to make the 8086 wait until the
8087 completes the FSTSW instruction, the 8086 will go on
and execute the MOV AX , STATUS with erroneous data .
 We solve this problem by connecting the 8087 BUSY output
to the TEST pin of the 8086 and putting on the WAIT
instruction in the program.

MYSURU 2
8087 (cont.)
 While 8087 is executing an instruction it asserts its BUSY
pin high. When it is finished with an instruction,
the 8087 will drop its BUSY pin low. Since the BUSY pin
from 8087 is connected to the TEST pin 8086 the processor
can check its pin of 8087 whether it finished it instruction or
not.
 You place the 8086 WAIT instruction in your program after
the 8087 FSTSW instruction .When 8086 executes the WAIT
instruction it enters an internal loop where it repeatedly checks
the logic level on the TEST input. The 8086 will stay in this
loop until it finds the TEST input asserted low, indicating the
8087 has completed its instruction. The 8086 will then exit the
internal loop, fetch and execute the next instruction.
MYSURU 3
Example (cont..)
FSTSW STATUS ;copy 8087 status word to memory

MOV AX, STATUS ;copy status word to AX to check
; bits
(a)
 In this set of instructions we are not using WAIT instruction.

Due to this the flow of execution of command will takes
place continuously even
though the previous instruction had not finished it‟s
completion of its work .so we may lost data .

MYSURU 4
Example (cont..)
FSTSW STATUS ;copy 8087 status word to memory
FWAIT ;wait for 8087 to finish before-
; doing next 8086 instruction
MOV AX,STATUS ;copy status word to AX to check
; bits
(b)
 In this code we are adding up of FWAIT instruction so that it

will stop the execution of the command until the above
instruction is finishes it‟s work .so that you are not loosing
data and after that you will allow to continue the execution of
instructions.

MYSURU 5
8087 (cont.)
 Another case where you need synchronization of the
processor and the coprocessor is the case where a program
has several 8087 instructions in sequence.
 The 8087 are executed only one instruction at a time so you
have to make sure that 8087 has completed one instruction
before you allow the 8086 to fetch the next 8087 instruction
from memory.
 Here again you use the BUSY-TEST connection and the
FWAIT instruction to solve the problem. If you are hand
coding, you can just put the 8086 WAIT(FWAIT) instruction
after each instruction to make sure that instruction is
completed before going on to next.

MYSURU 6
Circuit Connection for 8086 – 8087
 If you are using the assembler which accepts 8087

mnemonics, the assembler will automatically insert the 8-bit
code for the WAIT instruction ,10011011 binary (9BH), as the
first byte of the code for 8087 instruction.

MYSURU 7
Interfacing ( cont..)
 Multiplexed address-data bus lines are connected directly
from the 8086 to 8087.
 The status lines and the queue status lines connected
directly from 8086 to 8087.
 The Request/Grant signal RQ/GT0 of 8087 is connected to
RQ/GT1 of 8086.
 BUSY signal 8087 is connected to TEST pin of 8086.
 Interrupt output INT of the 8087 to NMI input of 8086.
This intimates an error condition.
 A WAIT instruction is passed to keep looking at its TEST pin,
until it finds pin Low to indicates that the 8087 has completed
the computation.
MYSURU 8
Von Neumann and Harvard architecture
449
Interfacing
 SYNCHRONIZATION must be established between the
processor and coprocessor in two situations.
a) The execution of an ESC instruction that require the
participation of the NUE must not be initiated if the NUE
has not completed the execution of the previous instruction.
b) When a processor instruction accesses a memory
location that is an operand of a previous coprocessor
instruction .In this case CPU must synchronize with NPX
to ensure that it has completed its instruction.
Processor WAIT instruction is provided.

MYSURU 0
RISC/CISC Architecture
• 1950s IBM instituted a research program
• 1964 Release of System/360
• Mid-1970s improved measurement tools demonstrated on CISC
• 1975 801 project initiated at IBM’s Watson Research Center
• 1979 32-bit RISC microprocessor (801) developed led by Joel Birnbaum
• 1984 MIPS developed at Stanford, as well as projects done at Berkeley
• 1988 RISC processors had taken over high-end of the workstation market
• Early 1990s IBM’s POWER (Performance Optimization With Enhanced RISC)
architecture introduced w/ the RISC System/6k
– AIM (Apple, IBM, Motorola) alliance formed, resulting in PowerPC

What is CISC?
• CISC is an acronym for Complex Instruction Set Computer and are chips that are
easy to program and which make efficient use of memory. Since the earliest
machines were programmed in assembly language and memory was slow and
expensive, the CISC philosophy made sense, and was commonly implemented in
such large computers as the PDP-11 and the DECsystem 10 and 20 machines.
• Most common microprocessor designs such as the Intel 80x86 and Motorola 68K
series followed the CISC philosophy.
• But recent changes in software and hardware technology have forced a re-
examination of CISC and many modern CISC processors are hybrids, implementing
many RISC principles.
• CISC was developed to make compiler development simpler. It shifts most of the
burden of generating machine instructions to the processor. For example, instead
of having to make a compiler write long machine instructions to calculate a
square-root, a CISC processor would have a built-in ability to do this.

CISC Attributes
The design constraints that led to the development of CISC (small amounts of slow
memory and fact that most early machines were programmed in assembly
language) give CISC instructions sets some common characteristics:
• A 2-operand format, where instructions have a source and a destination. Register
to register, register to memory, and memory to register commands. Multiple
addressing modes for memory, including specialized modes for indexing through
arrays
• Variable length instructions where the length often varies according to the
addressing mode
• Instructions which require multiple clock cycles to execute.
E.g. Pentium is considered a modern CISC processor

Most CISC hardware architectures have several characteristics in common:
• Complex instruction-decoding logic, driven by the need for a single
instruction to support multiple addressing modes.
• A small number of general purpose registers. This is the direct result of
having instructions which can operate directly on memory and the limited
amount of chip space not dedicated to instruction decoding, execution,
and microcode storage.
• Several special purpose registers. Many CTSC designs set aside special
registers for the stack pointer, interrupt handling, and so on. This can
simplify the hardware design somewhat, at the expense of making the
instruction set more complex.
• A 'Condition code" register which is set as a side-effect of most
instructions. This register reflects whether the result of the last operation
is less than, equal to, or greater than zero and records if certain error
conditions occur.

At the time of their initial development, CISC machines used available
technologies to optimize computer performance.
• Microprogramniing is as easy as assembly language to implement, and
much less expensive than hardwiring a control unit.
• The ease of microcoding new instructions allowed designers to make CISC
machines upwardly compatible: a new computer could run the same
programs as earlier computers because the new computer would contain
a superset of the instructions of the earlier computers.
• As each instruction became more capable, fewer instructions could be
used to implement a given task. This made more efficient use of the
relatively slow main memory.
• Because microprogram instruction sets can be written to match the
constructs of high-level languages, the compiler does not have to be as
complicated.

CISC Disadvantages
Designers soon realised that the CISC philosophy had its own problems, including:
• Earlier generations of a processor family generally were contained as a subset in
every new version - so instruction set & chip hardware become more complex with
each generation of computers.
• So that as many instructions as possible could be stored in memory with the least
possible wasted space, individual instructions could be of almost any length - this
means that different instructions will take different amounts of clock time to
execute, slowing down the overall performance of the machine.
• Many specialized instructions aren't used frequently enough to justify their
existence -approximately 20% of the available instructions are used in a typical
program.
• CISC instructions typically set the condition codes as a side effect of the
instruction. Not only does setting the condition codes take time, but programmers
have to remember to examine the condition code bits before a subsequent
instruction changes them.

What is RISC?
• RISC?
RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture
that utilizes a small, highly-optimized set of instructions, rather than a more
specialized set of instructions often found in other types of architectures.
• History
The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s
and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all
designed with a similar philosophy which has become known as RISC. Certain
design features have been characteristic of most RISC processors:
– one cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle.
This is due to the optimization of each instruction on the CPU and a technique called
PIPELINING
– pipelining: a techique that allows for simultaneous execution of parts, or stages, of
instructions to more efficiently process instructions;
– large number of registers: the RISC design philosophy generally incorporates a larger
number of registers to prevent in large amounts of interactions with memory

RISC Attributes
The main characteristics of CISC microprocessors are:
• Extensive instructions.
• Complex and efficient machine instructions.
• Microencoding of the machine instructions.
• Extensive addressing capabilities for memory operations.
• Relatively few registers.
In comparison, RISC processors are more or less the opposite of the above:
• Reduced instruction set.
• Less complex, simple instructions.
• Hardwired control unit and machine instructions.
• Few addressing schemes for memory operands with only two basic instructions,
LOAD and
• STORE
• Many symmetric registers which are organised into a register file.

Pipelining
RISC Pipelines
A RISC processor pipeline operates in much the same way, although the
stages in the pipeline are different. While different processors have
different numbers of steps, they are basically variations of these five,
used in the MIPS R3000 processor:
- fetch instructions from memory
- read registers and decode the instruction
- execute the instruction or calculate an address
- access an operand in data memory
- write the result into a register

RISC Disadvantages
• There is still considerable controversy among experts about the ultimate
value of RISC architectures. Its proponents argue that RISC machines are
both cheaper and faster, and are therefore the machines of the future.
• However, by making the hardware simpler, RISC architectures put a
greater burden on the software. Is this worth the trouble because
conventional microprocessors are becoming increasingly fast and cheap
anyway?

CISC versus RISC
CISC RISC
Emphasis on hardware Emphasis on software

Includes multi-clock Single-clock,
complex instructions reduced instruction only
Memory-to-memory: Register to register:
"LOAD" and "STORE" "LOAD" and "STORE"
incorporated in instructions are independent instructions
Small code sizes, Low cycles per second,
high cycles per second large code sizes
Transistors used for storing Spends more transistors
complex instructions on memory registers

Summation
• As memory speed increased, and high-level languages displaced assembly
language, the major reasons for CISC began to disappear, and computer designers
began to look at ways computer performance could be optimized beyond just
making faster hardware.
• One of their key realizations was that a sequence of simple instructions produces
the same results as a sequence of complex instructions, but can be implemented
with a simpler (and faster) hardware design. (Assuming that memory can keep up.)
RISC (Reduced Instruction Set Computers) processors were the result.
• CISC and RISC implementations are becoming more and more alike. Many of
today’s RISC chips support as many instructions as yesterday's CISC chips. And
today's CISC chips use many techniques formerly associated with RISC chips.
• To some extent, the argument is becoming moot because CISC and RISC
implementations are becoming more and more alike. Many of today's RISC chips
support as many instructions as yesterday's CISC chips. And today's CISC chips use
many techniques formerly associated with RISC chips.

Modern Day Advancement
• CISC and RISC Convergence
State of the art processor technology has changed significantly since RISC
chips were first introduced in the early '80s. Because a number of
advancements are used by both RISC and CISC processors, the lines
between the two architectures have begun to blur. In fact, the two
architectures almost seem to have adopted the strategies of the other.
Because processor speeds have increased, CISC chips are now able to
execute more than one instruction within a single clock. This also allows
CISC chips to make use of pipelining. With other technological
improvements, it is now possible to fit many more transistors on a single
chip.

• This gives RISC processors enough space to incorporate more complicated,
CISC-like commands. RISC chips also make use of more complicated
hardware, making use of extra function units for superscalar execution. All
of these factors have led some groups to argue that we are now in a "post-
RISC" era, in which the two styles have become so similar that
distinguishing between them is no longer relevant. However, it should be
noted that RISC chips still retain some important traits. RISC chips stricly
utilize uniform, single-cycle instructions. They also retain the register-to-
register, load/store architecture. And despite their extended instruction
sets, RISC chips still have a large number of general purpose registers.


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MICROPROCESSORS

Dept. of ECE, ATMECE, MYSURU 1

 It can prefetches up to 6 instruction bytes from

 It requires +5V power supply.

 A 40 pin dual in line package.

 Address ranges from 00000H to FFFFFH

 Memory is byte addressable - Every byte has a

Dept. of ECE, ATMECE, MYSURU 4

Dept. of ECE, ATMECE, MYSURU 5

Dept. of ECE, ATMECE, MYSURU 6

• Decodes instructions fetched by the BIU

The main parts are:

Dept. of ECE, ATMECE, MYSURU 7

AH Byte multiply, byte divide

BX Store address information

CX String operation, loops

CL Variable shift and rotate

DX Word multiply, word divide, indirect I/O

Dept. of ECE, ATMECE, MYSURU 10

• DI: Destination Index register

• The SI and the DI registers may also be used to access

• A flag is a flip flop which indicates some conditions

Sign Auxiliary Carry

Parity (PF) PF=0;odd parity, PF=1;even parity.

Dept. of ECE, ATMECE, MYSURU 14

Dept. of ECE, ATMECE, MYSURU 16

• This queue permits pre-fetch of up to 6 bytes of

Dept. of ECE, ATMECE, MYSURU 17

• After a byte is loaded at the input end of the queue, it

• The EU accesses the queue from the output end. It

• The intervals of no bus activity, which may occur

The CPU 8086 is able to address

Dept. of ECE, ATMECE, MYSURU 19

– Code segment is used for storing the instructions.

* In the assembly language programming, more than one

Advantages of Segmented memory Scheme

Dept. of ECE, ATMECE, MYSURU 22

Each segment register store the upper

Dept. of ECE, ATMECE, MYSURU 25

Dept. of ECE, ATMECE, MYSURU 27

• If the data segment starts at location 1000h and

Required Address 0001 0000 0000 0010 1001

Dept. of ECE, ATMECE, MYSURU 28

• DS:DI (for other than string operations)

• ES:DI (for string operations)

Dept. of ECE, ATMECE, MYSURU 29

Dept. of ECE, ATMECE, MYSURU 30

Dept. of ECE, ATMECE, MYSURU 31

Dept. of ECE, ATMECE, MYSURU 32

Dept. of ECE, ATMECE, MYSURU 33

2. Immediate addressing mode

Dept. of ECE, ATMECE, MYSURU 35

Dept. of ECE, ATMECE, MYSURU 36

+ = 20-bit physical address

Dept. of ECE, ATMECE, MYSURU 37

• The effective address of memory operand

Dept. of ECE, ATMECE, MYSURU 38

Dept. of ECE, ATMECE, MYSURU 39