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Opamp 68571
Opamp 68571
5 –90
Hz
4
–100
INPUT VOLTAGE NOISE – nV/
0.001
3
THD – dB
THD – %
–110 0.0003
–120 0.0001
1
MEASUREMENT
LIMIT
0 –130
10 100 1k 10k 100k 1M 10M 100 300 1k 3k 10k 30k 100k 300k
FREQUENCY – Hz FREQUENCY – Hz
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
AD797–SPECIFICATIONS (@ T = +258C and V = 615 V dc, unless otherwise noted)
A S
AD797A/S1 AD797B
Model Conditions VS Min Typ Max Min Typ Max Units
–2– REV. C
AD797
ABSOLUTE MAXIMUM RATINGS 1 3
The AD797’s inputs are protected by back-to-back diodes. To achieve low noise,
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V internal current limiting resistors are not incorporated into the design of this
amplifier. If the differential input voltage exceeds ± 0.7 V, the input current should
Internal Power Dissipation @ +25°C2 be limited to less than 25 mA by series protection resistors. Note, however, that this
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS will degrade the low noise performance of the device.
Differential Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . ± 0.7 V
Output Short Circuit Duration . . . . . . . Indefinite Within max ESD SUSCEPTIBILITY
Internal Power Dissipation ESD (electrostatic discharge) sensitive device. Electrostatic
Storage Temperature Range (Cerdip) . . . . . . –65°C to +150°C charges as high as 4000 volts, which readily accumulate on the
Storage Temperature Range (N, R Suffix) . . –65°C to +125°C human body and on test equipment, can discharge without
Operating Temperature Range detection. Although the AD797 features proprietary ESD pro-
AD797A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C tection circuitry, permanent damage may still occur on these
AD797S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C devices if they are subjected to high energy electrostatic dis-
Lead Temperature Range (Soldering 60 sec) . . . . . . . +300°C charges. Therefore, proper ESD precautions are recommended
NOTES to avoid any performance degradation or loss of functionality.
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only, and functional ORDERING GUIDE
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute Temperature Package Package
maximum rating conditions for extended periods may affect device reliability. Model Range Description Option
2
Internal Power Dissipation:
8-Pin SOIC = 0.9 Watts (T A–25°C)/θJA AD797AN –40°C to +85°C 8-Pin Plastic DIP N-8
8-Pin Plastic DIP and Cerdip = 1.3 Watts – (T A–25°C)/θJA AD797BN –40°C to +85°C 8-Pin Plastic DIP N-8
Thermal Characteristics AD797BR –40°C to +85°C 8-Pin Plastic SOIC SO-8
8-Pin Plastic DIP Package: θJA = 95°C/W AD797BR-REEL –40°C to +85°C 8-Pin Plastic SOIC SO-8
8-Pin Cerdip Package: θJA = 110°C/W
AD797BR-REEL7 –40°C to +85°C 8-Pin Plastic SOIC SO-8
8-Pin Small Outline Package: θJA = 155°C/W
AD797AR –40°C to +85°C 8-Pin Plastic SOIC SO-8
AD797AR-REEL –40°C to +85°C 8-Pin Plastic SOIC SO-8
AD797AR-REEL7 –40°C to +85°C 8-Pin Plastic SOIC SO-8
5962-9313301MPA –55°C to +125°C 8-Pin Cerdip Q-8
METALIZATION PHOTO
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
NOTE
The AD797 has double layer metal. Only one layer is shown here for clarity.
REV. C –3–
AD797–Typical Characteristics
20
INPUT COMMON-MODE RANGE – ±Volts
10
0
0 5 10 15 20
HORIZONTAL SCALE – 5 sec/DIV
SUPPLY VOLTAGE – ±Volts
20 0.0
OUTPUT VOLTAGE SWING – ±Volts
10 –1.0
+VOUT
–V OUT
5 –1.5
0 –2.0
0 5 10 15 20 –60 –40 –20 0 20 40 60 80 100 120 140
SUPPLY VOLTAGE – ±Volts TEMPERATURE – °C
Figure 2. Output Voltage Swing vs. Supply Figure 5. Input Bias Current vs. Temperature
30 140
OUTPUT VOLTAGE SWING – Volts p-p
VS = ±15V 120
20
100
SOURCE CURRENT
SINK CURRENT
80
10
V S = ±5V
60
40
0
10 100 1k 10k –60 –40 –20 0 20 40 60 80 100 120 140
LOAD RESISTANCE – Ω TEMPERATURE – °C
–4– REV. C
AD797
11 140
QUIESCENT SUPPLY CURRENT – mA
80 125
+25°C
8 CMR
60 100
7
40 75
–55°C
6 20 50
0 5 10 15 20 1 10 100 1k 10k 100k 1M
SUPPLY VOLTAGE – ±Volts FREQUENCY – Hz
Figure 7. Quiescent Supply Current vs. Supply Voltage Figure 10. Power Supply and Common-Mode Rejection
vs. Frequency
–60
12
FREQ = 1kHz RL = 600 Ω
G = +10
RL = 600Ω
FREQ = 10kHz
OUTPUT VOLTAGE – Volts rms
G = +10
NOISE BW = 100kHz
9
THD + NOISE – dB
–80
6 VS = ±5V
–100
3 VS = ±15V
0 –120
0 ±5 ±10 ±15 ±20 0.01 0.1 1.0 10
SUPPLY VOLTAGE – Volts OUTPUT LEVEL – Volts
Figure 8. Output Voltage vs. Supply for 0.01% Distortion Figure 11. Total Harmonic Distortion (THD) + Noise vs.
Output Level
1.0 30
±15V SUPPLIES
RL = 600 Ω
0.8
0.0015%
SETTLING TIME – µs
20
0.6
0.01%
0.4
10
±5V SUPPLIES
0.2
0.0 0
0 2 4 6 8 10 10k 100k 1M 10M
STEP SIZE – Volts
Figure 9. Settling Time vs. Step Size (± ) Figure 12. Large Signal Frequency Response
REV. C –5–
AD797–Typical Characteristics
5 35 120
4 GAIN/BANDWIDTH PRODUCT
30 110
INPUT VOLTAGE NOISE – nV/
2
SLEW RATE
FALLING EDGE
20 90
1
0 15 80
10 100 1k 10k 100k 1M 10M –60 –40 –20 0 20 40 60 80 100 120 140
FREQUENCY – Hz TEMPERATURE – °C
Figure 13. Input Voltage Noise Spectral Density Figure 16. Slew Rate & Gain/Bandwidth Product vs.
Temperature
120 +100 160
PHASE MARGIN
RS*
WITH RS*
OPEN-LOOP GAIN – dB
OPEN-LOOP GAIN – dB
80 +60 140
60 +40
GAIN
40 +20 120
WITHOUT
*RS = 100Ω RS*
20 0
SEE FIGURE 22
WITH RS*
0 100
100 1k 10k 100k 1M 10M 100M 100 1k 10k
FREQUENCY – Hz LOAD RESISTANCE – Ohms
Figure 14. Open-Loop Gain & Phase vs. Frequency Figure 17. Open-Loop Gain vs. Resistive Load
300 100
MAGNITUDE OF OUTPUT IMPEDANCE – Ohms
INPUT OFFSET CURRENT – nA
OVER COMPENSATED
150 10
* SEE FIGURE 29
0 1
WITHOUT CN*
–150 0.1
UNDER COMPENSATED
WITH CN*
–300 0.01
–60 –40 –20 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1M
TEMPERATURE – °C FREQUENCY – Hz
Figure 15. Input Offset Current vs. Temperature Figure 18. Magnitude of Output Impedance vs. Frequency
–6– REV. C
AD797
20pF
1µs 50mV 100ns
AD797 6 VOUT
3 4 10 10
** 0% 0%
5V
–VS
** SEE FIGURE 32
Figure 19. Inverter Figure 20. Inverter Large Signal Figure 21. Inverter Small Signal
Connection Pulse Response Pulse Response
100Ω
5V 1µs 50mV 100ns
+V S
100 100
**
90 90
2 7
VOUT
RS* AD797 6
V IN 3 4 600Ω
**
10 10
–VS 0% 0%
Figure 22. Follower Figure 23. Follower Large Signal Figure 24. Follower Small Signal
Connection Pulse Response Pulse Response
100 100
90 90
Figure 25. 16-Bit Settling Time Figure 26. 16-Bit Settling Time
Positive Input Pulse Negative Input Pulse
REV. C –7–
AD797
THEORY OF OPERATION This matching benefits not just dc precision but since it holds
The new architecture of the AD797 was developed to overcome up dynamically, both distortion and settling time are also
inherent limitations in previous amplifier designs. Previous pre- reduced. This single stage has a voltage gain of >5 × 106 and
cision amplifiers used three stages to ensure high open-loop VOS <80 µV, while at the same time providing THD + noise of
gain, Figure 27b, at the expense of additional frequency com- less than –120 dB and true 16 bit settling in less than 800 ns.
pensation components. Slew rate and settling performance are The elimination of second stage noise effects has the additional
usually compromised, and dynamic performance is not ad- benefit of making the low noise of the AD797 (<0.9 nV/√Hz)
equate beyond audio frequencies. As can be seen in Figure 27b, extend to beyond 1 MHz. This means new levels of perfor-
the first stage gain is rolled off at high frequencies by the com- mance for sampled data and imaging systems. All of this perfor-
pensation network. Second stage noise and distortion will then mance as well as load drive in excess of 30 mA are made
appear at the input and degrade performance. The AD797 on possible by Analog Devices’ advanced Complementary Bipolar
the other hand, uses a single ultrahigh gain stage to achieve dc (CB) process.
as well as dynamic precision. As shown in the simplified sche- Another unique feature of this circuit is that the addition of a
matic (Figure 28), nodes A, B, and C all track in voltage forcing single capacitor, CN (Figure 28), enables cancellation of distor-
the operating points of all pairs of devices in the signal path to tion due to the output stage. This can best be explained by
match. By exploiting the inherent matching of devices fabricated referring to a simplified representation of the AD797 using ide-
on the same IC chip, high open-loop gain, CMRR, PSRR, and alized blocks for the different circuit elements (Figure 29).
low VOS are all guaranteed by pairwise device matching (i.e.,
NPN to NPN & PNP to PNP), and not absolute parameters A single equation yields the open-loop transfer function of this
such as beta and early voltage. amplifier, solving it (at Node B) yields:
VO gm
=
V IN CN C
gm BUFFER VOUT jω – CN jω – C jω
A A
R1 C1 RL
gm = the transconductance of Q1 and Q2
A = the gain of the output stage, (~1)
GAIN = gmR1 ≈ 5 x 10 6 VO = voltage at the output
a. VIN = differential input voltage
When CN is equal to CC this gives the ideal single pole op amp
C2 response:
VO gm
=
VIN jωC
gm A2 A3 BUFFER VOUT
R1 RL
The terms in A, which include the properties of the output
C1
stage such as output impedance and distortion, cancel by
R2 simple subtraction, and therefore the distortion cancellation
GAIN = gmR1 *A2 *A3 does not affect the stability or frequency response of the ampli-
fier. With only 500 µA of output stage bias the AD797 delivers
b. a 1 kHz sine wave into 600 Ω at 7 V rms with only 1 ppm of
Figure 27. Model of AD797 vs. That of a Typical distortion.
Three-Stage Amplifier
VCC
I1 I2 CN
R2 R3 CN
R1 I5
Q4 A B
Q3 Q7 Q10 OUT
A
A B
OUT
Q9 +IN –IN CURRENT CC
–IN Q1 Q2 MIRROR
+IN Q12 Q8
Q1 Q2 Q5 Q6 CC
Q11
1
I6 I3 C I4
C
I1 I7 I4
VSS
Figure 29. AD797 Block Diagram
Figure 28. AD797 Simplified Schematic
–8– REV. C
AD797
NOISE AND SOURCE IMPEDANCE CONSIDERATIONS LOW FREQUENCY NOISE
The AD797’s ultralow voltage noise of 0.9 nV/√Hz is achieved Analog Devices specifies low frequency noise as a peak to peak
with special input transistors running at nearly 1 mA of collector (p-p) quantity in a 0.1 Hz to 10 Hz bandwidth. Several tech-
current. It is important then to consider the total input referred niques can be used to make this measurement. The usual tech-
noise (eNtotal), which includes contributions from voltage noise nique involves amplifying, filtering, and measuring the amplifiers
(eN), current noise (iN), and resistor noise (√4 kTrS). noise for a predetermined test time. The noise bandwidth of the
eNtotal = [eN2 + 4 kTrS + 4 (iNrS)2]l/2 Equation 1 filter is corrected for and the test time is carefully controlled
since the measurement time acts as an additional low frequency
where rS = total input source resistance. roll-off.
This equation is plotted for the AD797 in Figure 30. Since opti- The plot in Figure 4 was made using a slightly different tech-
mum dc performance is obtained with matched source resis- nique. Here an FFT based instrument (Figure 31) is used to
tances, this case is considered even though it is clear from generate a 10 Hz “brickwall” filter. A low frequency pole at
Equation 1 that eliminating the balancing source resistance will 0.1 Hz is generated with an external ac coupling capacitor, the
lower the total noise by reducing the total rS by a factor of two. instrument being dc coupled.
At very low source resistance (rS <50 Ω), the amplifiers’ voltage Several precautions are necessary to get optimum low frequency
noise dominates. As source resistance increases the Johnson noise performance:
noise of rS dominates until at higher resistances (rS >2 kΩ) the
current noise component is larger than the resistor noise. 1. Care must be used to account for the effects of rS, even a
10 Ω resistor has 0.4 nV/√Hz of noise (an error of 9% when
100 root sum squared with 0.9 nV/√Hz).
2. The test set up must be fully warmed up to prevent eOS drift
from erroneously contributing to input noise.
3. Circuitry must be shielded from air currents. Heat flow out
10 TOTAL NOISE
of the package through its leads creates the opportunity for a
Hz
RESISTOR
Selective heating and cooling of these by random air currents
NOISE will appear as 1/f noise and obscure the true device noise.
ONLY
1 4. The results must be interpreted using valid statistical
techniques.
100kΩ
0.1
10 100 1000 10000 +VS
**
SOURCE RESISTANCE – Ω
1Ω
Figure 30. Noise vs. Source Resistance 2 7 1.5µF HP 3465
DYNAMIC SIGNAL
The AD797 is the optimum choice for low noise performance AD797 6 ANALYZER
VOUT
provided the source resistance is kept <1 kΩ. At higher values of 3 4
(10Hz)
source resistance, optimum performance with respect to noise **
Table I. Recommended Amplifiers for Different Source Figure 31. Test Setup for Measuring 0.1 Hz to 10 Hz Noise
Impedances
WIDEBAND NOISE
rS, ohms Recommended Amplifier The AD797, due to its single stage design, has the property that
its noise is flat over frequencies from less than 10 Hz to beyond
0 to <1 k AD797
1 MHz. This is not true of most dc precision amplifiers where
1 k to <10 k AD707, AD743/AD745, OP27/OP37, OP07
second stage noise contributes to input referred noise beyond
10 k to <100 k AD705, AD743/AD745, OP07
the audio frequency range. The AD797 offers new levels of per-
>100 k AD548, AD549, AD645, AD711, AD743/
formance in wideband imaging applications. In sampled data
AD745
systems, where aliasing of out of band noise into the signal band
is a problem, the AD797 will out perform all previously avail-
able IC op amps.
REV. C –9–
AD797
BYPASSING CONSIDERATIONS follower. Operation on 5 volt supplies allows the use of a 100 Ω
To take full advantage of the very wide bandwidth and dynamic or less feedback network (R1 + R2). Since the AD797 shows
range capabilities of the AD797 requires some precautions. no unusual behavior when operating near its maximum rated
First, multiple bypassing is recommended in any precision current, it is suitable for driving the AD600/AD602 (Figure 47)
application. A 1.0 µF–4.7 µF tantalum in parallel with 0.1 µF while preserving their low noise performance.
ceramic bypass capacitors are sufficient in most applications. Optimum flatness and stability at noise gains >1 sometimes
When driving heavy loads a larger demand is placed on the sup- requires a small capacitor (CL) connected across the feedback
ply bypassing. In this case selective use of larger values of tanta- resistor (R1, Figure 35). Table II includes recommended values
lum capacitors and damping of their lead inductance with small of CL for several gains. In general, when R2 is greater than
value (1.1 Ω to 4.7 Ω) carbon resistors can be an improvement. 100 Ω and CL is greater than 33 pF, a 100 Ω resistor should
Figure 32 summarizes bypassing recommendations. The symbol be placed in series with CL. Source resistance matching is
(**) is used throughout this data sheet to represent the parallel assumed, and the AD797 should never be operated with unbal-
combination of a 0.1 µF and a 4.7 µF capacitor. anced source resistance >200 kΩ/G.
VS VS CL
VIN 3 4
Figure 32. Recommended Power Supply Bypassing ** 600 Ω
CS*
–VS
THE NONINVERTING CONFIGURATION
Ultralow noise requires very low values of rBB’ (the internal * SEE TEXT
parasitic resistance) for the input transistors (≈6 Ω). This im- ** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
plies very little damping of input and output reactive interac- Figure 34. Alternative Voltage Follower Connection
tions. With the AD797, additional input series damping is
required for stability with direct input to output feedback. A CL
100 Ω resistor in the inverting input (Figure 33) is sufficient;
the 100 Ω balancing resistor (R2) is recommended, but is not R2
required for stability. The noise penalty is minimal (eNtotal
≈2.1 nV/√Hz), which is usually insignificant. Best response +VS
flatness is obtained with the addition of a small capacitor **
(CL < 33 pF) in parallel with the 100 Ω resistor (Figure 34). R1
2 7
The input source resistance and capacitance will also affect the
response slightly and experimentation may be necessary for best AD797 6 VOUT
results. VIN 3 4
** RL
R1
100Ω –VS
–10– REV. C
AD797
20–120pF 100 Ω DRIVING CAPACITIVE LOADS
The capacitive load driving capabilities of the AD797 are dis-
R1
played in Figure 38. At gains over 10 usually no special precau-
+VS
tions are necessary. If more drive is desirable the circuit in
** Figure 39 should be used. Here a 5000 pF load can be driven
IIN
cleanly at any noise gain ≥ 2.
2 7
3 4
** 600 Ω
* SEE TEXT
1nF
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
CL 200pF 100 Ω
+VS
R2 **
1k Ω
+VS 2 7
** VIN 33 Ω
R1 AD797 6 VOUT
2 7 C1
3 4
VIN **
AD797 6 VOUT
3 4 –VS
** RL
RS* ** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
–VS
Figure 39. Recommended Circuit for Driving a High
* SEE TEXT Capacitance Load
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
REV. C –11–
AD797
TO TEKTRONIX R1
7A26
OSCILLOSCOPE 1M Ω 20pF 50pF
PREAMP INPUT
SECTION
226 Ω R2
4.26k Ω
2 8
(VIA LESS THAN 1FT
50Ω COAXIAL CABLE) AD797 6
2
A2 250ΩΩ VERROR X 5 VIN 3
AD829 6
3 7
2x
4 HP2835
2x 0.47µF a.
HP2835
0.47µF
R1
+VS
–VS C2
1kΩ Ω 1kΩ Ω C1
R2
NOTE:
100Ω Ω 1kΩΩ USE CIRCUIT 2 8
TEKTRONIX
CALIBRATION BOARD
WITH GROUND
AD797 6
FIXTURE VIN
1kΩΩ 20pF PLANE VIN 3
2
A1 C1, SEE TABLE
6 C2 = 50pF – C1
AD797
7 51pF
3
4 b.
1µF 0.1µF
Figure 41. Recommended Connections for Distortion
1µF 0.1µF Cancellation and Bandwidth Enhancement
+VS
–VS Table IV. Recommended External Compensation
Figure 40. Settling Time Test Circuit A/B A B
R1 R2 C1 C2 3 dB C1 C2 3 dB
DISTORTION REDUCTION Ω Ω (pF) BW (pF) BW
The AD797 has distortion performance (THD < –120 dB, @
20 kHz, 3 V rms, RL = 600 Ω) unequaled by most voltage G = 10 909 100 0 50 6 MHz 0 50 6 MHz
feedback amplifiers. G = 100 1 k 10 0 50 1 MHz 15 33 1.5 MHz
G = 1000 10 k 10 0 50 110 kHz 33 15 450 kHz
At higher gains and higher frequencies THD will increase due
to reduction in loop gain. However in contrast to most conven-
tional voltage feedback amplifiers the AD797 provides two effec- –80 0.01
tive means of reducing distortion, as gain and frequency are G=1000
increased; cancellation of the output stage’s distortion and gain RL=600Ω
THD – %
G = 100.
THD – dB
RL =10kΩ
–100 0.001
G=100
The unique design of the AD797 provides for cancellation of the RL =600Ω
output stage’s distortion (patent pending). To achieve this a ca- NOISE LIMIT, G=100
–110 0.0003
pacitance equal to the effective compensation capacitance, usu-
ally 50 pF, is connected between Pin 8 and the output (C2 in
Figure 41). Use of this feature will improve distortion perfor- G=10
–120 RL =600Ω 0.0001
mance when the closed loop gain is more than 10 or when fre-
quencies of interest are greater than 30 kHz.
100 300 1k 3k 10k 30k 100k 300k
Bandwidth enhancement via decompensation is achieved by FREQUENCY – Hz
connecting a capacitor from Pin 8 to ground (C1 in Figure 41)
effectively subtracting from the value of the internal compensa- Figure 42. Total Harmonic Distortion (THD) vs. Frequency
tion capacitance (50 pF), yielding a smaller effective compensa- @ 3 V rms for Figure 41b
tion capacitance and, therefore, a larger bandwidth. The
benefits of this begin at closed loop gains of 100 and up. A
maximum value of ≈33 pF at gains of 1000 and up is recom-
mended. At a gain of 1000 the bandwidth is 450 kHz.
Table IV and Figure 42 summarize the performance of the
AD797 with distortion cancellation and decompensation.
–12– REV. C
AD797
Differential Line Receiver A General Purpose ATE/Instrumentation Input/Output
The differential receiver circuit of Figure 43 is useful for many Driver
applications from audio to MRI imaging. It allows extraction of The ultralow noise and distortion of the AD797 may be com-
a low level signal in the presence of common-mode noise. As bined with the wide bandwidth, slew rate, and load drive of a
shown in Figure 44, the AD797 provides this function with only current feedback amplifier to yield a very wide dynamic range
9 nV/√Hz noise at the output. Figure 45 shows the AD797’s general purpose driver. The circuit of Figure 46 combines the
20-bit THD performance over the audio band and 16-bit accu- AD797 with the AD811 in just such an application. Using the
racy to 250 kHz.
–90 0.003
20pF
1kΩ WITHOUT
1kΩ
–100 OPTIONAL 0.001
50pF CN
+VS
**
50pF*
THD – dB
THD – %
DIFFERENTIAL 7 –110 0.0003
INPUT 2 MEASUREMENT
8 LIMIT
AD797 6
OUTPUT
4
3 –120 0.0001
WITH
*OPTIONAL OPTIONAL
** –VS 50C N
** USE POWER SUPPLY
1kΩ 1kΩ –130
BYPASSING SHOWN IN
100 300 1k 3k 10k 30k 100k 300k
FIGURE 32.
FREQUENCY – Hz
20pF
Figure 45. Total Harmonic Distortion (THD) vs. Frequency
for Differential Line Receiver
Figure 43. Differential Line Receiver
component values shown, this circuit is capable of better than
–90 dB THD with a ± 5 V, 500 kHz output signal. The circuit is
16
therefore suitable for driving high resolution A/D converters and
as an output driver in automatic test equipment (ATE) systems.
OUTPUT VOLTAGE NOISE — nV/ Hz
14 Using a 100 kHz sine wave, the circuit will drive a 600 Ω load to
a level of 7 V rms with less than –109 dB THD, and a 10 kΩ
load at less than –117 dB THD.
12
22pF
10 R2
+VS 2kΩ
**
8 +VS
**
2 7
6 1kΩ
AD797 6 3 7
10 100 1k 10k 100k 1M 10M
3 4 AD811 6
FREQUENCY — Hz **
INPUT OUTPUT
2 4
Figure 44. Output Voltage Noise Spectral Density for **
–V S
Differential Line Receiver
** USE POWER SUPPLY 649Ω –VS
BYPASSING SHOWN IN
FIGURE 32.
649Ω
REV. C –13–
AD797
Ultrasound/Sonar Imaging Preamp –30 100
The AD600 variable gain amplifier provides the time controlled
gain (TCG) function necessary for very wide dynamic range so-
VOUT – dB Re 1V/µA
preserve its low noise performance. To optimize dynamic range
–50 60
this buffer should have at most 6 dB of gain. The combination
of low noise and low gain is difficult to achieve. The input
buffer circuit shown in Figure 47 provides 1 nV/√Hz noise per- –60 40
formance at a gain of two (dc to 1 MHz) by using 26.1 Ω resistors
in its feedback path. Distortion is only –50 dBc @ 1 MHz at a
2 volt p-p output level and drops rapidly to better than –70 20
3 4
**
+VS
**
–V S
IS
CS AD797 6 Figure 50. A Professional Audio DAC Buffer
1000pF
3 4
**
–VS
–14– REV. C
AD797
OPERATIONAL AMPLIFIERS
LOW NOISE
REV. C –15–
AD797
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C1677–24–6/92
8 5
0.310 (7.87)
0.220 (5.59)
1 4
0.070 (1.78)
0.030 (0.76) 0.320 (8.13)
0.405 (10.29) MAX 0.290 (7.37)
0.150
0.200 (5.08) 0.015 (0.38)
(3.81)
0.125 (3.18) 0.008 (0.20)
MIN
Plastic Mini-DIP
(N) Package
8 5
0.25 0.31
(6.35) (7.87)
1 4
0.30 (7.62)
0.39 (9.91)
REF
MAX
0.035 ± 0.01
0.165 ± 0.01 (0.89 ± 0.25)
(4.19 ± 0.25)
SEATING PLANE
0.125 (3.18) 0.011 ± 0.003
MIN (4.57 ± 0.76)
0.18 ± 0.03
0.018 ± 0.003 0.10 (4.57 ± 0.76) 0 - 15
(0.46 ± 0.08) (2.54)
TYP
0.033
(0.84)
NOM
0.198 (5.03)
0.188 (4.77)
8 5 PRINTED IN U.S.A.
0.158 (4.00)
0.150 (3.80)
0.244 (6.200)
1 4 0.228 (5.80)
0.018 (0.46)
0.050 (1.27) 0.014 (0.36) 0.205 (5.20)
TYP 0.181 (4.60)
0.069 (1.75)
0.010 (0.25) 0.053 (1.35) 0.015 (0.38) 0.045 (1.15)
0.004 (0.10) 0.007 (0.18) 0.020 (0.50)
–16– REV. C