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Design of An Efficient FIFO Buffer For Network On Chip Routers
Design of An Efficient FIFO Buffer For Network On Chip Routers
Design of An Efficient FIFO Buffer For Network On Chip Routers
Chip Routers
Amardeep Chatrath, Mukul Varshney, Manoj Kumar Pandey and Sujata Pandey
Amity School of Engineering and Technology
Amity University Uttar Pradesh, Noida Uttar Pradesh
Abstract: The paper presents the an efficient first in been used to design the hardware system. The results
first out (FIFO) buffer for use in network on chip show that the designed system is working efficiently
routers. Further we have designed a heterogeneous when implemented in the Network on chip router.
router using the efficient FIFO buffer, in which each
channel can have a different buffer size. Ehen the II. SYSTEM DESIGN
FIFO of a particular channel is full it can borrow
more buffer length from neighbouring channels. In A FIFO or Queue or first-in first-out buffer is a
this new architecture read and write operations are memory in array form which is used to transfer data
managed by the FIFO and channel itself, thus between two circuits but having separate clocks.
reducing the circuitry and making the it high speed FIFO uses a dual port memory and has two pointers
router. called write (wr) pointer and read (rd) pointer. A
FIFO provides temporary storage of data, as per
Keywords: Network on Chip, FIFO buffer, Verilog need FIFO can have any size and transfer data
between devices with separate clocks. A FIFO
I. INTRODUCTION Buffer has a read pointer (RP) and a Write pointer
FIFOs are increasingly becoming important keeping (WP) as shown in Figure 1
in view of heterogeneous blocks in latest integrated
circuits. The various modules may operate at
different frequencies and data may travel at different
rates in these FIFOs. Efficient communication
among these blocks may require efficient FIFOs and
CAD designers may requires different types if
FIFOs ranging from synchronous to asynchronous
types.
FIFO buffer
Input to the module are data_in of 10 bit for input
data, clock for synchronisation, read signal of 1 bit
for read operation, write signal of 1 bit for write
operation and reset signal of 1 bit to make buffer
Figure 3: Flow chart of FIFO
reset. Outputs are data_out of 10 bit to pop the value
from the buffer. Figure 5 shows the simulation result
of the FIFO.
(a)
The Channel
clk,rst,rd_s,rd_e,rd_w,wr_s,wr_e,wr_w,din_s,din_s
_e,din_s_w,din_e,din_w are inputs to channel. The
inputs din_s,din_s_e,din_s_w,din_e,din_w are of 4
bit each. The outputs dout_s
,dout_e_s,dout_w_s,dout_s_e,dout_s_w are also of
4 bits each. The simulation results for the channel is
shown in Figure 6.
(b)
Figure 7: Channel waveforms (a) for input, (b) for
output