MSP430 Communication Peripherals

Some of the common serial communication protocols supported by MSP430 are

• Serial peripheral interface (SPI). Synchronous Transmission
• Inter-integrated circuit (I²C) bus.
• Asynchronous serial communication (usually, if inaccurately, called RS-232)→UART
The practical difference is that SPI and I²C are typically used between a microcontroller and
other devices on the same PCB, while asynchronous communication is used to exchange
data with other equipment such as a PC. Theoretical difference lies in the way in which
timing in managed. SPI and I²C are synchronous i.e clock signal is sent along with the data.
While, Asynchronous serial communication doesn’t need a clock. The major difference
between SPI & I²C is that I2C can accommodate a large number of devices & is half duplex.
SPI and I²C are often used to communicate with
• Port expanders to increase the effective number of pins for digital input and output.
• ADCs and DACs.
• Sensors with digital outputs, such as thermometers.
• External memory (data flash, EEPROM).
• Real-time clocks.
• Other processors.

Communication Peripherals in the MSP430

MSP430 offers three types of communication peripherals.

MSP430 communication peripherals_Lavanya Notes Page 1

Comparison of Communication peripherals in MSP430

Serial Peripheral Interface

Advantages Disadvantages
Full duplex. But only one data line (slave) is More pins(4 wires) than UART & I2C
active at a time
Higher speed (25 Mbps) than UART + I2C Short distances(20 cm) Vs RS-232/ RS-485
Not limited to 8-bit words Several variants like dual SPI, quad SPI etc..
Lower power requirement No error-checking protocol is defined
Extremely simple hardware interfacing No hardware slave acknowledgment

Concept of SPI
It is the simplest synchronous serial communication protocol introduced by Motorola for
short-distance communication. It is also called four-wire bus. SPI devices communicate
in full duplex mode using master-slave architecture. The embedded controller is the master
& the other device such as the ADC or flash memory could serve as the receiver.
The SPI bus specifies four logic signals:
SCLK: Serial Clock. This is initiated by the
master device whenever data transmission
is required.
MOSI: Master Output Slave Input
MISO: Master Input Slave Output
Master configures the clock, using a
frequency supported by the slave device,
typically up to a few MHz.

Usually eight-bit words are transmitted using two shift registers connected in a ring
topology as shown in the figure. During each clock cycle master sends a bit on the MOSI line

MSP430 communication peripherals_Lavanya Notes Page 2

and the slave reads it, while the slave sends a bit on the MISO line and the master reads it.
An active low Slave select bit S̅S̅ selects the slave in case of multiple connected devices.
In addition to setting the clock frequency, the master also configures the clock polarity and
phase using bits CPOL (for polarity) and CPHA (for phase) as shown in fig below. Care should
be taken to see that the slave is selected prior to the clock & delays in the slave should be
accounted to ensure that the peripheral clock is not active even before the data is ready for
transmission.
Polarity:
If CPOL = 0, Clock idles low
between transfers
If CPOL = 1, Clock idles High
between transfers

Phase:
If CPHA =0, the next bit of
data transition takes place
during the trailing edge of
clock
If CPHA =1, the next bit of
data transition takes place
during the rising edge of
clock
Depending on the combination of polarity & phase bits, there are 4 modes of SPI operation
Mode CPOL CPHA
0 0 0
1 0 1
2 1 0
3 1 1

SPI Operation:
SPI is one master and multi slave communication interface. It can be used in Independent
slave configuration & Daisy Chain configurations as shown in Fig below.

MSP430 communication peripherals_Lavanya Notes Page 3

In Independent Slave Configuration, MISO pins of the slaves are connected together. The
master sends an active low on the slave select (S̅S̅ =0) line of the corresponding slave device
with which data transfer has to be done. The number of S̅S̅ lines increases with the number
of devices with which the embedded controller is connected. Communication happens with
only one slave at a time. The other slaves whose select lines are high ignore the clock & data
from the master.

In Daisy Chain Configuration, MISO pins of the first slave is connected the MOSI pin of the
second slave so on. Each slave copies input to output in the next clock cycle until S̅S̅ =1.
Advantage of this configuration is that it requires only a single SS line from the master,
rather than several lines for each slave.

Bit Banging:
If no hardware is available, slow communication can be achieved by driving the pins using
software. This is known as bit-banging and is helpful for asynchronous serial
communication. Here the signals has to be controlled by software & is assisted by Timer_A

Asynchronous Serial Communication

Asynchronous serial communication can be managed in hardware by a peripheral called a
universal asynchronous receiver/transmitter (UART often called RS232), which is built into
many microcontrollers.
Asynchronous serial communication requires only a single wire for each direction plus a
common ground. Connections are full duplex, meaning that data can be sent simultaneously
in both directions. Data is simply sent when required. Issues such as the detection and
correction of errors are usually handled by the application that supervises the
communication. Data are sent in short frames containing one low start bit (ST), eight data
bits (usually lsb first) & one high stop bit (SP). The bits are either high or low and have no
gaps between them, a format known as non-return to zero (NRZ). A parity bit may also be
added to 8-bit data and the MSP430 bootstrap loader uses this format. The baud rate gives
the frequency at which bits are transmitted on the line. No clock is transmitted in
asynchronous communication so the transmitter and receiver must run independently at
nearly the same baud rates.

For a 9600 baud rate, bit time = 1/ 9600 = 104.17 µs considering that the MSP430 is working
on ACLK = 32768 Hz, the clock bit time = 1/32768 = 30.517 µs. simply multiplying this clock
bit time by an integer factor will not give the exact bit time. (i.e 3 × 30.517 µs = 91.55 µs or 4
× 30.517 µs = 122.07 µs, but not exactly 104.17 as required). This introduces cumulative
error. Modulation minimizes this cumulative error. Asynchronous communication is usually
used between separate pieces of equipment. Therefore an interface is needed between the
UART in the microcontroller and the outside world. This is where RS-232 comes in.

MSP430 communication peripherals_Lavanya Notes Page 4

RS-232Interface Standard
The current version of RS-232 is ANSI/TIA/EIA-232-F. But RS-232 still popularly persists. RS-
232 standard defines the voltage levels that correspond to logical 1 & logical 0 & control
signals.
Logic Signal Called as Voltage
0 Space +3V to +15 V
1 Mark -15 to -3 V
As the voltage range of MSP430 are not covered by these specifications, special transceiver
IC’s such as MAX232 are used with MSP430 that generate the voltages required for RS232
transmission.
RS232 has the following pins for data transfer & control. They are available as 9 pin / 25 pin
D connectors. Advanced versions such as RS-422 & RS-485 are also available.
Pin Abbreviation Direction Function
DCD Data Carrier detect In DCE is receiving a carrier from a remote DTE
RXD Receive data In Carries data from DCE to DTE
TXD Transmit data Out Carries data from DTE to DCE
DTR Data terminal ready Out DTE is ready to receive
GND Ground -
DSR Data Set Ready In DCE is ready to receive & send data
RTS Request to send Out DTE requests the DCE to prepare the transmit
data
CTS Clear to send In DCE is ready to accept data from the DTE
RI Ring Indicator In DCE detected an incoming signal on the
telephone line

Interfacing using RS-232

RXD

PC USB USB to RS232 RS-232

Converter TXD

R in R out
RXD
Micro
MAX232
controller T out
T in
TXD

Asynchronous Communication with USCI_A

USCI_A interface can be configured to handle UART & SPI. This section describes configuring
USCI_A of MSP430 to handle UART. The asynchronous mode is set by using the UCSYNC bit
in the UCA0CTL0 register.
UCAxCTL0 register
7 6 5 4 3 2 1 0
UCPEN UCPAR UCMSB UC7BIT UCSPB UCMODEx UCSYNC
Parity enable Parity Select MSB first select Character Stop bit select USCI mode; when Synchronous
0=Parity disable Not used when 0=lsb first length 7/8 bits 0=one stop bit UCSYNC=0, mode enable
1=Parity enable UCPEN=0 1=MSB first 0=8 bit data 1=two stop bits 00=UART mode; 01 & 0= Async mode
0=odd parity 1=7 bit data 10=multiprocessor 1=Sync mode
1=even parity modes;11=UART mode
with automatic baud rate

MSP430 communication peripherals_Lavanya Notes Page 5

Setting Baud rate with USCI_A
As the baud rate is not an integer factor of the clock rate, cumulative errors occur.
Modulation minimizes this cumulative error. There are 2 modes (oversampling mode & low
frequency mode) of setting baud rate in USCI_A. It is controlled by the bits in UCA0MCTL
register.
7 6 5 4 3 2 1 0
UCBRFx UCBRSx UCO16
First modulator stage select Second modulation stage select. This determines Oversampling mode
When UC016=1, these bits determine the modulation the modulation pattern for BITCLK 0=Low freq. mode
pattern for BITCLK. If UC016=0, modulation is ignored 1=Oversampling
mode

Oversampling mode Baud rate Generator

There are 3 clocks in USCI_A: BRCLK, BITCLK & BITCLK16

BRCLK is the input to the module (SMCLK, ACLK or UCA0CLK)
BITCLK controls the rate at which bits are received & transmitted. Its freq. should be same
as baud rate. fBITCLK = fbaud
BITCLK16 is the sampling clock in oversampling mode with a frequency fBITCLK16 = 16 fBITCLK

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UBAxBR0 & UCAxBR1 together termed as UCBRx provides the main divider of BRCLK.
UCBRFx & UCBRSx modulate the dividers to give BITCLK16 & BITCLK respectively to reduce
the cumulative error.

We want fBITCLK16 =16 fbaud =16×9600 = 153.6 KHz. With fBRCLK= 220 Hz, the divider/pre-scaler
should use a factor of 220 Hz / 153, 600 = 6.83. So the value 0006h is set for UBAxBR0 &
UCAxBR1 and the modulation index of 0D is set for UCBRFx to get a closer value.
UxBR1 | UxBR0 | UxMCTL= 00h | 06h | 7D h ; where 0D is the modulation pattern. In most
cases this procedure brings fBITCLK close enough to fbaud. If it does not, it is also possible to
modulate the second division from BITCLK16 to BITCLK by using UCBRSx
The equation to find UCBRx & UCBRFx is given by:
nint (fBRCLK / fbaud) = (16 – UCBRFx) UCBRx + UCBRFx (UCBRx +1) = 16 UCBRx +UCBRFx
nint (220 / 9600) = (16-13)6 + 13 (6 +1)
nint (109) = 18 + 91 = 109

Low frequency mode of Baud rate Generator

Only a single divider and modulator is used in
the low-frequency mode.

The divider UCBRx and the modulation index UCBRSx are given by:
nint(8 × fBRCLK / fbaud ) = (8−UCBRSx) UCBRx + UCBRSx (UCBRx+1) = 8UCBRx + UCBRSx.
Considering ACLK =32 KHz,
nint ((8 × 32000) / 9600 ) = 8UCBRx + UCBRSx
nint (26.66) = (8 × 3) + 4
27 = 27
Hence UCBRx = 3 & UCBRSx =4

Interrupts in USCI_A
Once configured, a character for transmission is written to UCA0TXBUF after checking that
the flag UCA0TXIFG is raised. Similarly, the flag UCA0RXIFG is raised when a new character
has been received and is available in UCA0RXBUF. There is usually no way of telling the
remote transmitter to pause so it is important to read the buffer promptly before it is
overwritten. The overrun flag UCOE is raised if this happens.

Parallel ports/ GPIO

All General purpose registers in MSP430 are of 16 bits. In F2013, there are 2 ports P0 & P1 with 8
pins P0 [7:0] and P1 [1:0] respectively. All these ports are memory mapped in the peripheral
registers of byte size. System registers used for configuring GIPO pins of MSP430 are PxDIR, PxIN,
PXOUT
If PxDIR=1, then the pin is configured as output. By default a pin is input. Ex:P1DIR=0x80 sets P1.7 as
output.
1 0 0 0 0 0 0 0

P1.7
Then when P1OUT|=0x80, high is written on P1.7
PxOUT performs 2 functions:
• If port is configured as GIPO & direction is set as o/p, then P1OUT holds logical high/low status
based on what is written to PxOUT

MSP430 communication peripherals_Lavanya Notes Page 7

• If Port is configured as GIPO & direction is i/p, then it becomes important to configure the i/p
pins in pull up/pull down mode
i.e either pull up/ pull down register need to be enabled. Therefore a special function PxREN
register is required to enable/disable the pull up/down resistor connected to corresponding pin.
Bit = 0, pull up or pull down resistor is disabled.
Bit = 1, pull up or pull down resistor is enabled.
• But if Bit = 1 in PxREN Pull up/down is enabled. It is important to know how to decide whether it
is pull up or pull down. This is decided by PxOUT register.
If Bit = 0, pin is pulled down; If Bot = 1, pin is pulled up.
Ex: P1DIR = 0x00; P1.7 : P1.0 as i/p
P1REN = 0x80; P1.7 is enabled for pull up (or) Pull down
Now if P1OUT = 0x08 ; P1.7 is pull up
If P1OUT = 0x00; P1.7 is pull down

But in MSP430, pull up/ pull down are inbuilt and are selected based on status of P1DIR, P1REN &
P1OUT. Example:

P1DIR=0x00; P1.7: p1.0 as i/p

P1REN = 0x80; P1.7 is enabled for pull up/down
P1Out = 0x80 ; P1.7 is pull up internally.
When switch is pressed, logic 0 goes as i/p or else logic
high. Therefore pin is not floating

MSP430 communication peripherals_Lavanya Notes Page 8