M.E Applied Notes 1

M.
E (Applied Electronics)
2013, Regulations, Curriculum & Syllabi
BANNARI AMMAN INSTITUTE OF TECHNOLOGY

(An Autonomous Institution Affiliated to Anna University, Chennai
Approved by AICTE - Accredited by NBA New Delhi, NAAC with ‘A’ Grade and ISO 9001:2008 Certified)
SATHYAMANGALAM – 638 401 Erode District Tamil Nadu
Phone : 04295 226000 Fax : 04295 226666
Web:www.bitsathy.ac.in E-mail : bitsathy@bannari.com
Contents
Page No.
Regulations i
Programme Educational Objectives (PEOs) viii
Programme Outcomes (POs) ix
Mapping of PEOs and POs x
Curriculum 2013 1
Syllabi 3
Electives 16
M.E / M. Tech. Rules and Regulations – 2013
Approved in VII Academic Council Meeting held on 18.05.2013
Rules and Regulations
M. E. / M. Tech. Programmes
(For the batch of students admitted in 2013-2014 and onwards)
NOTE: The regulations hereunder are subject to amendments as may be decided by the Academic Council of the
Institute from time to time. Any or all such amendments will be effective from such date and to such batches of students
including those already in the middle of the programme) as may be decided by the Academic Council.
1. Conditions for Admission
(i) Candidates for admission to the I Semester of M. E. / M. Tech. degree programme will be
required to satisfy the conditions of admission thereto prescribed by the Anna University,
Chennai and Government of Tamil Nadu.
(ii) Part–time candidates should satisfy conditions regarding experience, sponsorship, place of work,
etc., that may be prescribed by Anna University, Chennai from time to time, in addition to
satisfying requirements as in Clause 1(i).
2. Duration of the Programme
(i) Minimum Duration: The programme will lead to the Degree of Master of Engineering (M.E.) /
Master of Technology (M. Tech.) of the Anna University, Chennai extend over a period of two
years. The two academic years (Part-time three academic years) will be divided into four
semesters (Part-time six Semesters) with two semesters per year.
(ii) Maximum Duration: The candidate shall complete all the passing requirements of the M. E. /
M. Tech. degree programmes within a maximum period of 4 years / 8 semesters in case of full-
time programme and 6 years / 12 semesters in case of part-time programme, these periods being
reckoned from the commencement of the semester to which the candidate was first admitted.
3. Branches of Study
The following are the branches of study of M.E. / M.Tech. Programmes
M.E.
Branch I Applied Electronics

Branch II CAD/CAM
Branch III Communication Systems
Branch IV Computer Science and Engineering
Branch V Embedded Systems
Branch VI Engineering Design
Branch VII Power Electronics and Drives
Branch VIII Software Engineering
Branch IX Structural Engineering
Branch X VLSI Design
Branch XI Biotechnology
M. Tech.
Branch I Biotechnology
4. Structure of Programmes
(i) Curriculum: The curriculum for each programme includes Courses of study and detailed syllabi.
The Courses of study include theory Courses (including electives), seminar, practicals, Industrial
i
training / Mini-project, Project Work (Phase I) and Project Work (Phase II) as prescribed by the
respective Boards of Studies from time to time.
Full-time Programme: Every full-time candidate shall undergo the Courses of his/her
programme given in clause 12 in various semesters as shown below:
Semester 1: 6 Theory Courses and two Practicals

Semester 2: 6 Theory Courses, one Practical and a Technical Seminar
Semester 3: 3 Theory Courses and Project Work (Phase I)
Semester 4: Project work (Phase II).
Part-time Programme: Every part-time candidate shall undergo the Courses of his/her
programme in various semesters as shown below:
Semester 1: 3 Theory Courses and one Practical

Semester 2: 3 Theory Courses and one Practical
Semester 3: 3 Theory Courses, Technical Seminar and one Practical
Semester 4: 3 Theory Courses
Semester 5: 3 Theory Courses and Project Work (Phase I)
Semester 6: Project Work (Phase II)
(ii) Theory Courses: Every candidate shall undergo core theory, elective, and practical Courses
including project work of his/her degree programme as given in clause 12 and six elective theory
Courses. The candidate shall opt electives from the list of electives relating to his/her degree
programme as given in clause 12 in consultation with the Head of the Department. However, a
candidate may be permitted to take a maximum of two electives from the list of Courses of other
M.E. / M.Tech. Degree programmes with specific permission from the respective Heads of the
Departments.
(iii) Project Work: Every candidate individually shall undertake the Project Work (Phase I) during
the third semester (fifth semester for part-time programme) and the Project Work (Phase II)
during the fourth semester (Sixth semester for part-time programme). The Project Work (Phase
II) shall be a continuation work of the Project Work (Phase I). The Project Work can be
undertaken in an industrial / research organisation or in the Institute in consultation with the
faculty guide and the Head of the Department. In case of Project Work at industrial / research
organization, the same shall be jointly supervised by a faculty guide and an expert from the
organization.
(iv) Industrial Training / Mini Project: Every full-time candidate shall opt to take-up either
industrial training or Mini Project under the supervision of a faculty guide.
(v) Value added / Certificate Courses: Students can opt for any one of the Value added Courses in
II and III semester. A separate certificate will be issued on successful completion of the Course.
(vi) Special Self-Study Elective Courses: Students can opt for any one of the special elective
Courses as Self-Study in addition to the electives specified in the curriculum in II and III
semesters, under the guidance of the faculty. The grades of only passed candidates will be
indicated in the mark sheet, but will not be taken into account for assessing CGPA.
(vii) Application oriented and Design Experiments: The students are to carryout Application
oriented and Design Experiments in each laboratory in consultation with the respective faculty
and Head of the department.
(viii) Mini project: A Mini Project shall be undertaken individually or in a group of not more than 3 in
consultation with the respective faculty and the Heads of the Department, in any one of the
laboratories from I to III semesters.
ii
(ix) Credit Assignment: Each course is normally assigned a certain number of credits with 1 credit
per lecture hour per week, 1 credit for 1 or 2 hours of practical per week (2 credits for 3 hours of
practical), 4 credits for theory with lab component with 3 hours of lecture and 2 hours of practical
per week, 2 credits for 3 hours of seminar per week, 6 credits for the Project Phase I and 12
credits for the Project Phase II. The exact numbers of credits assigned to the different courses of
various programmes are decided by the respective Boards of Studies.
(x) Minimum Credits: For the award of the degree, the candidate shall earn a minimum number of
total credits as prescribed by the respective Board of Studies as given below:
M.E./M. Tech. Programmes Total Credits

M.E. Applied Electronics 75
M.E. CAD / CAM 75
M.E. Communication Systems 75
M.E. Computer Science and Engineering 75
M.E. Embedded Systems 75
M.E. Engineering Design 77
M.E. Power Electronics and Drives 76
M.E. Software Engineering 76
M.E. Structural Engineering 77
M.E. VLSI Design 75
M.Tech. Biotechnology 76
5. Requirements for Completion of Study of a Semester
(i) a) Candidate will be deemed to have completed the study of any semester only if he /she has kept
not less than 70% of attendance in each course and at least 80% of attendance on an average in
all courses in that semester put together.
b) On medical grounds, 10% relaxation in the attendance can be allowed
(ii) his/her progress has been satisfactory, and
(iii) his/her conduct has been satisfactory
6. Assessment and Passing Requirements
(i) Assessment: The assessment will comprise continuous assessment and final examination,
carrying marks as specified in the scheme (clause 10). Continuous assessment will be made as
per the guidelines framed by the Institute from time to time. All assessments will be done on
absolute marks basis. However, for the purpose of reporting the performance of a candidate, letter
grades and grade points will be awarded as per clause 6(v).
(ii) Final Examinations: Final examinations will normally be conducted during November /
December and during April / May of each year. Supplementary examinations may be conducted
at such times as may be decided by the Institute.
A candidate will be permitted to appear for the final examination of a semester only if he/she has
completed the study of that semester satisfying the requirements given in clause 5 and registers
simultaneously for the examinations of the highest semester eligible and all the Courses which
he/she is in arrears of. A candidate, who is not permitted to appear at the final examination of a
semester, is not permitted to proceed to the next semester. A candidate who is not permitted to
appear at the final examination of any semester has to register for and redo the Courses of that
semester at the next available opportunity.
(iii) Rejoining the Programme: A candidate who has not completed the study of any semester as per
clause 5 or who is allowed to rejoin the programme after a period of discontinuance or who on
his/her own request is permitted to repeat the study of any semester, may join the semester which
he/she is eligible or permitted to join, only at the time of its normal commencement for a regular
iii
batch of candidates and after obtaining the approval from the Director of Technical Education
and Anna University, Chennai. No candidate will however be enrolled in more than one semester
at any point of time. In the case of repeaters, the earlier continuous assessment in the repeated
Courses will be disregarded.
(iv) Industrial Training, Mini-project and Project Work:

Every candidate shall submit reports on Industrial training / Mini-project, Project Work (Phase I)
and Project Work (Phase II) on dates announced by the Institute / department through the faculty
guide to the Head of the Department. If a candidate fails to submit the reports of any of these
Courses not later than the specified date, he/she is deemed to have failed in it. Every candidate
shall present report/papers in the seminars in each of the relevant semesters about the Industrial
training / Mini-project, Project Work (Phase I) and Project Work (Phase II). The reports/papers
shall be presented in the seminar before a review committee constituted by the Head of the
Department. The Industrial training / Mini-project, Project Work (Phase I) and Project Work
(Phase II) will be evaluated based on the presentations in the seminar, reports and viva-voce
examinations. In case of the industrial training for the full-time candidates, evaluation will be
carried out in the third semester.
In case of Project Work (Phase II), the viva-voce examination will be carried out by a team
consisting of an internal examiner, usually the supervisor, and an external examiner, appointed by
the Principal.
1. Due weight will be given for the training report from the Organisation / Industry while
evaluating the report and its presentation at the seminar about the nature of the training and
what the student has learnt. The student shall be required to get a grade not less than “C”.
The grade will be indicated in the mark sheet. This will not be taken into account for
assessing CGPA.
2. The evaluation of the Mini Project will be based on the report, presentation at the seminar
and viva-voce. The student shall be required to get a Grade not less than “C”. The grade will
be indicated in the mark sheet. This will not be taken into account for assessing CGPA.
3. Every Candidate shall pursue Project work-Phase I in third semester and Project Work –
Phase II in fourth semester which is in continuation of Phase I. Project work –Phase I and
Phase II will be evaluated as given below in the scheme of evaluation
A candidate is permitted to register for the Project Work (Phase II), only after passing the Project
Work (Phase I). A candidate who fails in Industrial training / Mini-project, Project Work (Phase
I) or Project Work (Phase II) shall register for redoing the same at the beginning of a subsequent
semester.
(v) Letter grade and grade point: The letter grade and the grade point are awarded based on
percentage of total marks secured by a candidate in an individual Course as detailed below:
Range of Percentage of Total Marks Letter Grade Point

grade (g)
90 to 100 S 10
80 to 89 A 9
70 to 79 B 8
60 to 69 C 7
55 to 59 D 6
50 to 54 E 5
0 to 49 or less than 50% in final examination RA
Incomplete I 0
Withdrawal W
“RA” denotes reappearance in the course.

“I” denotes incomplete as per clause 5 (i) & (ii) and hence prevented from writing
semester end examination.
“W” denotes withdrawal from the final examination
iv
After completion of the programme earning the minimum number of credits, the Cumulative Grade
Point Average (CGPA) from the semester in which the candidate has joined first to the final
semester is calculated using the formula:
CGPA =
∑ g *Ci i
∑C i
Where g i : Grade point secured corresponding to the Course

Ci : Credits allotted to the Course.
(vi) Passing a Course: A candidate who secures grade point 5 or more in any Course of study will be
declared to have passed that Course, provided a minimum of 50% is secured in the final
examination of that Course of study.
A candidate, who is absent for the final examination or withdraws from final examination or
secures a letter grade RA (Grade point 0) in any Course carrying continuous assessment and final
examination marks, will retain the already earned continuous assessment marks for two
subsequent appearances in the examination of that Course and thereafter he/she will be solely
assessed by the final examination carrying the entire marks of that Course.
A candidate, who scores a letter grade RA (Grade point 0) in any Course carrying only
continuous assessment marks, will be solely examined by a final examination carrying the entire
marks of that Course, the continuous assessment marks obtained earlier being disregarded.
7. Qualifying for the Award of the Degree
A candidate will be declared to have qualified for the award of the M.E. / M.Tech. Degree provided:
(i) he/she has successfully completed the Course requirements and has passed all the prescribed
Courses of study of the respective programme listed in clause 12 within the duration specified in
clause 2.
(ii) No disciplinary action is pending against the candidate
8. Classification of Degree
(i) First Class with Distinction: A candidate who qualifies for the award of degree (vide clause 7)
having passed all the Courses of all the semesters at the first opportunity within four consecutive
semesters (six consecutive semesters for part-time) after the commencement of his / her study
and securing a CGPA of 8.5 and above shall be declared to have passed in First Class with
Distinction. For this purpose the withdrawal from examination (vide clause 9) will not be
construed as an opportunity for appearance in the examination.
(ii) First Class: A candidate who qualifies for the award of degree (vide clause 7) having passed all
the Courses of all the semesters within a maximum period of six semesters for full-time and eight
consecutive semesters for part-time after commencement of his /her study and securing a CGPA
of 6.50 and above shall be declared to have passed in First Class.
(iii) Second Class: All other candidates who qualify for the award of degree (vide clause 7) shall be
declared to have passed in Second Class.
9. Withdrawal from Examination
(i) A candidate may, for valid reasons, be granted permission to withdraw from appearing for the
examination in any Course or Courses of only one semester examination during the entire
duration of the degree programme. Also, only one application for withdrawal is permitted for that
semester examination in which withdrawal is sought.
(ii) Withdrawal application shall be valid only if the candidate is otherwise eligible to write the
examination and if it is made prior to the commencement of the semester examinations and also
recommended by the Head of the Department and the Principal.
v
(iii) Withdrawal shall not be construed as an opportunity for appearance in the examination for the
eligibility of a candidate for First Class with Distinction.
10. Scheme of Assessment
• Students who were absent for the previous periodicals and those who wish to improve their
periodical test marks shall take up an optional test consisting of two units prior to the
commencement of model examination.
Scheme of Evaluation
i) Theory
Final Examination : 50 Marks
Internal Assessment : 50 Marks
Distribution of marks for internal assessment:
Assignment/Tutorial : 05
Test 1 : 10
Test 2 : 10
Model Exam : 15 (Entire syllabus)
Innovative Presentation# : 10
---------
: 50
---------
#
Innovative Presentation includes Seminar / Quiz / Group Discussion / Case Study /Soft Skill Development
/ Mini Project / Review of State-of-the art
ii) Technical Seminar : 100 Marks
Three Seminars (3X25) : 75 Marks

Report : 25 Marks
iii) Practical
Final Examination : 50 Marks

Internal Assessment : 50 Marks
Distribution of marks for internal assessment:
Preparation : 5
Conduct of Experiments : 10
Observation & Analysis of results : 10
Record : 10
Model Exam & Viva-voce : 15
---------
: 50
---------
vi
iv) Project Work Phase – I Marks
Internal
Project Identification : 10
Literature survey + analysis : 15
-------
Sub Total : 25
Approach & Progress : 25
-------
Total : 50
-------
External – Final Evaluation
Report Preparation & Presentation : 25
Viva Voce : 25
-------
: 50
-------
v) Project Work Phase – II Marks
Internal
Continuation of Approach & Progress : 50
Findings, Discussion & Conclusion : 50
-------
Total : 100
-------
External – Final Evaluation
Report Preparation & Presentation : 50
Viva Voce : 50
-------
: 100
-------
11 . Question paper pattern for Theory Examination
Max. Marks : 100

Time : 3 Hours
PART A
Short Answer Questions: 15
(15X 2 Marks) : 30 Marks
(Three Questions from each unit)
PART B
(Questions may be framed from any of the five Units)
Lengthy Answer Questions: 2

(2 X 14 Marks) (Compulsory) : 28
(Questions may be framed from any of the five units)
Lengthy Answer Questions: 3
(3X 14 Marks) (Either Or Type) : 42
(Questions may be framed from the remaining three units)
---------
Total Marks : 100
---------
12. Curriculum and Syllabi
vii
PEOs & POs M.E Applied Electronics │Regulation 2013
Approved in the IX Academic Council held on 07-12-2013
{{
M.E Applied Electronics
Program Educational Objectives (PEOs)
I. The Graduates will demonstrate their outstanding education skills that will enable them to integrate
undergraduate fundamentals with advanced knowledge to solve complex electronics engineering problems.
II. The Graduates will demonstrate their professional and ethical responsibility, effective communication
skills, teamwork skills, multidisciplinary approach, and the life-long learning needed for a successful
professional career.
III. The Graduates will demonstrate their strong fundamental knowledge to pursue higher education, to
enhance research and continue professional development.
IV. The Graduates with good scientific and engineering breadth so as to comprehend, analyze, design and
create novel products and solutions for real life problems.
viii
PROGRAMME OUTCOMES (POs)

(a) The Graduates will able to apply knowledge from undergraduate engineering and other disciplines to
identify, formulate, solve novel advanced electronics engineering along with soft computing and
networking problems that require advanced knowledge within the field.
(b) The Graduates will able to understand and integrate new knowledge within the field.
(c) The Graduates will able to apply advanced technical knowledge in multiple contexts.
(d) The Graduates will able to understand and design advanced electronics systems (Analog and Digital
Systems) and conduct experiments, analyze and interpret data.
(e) The Graduates will able to demonstrate the skills to use modern engineering tools, software and equipment
to analyze problems.
(f) The Graduates will able to plan, conduct an organized and systematic study on significant research topic
within the field.
(g) The Graduates will able to convey technical material through formal written reports which satisfy accepted
standards of writing style.
(h) The Graduates will able to communicate professionally.
(i) The Graduates will able to become knowledgeable about contemporary developments.
(j) The Graduates will able to develop confidence for self education and able to for lifelong learning.
ix
Mapping of PEOs & POs
Programme Educational Objectives Program Outcomes
PEO: I The Graduates of Applied Electronics will (a),(b),(e)

demonstrate their outstanding education skills
that will enable them to integrate undergraduate
fundamentals with advanced knowledge to solve
complex electronics engineering problems.
PEO: II The Graduates of Applied Electronics will (f),(c) and (i)
demonstrate their professional and ethical
responsibility, effective communication skills,
teamwork skills, multidisciplinary approach, and
the life-long learning needed for a successful
professional career.
PEO: III The Graduates of Applied Electronics will (d),(g)
demonstrate their strong fundamental knowledge
to pursue higher education, to enhance research
and continue professional development.
PEO: IV The Applied Electronics Graduates with good (h),(j)
scientific and engineering breadth so as to
comprehend, analyze, design and create novel
products and solutions for real life problems.
x
Curriculum of M.E Applied Electronics │Minimum Credits to be earned: 75│Regulation 2013
M.E. Applied Electronics

First Semester
Code Objectives & Outcomes
Courses L T P C
No. PEOs POs
13AE11 Applied Mathematics I,III (a),(b),(c),(j) 3 1 0 4
13AE12 Analog VLSI Circuit Design $
I,III (b) , (c), (d) 3 0 0 3
13AE13 Digital System Design% I,III (a), (b), (e), (f) 3 1 0 4
13AE14 Advanced Digital Signal Processing# I,III,IV (a), (b), (c), (d), (e) 3 0 0 3
13AE15 Microprocessors and Embedded Systems I,III (a), (b), (c) 3 0 0 3
13AE16 Machine Vision I,III (a), (b), (e), (f) 3 0 0 3
13AE17 Electronics Design Laboratory I III (b), (c), (d), (e), (f) 0 0 3 2
13AE18 Microprocessor and Embedded Laboratory III (a), (b), (c), (d), (e) 0 0 3 2
Total 18 2 6 24
Second Semester
Subjects L T P C
No. PEOs POs
13AE21 Automotive Electronics I,II (a), (c), (d), (f), (g) 3 0 0 3
13AE22 Neural Computing$ I,III (a), (b), (e), (f) 3 1 0 4
13AE23 Digital Control Systems% I,III (a), (b), (c), (d), (e) 3 1 0 4
Elective* 3 0 0 3
Elective* 3 0 0 3
Elective* 3 0 0 3
13AE24 Advanced Electronics Design Laboratory III (b), (c), (d), (e), (f) 0 0 3 2
13AE25 Technical Seminar IV (f), (g), (h), (i), (j) 0 0 3 2
Total 18 2 6 24
Third Semester
Courses L T P C
No. PEOs POs
Elective* 3 0 0 3
Elective* 3 0 0 3
Elective* 3 0 0 3
13AE31 Project Phase I III,IV (e), (f), (g) 6
Total - - - 15
Fourth Semester
Subjects L T P C
No. PEOs POs
13AE41 Project Phase II III,IV (e), (f), (g) - 12
-
-
$
Common with VL
% Common with ES
# Common with CO & ES
% Common with ES
* Hours & Credit Pattern: Electives with Lab Component 3 0 2 4 | Electives with Tutorial 3 1 0 4 | Electives without Lab & Tutorial Component 3 0 0 3
1
Curriculum of M.E Applied Electronics │Minimum Credits to be earned: 75│Regulation 2013
Approved in the VII Academic Council held on 18-05-2013
List of Electives
Courses L T P C
No. PEOs POs
13AE51 Advanced Wireless Networks II,III,IV (a), (b), (c), (d) ,(e), (i), (j) 3 0 0 3
13AE52 Medical Image Processing I,III (a), (b), (c), (d), (e), (i), (j) 3 0 0 3
13AE53 Multimedia Communication Systems I,III (a), (b), (c), (d), (e) 3 0 0 3
13AE54 Wireless Security+ II,IV (a), (b), (c), (d), (e), (h) 3 0 0 3
13AE55 Low Power VLSI Design$$ I,III (a), (b), (c), (d), (e) 3 0 0 3
13AE56 VLSI Signal Processing$ II,III,IV (a), (b), (c), (d), (e), (f),(i), (j) 3 0 0 3
13AE57 DSP Integrated Circuits I,III (a), (b), (c), (d), (e), (f),(i), (j) 3 0 0 3
13AE58 Computer Aided Design of VLSI Circuits% I,III (a), (b), (c), (d), (e), (f),(i), (j) 3 0 2 3
13AE59 Evolutionary Computing + I,III (a), (b), (c), (d), (e) 3 0 0 3
13AE60 Multimedia Compression Techniques++ II,IV (a), (b), (c), (d), (e) 3 0 0 3
13AE61 Reliability Engineering % I,III (a), (b), (c), (d), (e) 3 0 0 3
13AE62 Network Security II, III, IV (a), (b), (c), (d) 3 0 0 3
13AE63 Wired and Wireless LAN I (a), (b), (c), (d) 3 0 0 3
13AE64 ASIC Design$$ I,III (a), (c), (d), (e), (f) 3 0 0 3
13AE65 DSP Processor Architecture and I,III (a), (b), (c), (d), (e) 3 0 0 3
Programming
13AE66 VLSI Technology$ I,III (a), (b), (c), (d), (e) 3 0 0 3
13AE67 VLSI subsystem Design$ II,IV (a), (b), (e), (f) 3 0 0 3
13AE68 Communication Networks++ II,IV (a), (b), (c), (d) 3 0 0 3
13AE69 Robotics** II,IV (a), (b), (c), (d), (e) 3 0 0 3
13AE70 Pattern Recognition & Artificial Intelligent II,III,IV (a), (b), (c), (d), (e) 3 0 0 3
Techniques@
13AE71 Cyber crime Investigations and Digital II,IV (a), (b), (c) 3 0 0 3
Forensics**
Self Study Electives
Subjects L T P C
No. PEOs POs
13AE01 Wavelets and Multi-resolution Processing ## I,III (a), (b), (c), (d), (e) - - - 3
13AE02 Mobile Networks II,IV (a), (b), (c), (d) - - - 3
13AE03 Intrusion Detection and Prevention System II,III,IV (a), (b), (c), (d), (e) - - - 3
+
Common with CO
$$ Common with VL & ES
$ Common with VL
% Common with ES
++ Common with VL & CO
** Open Electives
## Common with CO & ES
@ Common with CO, ES & AE
2
Syllabi: M.E Applied Electronics (Core) │Minimum Credits to be Earned: 75│Regulation 2013
13AE11 APPLIED MATHEMATICS

3104
Objectives
 To impart knowledge on the calculus of variations, with emphasis on its applications in several
scientific fields.
 To understand the basic concepts of vector spaces and their applications.
 To find the optimum solution of the complex problem.
 Ability to find the Eigen values and Eigen vectors of the matrix.
 Acquire the knowledge of interest in graph theory.
Course Outcomes (COs)
 To provide the students with outstanding educational skills that will enable them to integrate
under graduate fundamentals with advanced knowledge to solve complex problems.
 Can get the idea of optimization and its applications.
 Able to use a combination of theoretical knowledge and independent mathematical thinking using
graph theory.
Programme Outcomes (POs)
(a) Able to apply knowledge from undergraduate engineering and other disciplines to identify,
formulate, solve novel advanced electronics engineering along with soft computing problems that
require advanced knowledge within the field .
(b) Able to understand and integrate new knowledge within the field.
(c) Able to apply advanced technical knowledge in multiple contexts.
(d) Able to develop confidence for self-education and lifelong learning.
Unit I
Calculus of Variations
Introduction to variation problems - Euler’s equation - Functional dependent on first and higher order
derivatives - Functional dependent on functions of several independent variables - Some applications -
Direct methods: Ritz methods.
9 Hours
Unit II
Vector space
Definition and examples of linear space - Linear dependence and independence - Basis and Dimension -
lnner product space - Orthogonalisation process - Gram - Schmidt process Least - square problems -
Applications of inner product spaces.
9 Hours
Unit III
Eigen values and Eigen vectors
Generalized Eigen values and Eigen vectors - Characteristic equation - Diagonalization - Eigen vectors &
linear transformations - Complex eigen values - Applications to differential equations - Iterative estimates
for Eigen values.
9 Hours
Unit IV
Symmetric Matrices and Quadratic forms
Diagonalization of symmetric matrices - Quadratic forms - Singular values decomposition - Change of
basis.
9 Hours
Unit V
Graph Theory
Introduction - Basic terminology - Representation of graphs - Connected graphs - Matrix representation of
graphs (excluding graphs) - Applications - Critical path method - Shortest path problems - Trees -
Definition - Binary tree.
9 Hours
Total:45+15 Hours
Reference(s)
1. Elsgolts.L, Differential Equation and Calculus of variations, MIR Publishers, 1996.
3
2. David C Lay, Linear Algebra and its Applications, Pearson Education Asia, New Delhi, 2003.
3. Howard Anton, Elementary Linear Algebra”, John Wiley & Sons, 2008.
4. Jonathan Gross and Jay Yellen, Graph Theory and its Applications, CRC Press, 2006.
5. Narsingh Deo, Graph Theory with Applications to Engineering and Computer Science, Prentice
Hall,2004.
13AE12 / 13VL12 ANALOG VLSI CIRCUIT DESIGN
3003
Objectives
 To understand the operation of BJTs and MOS devices.
 To analyze various devices in small and large signal conditions.
 To impart in-depth knowledge about switched capacitors, ADCs and DACs.
 To acquire knowledge of how a circuit works.
 To learn to analyze the circuit.
 To view analog integrated circuit design from a hierarchical viewpoint.
 To realize schematic of the circuit, dc currents, and W/L ratio.
(d) Able to understand and design advanced Analog circuit and conduct experiments, analyze and
interpret data.
Unit I
CMOS Technology and Device Modeling
Basic MOS semiconductor fabrication processes-other considerations of CMOS technology-MOS large
signal model and parameters-Small signal model for the MOS transistor-Computer simulation models-Sub
threshold MOS model.
9 Hours
Unit II
Analog CMOS Sub circuits, CMOS Amplifiers
MOS switch-MOS diode and active resistor-Current sinks and sources-Current mirrors-Current and voltage
References:-Band gap References:-Invertors-Differential amplifiers - Cascode amplifiers – Current
amplifiers - Output amplifiers- High gain amplifiers architectures.
9 Hours
Unit III
High-Performance CMOS Operational Amplifiers
Buffered operational amplifiers-High speed and frequency operational amplifiers-Differential output
operational amplifiers-Microwave operational amplifiers - Low noise operational amplifiers - Low voltage
operational amplifiers.
9 Hours
Unit IV
Switched Capacitor Circuits
Switched Capacitor Circuits-Switched Capacitor amplifiers-Switched Capacitor integrators-z domain
models of two phase switched capacitor circuits-First order switched capacitor circuits- Second order
switched capacitor circuits-Switched Capacitor Filters.
9 Hours
Unit V
Digital-Analog and Analog-Digital Converters
Introduction and characterization of DAC-Parallel DAC-Extending the resolution of parallel DAC-Serial
DAC-Introduction and characterization of ADC-Serial ADC-Medium ADC-High speed ADC.
9 Hours
Total: 45 Hours
Reference(s)
1. Phillip E.Allen and Douglas R.Holberg, CMOS Analog Circuit Design, Oxford University Press,
2002.
4
2. Malcom R.Haskard and Lan C.May, Analog VLSI Design - NMOS and CMOS, Prentice Hall,
1998.
3. Jose E.France and Yannis Tsividis, Design of Analog-Digital VLSI Circuits for
Telecommunication and Signal Processing, Prentice Hall, 1994.
4. Randall L Geiger, Phillip E. Allen and Noel K.Strader, VLSI Design Techniques for Analog and
Digital Circuits, Mc Graw Hill International Company, 1990.
5. K.Radhakrishna Rao, Electronics for Analog Signal Processing-I, NPTEL, Courseware, 2005
13AE13/13ES15 DIGITAL SYSTEM DESIGN
3104
Objectives
 To understand the concepts of Asynchronous Sequential Circuit Design.
 To study the concepts of Fault Diagnosis and Testability Algorithms.
 To understand the concepts of System Design Using VHDL and Programmable Devices.
 Design and analysis of asynchronous sequential circuit
 Explore fault diagnosis and testability algorithm
 Study of programmable logic devices
 Design and analysis of clocked synchronous sequential networks
formulate, solve novel advanced electronics engineering along with soft computing and
(e) Able to use modern engineering tools, software and equipments to analyze problems.
(f) Able to plan, conduct an organized and systematic study on significant research topic within the
field.
Unit I
Sequential Circuit Design
Analysis of Clocked Synchronous Sequential Networks (CSSN) Modeling of CSSN – State Stable
Assignment and Reduction – Design of CSSN – Design of Iterative Circuits – ASM Chart –ASM
Realization.
9 Hours
Unit II
Asynchronous Sequential Circuit Design
Analysis of Asynchronous Sequential Circuit (ASC) – Flow Table Reduction – Races in ASC – State
Assignment – Problem and the Transition Table – Design of ASC – Static and Dynamic Hazards –
Essential Hazards.
9 Hours
Unit III
Fault Diagnosis and Testability Algorithms
Fault Table Method – Path Sensitization Method – Boolean Difference Method – Kohavi Algorithm –
Tolerance Techniques – The Compact Algorithm – Fault in PLA – Test Generation – Masking Cycle –
Built- in Self Test.
9 Hours
Unit IV
Synchronous Design Using Programmable Devices
EPROM to Realize a Sequential Circuit – Programmable Logic Devices – Designing a Synchronous
Sequential Circuit using a GAL – EPROM – Realization State machine using PLD – FPGA – Xilinx FPGA
– Xilinx 2000 -Xilinx 3000.
9 Hours
Unit V
System Design Using VHDL
VHDL Description of Combinational Circuits – Arrays – VHDL Operators – Compilation and Simulation
of VHDL Code – Modeling using VHDL – Flip Flops – Registers – Counters – Sequential Machine –
5
Combinational Logic Circuits - VHDL Code for – Serial Adder, Binary Multiplier – Binary Divider –
complete Sequential Systems – Design of a Simple Microprocessor.
9 Hours
Total: 45+15 Hours
Reference(s)
1. G.Donald Givone, Digital principles and Design, Tata McGraw Hill 2002.
2. M.John Yarbrough, Digital Logic Applications and Design, Thomson Learning, 1996.
3. N.Nripendra Biswas, Logic Design Theory, Prentice Hall of India, 2001.
4. H.Charles Roth, Digital System Design using VHDL, Thomson Learning, 2007.
5. H.Charles Roth, Fundamentals of Logic design, Thomson Learning, 2003.
6. Stephen Brown and Zvonk Vranesic, Fundamentals of Digital Logic with VHDL Design, Tata
McGraw Hill, 2008.
7. D. Roychoudhury, Digital System Design, NPTEL Video Courseware,2009.
13AE14 / 13CO13 / 13ES16 ADVANCED DIGITAL SIGNAL PROCESSING
3104
Objectives
 To explore the concepts of multi rate signal processing and multi rate filters.
 To study the adaptive filters and its applications.
 To learn fundamental concepts on signal processing in power spectrum estimation.
 Acquiring knowledge of how a multi rate system works.
 Ability to design and implement decimator and interpolator and to design multi rate filter bank.
 Understanding different spectral estimation techniques and linear prediction.
 Ability to design LMS and RLS adaptive filters for signal enhancement, channel equalization.
 Apply above knowledge and skills to engineering problems.
Programme outcomes (POs)
(a) Able to apply knowledge from basic engineering and other disciplines to identify, formulate and
present solutions to technical problems in a variety of specialty area related to telecommunications
engineering technology.
(b) Able to learn new related technologies in the fields of telecommunication and wireless networks
along with the concepts of that require advanced knowledge within the field.
(d) Able to use the techniques, skills, modern engineering tools, software and equipment necessary to
evaluate and analyze the systems in telecommunication environments.
Unit I
Multirate signal Processing
Introduction-Sampling and Signal Reconstruction-Sampling rate conversion – Decimation by an integer
factor – interpolation by an integer factor –Sampling rate conversion by a rational factor –poly-phase FIR
structures – FIR structures with time varying coefficients - Sampling rate conversion by a rational factor-
Multistage design of decimator and interpolator.
9 Hours
Unit II
Multirate FIR Filter Design
Design of FIR filters for sampling rate conversion –Applications of Interpolation and decimation in signal
processing –Filter bank implementation –Two channel filter banks-QMF filter banks –Perfect
Reconstruction Filter banks – tree structured filter banks - DFT filter Banks – M-channel filter banks-
octave filter banks
9 Hours
Unit III
Linear Estimation and Prediction
Linear prediction- Forward and backward predictions, Solutions of the Normal equations- Levinson-Durbin
algorithms. Least mean squared error criterion -Wiener filter for filtering and prediction , FIR Wiener filter
and Wiener IIR filters ,Discrete Kalman filter.
9 Hours
6
Unit IV
Adaptive Filters
FIR Adaptive filters - Newton's steepest descent method – Adaptive filters based on steepest descent
method - LMS Adaptive algorithm – other LMS based adaptive filters- RLS Adaptive filters -
Exponentially weighted RLS - Sliding window RLS - Simplified IIR LMS Adaptive filter-Applications:
Adaptive channel equalization - Adaptive echo canceller - Adaptive noise cancellation.
9 Hours
Unit V
Power Spectral Estimation
Estimation of spectra from finite duration observations of a signal –The Periodogram-Use of DFT in Power
spectral Estimation –Non-Parametric methods for Power spectrum Estimation – Bartlett. Welch and
Blackman–Tukey methods –Comparison of performance of Non – Parametric power spectrum Estimation
methods –Parametric Methods - Relationship between auto correlation and model parameters, Yule-Walker
equations, solutions using Durbin’s algorithm,AR, MA, ARMA model based spectral estimation.
Application: speech enhancement using power spectrum estimation
9 Hours
Total: 45 Hours
Reference(s)
1. H. Monson Hayes, Statistical Digital Signal Processing and Modeling, John Wiley and Sons,2008.
2. G.. John Proakis and G. Dimitris Manolakis, Digital Signal Processing, Pearson Education, 2006.
3. P.P.Vaidyanathan , Multirate Syatems and Filter Banks, Pearson Education, 2008.
4. N.J.Filege, Multirate Digital Signal Processing, John Wiley and Sons, 2000.
5. G..John Proakis, Algorithms for Statistical Signal Processing, Pearson Education, 2002.
6. G.Dimitris and G.Manolakis., Statistical and Adaptive Signal Processing, McGraw Hill, 2002.
7. Sophoncles J. Orfanidis, Optimum Signal Processing, McGraw Hill, 2007.
13AE15 MICROPROCESSORS AND EMBEDDED SYSTEMS
3003
Objectives
 To understand RISC and CISC architecture and evaluation.
 To acquire sound knowledge about ARM processors and CPU cores.
 To understand the concepts of 32 bit Free scale Cold Fire Processors and Programming skills.
 Analysis the procedure for various microprocessor Architecture
 Identification of types of interrupts and exceptions related to microprocessor Systems
 Diagnose the design in methodologies in hardware and software design.
 Identification of new developments in microprocessor systems.
(c) Able to apply advanced technical knowledge in multiple contexts;
(d) Able to use modern engineering tools, software and equipments to analyze problems.
Unit I
RISC and CISC Architecture
Instruction set – Data formats – Instruction formats – Addressing modes – Memory hierarchy – register file
Cache – Virtual memory and paging – Segmentation – Pipelining – The instruction pipeline – pipeline
Hazards The software model – functional description – CPU pin descriptions – RISC concepts – bus
operations – Super scalar architecture – pipe lining – Branch prediction – The instruction and caches –
Floating point unit –protected mode operation – Segmentation – paging – Protection – multitasking –
Exception and interrupts – Input /Output – Virtual 8086 model – Interrupt processing -Instruction types –
Addressing modes – Processor flags – Instruction set -programming the Pentium processor.
9 Hours
7
Unit II
ARM Processors
The ARM architecture – ARM assembly language program – ARM organization and implementation –
The ARM instruction set - The thumb instruction set – ARM CPU cores.
9 Hours
Unit III
Freescale ColdFire 32 bit Processor
Introduction to ColdFire Core, User and Supervisor Programming Model, Addressing modes, Special
instructions, Exceptions and Interrupt controller, cache, DMA controller, Flex CAN, Fast Ethernet
Controller, USB, Timers, TPU, Code Warrior tools.
9 Hours
Unit IV
Embedded Architecture
Embedded systems Overview, Design Challenge – Optimizing design metrics, Processor Technology,
Embedded system design process- Requirements, Specification, Architectural Design, Designing Hardware
and Software Components, System Integration.
9 Hours
Unit V
Real-Time Characteristics
Introduction to RTOS- Special considerations in an RTOS, Clock driven Approach, weighted round robin
Approach, Priority driven Approach, Dynamic Versus Static systems, effective release times and deadlines,
Optimality of the Earliest deadline first (EDF) algorithm, challenges in validating timing constraints in
priority driven systems, Off-lineVersus On-line scheduling
9 Hours
Total: 45 Hours
Reference(s)
1. Daniel Tabak, Advanced Microprocessors, McGraw Hill, 2001.
2. L. James Antonakos, The Pentium Microprocessor, Pearson Education, 2000.
3. Munir Bannaoura, Rudan Bettelheim and Richard Soja, ColdFire Microprocessors and
Microcontrollers, AMT Publishing, 2007.
4. Steve Furber, ARM System –On –Chip architecture, Addison Wesley, 2000.
5. S.P. Das, Microcontrollers and Applications, NPTEL Courseware, 2004.
6. Wayne Wolf, Computers as Components: Principles of Embedded Computing System Design,
Morgan Kaufman Publishers, 2008.
7. Jane.W.S Liu, Real-Time systems, Pearson Education Asia, 2000.
13AE16 MACHINE VISION
3003
Objectives
 To learn the image fundamentals and mathematical transforms necessary for image processing.
 To understand the image enhancement and restoration methods.
 To study the concepts of optics and lens systems.
1. Analysis image enhancement and edge detection methods
2. Diagnose the degree of complications in optical image processing methods
3. Identification of new developments in object recognition systems.
4. Analysis the procedure for various image processing principles in machine vision.
field
8
Unit I
Binary Image processing
Introduction – Machine vision –Relationship to other fields –Image definitions levels of computation-
Binary image processing – Thresholding Geometric properties – position –orientation –Run length
encoding Binary algorithms – Definitions - Component labeling –Size filter –Euler number –Region
boundary –Area perimeter – compact Distance measures- Distance transforms – Medial axis – Thinning
expanding and shrinking –morphological operators.
9 Hours
Unit II
Regions
Regions and Edges - Regions segmentation – Automatic thresholding, Limitations of Histogram methods –
Region representation – array representation - Hierarchical representation - Split and merge – region
merging –Removing weak edges –Region splitting - split and merge – Region growing.
9 Hours
Unit III
Edge detection
Gradient – Steps in edge deduction –Roberts operator –sober operator – pewit operator –Comparison
Second derivative operator, Laplacian operator, Second derivative Image approximation – Gaussian edge
Detection –Canny edge detector –Subpixel location estimation –Edge detector performance- methods of
Evaluating performance – Figure of merit –Sequential methods – Line detection.
9 Hours
Unit IV
Optics and shading
Optics – lens equation –Image resolution –Depth of Field view volume –Exposure- shading – Image
Inductance –Illumination – Reflector –Surface orientation –shape from shading depth –Stereo imaging –
Cameras in arbitrary position and orientation –Stereo matching –Edge matching – Region correlation shape
from X – Range imaging – structural lighting – Imaging Radar- Active vision.
9 Hours
Unit V
Dynamic vision & object recognition
Change detection –Difference pictures – Static segmentation and matching –object recognition – system
components – complexity of object recognition – object representation -observer -centered –object
centered representations – feature detection –recognition strategies – classification – Matching Feature
indexing - verification – Temperature matching –morphological approach – symbolic – analogical
methods.
9 Hours
Total: 45 Hours
Reference(s)
1. Ramesh Jain, RangacharKasturi and Brian G. Schunck, Machine Vision, McGraw Hill
International Edition, 2006.
2. Anil K. Jain, Fundamentals of Digital Image Processing, PHI, 2006.
3. Gregory A Baxes, Digital Image Processing, John Wiley & Sons, 1994.
4. W.K. Pratt, Digital Image Processing, John Wiley and Sons, 2001.
13AE17 ELECTRONICS DESIGN LABORATORY I
0032
Objectives
 To design and simulate digital circuits.
 To write programs in VHDL and Verilog for modeling digital circuits
 To study and verify the combinational and sequential logic circuits with various levels of
modeling and EDA Tools.
 To study this course the student will know basic electronics involved in the design of MOS
circuits
9
Course Outcomes(CO)
 Student will be able to make models of transistor circuits and simulate them for various
operational requirements.
 Design of different types of multiplier using EDA Tool.
 Design of FIR Filter using EDA Tool.
 Analysis and design of VLSI circuits.
(d) Able to understand and design advanced electronics systems (Analog and Digital Systems) and
conduct experiments, analyze and interpret data
field
List of Experiments
Simulation and Implementation of FPGA:
1. Design and simulation of Sequential circuits using HDL,
2. Design and Implementation of ALU, shift registers and carry save adder using HDL.
3. Design and Implementation of Multiplier using HDL
4. Design and Implementation of FSM using HDL
5. Design and Implementation of Traffic Light Controller using VHDL
6. Writing Test benches using VHDL/ Verilog.
TANNER EDA and MENTOR GRAPHICS Experiments:
7. Design and simulation of combinational circuits using EDA Tools.
8. Design and simulation of Sequential Circuit using EDA Tools.
9. IC layout design using EDA Tools
10. Design and simulation of Analog circuits using EDA Tools
11. Mini project
Total: 45 Hours
13AE18 MICROPROCESSORS AND EMBEDDED LABORATORY
0032
Objectives
 To understand and Implement Microprocessor based system using ColdFire and ARM processor.
 To understand and Implement Microcontroller based system using following Devices
S12X Microcontroller, PIC Microcontroller
 To Interface the peripherals using Microprocessor and Microcontroller.
 Embedded Programming skills can be improved.
 Real Time Application oriented design can be developed with advanced processor and controller.
 Ability to interface the peripherals with the ARM and Coldfire processors.
Programme outcomes (POs)
[[
(a) Able to understand the advanced architecture of processors and Controllers.

(b) Able to interface the peripherals with the processors and Controllers.
(c) Able to understand about the data conversion in controller.
(d) Able to use advanced processor and controllers ,software and equipments to analyze problems.
(e) Able to plan, conduct an organized and systematic study on significant research topic within the
[
field.
List of Experiments
1. Design and Implementation of various peripherals interfacing in S12x Controllers.
2. Design and development of embedded application using S12x Microcontroller.
3. Implementation of serial communication using S12x Microcontroller.
4. Design and development of digital application using ColdFire.
5. Design and Implementation of Display interfacing using PIC microcontroller.
10
6. Design and development of Embedded system using ARM Processors.

7. Miniprojects.
Total: 45 Hours
13AE21 AUTOMOTIVE ELECTRONICS
3003
Objectives
 To study the basics of automotive electronics.
 To understand sensors and activators
 To study charging systems
Course Outcomes(COs)
 To study different batteries and its efficiency.
 To learn different starters and regulators.
 To study sensor types.
(i) Able to become knowledgeable about contemporary developments.
Unit I
Fundamentals of Automotive Electronics
Current trends in automotive electronic engine management system, electromagnetic interference
suppression, electromagnetic compatibility, electronic dashboard instruments, onboard diagnostic system-
Security and warning system.
9 Hours
Unit II
Starting System
Condition at starting, behavior of starter during starting, series motor and its characteristics, principle and
construction of starter motor, working of different starter drive units, care and maintenances of starter
motor-Starter switches.
9 Hours
Unit III
Charging System
Generation of direct current, shunt generator characteristics, armature reaction, third brush regulation,
cutout. Voltage and current regulators, compensated voltage regulator, alternators principle and
constructional aspects-Bridge rectifiers and new developments.
9 Hours
Unit IV
Batteries and Accessories
Principle and construction of lead acid battery, characteristics of battery, rating capacity and efficiency of
batteries, various tests on batteries, maintenance and charging. Lighting system: insulated and earth return
system, details of head light and side light, LED lighting system, head light dazzling and preventive
methods-Horn, wiper system and trafficator.
9 Hours
Unit V
Sensors and Activators
Types of sensors: sensor for speed, throttle position, exhaust oxygen level, manifold pressure, crankshaft
position, coolant temperature, exhaust temperature, air mass flow for engine application. Solenoids-Stepper
motors and relay.
9 Hours
Total: 45 Hours
Reference(s)
1. Bechhold,Understanding Automotive Electronics, SAE, 1998.
2. W.H.Crouse ,Automobile Electrical Equipment, McGraw-Hill, 1996.
3. A W Judge, Modern Electrical Equipment of Automobiles, Chapman & Hall, 1992.
4. P.L.Kholi, Automotive Electrical Equipment, Tata McGraw-Hill, 1995.
11
5. Robert Bosch Automotive Hand Book, SAE, 2000.

6. A.P.Young, L.Griffiths Automotive Electrical Equipment, ELBS & New Press, 1999.
7. William.B.Riddens, Understanding Automotive Electronics, Butter worth Heinemann Woburn,
1998.
13AE22/13VL01 NEURAL COMPUTING
3 1 04
Objectives
 To study the concepts of biological and artificial neurons
 To explore the fundamentals of various algorithms related to supervised neural networks and its
applications
 To explore the Applications of various algorithms related Genetic algorithms and SVM
Course outcome (COs)
 Analysis the procedure for various neural network principles in real world problem.
 Analysis feature enhancement and optimization methods
 Analysis the windowing of better solution in rough surface searching algorithms both using
association and non association rules.
 Identification of new developments in object recognition systems
Program Outcomes (POs)
field
Unit I
Fundamental Concepts and Models of Artificial Neural Systems
Biological Neurons and their Artificial models, Models of Artificial Neural Networks, Learning and
Adaptation, Neural Network Learning Rules, Single Layer Perceptron Classifiers.
9 Hours
Unit II
BPN and BAM
Back Propagation Network, Generalised Delta Rule, BPN Application, Associative Memory Definition,
BAM,Hop field Memory,Simulated Annealing-Boltzmann Machine.
9 Hours
Unit III
Other Networks
Counter Propagation Network, Feature Mapping, Self Organizing Feature Maps, Adaptive Resonance
Theory (ART) Network-Spatio-temporal neural networks Descriptions and applications.
9 Hours
Unit IV
Genetic Algorithms & Implementation Techniques
The Appeal of Evolution, Search Spaces and Fitness Landscapes, Elements of Genetic Algorithms,
Data Structures, Adaptive Encoding. Selective Methods, Genetic Operators, Fitness Scaling
9 Hours
Unit V
Advances and Applications
Support Vector Machines, RBF Network, Neocognitron Evolving neural networks using GA,
Applications of ANN in signal analysis and Medical image analysis
9 Hours
Total: 45+15 Hours
12
Reference(s)
1. Sathish Kumar, Neural networks-A Class Room approach, third edition, Tata Mc Graw Hill
New Delhi, 2012
2. James Freeman A. and David Skapura M., Neural Networks - Algorithms, Applications &
Programming Techniques, Addison Wesley, 1992.
3. Yegnanarayana B., Artificial Neural Networks, Prentice Hall of India Private Ltd., New Delhi,
1999.
4. Laurence Fausett, Fundamentals of Neural Networks: Architecture, Algorithms and Applications,
5. Prentice Hall, 1994.
6. Simon Haykin, “Neural Networks: A Comprehensive Foundation”, 2nd Edition,Prentice Hall
India,2002..
7. David Goldberg, Genetic Algorithms in Search, Optimization and Machine
Learning, Addison - Wesley USA,1997.
8. Melanie Mitchell, An Introduction to Genetic Algorithms: Prentice Hall of India, New
Delhi 1998.
13AE23/13ES21 DIGITAL CONTROL SYSTEMS
3 10 4
Objectives
 To learn the fundamental principles of feedback control and dynamic systems
 To acquire the concepts of Optimal Control Systems and Digital Control Systems
 To Model and control hybrid systems
 To learn how to perform the stability analysis of Feedback Control Systems
 be familiar with The Design of Feedback Control Systems employing the previously learnt
techniques such as the Bode Diagram, and the Root Locus method
 Become familiar with issues faced in sampling, digital data and discrete time systems.
 acquire the concepts of the Stability in the Frequency Domain employing The Nyquist Criterion,
the Relative Stability, and Time Domain Performance Criteria in the Frequency Domain
(c) Able to apply advanced technical knowledge in multiple contexts
Unit I
Introduction to Control Systems
Brief History of Automatic Control - Engineering Design - Control System Design - Differential Equations
of Physical Systems - Linear Approximations of Physical Systems - The Transfer Function of Linear
Systems - The State Variables of a Dynamic System - The State Differential Equation - The Transfer
Function from the State Equation - The Time Response and the State Transition Matrix
9 Hours
Unit II
Feedback Control System
Introduction - Error Signal Analysis - Sensitivity of Control Systems to Parameter Variations - Disturbance
Signals in a Feedback Control System - Control of the Transient Response - Steady-State Error - The Cost
of Feedback - Test Input Signals - Performance of Second-Order Systems - Effects of a Third Pole and a
Zero on the Second-Order System Response - The s-Plane Root Location and the Transient Response - The
Steady-State Error of Feedback Control Systems - Performance Indices
9 Hours
13
Unit III
The Stability of Linear Feedback Systems
The Concept of Stability - The Routh—Hurwitz Stability Criterion - The Relative Stability of Feedback
Control Systems - The Stability of State Variable Systems - The Root Locus Concept - The Root Locus
Procedure - Sensitivity and the Root Locus - PID Controllers - Negative Gain Root Locus
9 Hours
Unit IV
Frequency Response
Frequency Response Plots - Frequency Response Measurements - Performance Specifications in the
Frequency Domain - Log Magnitude and Phase Diagrams - The Nyquist Criterion - Relative Stability and
the Nyquist Criterion - Time-Domain Performance Criteria in the Frequency Domain - PID Controllers in
the Frequency Domain - Phase-Lead Design - Phase-Lag Design
9 Hours
Unit V
Sampled-Data Systems
Introduction - Digital Computer Control System Applications - Sampled-Data Systems - The z-Transform -
Closed-Loop Feedback Sampled-Data Systems - Performance of a Sampled-Data, Second-Order System -
Closed-Loop Systems with Digital Computer Compensation - The Root Locus of Digital Control Systems -
Implementation of Digital Controllers - Design Examples
9 Hours
Total : 45+15 Hours
Reference(s)
1. Bishop and Dorf, Digital control systems Design, Prentice Hall; 12 edition, 2010
2. Mohammed S. Santina, Allen R. Stubberud, Gene H. Hostetter, Digital control system design,
Oxford University Press, 2 edition, 1994
3. Gopal, Digital Control and State Variable Methods, Tata McGraw Hill, 2008
13AE24 ADVANCED ELECTRONICS DESIGN LABORATORY
0032
Objectives
 To learn the student will be able to, Write programs in VHDL and verilog for modeling digital
circuits
 To study this course the student will know basic electronics involved in the design of MOS
circuits.
 To design a schematic and layout for Combinational and Sequential Circuits and to analyze the
power and timing of Combinational and Sequential Circuits using EDA tools
 By studying this subject the student will be able to make models of transistor circuits and simulate
them for various operational requirements.
 Design of different types of multiplier using TANNER EDA Tool.
 Design of FIR Filter using TANNER EDA Tool.
 Analysis and design of VLSI circuits.
Program outcomes (POs)
(f ) Able to plan, conduct an organized and systematic study on significant research topic within the
field .
List of Experiments
Simulation and Implementation OF FPGA
a. Design and simulation of Multiplier using HDL
14
b. Design and Implementation of Stepper Motor and Seven Segment Display using HDL
c. Design and Implementation 32x8 bit ROM and RAM model using VHDL
d. Design and Implementation of FIR filter using HDL
e. Design and Implementation of Lift controller using HDL.
TANNER EDA and MENTOR GRAPHICS Experiments
f. Design and simulation of Multiplier using EDA Tools.
g. Design and simulation of 4-tap FIR Filter using EDA Tools
h. Draw the layout diagram for combinational Circuits using EDA Tools.
i. Generation of synthesis report using Mentor Graphics using EDA Tools
j. Design, implementation, layout generation and verification of a digital building block using an
EDA tool
Mini project
Total : 45 Hours
15
Syllabi: M.E Applied Electronics (Electives) │Minimum Credits to be Earned: 75│Regulation 2013
13AE51 ADVANCED WIRELESS NETWORKS

3003
Objectives
 To study fundamentals of 4G networks
 To explore issues and challenges in designing adaptive MAC for adhoc networks
 To understand adaptation of the routing protocols in mobile networks
 To explore issues and challenges in sensor network deployment
 To develop security protocols for wireless networks
 Ability to identify the various challenges in 4G networks
 Obtain awareness for adaptation in MAC, IP, protocols for advanced mobile networks.
 Understand and recognize the architectures, designing TCP and security protocols
 Analyze the solutions for covering the security principles of wireless networks.
 Analyze and design security systems for wireless networks.
 Apply in-depth knowledge of wireless communications principles, systems, and networks to the
solution of wireless engineering problems.
(j) Able to develop confidence for self education and lifelong learning.
Unit I
Fundamentals of 4G Networks
Protocol Boosters-Hybrid 4G Wireless Network Protocols-Green Wireless Networks-Physical Layer and
Multiple Access-ATDMA-CDMA-OFDM.
9 Hours
Unit II
Adaptive MAC and Network Layer
WLAN Enhanced Distributed Coordination Function- Adaptive MAC for WLAN – MAC for Wireless
Sensor Networks-MAC for AdHoc Networks-Adaptive Network Layer- Graphs and Routing Protocols –
Graph theory – Routing topology Aggregation – Network and Aggregation Models.
9 Hours
Unit III
Adaptive TCP Layer
Introduction-TCP operations and Performance – TCP for Mobile Cellular Networks-RED Gateways for
Congestion Avoidance- TCP for Mobile AdHoc Networks – Cross Layer optimization – Introduction to
Mobility Management- Location Registration and Call Delivery in 4G.
[
9 Hours
Unit IV
AD HOC Networks
Routing protocols – Hybrid Routing Protocols – Scalable Routing Strategies – Multipath Routing –
Clustering Protocols – Caching Schemes for Routing- Distributed QoS Routing.
9 Hours
Unit V
Sensor Networks and Security
Introduction – Sensor Networks parameters- Architecture – Mobile Sensor Networks Deployment-
Directed Diffusion- Aggregation in Wireless Sensor Networks – Boundary Estimation – Back off
16
Phenomenon- Data Funneling- Equivalent Transport Control Protocols in Sensor Networks – Security –
Authentication – Security Architecture- Key management – Security management in GSM, UMTS –
Security in AdHoc and Sensor Networks.
9 Hours
Total: 45 Hours
Reference(s)
1. Young Kyun Kim and Ramjee Prasad,4G Roadmap and Emerging Communication
Technologies, Universal Personal Communication Series, Artech House, Boston, 2006.
2. Hendrik Berndt, Towards 4G Technologies, Wiley Publishers, Lancaster, England, 2008.
3. IEEE Transactions on Networking.
4. IEEE Transactions on Mobile Computing.
13AE52 MEDICAL IMAGE PROCESSING

3003
Objectives
 To study about various medical image acquisition methods.
 To understand 2D and 3D image reconstruction techniques.
 To gain sound knowledge about CT, MRI, nuclear and ultrasound imaging.
 To realize the factors those affect the quality of medical images.
 Bring out the procedure for medical image acquisitions.
 Describe and determine the performance of different Image reconstruction techniques.
 Analysis the physiological events associated with the human system.
 Describe the influences of artifacts in image quality
 Identification of new developments in health care system
(e) Able to demonstrate the skills to use modern engineering tools, software and equipment to analyze
problems.
Unit I
Acquisition of Images
Introduction to Imaging Techniques- Single crystal scintillation camera – Principles of scintillation camera
– multiple crystal scintillation camera –solid state camera –rectilinear scanner –Emission computed
Tomography.
9 Hours
Unit II
Mathematical Preliminaries for Image Reconstruction
Image Reconstruction from Projections in Two dimensions –Mathematical Preliminaries for Two and
Three dimensional Image Reconstructions –Radon Transform –Projection Theorem –central slice Theorem
– Sinogram – Two Dimensional Projection Reconstruction –Three Dimensional Projection Reconstruction
– Iterative Reconstruction Techniques.
9 Hours
17
Unit III
Fluoroscopy, CT, Image quality
Digital fluoroscopy – Automatic Brightness control- cinefluorography –Principles of computed
Tomographic Imaging- Reconstruction algorithms- Scan motions – X –ray sources Influences of Images
quality:Unsharpness – contrast- Image Noise.
9 Hours
Unit IV
Magnetic Resonance Imaging and Spectroscopy
Fundamentals of magnetic resonance – overview – Pulse techniques – spatial encoding of magnetic
resonance imaging signal – motion suppression techniques – contrast agents- tissue contrast in MRI – MR
angiography, spectrography.
9 Hours
Unit V
Ultra sound, Neuro magnetic Imaging: ultra Sound: Presentation modes – Time required to obtain
Images – System components, signal processing –dynamic Range – Ultrasound Image Artifacts – Quality
control, Origin of Doppler shift – Limitations of Doppler systems. Neuromagnetic Imaging: Background
9 Hours
Total : 45 hours
Reference(s)
1. William R. Hendee, E. Russell Ritenour, Medical Imaging Physics: A John Wiley & sons, Inc.,
Publication, Fourth Edition 2002.
2. Z.H. Cho., J-oie, P. Jones and Manbir Singh, Foundations of Medical Imaging: John Wiley and
sons Inc.
3. Avinash C. Kak, Malcolm Shaney, Principles of Computerized Tomographic Imaging, IEEE
Press, Newyork-1998.
13AE53 MULTIMEDIA COMMUNICATION SYSTEMS

3003
Objectives
 Identify the various Multimedia Networking characteristics.
 The ability to apply Broad Band Network Technology.
 The ability to apply above knowledge and skills to compression techniques
 To explore the special features and representations of different data types.
 To analyze different Multimedia Communication Standards
 To analyze Transport Protocol and Applications
conduct experiments, analyze and interrupt data.
Unit I
Multimedia Networking
Digital sound, video and graphics – Basic multimedia networking - Multimedia characteristics- Evolution
of Internet services model - Network requirements for audio/ video transform-Multimedia coding and
compression for text , image, audio and video.
9 Hours
18
Unit II
Broad Band Network Technology
Broadband services - ATM and IP - IPV6 - High speed switching - Resource reservation – Buffer
management - Traffic shaping – Caching - Scheduling and policing – Throughput - Delay and jitter
performance. Storage and media services, voice and video over IP - MPEG-2 over AM/IP – indexing
synchronization of requests - Recording and remote control
9 Hours
Unit III
Reliable Transport Protocol and Applications
Multicast over shared media network - Multicast routing and addressing - Scalping multicast and NBMA
networks - Reliable transport protocols - TCP adaptation algorithm – RTP - RTCP. MIME - Peer- to-Peer
computing - Shared application - Video conferencing - Centralized and distributed conference control
Distrbuted virtual reality - Light weight session philosophy.
9 Hours
Unit IV
Multimedia Communication Standards
Objective of MPEG- 7 standard - Functionalities and systems of MPEG-7 - MPEG-21 Multimedia
Framework Architecture - Content representation - Content Management and usage - Intellectual property
management – Audio visual system- H322: Guaranteed QOS LAN systems- MPEG_4 video Transport
across internet.
9 Hours
Unit V
Multimedia Communication across Networks
Packet Audio/video in the network environment - Video transport across Generic networks- Layered video
coding - Error Resilient video coding techniques - Scalable Rate control, Streaming video across Internet -
Multimedia transport across ATM networks and IP network – Multimedia across wireless Networks.
9 Hours
Total: 45 Hours
Reference(s)
1. Jon Crowcroft, Mark Handley and Ian Wakeman, Internetworking Multimedia, Harcourt Asia Pvt.
Ltd., 1999.
2. K.R Rao, Zoran S. Bojkovic and Dragorad A. Milovanovic, Multimedia Communication Systems,
PHI, 2003.
3. Tay Vaughan, Multimedia Making it to Work, Tata McGraw Hill, 2006.
13AE54/13CO59 WIRELESS SECURITY

3003
Objectives
 To explore variety of attacks and threats and its impact on MAC layer and Network layer
 To study characteristics, vulnerabilities and challenges of ad hoc networks
 To provide solution for covering the security principles and flaws of popular wireless technologies
 To evaluate the performance of secured routing protocols in MANETs.
 Ability to identify the various attacks and threads of wireless Networks.
 Understand and recognize the architectures, vulnerabilities and challenges of mobile protocols.
19

Unit I
Attacks on Routing Protocols
Vulnerability of MANET to attack - review of AODV and DSR - type of attack - active and passive -
internal and external - behavior of malicious node - black hole, DoS, Routing table overflow,
Impersonation, Energy consumption, Information Disclosure - Misuse type – Misuse goals – Security flaw
in AODV -attack on AODV - wormhole and rushing attack -Performance analysis of AODV in the
presence of malicious node.
9 Hours
Unit II
Intrusion Detection in Wireless Ad Hoc Networks
Problem in current IDS techniques - requirements of IDS - classification of IDS – Network and host based -
anamoly detection, misuse detection, specification based - intrusion detection in MANETs using distributed
IDS and mobile agents - AODV protocol based IDS - Intrusion resistant routing algorithms - Comparison
of IDS.
9 Hours
Unit III
Mitigating Techniques for Routing Misbehavior
Watchdog, Parthrater, Packet leashes and RAP.
9 Hours
Unit IV
Secure Routing Protocols:
Self organized network layer security in MANETs - mechanism to improve authentication and integrity in
AODV using hash chain and digital signatures - on demand secure routing protocol resilent to Byzantine
failures - ARIADNE, SEAD, SAR, and ARAN.
9 Hours
Unit V
Challenges in Routing Security
Security - Challenges and solutions - Providing Robust and Ubiquitous security support - Adaptive security
for multilevel Ad Hoc Network - Denial of service Attack at the MAC layer - Detection and handling of
MAC layer Misbehavior.
9 Hours
Total: 45 Hours
Reference(s)
1. C.Siva Ram Murthy and B.S.Manoj, AdHoc Wireless Networks: Architectures and Protocols,
Prentice Hall PTR, 2004.
2. Ivan Stojmenović, Handbook of Wireless Networks and Mobile Computing, Wiley, 2002.
3. Hongmei Deng, Wei Li and Dharma P. Agrawal, Routing Security in Wireless Ad Hoc Networks,
IEEE Communication Magazine, Oct 2002.
4. Peng Ning, Kun Sun, How To Misuse AODV: A Case Study of Insider Attacks Again Mobile Ad
Hoc Routing Protocols in proceeding of the 4th annaul IEEE information assurance workshop,
page 60 – 67 west point, June 2003.
5. Amitabh Mishra, Intrusion Detection in Wireless Ad Hoc Networks, IEEE Wireless
Communication, February 2004.
6. S.Marti, Mitigating Routing Misbehaviour in Mobile Ad Hoc Networks, ACM MOBICOM, 2000.
20
13AE55/13VL23/13ES60 LOW POWER VLSI DESIGN

3003
Objectives
 To understand different sources of power dissipation in CMOS & MIS structure.
 To understand the different types of low power adders and multipliers
 To focus on synthesis of different level low power transforms.
 To gain knowledge on low power static RAM architecture & the source of power dissipation in
SRAM
 To understand the various energy recovery techniques used in low power design
 An ability to analyze different source of power dissipation and the factors involved in.
 Able to understand the different techniques involved in low power adders and multipliers
 Understandings of the impact of various low power transform
 An ability to identify and analyze the different techniques involved in low power SRAM.
 Able to understand various energy recovery techniques.
(a) able to apply knowledge from undergraduate engineering and other disciplines to identify,
formulate and present solutions to technical problems in various engineering fields related to VLSI
design and technology.
(b) able to learn advanced technologies in the fields of VLSI design along with the fundamental
concepts
(c) able to apply advanced technical knowledge in multiple contexts
(f) able to plan, conduct an organized and systematic study on significant research topic within the
field of VLSI and its allied field.
Unit I
Power Dissipation in CMOS
Sources of power Dissipation–Physics of power dissipation in MOSFET devices, Power dissipation in
CMOS, Low power VLSI design limits.
9 Hours
Unit II
Low Power adders and multipliers
Standard adder cells, CMOS adder architectures, BiCMOS adder, overview and types of Multipliers- Braun
Multiplier, Baugh – Wooley Multiplier, Wallace Tree Multiplier, Booth Multiplier.
9 Hours
Unit III
Synthesis for Low power
Behavioral level transforms-Algorithm using First –Order, second, Mth Order Differences-Parallel
Implementation Pipelined Implementation- Logic level optimization– Technology dependent and
Independent– -Circuit level- Static,Dynamic,PTL,DCVSL,PPL.
9 Hours
Unit IV
Low power static RAM Architectures
Organization of a static RAM, MOS static RAM memory cell, Banked organization of SRAMs, Reducing
voltage swings on bit lines, Reducing power in the write diver circuits, Reducing power in sense amplifier
circuits.
9 Hours
Unit V
Low energy computing using energy recovery techniques
Energy dissipation in transistor channel using an RC model, Energy recovery circuit design, Designs with
partially reversible logic, Supply clock generation.
9 Hours
Total: 45 Hours
21
Reference(s)
1. K.Roy and S.C. Prasad, Low Power CMOS VLSI Circuit Design, Wiley, 2000.
2. K.S. Yeo and K.Roy, Low-Voltage, Low-Power VLSI Subsystems, Tata McGraw-Hill, 2004.
3. Dimitrios Soudris, Chirstian Pignet and Costas Goutis, Designing CMOS Circuits for Low
Power, Kluwer, 2009
4. James B. Kuo and Shin – Chia Lin, Low voltage SOI CMOS VLSI Devices and Circuits, John
Wiley and Sons, 2001.
5. J.B Kuo and J.H Lou, Low voltage CMOS VLSI Circuits, Wiley, 1999.
6. Gary Yeap, Practical Low Power Digital VLSI Design, Kluwer, 1997.
13AE56/13VL66 VLSI SIGNAL PROCESSING
3003
Objectives
 To understand the basic concepts of DSP algorithms.
 To analyze the various pipelining and parallel processing techniques.
 To analyze the retiming and unfolding algorithms for various DSP applications.
 To know the basics of signal processing algorithms.
 Identification of new algorithms in VLSI signals processing.
 Analysis of Z Transform and FFT using mathematical representation.
field.
Unit I
Introduction to DSP
Introduction To DSP Systems -Typical DSP algorithms Iteration Bound – data flow graph representations,
loop bound and iteration bound - Longest path Matrix algorithm - Pipelining and parallel processing –
Pipelining of FIR digital filters, parallel processing, pipelining and parallel processing for low power.
9 Hours
Unit II
Retiming
Retiming - definitions and properties; Unfolding – an algorithm for Unfolding, properties of unfolding,
sample period reduction and parallel processing application - Algorithmic strength reduction in filters and
transforms – 2-parallel FIR filter - 2-parallel fast FIR filter, DCT algorithm architecture transformation,
parallel architectures for rank-order filters, Odd- Even Merge- Sort architecture, parallel rank-order filters.
9 Hours
Unit III
Fast Convolution
Fast convolution – Cook-Toom algorithm, modified Cook-Took algorithm - Pipelined and parallel
recursive and adaptive filters – inefficient/efficient single channel interleaving, Look- Ahead pipelining in
first- order IIR filters, Look-Ahead pipelining with power-of-two decomposition, Clustered Look-Ahead
pipelining, parallel processing of IIR filters, combined pipelining and parallel processing of IIR filters,
pipelined adaptive digital filters, relaxed look-ahead, pipelined LMS adaptive filter.
9 Hours
22
Unit IV
Bit-Level Arithmetic Architectures
Scaling and round off noise- scaling operation, round off noise, state variable description of digital filters,
scaling and round off noise computation, round off noise in pipelined first-order filters - Bit-Level
Arithmetic Architectures- parallel multipliers with sign extension, parallel carry-ripple array multipliers,
parallel carry-save multiplier, 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and
implementation, design of Lyon’s bit-serial multipliers using Horner’s rule, bit-serial FIR filter, CSD
representation, CSD multiplication using Horner’s rule for precision improvement.
9 Hours
Unit V
Programming Digital Signal Processors
Numerical Strength Reduction – sub expression elimination, multiple constant multiplications, iterative
matching. Linear transformations - Synchronous, Wave and asynchronous pipelining- synchronous
pipelining and clocking styles, clock skew in edge-triggered single-phase clocking, two-phase clocking,
wave pipelining, asynchronous pipelining bundled data versus dual rail protocol - Programming Digital
Signal Processors – general architecture with important features; Low power Design – needs for low power
VLSI chips, charging and discharging capacitance, short-circuit current of an inverter, CMOS leakage
current, basic principles of low power design.
9 Hours
Total: 45 Hours
Reference(s)
1. Keshab K.Parhi, VLSI Digital Signal Processing Systems, Design and Implementation, Wiley Inte
Sci,2008.
2. Gary Yeap, Practical Low Power Digital VLSI Design, Kluwer Academic Publishers, 1998.
3. Mohammed Isamail and Terri Fiez, Analog VLSI Signal and Information Processing, Mc Graw-
Hill, 1994.
4. S.Y. Kung, H.J. White House and T. Kailath, VLSI and Modern Signal Processing, Prentice
Hall,1985.
5. Jose E. France and Yannis T sividis, Design of Analog - Digital VLSI Circuits for
Telecommunication and Signal Processing, Prentice Hall, 1994.
13AE57 DSP INTEGRATED CIRCUITS
3003
Objectives
 To learn how DSP applications are implemented using VLSI Technology.
 To understand various VLSI fabrication techniques and trends in CMOS technology
 To impart knowledge about the DSP Processor Architecture using VLSI Technology.
 Understanding of discrete-time transforms.
 The ability to design FIR and IIR filters.
 Knowledge of spectral estimation and linear prediction.
 The ability to apply above knowledge and skills to engineering problems.
Programme Outcomes(POs)
field.
23
Unit I
DSP Integrated Circuits and VLSI circuit Technologies
Standard digital signal processors-Application specific IC’s for DSP - DSP systems - DSP system design -
Integrated circuit design - MOS transistors - MOS logic - VLSI process technologies - Trends in CMOS
technologies.
9 Hours
Unit II
Digital Signal Processing
Digital signal processing - Sampling of analog signals - Selection of sample frequency – Signal -processing
systems - Frequency response - Transfer functions - Signal flow graphs - Filter structures - Adaptive DSP
algorithms - DFT - The Discrete Fourier Transform - FFT - The Fast Fourier Transform Algorithm - Image
coding - Discrete cosine transforms.
9 Hours
Unit III
Digital Filters and Finite Word Length Effects
FIR filters - FIR filter structures - FIR chips - IIR filters - Specifications of IIR filters - Mapping of analog
transfer functions - Mapping of analog filter structures - Multirate systems - Interpolation with an integer
factor L - Sampling rate change with a ratio L/M - Multirate filters - Finite word length effects - Parasitic
oscillations - Scaling of signal levels - Round-off noise - Measuring round-off noise - Coefficient
sensitivity - Sensitivity and noise.
9 Hours
Unit IV
DSP Architectures and Synthesis of DSP Architectures
DSP system architectures - Standard DSP architecture - Ideal DSP architectures - Multiprocessors and multi
computers - Systolic and Wave front arrays - Shared memory architectures - Mapping of DSP algorithms
onto hardware - Implementation based on complex PEs - Shared memory architecture with Bit-serial PEs.
9 Hours
Unit V
Arithmetic Units and Integrated Circuit Design
Conventional number system - Redundant Number system - Residue Number System - Bit-parallel and Bit-
Serial arithmetic - Basic shift accumulator - Reducing the memory size - Complex multipliers - Improved
shift – accumulator - Layout of VLSI circuits - FFT processor - DCT processor and Interpolator as case
studies.
9 Hours
Total: 45 Hours
Reference(s)
1. Lars Wan hammer, DSP Integrated Circuits, Academic Press, 1999.
2. A.V. Oppenheim, R.W.Schafer and J.R.Buck, Discrete-time Signal Processing, Prentice Hall,
2009.
3. Emmanuel C. I feachor and Barrie W.Jervis, Digital Signal Processing – A Practical Approach,
Pearson Education, 2001.
4. Keshab K. Parhi, VLSI Digital Signal Processing Systems Design and Implementation, John Wiley
& Sons, 2008.
13AE58/13ES56 COMPUTER AIDED DESIGN OF VLSI CIRCUITS
3003
Objectives
 To gain knowledge on graph theory based optimization techniques for the development of
Computer Aided Design tools for VLSI design.
 To understand various types of algorithms used in physical design process such as partitioning,
placement and routing.
24
 To obtain sound knowledge on simulations and synthesis process of CAD tools.

 Understanding the various types of graph models and data structure algorithms
 Understanding the concept behind the combinatorial optimization
 Problem solving skills for partitioning and routing algorithms
 Problem solving skills in synthesis process
field.
Unit I
VLSI Design and Graph Theory
Introduction to VLSI Design methodologies - Review of Data structures and algorithms - Review of VLSI
Design automation tools - Algorithmic Graph Theory and Computational Complexity - Tractable and
Intractable problems - general purpose methods for combinatorial optimization.
9 Hours
Unit II
Physical Design Process -I
Placement and partitioning - Circuit representation - Placement algorithms – partitioning Floor planning
concepts - shape functions and floor plan sizing.
9 Hours
Unit III
Physical Design Process -II
Types of local routing problems - Area routing - channel routing - global routing - algorithms for global
routing -Layout Compaction - Design rules - problem formulation - algorithms for constraint graph
compaction.
9 Hours
Unit IV
Simulations
Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation - Combinational
Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis.
9 Hours
Unit V
Synthesis
High level Synthesis - Hardware models - Internal representation - Allocation assignment and scheduling -
Simple scheduling algorithm - Assignment problem – High level transformations.
9 Hours
Lab components
1. Design of NAND Gate using TANNER
2. Design of NOR Gate using CADENCE VIRTUSO
3. Design of Combinational Circuits using CAD Tools
4. Design of Sequential Circuits using CAD Tools
Total: 45 Hours
25
Reference(s)
1. H. Gerez., Algorithms for VLSI Design Automation, John Wiley & Sons, 2002.
2. N.A Sherwani, Algorithms for VLSI Physical Design Automation, Kluwar Academic Publishers,
2002.
3. R.Drechsler, Evolutionary Algorithms for VLSI CAD, Kluwer Academic Publishers, 2010.
4. D.Hill, Shugard, J. Fishburn and K.Keutzer, Algorithms and Techniques for VLSI Layout
Synthesis, Kluwer Academic Publishers, 1989.
13AE59/13C069 EVOLUTIONARY COMPUTING

3003
Objectives
 To study different types of optimization techniques.
 To understand the concepts of genetic algorithms.
 To attain sound knowledge applications of soft computing.
 Analysis the procedure for various principles of Evolutionary computing in real world problem.
 Analysis feature enhancement and optimization methods using soft computing techniques.
 Identification of new developments in object recognition systems.
Unit I
Fuzzy Systems
Fuzzy set theory-fuzzy rules and fuzzy reasoning-fuzzy inference systems-decomposition-fuzzy automata
and languages-fuzzy control methods.
9 Hours
Unit II
Neural Networks
Basic concepts-knowledge based processing-single layer perceptron-multilayer perceptron-supervised and
unsupervised learning-feed forward and back propagation and counter propagation networks-kohens self
organizing networks-Hopfield networks.
9 Hours
Unit III
Neuro Fuzzy Modeling
Adaptive neuro fuzzy inference systems-classification and regression trees- data clustering-rule base
structure identification-neuro fuzzy controls.
9 Hours
Unit IV
Genetic Algorithms
Basics of GA- choice of encoding-selection probability-mutation and crossover-fitness evaluation
improving convergence rate-a simplex GA- Hybrid approach.
9 Hours
26
Unit V
Applications of Soft Computing
Fuzzy techniques for inverted pendulum case-SIRM fuzzy systems-MCDM for weather forecasting and
financial marketing-Neural networks for pattern recognition-TS problems-Routers - GA application to
metabolic modeling.
9 Hours
Total : 45 Hours
Reference(s)
1. Jang J.S.R.,Sun C.T and Mizutani E,“Neuro Fuzzy and Soft computing”, Pearson Education
(Singapore), 2006
2. David E.Goldberg, “Genetic Algorithms in Search, Optimization, and Machine Learning”,
Pearson Education, Asia, 2001.
3. Timothy J.Ross, “Fuzzy Logic Engineering Applications”, McGrawHill, NewYork, 2002.
4. S.Rajasekaran and G.A.Vijayalakshmi Pai, “Neural networks, Fuzzy logics and Genetic
algorithms”, Prentice Hall of India, 2003.
5. George J.Klir and Bo Yuan,”Fuzzy Sets and Fuzzy Logic”, Prentice Hall Inc., New Jersey, 2002.
13AE60/13CO51/13VL02 MULTIMEDIA COMPRESSION TECHNIQUES
3003
Objectives
 To explore the special features and representations of different data types.
 To analyze different compression techniques for text data and audio signals
 To analyze various compression techniques for image and video signals
 Identify the various compression techniques in text and audio.
 The ability to apply various compression techniques in image and video compression.
 The ability to apply above knowledge and skills to compression techniques.
Unit I
Introduction
Special features of Multimedia – Graphics and Image Data Representations – Fundamental Concepts in
Text, Images, Graphics, Video and Digital Audio – Storage requirements for multimedia applications -
Need for Compression – Lossy & Lossless compression techniques – Overview of source coding,
Information theory & source models- Kraft McMillan Inequality – vector quantization –LBZ algorithm.
9 Hours
Unit II
Text Compression
Compression techniques – Huffmann coding – Adaptive Huffmann Coding – Arithmetic coding – Shannon-
Fano coding – Dictionary techniques –LZ77, LZ78, LZW family algorithms.
9 Hours
Unit III
Audio Compression
Audio compression techniques - μ- Law and A- Law compounding - Frequency domain and filtering –
27
Basic sub-band coding –DPC M- ADPCM-DM-LPC-CELP -Application to speech coding – G.722 –

Application to audio coding – MPEG audio, progressive encoding for audio – Silence compression
techniques.
9 Hours
Unit IV
Image Compression
MMR coding –Transform Coding – JPEG Standard – Sub-band coding algorithms - Design of Filter banks
– Wavelet based compression - Implementation using filters – EZW, SPIHT coders – JPEG 2000 standards
- JBIG, JBIG2 standards- Run length coding.
9 Hours
Unit V
Video Compression
Video compression techniques and standards – MPEG Video Coding I: MPEG – 1 and 2 – MPEG Video
Coding II - MPEG – 4 and 7 – Motion estimation and compensation techniques – H.261 Standard – DVI
technology – DVI real time compression – Packet Video.
9 Hours
Total: 45 Hours
Reference(s)
1. Khalid Sayood, Introduction to Data Compression, Morgan Kauffman Harcourt India, 2005.
2. David Salomon, Data Compression – The Complete Reference, Springer Verlang, 2006.
3. Yun Q.Shi and Huifang Sun, Image and Video Compression for Multimedia Engineering –
Fundamentals, Algorithms & Standards, CRC press, 2003.
4. Peter Symes, Digital Video Compression, McGraw Hill Publication, 2004.
5. Mark Nelson, Data Compression, BPB Publishers, 2000.
6. Mark S.Drew and Ze-Nian Li, Fundamentals of Multimedia, PHI, 2003
13AE61/13ES03 RELIABILITY ENGINEERING
3003
Objectives
 To understand different test environments.
 To design an integrated reliability programmes and Production failure report.
 Discuss the techniques of enhancing system reliability.
 Develops and analyses reliability and cost models for hierarchical systems.
 Analysis of fault tree techniques for system reliability.
Unit I
Probability Plotting and Load-Strength Interference
Statistical distribution, statistical confidence and hypothesis testing, Probability plotting techniques –
Weibull, extreme value, hazard - binomial data- Analysis of load – strength interference, Safety margin and
loading roughness on reliability.
9 Hours
Unit II
Reliability Prediction, Modelling and Design
Statistical design of experiments and analysis of variance Taguchi method, Reliability prediction,
28
Reliability modeling, Block diagram and Fault tree Analysis ,Petric Nets, State space Analysis, Monte
Carlo simulation, Design analysis methods – quality function deployment, load strength analysis, failure
modes, effects and criticality analysis.
9 Hours
Unit III
Electronics and Software Systems Reliability
Reliability of electronic components, component types and failure mechanisms, Electronic system
reliability prediction, Reliability in electronic system design - software errors, software structure and
modularity, fault tolerance, software reliability, prediction and measurement, hardware/software interfaces.
9 Hours
Unit IV
Reliability Testing and Analysis
Test environments, testing for reliability and durability, failure reporting, Pareto analysis, Accelerated test
data analysis, CUSUM charts, Exploratory data analysis and proportional hazards modeling, reliability
demonstration, reliability growth monitoring.
9 Hours
Unit V
Manufacture and Reliability Management
Control of production variability, Acceptance sampling, Quality control and stress screening, Production
failure reporting - preventive maintenance strategy, Maintenance schedules, Design for maintainability,
Integrated reliability programmes, reliability and costs, standard for reliability, quality and safety,
specifying reliability, organization for reliability.
9 Hours
Total: 45 Hours
Reference(s)
1. Patrick D. T. O'Connor, David Newton and Richard Bromley, Practical Reliability Engg, John
Wiley & Sons, 2002.
2. David J. Klinger, Yoshinao Nakada, Maria A. Menendez and Von Nostrand Reinhold, AT & T
Reliability Manual, 1998.
3. Gregg K. Hobbs, Accelerated Reliability Engineering - HALT and HASS, John Wiley & Sons,
2000.
4. Lewis, Introduction to Reliability Engineering, Wiley International, 1996.
13AE62 NETWORK SECURITY
3003
Objectives
 To explore network concept and threats in Network layer
 To study characteristics, vulnerabilities and challenges in authentication
 To provide solution for covering IP and Internet security
 To evaluate the performance of system security
 Ability to identify the various attacks and threads in wired and wireless Networks.
 Understand and recognize the architectures of IP and WEB security protocols
 Analyze the solutions for Email security and privacy policies.
conduct experiments, analyze and interpret data able to use modern engineering tools, software
and equipments to analyze problems.
29
Unit I
Introduction
Network concepts – Threats in networks – Network security controls – Importance of security – Threat
models – Security concepts – Common mitigation methods.
9 Hours
Unit II
Authentication
Overview of authentication – Authentication of people – Security Handshake pitfalls – Strong password
protocols – Kerberos – Public key infrastructure.
9 Hours
Unit III
IP & Web Security
IP security: Overview - Architecture – Authentication Header - Encapsulating Security Payload - Key
management – Web security: Web security considerations – Secure Socket Layer and Transport Layer
Security – Secure electronic transaction – Web issues
9 Hours
Unit IV
Electronic Mail Security
Store and forward – Security services for e-mail – Establishing keys – Privacy – Authentication of the
Source – Message Integrity – Non-repudiation – Proof of submission and delivery - Pretty Good Privacy –
Secure/Multipurpose Internet Mail Extension.
9 Hours
Unit V
System Security
Intruders – Intrusion detection – Password management – Malicious software: Viruses and related threats –
virus countermeasures – Firewalls: Firewall design principles – Firewall configurations – Trusted systems
9 Hours
Total: 45 Hours
Reference(s)
1. Charles P. Fleeger, Security in Computing, Prentice Hall, New Delhi, 2009
2. Behrouz A.Forouzan, Cryptography & Network Security, Tata McGraw Hill, India, New Delhi,
2009.
3. William Stallings,Cryptography and Network Security, Prentice Hall, New Delhi, 2006.
4. Chalie Kaufman, Radia Perlman, Mike Speciner, Network Security: Private Communication in a
Public Network, Pearson Education, New Delhi, 2004.
5. Neal Krawetz, Introduction to Network Security, Thomson Learning, Boston, 2007.
6. Bruce Schneier, Applied Cryptography, John Wiley & Sons, New York, 2004.
13AE63 WIRED AND WIRELESS LAN
3003
Objectives
 To focus on wired and wireless LAN, MAN protocols.
 To study different methods for implementing LAN and MAN based enterprise intranets.
 To understand the operation of IEEE 802 MAC and physical layer protocols.
 To explore knowledge in ATM and Adhoc networks.
 Ability to describe wireless LAN standards, devices, radio technology and topologies
 Configure wireless access-points, bridges and client devices.
 Identify the various IEEE standards of wireless Networks
 Recognize architecture of GPRS mobile application protocols
 Study the code deviation multiple access standards and use formal approaches to monitor
maintain troubleshoot a wireless LAN
30

Unit I
Wireless LAN Technology
Radio wave LAN – Infrared LAN – Microwave LAN – Long distance LAN Systems and Services –
Wireless LAN Standards and Protocols.
9 Hours
Unit II
Packet Switching Networks
Routing in Packet Networks – Short Path Algorithm – Traffic Management and QoS – Congestion Control
- OSI / IP models - Ethernet (IEEE 802.3) – Token ring (IEEE 802.5) – FDDI – DQDB – Frame Relay –
SMDS.
9 Hours
Unit III
TCP/IP Networks:
Architecture - Internet protocol – IPv6 – User Datagram Protocol – Transmission Control Protocol –
DHCP and Mobile IP – Internet Routing Protocol – Multicast Routing – Performance of TCP / IP
Networks.
9 Hours
Unit IV
ATM Networks
Features of ATM – BISDN Reference Model – ATM Layer – ATM Adaptation Layer – ATM Signaling –
Routing – Management and control – Internetworking with ATM.
9 Hours
Unit V
AdHoc Networks
Infra structure Vs infrastructure less networks- Vulnerabilities and challenges-security issues-Active and
passive attacks- Review of AODV and DSR.
9 Hours
Total: 45 Hours
Reference(s)
1. William Stallings, Wireless Communications and Networking, PHI, 2004.
2. C .Siva Ram Murthy and B.S. Manoj, AdHoc Wireless Networks: Architectures and Protocols,
Prentice Hall PTR, 2004.
3. Jean Warland and Pravin Varaiya, High Performance Communication Networks, Harcourt and
Morgan Kauffman, 2002.
4. Sumit Kasera and Pankaj Sethi, ATM Networks, Tata McGraw Hill, 2006.
5. Behrouz A. Forouzan, Data Communication and Networking, Tata McGraw Hill, 2006.
6. Leon Garcia and Widjaja, Communication Networks, Tata McGraw Hill, 2004.
7. Hongmei Deng, Wei Li and Dharma P.Agrawal, Routing Security in Wireless Ad Hoc Networks,
IEEE Communication Magazine, Oct 2002
13AE64/13VL51/13ES53 ASIC DESIGN
3003
Objectives
 To acquire knowledge about different types of ASICs design.
 To study about various types of Programmable ASICs architectures and interconnects.
 To comprehend the low power design techniques and methodologies.
31

 Analysis the different types of ASICs design.
 Analysis the different Logic cell architecture and interconnects.
 Analysis about different programmable ASIC design software.
 Identification of new developments in SOC and low power design.
conducts experiments, analyze and interpret data
field
Unit I
Introduction to ASICS, CMOS Logic, ASIC Library Design:
Types of ASICs - Design flow – CMOS transistors- CMOS Design rules –Combinational logic Cell
Sequential logic cell - Transistor as Resistors - Transistor parasitic capacitance – Logical effort - Library
cell design – Library architecture.
9 Hours
Unit II
Programmable ASICS, Programmable ASIC Logic Cells and Programmable ASIC I/O Cells:
Anti fuse - Static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx
LCA –Altera FLEX - Altera MAX DC & AC inputs and outputs - Xilinx I/O blocks.
9 Hours
Unit III
Programmable ASIC Interconnect, Programmable ASIC Design Software And Low Level Design
Entry: Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera
FLEX –Design systems - Logic Synthesis - Half gate ASIC -Low level design language - PLA tools EDIF-
CFI design representation.
9 Hours
Unit IV
Silicon on Chip Design:
Voice over IP SOC - Intellectual Property – SOC Design challenges- Methodology and design-FPGA to
ASIC conversion – Design for integration-SOC verification-Set top box SOC.
9 Hours
Unit V
Physical and Low power Design:
Over view of physical design flow- tips and guideline for physical design- modern physical design
techniques- power dissipation-low power design techniques and methodologies-low power design tools-
tips and guideline for low power design.
9 Hours
Total: 45 Hours
Reference(s)
1. M.J.S. Smith, Application Specific Integrated Circuits, Pearson Education, 2008.
2. Farzad Nekoogar and Faranak Nekoogar, From ASICs to SOCs: A Practical Approach, Prentice
Hall PTR, 2003.
3. Wayne Wolf, FPGA-Based System Design, Prentice Hall PTR, 2009.
4. R.Rajsuman, System-on-a-Chip Design and Test, Santa Clara, CA: Artech House Publishers, 2000.
5. F.Nekoogar, Timing Verification of Application-Specific Integrated Circuits (ASICs), Prentice Hall
PTR, 1999.
32
6. S.Srinivasan, VLSI Circuits, NPTEL Courseware, 2007.

13AE65 DSP PROCESSOR ARCHITECTURE AND PROGRAMMING
3003
Objectives
 To study the fundamentals of Programmable DSPs.
 To impart knowledge on the operation of ADSP and Analog Processors.
 Analyse the procedure for various DSP System Architecture
 Diagnose the design methodologies in hardware and software.
 Identification of new developments in DSP systems.
 Design and implement various signal processing techniques using DSP processors.
(e) Able to use modern engineering tools, software and equipments to analyze problems
Unit I
Fundamentals of Programmable DSPs
Multiplier and Multiplier accumulator – Modified Bus Structures and Memory access in P-DSPs – Multiple
access memory – Multi-port memory – VLIW architecture- Pipelining – Special Addressing modes in
PDSPs– On chip Peripherals.
9 Hours
Unit II
TMS320C5X Processor
Architecture – Assembly language syntax - Addressing modes – Assembly language Instructions - Pipeline
structure– Operation – Programs for FIR and IIR filters.
9 Hours
Unit III
TMS320C3X Processor
Architecture – Data formats - Addressing modes – Groups of addressing modes- Instruction sets -
Operation–Generating and finding the sum of series- Convolution of two sequences- Programs for FIR and
IIR filters.
9 Hours
Unit IV
ADSP Processors
Architecture of ADSP-21XX and ADSP-210XX series of DSP processors- Addressing modes and
assemblylanguage instructions – Application programs – Programs on ADSP21xx for FIR and IIR filters.
9 Hours
Unit V
Advanced Processors
Architecture of TMS320C54X - Pipe line operation, Code Composer studio - Architecture of TMS320C6X
-Architecture of Motorola DSP563XX – Comparison of the features of DSP family processors.
9 Hours
Lab Components
1. Computation of Correlation of signals.
2. Computation of Convolution of signals.
3. Calculation of DFT.
33
4. Calculation of FFT.
5. Design an FIR Filter.
Total: 45 Hours
Reference(s)
1. B.Venkataramani. and M.Bhaskar, Digital Signal Processors – Architecture, Programming and
Applications, Tata McGraw – Hill Publishing Company Limited, 2003.
2. User guides of Texas Instruments, Analog Devices, Motorola Incorporation, 2005.
13AE66/13VL64 VLSI TECHNOLOGY
3003
Objectives
 To understand the Fabrication of ICs and purification of Silicon in different technologies.
 To impart in-depth knowledge about Etching and deposition of different layers.
 To understand the different packaging techniques of VLSI devices.
 The ability to use metallization techniques to create three-dimensional device structures and
devices.
 The ability to know methodology to fabricate an IC’s
Unit I
Crystal Growth, Wafer Preparation, Epitaxy and Oxidation
Electronic Grade Silicon, Czochralski crystal growing, Silicon Shaping, processing consideration, Vapor
phase Epitaxy, Molecular Beam Epitaxy, Epitaxial Evaluation, Growth Mechanism and kinetics, Thin
Oxides, Oxidation Techniques and Systems, Oxide properties, Redistribution of Dopants at interface,
Oxidation of Poly Silicon, Oxidation induced Defects.
9 Hours
Unit II
Lithography and Reactive Plasma Etching
Optical Lithography, Electron Lithography, X-Ray Lithography, Ion Lithography, Nanoimprint
Lithography, Plasma properties, Feature Size control and Anisotropic Etch mechanism, reactive Plasma
Etching techniques and Equipments.
9 Hours
Unit III
Deposition, Diffusion and Ion Implantation
Deposition process, Polysilicon, plasma assisted Deposition, Models of Diffusion in Solids, Fick’s one
dimensional Diffusion Equation - Measurement techniques - Range theory- Implant equipment –
Annealing- Shallow junction, High - energy implantation.
9 Hours
Unit IV
Metallization and VLSI Process Integration
Physical Vapour Deposition (PVD) –Patterning- NMOS IC Technology – CMOS IC Technology –
BICMOS IC Technology- MOS Memory IC technology - Bipolar IC Technology –Silicon on Insulator
Technology–Noise in VLSI Technologies
9 Hours
34
Unit V
Analytical, Assembly Techniques and Packaging of VLSI Devices
Analytical Beams – Beams Specimen interactions - Chemical methods – Package types – packaging design
consideration – VLSI assembly technology – Package fabrication technology.
9 Hours
Total: 45 Hours
Reference(s)
1. S.M .Sze, VLSI Technology, McGraw Hill, 2003.
2. Amar Mukherjee, Introduction to NMOS and CMOS VLSI System Design, PHI, 2000.
3. James D Plummer, Michael D. Deal and Peter B. Griffin, Silicon VLSI Technology:
Fundamentals Practice and Modeling, PHI, 2000.
4. Wai Kai Chen, VLSI Technology, CRC press, 2003.
5. Rainer Waser ,“Nano Electronics and Information Technology “, Wiley VCH – April 2003.
13AE67/13VL13 VLSI SUBSYSTEM DESIGN
3003
Objectives
 To learn the basic MOS Circuits
 To learn the MOS Process Technology
 To understand the operation of MOS devices..
 To impart in-depth knowledge about analog and digital CMOS circuits.
 Analysis the operation of CMOS
 Analysis of the design rules and layout diagram
 Design of low power Adders and Multipliers
 Analysis the physical design process of VLSI design flow.
 Design of CMOS Memories.
field
Unit I
MOS Circuit Design Process
Overview of VLSI Design Methodology VLSI design process- Basic MOS transistors- Enhancement mode
transistor operation - Drain current Vs voltage derivation -NMOS inverter- Determination of pull up to pull
down ratio for an NMOS inverter-CMOS inverter - DC Characteristics- Switching Characteristics – Power
dissipation.
9 Hours
Unit II
Logic Design
Pass transistor and transmission gate – static CMOS design, Pseudo NMOS, and dynamic CMOS logic –
Clocked CMOS logic – domino logic- Precharged domino logic, Dual rail logic with suitable examples.
9 Hours
Unit III
Sequential Logic
Clocked sequential circuits – Two phase clocking – charge storage – dynamic sequential circuits – JK Flip-
flop circuit, Memory Design-DRAM, SRAM and Flash Memory.
9 Hours
35
Unit IV
Datapath Subsystem
Introduction, Design of Adders: carry look ahead - carry select - carry save, One/Zero Detector,
Comparator- Magnitude, Equality, Counters-Binary Counter, LFSR, Parity generators.
9 Hours
Unit V
VLSI Building Block Design
PLA design – Arithmetic logic unit design- Design of multipliers: Parallel Multipliers, Array, 2’s
Complement, Booth - Braun – Baugh - Wooley - Wallace tree, Dadda Multipliers, Serial Multiplication.
9 Hours
Total: 45 Hours
Reference(s)
1. Kamran Eshraghian, Douglas A. Pucknell, Essentials of VLSI Circuits and Systems, Prentice Hall
of India, 2011
2. John P.Uyemura, Introduction to VLSI circuits and systems, John Wiley & Sons, 2012.
3. Neil Weste and Kamran Eshranghian, Principles of CMOS VLSI Design, Addison Wiley, 2012.
4. Jan M Rabaey, Digital Integrated Circuits- A Design, Prentice Hall, 2009.
5. C.Mead and L.Conway, Introduction to VLSI Systems, Addison Wesley, 1999.
6. Kang, CMOS Digital integrated Circuits, McGraw Hill, 2002.
7. L.Glaser and D.Dobberpuhl, The Design and Analysis of VLSI Circuits, Addison Wesley, 1995.
8. S.Srinivasan, VLSI Circuits, NPTEL Courseware, 2005.
13AE68/13CO56/13VL57 COMMUNICATION NETWORKS
3003
Objectives
 To study about the wired and wireless LANs and backbone networks.
 To gain depth knowledge about the routing protocol and congestion controls.
 To focus on simulation and modeling of Qualnet and NS2 simulators.
 To identify the type of networks and protocols for a given network scenario.
 To estimate the performance and throughput of a given network.
 Design a network aimed at optimum performance.
 Traffic modeling and congestion control in networks.
Unit I
Wired LANs
Standard Ethernet- Mac sub layer-physical layer, Bridged Ethernet, switched Ethernet, Fast Ethernet,
Gigabit Ethernet. Backbone Networks: Connecting devices, Hubs, Bridges, Routers, Gateway, three layer
switches, Virtual LAN-SONET.
9 Hours
Unit II
Flow/Congestion Control
Implementation, modeling, fairness, stability, open-loop, closed-loop and hybrid, traffic specification
(LBAP, leaky-bucket), window, rate, hop-by-hop , end-to-end flow control, implicit and explicit feedback,
36
aggregate flow control, reliable multicast. TCP variants (Tahoe, Reno, Vegas, New-Reno, SACK), DECbit,
Packet Pair, NETBLT, ATM Forum EERC, T/TCP.
Scheduling and Buffer Management
Implementation, faimess, performance bounds, admission control, priorities, work conservation, scheduling
best-effort (BE) flows, scheduling guaranteed-service (GS) flows (GPS, WRR, DRR, WFQ, EDD, RCSP),
aggregation, drop strategies (tail-drop, RED, WRED).
9 Hours
Unit III
Routing
Implementation, stability/convergence, link-state vs distance-vector vs link-vector, conventional routing,
Routing Information Protocol (RIP), Open Shortest Path First (OSPF), Multicast OSPF (MOSPF), Distance
Vector Multicast Routing Protocol (DVMRP), BGP instability, Fair queuing, TCP congestion control, TCP
variants, Random Early Detect, TCP RTT estimation, Fast retransmit, Fast recovery.
9 Hours
Unit IV
Congestion control
Congestion Control-open loop-closed loop, congestion control in TCP, congestion control in Frame relay-
Quality of service- Integrated Services, Resource Reservation Protocol (RSVP), Differentiated Services,
Overlay Networks, Peer-to-Peer Networks, Chord.
9 Hours
Unit V
Simulation and Modeling
Wide-Area Traffic Modeling, End-to-end Internet Packet Dynamics, Traffic engineering, Multi-Protocol
Label Switching (MPLS), Network Simulators- NS2, OPNET, QualNet.
IP Next Generation
IP Next Layer (IPNL), IPV6 features, including transition, Mobile IPV6 operation, Models to support
(WLAN) network roaming, IPV6 transition methods, Advanced IP routing and multihoming, IP Multicast.
9 Hours
Total: 45 Hours
Reference(s)
1. Larry Peterson and Bruce Davie, Computer Networks: A Systems Approach, Morgan Kaufmann,
2007.
2. Michael A Gallo and William M Hancock, Computer Communications and Networking
Technologies, Thomson Learning, 2002.
3. Jim Kurose and Keith Ross, Computer Networking: A Top-Down Approach Featuring the
Internet, Addison- Wesley, 2004.
4. William Stallings, Data and Computer Communications, Prentice Hall, 2006.
5. Andrew S Tanenbaum, Computer Networks, Prentice Hall, 2002.
6. Behrouz Forouzan, Data communications and Networking, TMH, 2007
7. Behrouz Forouzan, TCPIP Overview,TMH,2008
13AE69 ROBOTICS
3003
Objectives
 To study the fundamental concepts of kinematics.
 To gain the knowledge about various sensors used in robotics.
 By combining the concepts of computer vision and AI techniques to design a robot
 To understand the basic principles of robotics
 To acquire knowledge about navigation and movement of the robots and robotic arm..
 To obtain awareness the function of various sensors used in robotics.
 To become capable of design and implementation of robotics in specific applications.
37

(e) Able to plan, conduct an organized and systematic study on significant research topic within the
field.
Unit I
Introduction to Robotics
Robotic Classification, Robot Specifications, Motion – Bug and tangent algorithms, Potential Function,
Road maps- Topological roadmaps, Cell decomposition – Trapezoidal and Morse cell decompositions ,
Sensor and sensor planning- Kinematics-Forward and Inverse Kinematics - Transformation matrix and DH
transformation-Inverse Kinematics - Geometric methods and Algebraic methods.
9 Hours
Unit II
Computer Vision
Projection - Optics, Projection on the Image Plane and Radiometry. Image Processing - Connectivity,
Images-Gray Scale and Binary Images, Blob Filling, Thresholding, Histogram-Convolution - Digital
Convolution and Filtering and Masking Techniques- Edge Detection - Mono and Stereo Vision.
9 Hours
Unit III
Sensors and Sensing Devices
Introduction to various types of sensor- Resistive sensors. Range sensors - LADAR (Laser Distance and
Ranging), Sonar, Radar and Infra-red- Introduction to sensing - Light sensing, Heat sensing, touch sensing
and Position sensing.
9 Hours
Unit IV
Artificial Intelligence
Uniform Search strategies - Breadth first, Depth first, Depth limited, Iterative and deepening depth first
search and Bidirectional search. The A* algorithm-Planning - State-Space Planning Plan-Space Planning,
Graph plan/Sat Plan and their Comparison, Multi-agent planning 1, and Multi-agent planning 2,
Probabilistic Reasoning - Bayesian Networks, Decision Trees and Bayes net inference .
9 Hours
Unit V
Integration to Robot
Building of 4 axis or 6 axis robot - Vision System for pattern detection - sensors for obstacle detection - AI
algorithms for path finding and decision making. 9 Hours
Total: 45 Hours
Reference(s)
1. Duda, Hart and Stork, Pattern Recognition, Wiley-Inter science, 2000.
2. Mallot, Computational Vision: Information Processing in Perception and Visual Behavior,
Cambridge, 2000.
3. Stuart Russell and Peter Norvig, Artificial Intelligence-A Modern Approach, Pearson Education
Series in Artificial Intelligence, 2004.
4. Robert Schilling and Craig, Fundamentals of Robotics: Analysis and Control, Hall of India
Private Limited, 2003.
5. Forsyth and Ponce, Computer Vision: A Modern Approach, Person Education, 2003.
38
13AE70/13CO68/13ES61 PATTERN RECOGNITION & ARTIFICAL INTELLIGENT

TECHNIQUES
3003
Objectives
 To understand different supervised and unsupervised learning techniques
 To obtain sound knowledge on recent advancement on pattern recognition techniques..
 Analysis the procedure for various pattern recognition principles in real world problem.
 Analysis feature enhancement and optimization methods
 Identification of new developments in object recognition systems.
Unit I
Pattern Classifier
Overview of pattern recognition - Discriminant functions - Supervised learning - Parametric estimation -
Maximum likelihood estimation - Bayesian parameter estimation - Perceptron algorithm - LMSE algorithm
-Problems with Bayes approach - Pattern classification by distance functions - Minimum distance pattern
classifier.
9 Hours
Unit II
Unsupervised Classification
Clustering for unsupervised learning and classification - Clustering concept - C-means algorithm –
Hierarchical clustering procedures - Graph theoretic approach to pattern clustering - Validity of clustering
solutions.
9 Hours
Unit III
Structural Pattern Recognition
Elements of formal grammars - String generation as pattern description - Recognition of syntactic
description -Parsing - Stochastic grammars and applications - Graph based structural representation.
9 Hours
Unit IV
Feature Extraction and Selection
Entropy minimization - Karhunen - Loeve transformation - Feature selection through functions
approximation -Binary feature selection.
9 Hours
Unit V
Recent Advances
Neural network structures for Pattern Recognition - Neural network based Pattern associators –
Unsupervised learning in neural Pattern Recognition - Self organizing networks - Fuzzy logic - Fuzzy
pattern classifiers -Pattern classification using Genetic Algorithms.
9 Hours
Total:45 Hours
39
Reference(s)
1. Robert J.Schalkoff, Pattern Recognition: Statistical, Structural and Neural Approaches, John
Wiley &Sons Inc., New York, 2007.
2. Tou and Gonzales, Pattern Recognition Principles, Wesley Publication Company, London, 1974.
3. Duda R.O., Hart.P.E., and Strok, Pattern Classification, second Edition Wiley, New York, 2008.
4. Morton Nadier and Eric Smith P., Pattern Recognition Engineering, John Wiley & Sons, New
York, 1993.
5. IEEE Transaction on Pattern Recognition Techniques 2006.
6. IEEE Engineering Medicine and Biology Magazine 2006.
13AE71 CYBER CRIME INVESTIGATION AND DIGITAL FORENSICS
3003
Objectives
 To explore cyber crime issues in social networks
 To study characteristics, vulnerabilities and challenges in authentication
 To provide solution for covering IP and Internet security
 To evaluate the performance of system security
 Ability to identify thecyber attacks and threads in Internet.
 Understand and recognize cyber laws and issues
 Ability to identify investigation, solutions handling the cyber attacks..
 Ability to apply digital forensics methods
Unit I
Introduction
Introduction and Overview of Cyber Crime, Nature and Scope of Cyber Crime, Types of Cyber Crime:
Social Engineering, Categories of Cyber Crime, Property
9 Hours
Unit II
Cyber Crime Issues
Unauthorized Access to Computers, Computer Intrusions, White collar Crimes, Viruses and Malicious
Code, Internet Hacking and Cracking, Virus Attacks, Pornography, Software Piracy, Intellectual Property,
Mail Bombs, Exploitation ,Stalking and Obscenity in Internet, Digital laws and legislation, Law
Enforcement Roles and Responses.
9 Hours
Unit III
Investigation
Introduction to Cyber Crime Investigation, Investigation Tools, eDiscovery, Digital Evidence Collection,
Evidence Preservation, E-Mail Investigation, E-Mail Tracking, IP Tracking, E-Mail Recovery, Hands on
Case Studies. Encryption and Decryption Methods, Search and Seizure of Computers, Recovering Deleted
Evidences, Password Cracking.
9 Hours
Unit IV
Digital Forensics
Introduction to Digital Forensics, Forensic Software and Hardware, Analysis and Advanced Tools, Forensic
Technology and Practices, Forensic Ballistics and Photography, Face, Iris and Fingerprint Recognition,
Audio Video Analysis, Windows System Forensics, Linux System Forensics, Network Forensics.
9 Hours
40
Unit V
Cyber crime. Laws and acts
Laws and Ethics, Digital Evidence Controls, Evidence Handling Procedures, Basics of Indian Evidence
ACT IPC and CrPC , Electronic Communication Privacy ACT, Legal Policies.
9 Hours
Total: 45 Hours
Reference(s)
1. Nelson Phillips and Enfinger Steuart, “Computer Forensics and Investigations”, Cengage Learning,
New Delhi, 2009.
2. Kevin Mandia, Chris Prosise, Matt Pepe, “Incident Response and Computer Forensics “, Tata McGraw
-Hill, New Delhi, 2006.
3. Robert M Slade,” Software Forensics”, Tata McGraw - Hill, New Delhi, 2005.
4. Bernadette H Schell, Clemens Martin, “Cybercrime”, ABC – CLIO Inc, California, 2004.
SELF ELECTIVES
13AE01/13CO03/13ES63 WAVELETS AND MULTIRESOLUTION PROCESSING
3003
Objectives
 To study the fundamentals of vector and signal spaces
 To explore the concepts of multi resolution analysis of signals
 Understanding of continuous-time wavelet transforms.
 Understanding of discrete-time wavelet transforms.
 The ability to design wavelet filter banks
 Knowledge of Compression techniques
 The ability to apply above knowledge and skills to image processing applications.
Unit I
Introduction
Vector Spaces - properties - dot product - basis - dimension, orthogonality and orthonormality -
relationship between vectors and signals - Signal spaces - concept of Convergence - Hilbert spaces for
energy signals - Generalized Fourier Expansion.
9 Hours
Unit II
Multi Resolution Analysis
Definition of Multi Resolution Analysis (MRA) – Haar basis - Construction of general orthonormal
MRAWavelet basis for MRA – Continuous time MRA interpretation for the DTWT – Discrete time MRA-
Basis functions for the DTWT – PRQMF filter banks.
9 Hours
Unit III
Continuous Wavelet Transform
Wavelet Transform - definition and properties - concept of scale and its relation with frequency -
Continuous Wavelet Transform (CWT) - Scaling function and wavelet functions (Daubechies, Coiflet,
Mexican Hat, Sinc, Gaussian, Bi-Orthogonal) - Tiling of time -scale plane for CWT.
9 Hours
41
Unit IV
Discrete Wavelet Transform
Filter Bank and sub band coding principles - Wavelet Filters - Inverse DWT computation by Filter
banks -Basic Properties of Filter coefficients - Choice of wavelet function coefficients - Derivations of
Daubechies Wavelets -Mallat's algorithm for DWT – Multi-band Wavelet transforms. Lifting Scheme:
Wavelet Transform using Poly phase matrix Factorization - Geometrical foundations of lifting scheme -
Lifting scheme in Z –domain.
9 Hours
Unit V
Applications
Signal Compression – Image Compression techniques: EZW-SPHIT Coding Image denoising techniques-
Noise estimation - Shrinkage rules - Shrinkage Functions - Edge detection and object Isolation, Image
Fusion, and Object Detection. Curve and Surface Editing-Variational modeling and finite element method
using wavelets.
9 Hours
Total: 45 Hours
Lab Component
1. Simulation of QMF filter bank.
2. Signal denoising using wavelets.
3. Speech compression using DWT.
4. Image coding (EZW, SPHIT)
Reference(s)
1. G,.Strang and T.Nguyen, Wavelets and Filter Banks, Wellesley Cambridge Press, 1996
2. M .Vetterli and J.Kovacevic, Wavelets and Sub-band Coding, Prentice Hall, 1995
3. S.Mallat., Wavelet Tour of Signal Processing, Academic Press, 2008.
4. www.multiresolution.com
5. www.wavelet.org
6. IEEE transactions on Image Processing.
7. IEEE transactions on Neural Networks.
13AE02 MOBILE NETWORKS
3003
Objectives
 To study architecture and characteristics in cellular networks
 To explore enabling wireless technologies with mobile networks
 To understand Mobile IP and TCP protocols
 To explore issues and challenges in multicast routing in adhoc networks
 Ability to identify the various challenges and vulnerabilities in cellular networks
 Understand and recognize techniques of various wireless technologies
 Analyze the solutions for configuration of mobile networks
 Ability to adapt TCP protocols in mobile environment
 Analyze the solutions for multicast routing protocols for different applications
a. able to apply knowledge from undergraduate engineering and other disciplines to identify,
formulate, solve novel advanced electronics engineering along with soft computing problems that
require advanced knowledge within the field.
b. able to understand and integrate new knowledge within the field.
c. able to apply advanced technical knowledge in multiple contexts
d. able to understand and design advanced electronics systems (Analog and Digital Systems) and
e. able to use modern engineering tools, software and equipments to analyze problems.
42
Unit I
Cellular Concept
Introduction – Frequency reuse – Channel assignment strategies – Handoff strategies – Interference –
Truncking – Improving coverage and capacity in cellular systems.
9 hours
Unit II
Wireless LAN
Infrared vs. radio transmission- Infrastructure and Adhoc network – IEEE 802.11 – HIPERLAN –
Bluetooth.
9 hours
Unit III
Mobile Network Layer
Mobile Network layer - Mobile IP – Dynamic Host Configuration Protocol – Mobile adhoc networks.
9 hours
Unit IV
Mobile Transport Layer
Traditional TCP - Classical TCP improvements–TCP over 2.5/3G wireless networks.
9 hours
Unit V
Multicast Routing in Adhoc Wireless Networks
Introduction – Issues in designing a multicast routing protocol – Operations of multicast routing protocols-
Tree based multicast routing protocols – Mesh based multicast routing protocol – Application Dependent
multicast routing.
9 hours
Total 45 hours
Reference(s)
1. Jochen Schiller “Mobile communications”, Pearson Education, New Delhi, Second Edition, 2004.
2. Theodore S Rappaport, “Wireless Communications Principles and Practice”, Pearson Education,
New Delhi, Second Edition, 2003.
3. Siva Ram Murthy C and Manoj B S “Adhoc Wireless Networks, Architectures and Protocols”
Pearson Education, New Delhi, 2005.
4. Charles E Perkins, “Mobile IP: Design Principles and Practice”, Addison Wesley, USA, 1999.
13AE03 INTRUSION DETECTION AND PREVENTION SYSTEM
3003
Objectives
 To explore basics of intrusion, attacks and detection, prevention techniques
 To study computational systems for intrusion detection systems
 To provide solution for covering the security principles and flaws of popular wireless technologies
 To evaluate the performance of secured routing protocols in MANETs.
 Ability to identify the various attacks and threads of wireless Networks.
 Understand and recognize the architectures, vulnerabilities and challenges of mobile protocols.

43
Unit I
Introduction
Understanding Intrusion Detection – Intrusion detection and prevention basics – IDS and IPS analysis
schemes, Attacks, Detection approaches –Misuse detection – anomaly detection – specification based
detection – hybrid detection
9 Hours
Unit II
Theoretical foundations of detection
Taxonomy of anomaly detection system – fuzzy logic – Bayes theory – Artificial Neural networks –
Support vector machine – Evolutionary computation – Association rules – Clustering
9 Hours
Unit III
Architecture and Implementation
Centralized – Distributed – Cooperative Intrusion Detection - Tiered architecture. Justifying Intrusion
Detection: Intrusion detection in security – Threat Briefing – Quantifying risk – Return on Investment
(ROI)
9 Hours
Unit IV
Applications and Tools
Tool Selection and Acquisition Process - Bro Intrusion Detection – Prelude Intrusion Detection - Cisco
Security IDS - Snorts Intrusion Detection – NFR security.
9 Hours
Unit V
Legal Issues and Organizations Standards
Law Enforcement / Criminal Prosecutions – Standard of Due Care – Evidentiary Issues, Organizations and
Standardizations.
9 Hours
Total: 45 Hours
Reference(s)
1. Ali A. Ghorbani, Wei Lu, “Network Intrusion Detection and Prevention: Concepts and Techniques”,
Springer, 2010.
2. Carl Enrolf, Eugene Schultz, Jim Mellander, “Intrusion detection and Prevention”, McGraw Hill,
2004.
3. Paul E. Proctor, “The Practical Intrusion Detection Handbook “,Prentice Hall , 2001.
4. Ankit Fadia and Mnu Zacharia, “Intrusiion Alert”, Vikas Publishing house Pvt., Ltd, 2007.
5. Earl Carter, Jonathan Hogue, “Intrusion Prevention Fundamentals”, Pearson Education, 2006.
44

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M.

BANNARI AMMAN INSTITUTE OF TECHNOLOGY

Programme Educational Objectives (PEOs) viii

Programme Outcomes (POs) ix

Mapping of PEOs and POs x

Rules and Regulations

1. Conditions for Admission

2. Duration of the Programme

The following are the branches of study of M.E. / M.Tech. Programmes

Branch I Applied Electronics

Semester 1: 6 Theory Courses and two Practicals

Semester 1: 3 Theory Courses and one Practical

M.E./M. Tech. Programmes Total Credits

5. Requirements for Completion of Study of a Semester

6. Assessment and Passing Requirements

(iv) Industrial Training, Mini-project and Project Work:

Range of Percentage of Total Marks Letter Grade Point

“RA” denotes reappearance in the course.

Where g i : Grade point secured corresponding to the Course

7. Qualifying for the Award of the Degree

9. Withdrawal from Examination

10. Scheme of Assessment

Distribution of marks for internal assessment:

ii) Technical Seminar : 100 Marks

Three Seminars (3X25) : 75 Marks

Final Examination : 50 Marks

Distribution of marks for internal assessment:

iv) Project Work Phase – I Marks

v) Project Work Phase – II Marks

11 . Question paper pattern for Theory Examination

Max. Marks : 100

Lengthy Answer Questions: 2

Program Educational Objectives (PEOs)

PROGRAMME OUTCOMES (POs)

Mapping of PEOs & POs

Programme Educational Objectives Program Outcomes

PEO: I The Graduates of Applied Electronics will (a),(b),(e)

M.E. Applied Electronics

@ Common with CO, ES & AE

13AE11 APPLIED MATHEMATICS

(a) Able to understand the advanced architecture of processors and Controllers.

6. Design and development of Embedded system using ARM Processors.

5. Robert Bosch Automotive Hand Book, SAE, 2000.

13AE51 ADVANCED WIRELESS NETWORKS

13AE52 MEDICAL IMAGE PROCESSING

13AE53 MULTIMEDIA COMMUNICATION SYSTEMS

3. Tay Vaughan, Multimedia Making it to Work, Tata McGraw Hill, 2006.

13AE54/13CO59 WIRELESS SECURITY

Programme Outcomes (POs)

13AE55/13VL23/13ES60 LOW POWER VLSI DESIGN

 To obtain sound knowledge on simulations and synthesis process of CAD tools.

13AE59/13C069 EVOLUTIONARY COMPUTING

Basic sub-band coding –DPC M- ADPCM-DM-LPC-CELP -Application to speech coding – G.722 –

Program Outcomes (POs)

Course Outcomes (COs)

6. S.Srinivasan, VLSI Circuits, NPTEL Courseware, 2007.

Programme Outcomes (POs)

13AE70/13CO68/13ES61 PATTERN RECOGNITION & ARTIFICAL INTELLIGENT

Programme Outcomes (POs)

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