Encoder

1 -------------------------------------------------------
2 -- Design Name : encoder_using_if
3 -- File Name : encoder_using_if.vhd
4 -- Function : Encoder using If
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7 -------------------------------------------------------
8 library ieee;
9 use ieee.std_logic_1164.all;
10
11 entity encoder_using_if is
12 port (
13 enable :in std_logic;
-- Enable for the encoder
14 encoder_in :in
std_logic_vector (15 downto 0);-- 16-bit Input
15 binary_out :out
std_logic_vector (3 downto 0) -- 4 bit binary
Output
16
17 );
18 end entity;
19
20 architecture behavior of
encoder_using_if is
21
22 begin
23 process (enable, encoder_in)
begin
24 binary_out <= "0000";
25 if (enable = '1') then
26 if (encoder_in = X"0002")
then binary_out <= "0001"; end if;
27 if (encoder_in = X"0004")
then binary_out <= "0010"; end if;
28 if (encoder_in = X"0008")
then binary_out <= "0011"; end if;
29 if (encoder_in = X"0010")
then binary_out <= "0100"; end if;
30 if (encoder_in = X"0020")
then binary_out <= "0101"; end if;
31 if (encoder_in = X"0040")
then binary_out <= "0110"; end if;
32 if (encoder_in = X"0080")
then binary_out <= "0111"; end if;
33 if (encoder_in = X"0100")
then binary_out <= "1000"; end if;
34 if (encoder_in = X"0200")
then binary_out <= "1001"; end if;
35 if (encoder_in = X"0400")
then binary_out <= "1010"; end if;
36 if (encoder_in = X"0800")
then binary_out <= "1011"; end if;
 37 if (encoder_in = X"1000")
then binary_out <= "1100"; end if;
38 if (encoder_in = X"2000")
then binary_out <= "1101"; end if;
39 if (encoder_in = X"4000")
then binary_out <= "1110"; end if;
40 if (encoder_in = X"8000")
then binary_out <= "1111"; end if;
41 end if;
42 end process;
43 end architecture;
You could download file vhdl_examples here
   
Encoder - Using case
 
Statement
   
1
------------------------------------------------------
-
2 -- Design Name :
encoder_using_case
3 -- File Name :
encoder_using_case.vhd
4 -- Function : Encoder using
Case
5 -- Coder : Deepak Kumar Tala
(Verilog)
6 -- Translator : Alexander H Pham
(VHDL)
7
------------------------------------------------------
-
8 library ieee;
9 use
ieee.std_logic_1164.all;
10
11 entity encoder_using_case is
12 port (
13 enable :in
std_logic; --
Enable for the encoder
14 encoder_in :in
std_logic_vector (15 downto 0);--
16-bit Input
15 binary_out :out
std_logic_vector (3 downto 0) --
4 bit binary Output
16
17 );
18 end entity;
19
20 architecture behavior of
encoder_using_case is
21
22 begin
23 process (enable,
 encoder_in) begin
24 if (enable = '1')
then
25 case
(encoder_in) is
26 when
X"0002" => binary_out <= "0001";
27 when
X"0004" => binary_out <= "0010";
28 when
X"0008" => binary_out <= "0011";
29 when
X"0010" => binary_out <= "0100";
30 when
X"0020" => binary_out <= "0101";
31 when
X"0040" => binary_out <= "0110";
32 when
X"0080" => binary_out <= "0111";
33 when
X"0100" => binary_out <= "1000";
34 when
X"0200" => binary_out <= "1001";
35 when
X"0400" => binary_out <= "1010";
36 when
X"0800" => binary_out <= "1011";
37 when
X"1000" => binary_out <= "1100";
38 when
X"2000" => binary_out <= "1101";
39 when
X"4000" => binary_out <= "1110";
40 when
X"8000" => binary_out <= "1111";
41 when others
=> binary_out <= "0000";
42 end case;
43 end if;
44 end process;
45 end architecture;

Mux
Mux : Using with Statement
   
1 -------------------------------------------------------
2 -- Design Name : mux_using_with
3 -- File Name : mux_using_with.vhd
4 -- Function : 2:1 Mux using with-select
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7 -------------------------------------------------------
8 library ieee;
 9 use ieee.std_logic_1164.all;
10
11 entity mux_using_with is
12 port (
13 din_0 :in std_logic;-- Mux first input
14 din_1 :in std_logic;-- Mux Second input
15 sel :in std_logic;-- Select input
16 mux_out :out std_logic -- Mux output
17
18 );
19 end entity;
20
21 architecture behavior of mux_using_with is
22
23 begin
24 with (sel) select
25 mux_out <= din_0 when '0',
26 din_1 when others;
27
28 end architecture;
You could download file vhdl_examples here
   
   
  Mux : Using when Statement
   
1 -------------------------------------------------------
2 -- Design Name : mux_using_when
3 -- File Name : mux_using_assign.v
4 -- Function : 2:1 Mux using when
5 -- Coder : Deepak Kumar Tala
6 -------------------------------------------------------
7 library ieee;
8 use ieee.std_logic_1164.all;
9
10 entity mux_using_when is
11 port (
12 din_0 :in std_logic;-- Mux first input
13 din_1 :in std_logic;-- Mux Second input
14 sel :in std_logic;-- Select input
15 mux_out :out std_logic -- Mux output
16
17 );
18 end entity;
19
20 architecture behavior of mux_using_when is
21
22 begin
23 mux_out <= din_0 when (sel = '0') else
24 din_1;
25
26 end architecture;
You could download file vhdl_examples here
   
  Mux : Using if Statement
   
 1 -------------------------------------------------------
2 -- Design Name : mux_using_if
3 -- File Name : mux_using_if.vhd
4 -- Function : 2:1 Mux using If
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7 -------------------------------------------------------
8 library ieee;
9 use ieee.std_logic_1164.all;
10
11 entity mux_using_if is
12 port (
13 din_0 :in std_logic;-- Mux first input
14 din_1 :in std_logic;-- Mux Second input
15 sel :in std_logic;-- Select input
16 mux_out :out std_logic -- Mux output
17
18 );
19 end entity;
20
21 architecture behavior of mux_using_if is
22
23 begin
24 MUX:
25 process (sel, din_0, din_1) begin
26 if (sel = '0') then
27 mux_out <= din_0;
28 else
29 mux_out <= din_1;
30 end if;
31 end process;
32 end architecture;
You could download file vhdl_examples here
   
  Mux : Using case Statement
   
1 -------------------------------------------------------
2 -- Design Name : mux_using_case
3 -- File Name : mux_using_case.vhd
4 -- Function : 2:1 Mux using Case
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7 -------------------------------------------------------
8 library ieee;
9 use ieee.std_logic_1164.all;
10
11 entity mux_using_case is
12 port (
13 din_0 :in std_logic;-- Mux first input
14 din_1 :in std_logic;-- Mux Second input
15 sel :in std_logic;-- Select input
16 mux_out :out std_logic -- Mux output
17
18 );
 19 end entity;
20
21 architecture behavior of mux_using_case is
22
23 begin
24 MUX:
25 process (sel, din_0, din_1) begin
26 case sel is
27 when '0' => mux_out <= din_0;
28 when others => mux_out <= din_1;
29 end case;
30 end process;
31 end architecture;

Flip flops
  Asynchronous reset D- FF
  
1
------------------------------------------------------
-
2 -- Design Name : dff_async_reset
3 -- File Name :
dff_async_reset.vhd
4 -- Function : D flip-flop async
reset
5 -- Coder : Deepak Kumar Tala
(Verilog)
6 -- Translator : Alexander H Pham
(VHDL)
7
------------------------------------------------------
-
8 library ieee;
9 use
ieee.std_logic_1164.all;
10
11 entity dff_async_reset is
12 port (
13 data :in
std_logic;-- Data input
14 clk :in
std_logic;-- Clock input
15 reset :in
std_logic;-- Reset input
16 q :out std_logic
-- Q output
17
18 );
19 end entity;
20
21 architecture rtl of
dff_async_reset is
22
 23 begin
24 process (clk, reset)
begin
25 if (reset = '0') then
26 q <= '0';
27 elsif
(rising_edge(clk)) then
28 q <= data;
29 end if;
30 end process;
31
32 end architecture;
You could download file vhdl_examples
here
  
  Synchronous reset D- FF
  
1
------------------------------------------------------
-
2 -- Design Name : dff_sync_reset
3 -- File Name :
dff_sync_reset.vhd
4 -- Function : D flip-flop sync
reset
5 -- Coder : Deepak Kumar Tala
(Verilog)
6 -- Translator : Alexander H Pham
(VHDL)
7
------------------------------------------------------
-
8 library ieee;
9 use
ieee.std_logic_1164.all;
10
11 entity dff_sync_reset is
12 port (
13 data :in
std_logic;-- Data input
14 clk :in
std_logic;-- Clock input
15 reset :in
std_logic;-- Reset input
16 q :out std_logic
-- Q output
17
18 );
19 end entity;
20
21 architecture rtl of
dff_sync_reset is
22
23 begin
24 process (clk) begin
25 if
 (rising_edge(clk)) then
26 if (reset = '0')
then
27 q <= '0';
28 else
29 q <= data;
30 end if;
31 end if;
32 end process;
33
34 end architecture;

2)
1 -------------------------------------------------------
2 -- Design Name : tff_async_reset
3 -- File Name : tff_async_reset.vhd
4 -- Function : T flip-flop async reset
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7 -------------------------------------------------------
8 library ieee;
9 use ieee.std_logic_1164.all;
10
11 entity tff_async_reset is
12 port (
13 data :in std_logic;-- Data input
14 clk :in std_logic;-- Clock
input
15 reset :in std_logic;-- Reset
input
16 q :out std_logic -- Q output
17
18 );
19 end entity;
20
21 architecture rtl of tff_async_reset is
22 signal t :std_logic;
23 begin
24 process (clk, reset) begin
25 if (reset = '0') then
26 t <= '0';
27 elsif (rising_edge(clk)) then
28 t <= not t;
29 end if;
30 end process;
31 q <= t;
32 end architecture;
You could download file vhdl_examples here
   
  Synchronous reset T - FF
   
1
------------------------------------------------------
 -
2 -- Design Name : tff_sync_reset
3 -- File Name :
tff_sync_reset.vhd
4 -- Function : T flip-flop sync
reset
5 -- Coder : Deepak Kumar Tala
(Verilog)
6 -- Translator : Alexander H Pham
(VHDL)
7
------------------------------------------------------
-
8 library ieee;
9 use
ieee.std_logic_1164.all;
10
11 entity tff_sync_reset is
12 port (
13 data :in
std_logic;-- Data input
14 clk :in
std_logic;-- Clock input
15 reset :in
std_logic;-- Reset input
16 q :out std_logic
-- Q output
17
18 );
19 end entity;
20
21 architecture rtl of
tff_sync_reset is
22 signal t :std_logic;
23 begin
24 process (clk) begin
25 if
(rising_edge(clk)) then
26 if (reset = '0')
then
27 t <= '0';
28 else
29 t <= not t;
30 end if;
31 end if;
32 end process;
33 q <= t;
34 end architecture;

3)
Regular D Latch
   
1
 ------------------------------------------------------
-
2 -- Design Name : dlatch_reset
3 -- File Name : dlatch_reset.vhd
4 -- Function : DLATCH async
reset
5 -- Coder : Deepak Kumar Tala
(Verilog)
6 -- Translator : Alexander H Pham
(VHDL)
7
------------------------------------------------------
-
8 library ieee;
9 use
ieee.std_logic_1164.all;
10
11 entity dlatch_reset is
12 port (
13 data :in
std_logic;-- Data input
14 en :in
std_logic;-- Enable input
15 reset :in
std_logic;-- Reset input
16 q :out std_logic
-- Q output
17
18 );
19 end entity;
20
21 architecture rtl of
dlatch_reset is
22
23 begin
24 process (en, reset,
data) begin
25 if (reset = '0') then
26 q <= '0';
27 elsif (en = '1') then
28 q <= data;
29 end if;
30 end process;
31
32 end architecture;

Counters
 
  8-Bit Simple Up Counter
  
1 -------------------------------------------------------
2 -- Design Name : up_counter
3 -- File Name : up_counter.vhd
4 -- Function : Up counter
 5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7 -------------------------------------------------------
8 library ieee;
9 use ieee.std_logic_1164.all;
10 use ieee.std_logic_unsigned.all;
11
12 entity up_counter is
13 port (
14 cout :out std_logic_vector (7 downto
0); -- Output of the counter
15 enable :in std_logic;
-- Enable counting
16 clk :in std_logic;
-- Input clock
17 reset :in std_logic
-- Input reset
18 );
19 end entity;
20
21 architecture rtl of up_counter is
22 signal count :std_logic_vector (7 downto 0);
23 begin
24 process (clk, reset) begin
25 if (reset = '1') then
26 count <= (others=>'0');
27 elsif (rising_edge(clk)) then
28 if (enable = '1') then
29 count <= count + 1;
30 end if;
31 end if;
32 end process;
33 cout <= count;
34 end architecture;
8-Bit Up Counter With Load
  
1
--------------------------------------------------
-----
2 -- Design Name : up_counter_load
3 -- File Name : up_counter_load.vhd
4 -- Function : Up counter with load
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7
--------------------------------------------------
-----
8 library ieee;
9 use ieee.std_logic_1164.all;
10 use ieee.std_logic_unsigned.all;
11
12 entity up_counter_load is
13 port (
14 cout :out std_logic_vector (7 downto 0);
-- Output of the counter
15 data :in std_logic_vector (7 downto 0);
-- Parallel load for the counter
 16 load :in std_logic;
-- Parallel load enable
17 enable :in std_logic;
-- Enable counting
18 clk :in std_logic;
-- Input clock
19 reset :in std_logic
-- Input reset
20 );
21 end entity;
22
23 architecture rtl of up_counter_load is
24 signal count :std_logic_vector (7 downto
0);
25 begin
26 process (clk, reset) begin
27 if (reset = '1') then
28 count <= (others=>'0');
29 elsif (rising_edge(clk)) then
30 if (load = '1') then
31 count <= data;
32 elsif (enable = '1') then
33 count <= count + 1;
34 end if;
35 end if;
36 end process;
37 cout <= count;
38 end architecture;
8-Bit Up-Down Counter
  
1
--------------------------------------------------
-----
2 -- Design Name : up_down_counter
3 -- File Name : up_down_counter.vhd
4 -- Function : Up down counter
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7
--------------------------------------------------
-----
8 library ieee;
9 use ieee.std_logic_1164.all;
10 use ieee.std_logic_unsigned.all;
11
12 entity up_down_counter is
13 port (
14 cout :out std_logic_vector (7 downto
0); 15 up_down :in std_logic;
-- up_down control for counter
16 clk :in std_logic;
-- Input clock
17 reset :in std_logic
-- Input reset
18 );
19 end entity;
20
21 architecture rtl of up_down_counter is
22 signal count :std_logic_vector (7 downto
0);
 23 begin
24 process (clk, reset) begin
25 if (reset = '1') then
26 count <= (others=>'0');
27 elsif (rising_edge(clk)) then
28 if (up_down = '1') then
29 count <= count + 1;
30 else
31 count <= count - 1;
32 end if;
33 end if;
34 end process;
35 cout <= count;
36 end architecture;
  Random Counter (LFSR)
  
1
--------------------------------------------------
-----
2 -- Design Name : lfsr
3 -- File Name : lfsr.vhd
4 -- Function : Linear feedback shift
register
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7
--------------------------------------------------
-----
8 library ieee;
9 use ieee.std_logic_1164.all;
10
11 entity lfsr is
12 port (
13 cout :out std_logic_vector (7 downto 0);
14 enable :in std_logic; --
Enable counting
15 clk :in std_logic;
-- Input rlock
16 reset :in std_logic
-- Input reset
17 );
18 end entity;
19
20 architecture rtl of lfsr is
21 signal count :std_logic_vector
(7 downto 0);
22 signal linear_feedback :std_logic;
23
24 begin
25 linear_feedback <= not(count(7) xor
count(3));
26
27
28 process (clk, reset) begin
29 if (reset = '1') then
30 count <= (others=>'0');
31 elsif (rising_edge(clk)) then
32 if (enable = '1') then
33 count <= (count(6) & count(5)
& count(4) & count(3)
 34 & count(2) &
count(1) & count(0) &
35 linear_feedback);
36 end if;
37 end if;
38 end process;
39 cout <= count;
40 end architecture;
You could download file vhdl_examples here
  
  LFSR Up/Down
  
1
--------------------------------------------------
-----
2 -- Design Name : lfsr
3 -- File Name : lfsr_updown.vhd
4 -- Function : Linear feedback shift
register
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7
--------------------------------------------------
-----
8 library ieee;
9 use ieee.std_logic_1164.all;
10 use ieee.std_logic_unsigned.all;
11
12 entity lfsr_updown is
13 generic (
14 WIDTH :integer := 8
15 );
16 port (
17 clk :in std_logic;
-- Clock input
18 reset :in std_logic;
-- Reset input
19 enable :in std_logic;
-- Enable input
20 up_down :in std_logic;
-- Up Down input
21 count :out std_logic_vector
(WIDTH-1 downto 0); -- Count output
22 overflow :out std_logic
-- Overflow output
23 );
24 end entity;
25
26 architecture rtl of lfsr_updown is
27 signal cnt :std_logic_vector (WIDTH-1
downto 0);
28 begin
29
30 process (up_down, cnt) begin
31 if ((up_down = '1' and cnt = 1) or
32 (up_down = '0' and (cnt(WIDTH-1) =
'1' and
33 cnt(WIDTH-2 downto 0) = 0))) then
34 overflow <= '1';
 35 else
36 overflow <= '0';
37 end if;
38 end process;
39
40 process (clk, reset, cnt, enable, up_down)
41 variable temp_a :std_logic_vector
(WIDTH-1 downto 0);
42 variable temp_b :std_logic :='1';
43 begin
44
45 temp_a := cnt and "01100011";
46 temp_b :='1';
47 for i in 0 to WIDTH-1 loop
48 temp_b := temp_a(i) xnor temp_b;
49 end loop;
50
51 if (rising_edge(clk)) then
52 if (reset = '1') then
53 cnt <= (others=>'0');
54 elsif (enable = '1') then
55 if (up_down = '1') then
56 cnt <= (temp_b &
cnt(WIDTH-1 downto 1));
57 else
58 cnt <= (cnt(WIDTH-2 downto
0) & temp_b);
59 end if;
60 end if;
61 end if;
62 end process;
63 count <= cnt;
64
65 end architecture;
  LFSR Up/Down
  
1
--------------------------------------------------
-----
2 -- Design Name : lfsr
3 -- File Name : lfsr_updown.vhd
4 -- Function : Linear feedback shift
register
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7
--------------------------------------------------
-----
8 library ieee;
9 use ieee.std_logic_1164.all;
10 use ieee.std_logic_unsigned.all;
11
12 entity lfsr_updown is
13 generic (
14 WIDTH :integer := 8
15 );
16 port (
17 clk :in std_logic;
-- Clock input
18 reset :in std_logic;
 -- Reset input
19 enable :in std_logic;
-- Enable input
20 up_down :in std_logic;
-- Up Down input
21 count :out std_logic_vector
(WIDTH-1 downto 0); -- Count output
22 overflow :out std_logic
-- Overflow output
23 );
24 end entity;
25
26 architecture rtl of lfsr_updown is
27 signal cnt :std_logic_vector (WIDTH-1
downto 0);
28 begin
29
30 process (up_down, cnt) begin
31 if ((up_down = '1' and cnt = 1) or
32 (up_down = '0' and (cnt(WIDTH-1) =
'1' and
33 cnt(WIDTH-2 downto 0) = 0))) then
34 overflow <= '1';
35 else
36 overflow <= '0';
37 end if;
38 end process;
39
40 process (clk, reset, cnt, enable, up_down)
41 variable temp_a :std_logic_vector
(WIDTH-1 downto 0);
42 variable temp_b :std_logic :='1';
43 begin
44
45 temp_a := cnt and "01100011";
46 temp_b :='1';
47 for i in 0 to WIDTH-1 loop
48 temp_b := temp_a(i) xnor temp_b;
49 end loop;
50
51 if (rising_edge(clk)) then
52 if (reset = '1') then
53 cnt <= (others=>'0');
54 elsif (enable = '1') then
55 if (up_down = '1') then
56 cnt <= (temp_b &
cnt(WIDTH-1 downto 1));
57 else
58 cnt <= (cnt(WIDTH-2 downto
0) & temp_b);
59 end if;
60 end if;
61 end if;
62 end process;
63 count <= cnt;
64
65 end architecture;
You could download file vhdl_examples here
  
  
 1
--------------------------------------------------
-----
2 -- Design Name : lfsr
3 -- File Name : lfsr_updown_tb.vhd
4 -- Function : Linear feedback shift
register
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7
--------------------------------------------------
-----
8 library ieee;
9 use ieee.std_logic_1164.all;
10 use ieee.std_logic_textio.all;
11 use std.textio.all;
12
13 entity lfsr_updown_tb is
14 end entity;
15 architecture test of lfsr_updown_tb is
16
17 constant WIDTH :integer := 8;
18
19 signal clk :std_logic := '0';
20 signal reset :std_logic := '1';
21 signal enable :std_logic := '0';
22 signal up_down :std_logic := '0';
23 signal count :std_logic_vector (WIDTH-
1 downto 0);
24 signal overflow :std_logic;
25
26 component lfsr_updown is
27 generic (
28 WIDTH :integer := 8
29 );
30 port (
31 clk :in std_logic;
-- Clock input
32 reset :in std_logic;
-- Reset input
33 enable :in std_logic;
-- Enable input
34 up_down :in std_logic;
-- Up Down input
35 count :out std_logic_vector
(WIDTH-1 downto 0); -- Count output
36 overflow :out std_logic
-- Overflow output
37 );
38 end component;
39
40 constant PERIOD :time := 20 ns;
41
42 begin
43 clk <= not clk after PERIOD/2;
44 reset <= '0' after PERIOD*10;
45 enable <= '1' after PERIOD*11;
46 up_down <= '1' after PERIOD*22;
47
48 -- Display the time and result
 49 process (reset, enable, up_down, count,
overflow)
50 variable wrbuf :line;
51 begin
52 write(wrbuf, string'("Time: " ));
write(wrbuf, now);
53 write(wrbuf, string'(" rst: " ));
write(wrbuf, reset);
54 write(wrbuf, string'(" enable: " ));
write(wrbuf, enable);
55 write(wrbuf, string'(" up_down: " ));
write(wrbuf, up_down);
56 write(wrbuf, string'(" count: " ));
write(wrbuf, count);
57 write(wrbuf, string'(" overflow: "));
write(wrbuf, overflow);
58 writeline(output, wrbuf);
59 end process;
60
61 Inst_lfsr_updown : lfsr_updown
62 port map (
63 clk => clk,
64 reset => reset,
65 enable => enable,
66 up_down => up_down,
67 count => count,
68 overflow => overflow
69 );
70
71 end architecture;
Gray Counter
  
1
--------------------------------------------------
-----
2 -- Design Name : gray_counter
3 -- File Name : gray_counter.vhd
4 -- Function : 8 bit gray counters
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7
--------------------------------------------------
-----
8 library ieee;
9 use ieee.std_logic_1164.all;
10 use ieee.std_logic_unsigned.all;
11
12 entity gray_counter is
13 port (
14 cout :out std_logic_vector (7 downto
0); -- Output of the counter
15 enable :in std_logic;
-- Enable counting
16 clk :in std_logic;
-- Input clock
17 reset :in std_logic
-- Input reset
18 );
19 end entity;
20
 21 architecture rtl of gray_counter is
22 signal count :std_logic_vector (7 downto
0);
23 begin
24 process (clk, reset) begin
25 if (reset = '1') then
26 count <= (others=>'0');
27 elsif (rising_edge(clk)) then
28 if (enable = '1') then
29 count <= count + 1;
30 end if;
31 end if;
32 end process;
33 cout <= (count(7) &
34 (count(7) xor count(6)) &
35 (count(6) xor count(5)) &
36 (count(5) xor count(4)) &
37 (count(4) xor count(3)) &
38 (count(3) xor count(2)) &
39 (count(2) xor count(1)) &
40 (count(1) xor count(0)) );
41 end architecture;
One Hot Counter
  
1
--------------------------------------------------
-----
2 -- Design Name : one_hot_cnt
3 -- File Name : one_hot_cnt.vhd
4 -- Function : 8 bit one hot counter
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7
--------------------------------------------------
-----
8 library ieee;
9 use ieee.std_logic_1164.all;
10
11 entity one_hot_cnt is
12 port (
13 cout :out std_logic_vector (7 downto
0); -- Output of the counter
14 enable :in std_logic;
-- Enable counting
15 clk :in std_logic;
-- Input clock
16 reset :in std_logic
-- Input reset
17 );
18 end entity;
19
20 architecture rtl of one_hot_cnt is
21 signal count :std_logic_vector (7 downto
0);
22 begin
23 process (clk) begin
24 if (rising_edge(clk)) then
25 if (reset = '1') then
26 count <= "00000001";
27 elsif (enable = '1') then
 28 count <= (count(6) & count(5)
& count(4) & count(3) &
29 count(2) & count(1)
& count(0) & count(7));
30 end if;
31 end if;
32 end process;
33 cout <= count;
34 end architecture;
Divide by 2 Counter
  
1
--------------------------------------------------
-----
2 -- Design Name : clk_div
3 -- File Name : clk_div.vhd
4 -- Function : Divide by two counter
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7
--------------------------------------------------
-----
8 library ieee;
9 use ieee.std_logic_1164.all;
10
11 entity clk_div is
12 port (
13 cout :out std_logic; -- Output clock
14 enable :in std_logic; -- Enable
counting
15 clk :in std_logic; -- Input clock
16 reset :in std_logic -- Input reset
17 );
18 end entity;
19
20 architecture rtl of clk_div is
21 signal clk_div :std_logic;
22 begin
23 process (clk, reset) begin
24 if (reset = '1') then
25 clk_div <= '0';
26 elsif (rising_edge(clk)) then
27 if (enable = '1') then
28 clk_div <= not clk_div;
29 end if;
30 end if;
31 end process;
32 cout <= clk_div;
33 end architecture;
Divide By 3 Counter
This module divides the input clock frequency by 3
  
1
--------------------------------------------------
-----
2 -- Design Name : divide_by_3
3 -- File Name : divide_by_3.vhd
4 -- Function : Divide By 3
 5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7
--------------------------------------------------
-----
8 library ieee;
9 use ieee.std_logic_1164.all;
10 use ieee.std_logic_unsigned.all;
11
12 entity divide_by_3 is
13 port (
14 cout :out std_logic; -- Output clock
15 clk :in std_logic; -- Input clock
16 reset :in std_logic -- Input reset
17 );
18 end entity;
19
20 architecture rtl of divide_by_3 is
21 signal pos_cnt :std_logic_vector (1 downto
0);
22 signal neg_cnt :std_logic_vector (1 downto
0);
23 begin
24 process (clk, reset) begin
25 if (reset = '1') then
26 pos_cnt <= (others=>'0');
27 elsif (rising_edge(clk)) then
28 if (pos_cnt = 2) then
29 pos_cnt <= pos_cnt + 1;
30 end if;
31 end if;
32 end process;
33
34 process (clk, reset) begin
35 if (reset = '1') then
36 neg_cnt <= (others=>'0');
37 elsif (falling_edge(clk)) then
38 if (neg_cnt = 2) then
39 neg_cnt <= neg_cnt + 1;
40 end if;
41 end if;
42 end process;
43
44 cout <= '1' when ((pos_cnt /= 2) and
(neg_cnt /= 2)) else
45 '0';
46 end architecture;
47
--------------------------------------------------
-----
48 -- Testbench to check the divide_by_3 logic
49
--------------------------------------------------
-----
50 library ieee;
51 use ieee.std_logic_1164.all;
52 use ieee.std_logic_textio.all;
53 use std.textio.all;
54
55 entity div3_tb is
56 end entity;
 57 architecture test of div3_tb is
58
59 signal cout :std_logic;
60 signal clk :std_logic := '1';
61 signal reset :std_logic := '1';
62
63 component divide_by_3 is
64 port (
65 cout :out std_logic;
66 clk :in std_logic;
67 reset :in std_logic
68 );
69 end component;
70 begin
71
72 -- Generate clock
73 clk <= not clk after 10 ns;
74 reset <= '0' after 20 ns;
75
76 Inst_div3 : divide_by_3
77 port map (
78 cout => cout, -- Output
79 clk => clk, -- Input
80 reset => reset -- Iinput
81 );
82 end architecture;
Divide By 4.5 Counter
  
1
--------------------------------------------------
-----
2 -- Design Name : clk_div_45
3 -- File Name : clk_div_45.vhd
4 -- Function : Divide by 4.5
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7
--------------------------------------------------
-----
8 library ieee;
9 use ieee.std_logic_1164.all;
10 use ieee.std_logic_unsigned.all;
11
12 entity clk_div_45 is
13 port (
14 cout :out std_logic; -- Output clock
15 enable :in std_logic; -- Enable
counting
16 clk :in std_logic; -- Input clock
17 reset :in std_logic -- Input reset
18 );
19 end entity;
20
21 architecture rtl of clk_div_45 is
22 signal counter1 :std_logic_vector (2
downto 0);
23 signal counter2 :std_logic_vector (2
downto 0);
24 signal toggle1 :std_logic;
25 signal toggle2 :std_logic;
 26
27 begin
28 process (clk) begin
29 if (rising_edge(clk)) then
30 if (enable = '0') then
31 counter1 <= (others=>'0');
32 toggle1 <= '0';
33 elsif ((counter1 = 3 and toggle2 =
'1') or
34 (toggle1 = '0' and counter1
= 4)) then
35 counter1 <= (others=>'0');
36 toggle1 <= not toggle1;
37 else
38 counter1 <= counter1 + 1;
39 end if;
40 end if;
41 end process;
42
43 process (clk) begin
44 if (falling_edge(clk)) then
45 if (enable = '0') then
46 counter2 <= (others=>'0');
47 toggle2 <= '0';
48 elsif ((counter2 = 3 and toggle2 =
'0') or
49 (toggle2 = '1' and counter2
= 4)) then
50 counter2 <= (others=>'0');
51 toggle2 <= not toggle2;
52 else
53 counter2 <= counter2 + 1;
54 end if;
55 end if;
56 end process;
57 cout <= enable when (counter1 < 3 and
counter2 < 3) else
58 '0';
59 end architecture;

Package coding
LFSR Package
   
1 -------------------------------------------------------
2 -- Design Name : User Pakage
3 -- File Name : lfsr_pkg.vhd
4 -- Function : Defines function for LFSR
5 -- Coder : Alexander H Pham (VHDL)
6 -------------------------------------------------------
7 library ieee;
8 use ieee.std_logic_1164.all;
9 use ieee.std_logic_unsigned.all;
10
11 package lfsr_pkg is
12
13 -- LFSR Feedback for 2**n
 14 function many_to_one_fb (DATA, TAPS :std_logic_vector) return
std_logic_vector;
15 function one_to_many_fb (DATA, TAPS :std_logic_vector) return
std_logic_vector;
16
17 end;
18
19 package body lfsr_pkg is
20
21 function many_to_one_fb (DATA, TAPS :std_logic_vector) return
std_logic_vector is
22 variable xor_taps :std_logic;
23 variable all_0s :std_logic;
24 variable feedback :std_logic;
25 begin
26
27 -- Validate if lfsr = to zero (Prohibit Value)
28 if (DATA(DATA'length-2 downto 0) = 0) then
29 all_0s := '1';
30 else
31 all_0s := '0';
32 end if;
33
34 xor_taps := '0';
35 for idx in 0 to (TAPS'length-1) loop
36 if (TAPS(idx) = '1') then
37 xor_taps := xor_taps xor DATA(idx);
38 end if;
39 end loop;
40
41 feedback := xor_taps xor all_0s;
42
43 return DATA((DATA'length-2) downto 0) & feedback;
44
45 end function;
46
47 function one_to_many_fb (DATA, TAPS :std_logic_vector) return
std_logic_vector is
48 variable xor_taps :std_logic;
49 variable all_0s :std_logic;
50 variable feedback :std_logic;
51 variable result :std_logic_vector (DATA'length-1 downto 0);
52 begin
53
54 -- Validate if lfsr = to zero (Prohibit Value)
55 if (DATA(DATA'length-2 downto 0) = 0) then
56 all_0s := '1';
57 else
58 all_0s := '0';
59 end if;
60
61 feedback := DATA(DATA'length-1) xor all_0s;
62
63 -- XOR the taps with the feedback
64 result(0) := feedback;
65 for idx in 0 to (TAPS'length-2) loop
66 if (TAPS(idx) = '1') then
 67 result(idx+1) := feedback xor DATA(idx);
68 else
69 result(idx+1) := DATA(idx);
70 end if;
71 end loop;
72
73 return result;
74
75 end function;
76 end package body;
77
78
79
You could download file vhdl_examples here
   
Package Implementation
   
1 -------------------------------------------------------
2 -- Design Name : lfsr_implement
3 -- File Name : lfsr_implement.vhd
4 -- Function : Use of the lfsr package
5 -- Coder : Alexander H Pham (VHDL)
6 -------------------------------------------------------
7 library ieee;
8 use ieee.std_logic_1164.all;
9 use work.lfsr_pkg.all;
10
11 entity lfsr_implement is
12 port (
13 clk :in std_logic;
14 rst :in std_logic;
15 lfsr_1 :out std_logic_vector (7 downto 0);
16 lfsr_2 :out std_logic_vector (7 downto 0)
17 );
18 end entity;
19
20 architecture rtl of lfsr_implement is
21 constant taps :std_logic_vector (7 downto 0) := "10001110";
22 signal lfsr_a :std_logic_vector (7 downto 0);
23 signal lfsr_b :std_logic_vector (7 downto 0);
24
25 begin
26
27 process (clk, rst) begin
28 if (rst = '1') then
29 lfsr_a <= (others=>'0');
30 lfsr_b <= (others=>'0');
31 elsif (rising_edge(clk)) then
32 lfsr_a <= many_to_one_fb (lfsr_a, taps);
33 lfsr_b <= one_to_many_fb (lfsr_b, taps);
34 end if;
35 end process;
36
37 lfsr_1 <= lfsr_a;
38 lfsr_2 <= lfsr_b;
39 end architecture;
 40
41 ------------------------------------------------------------------------------
42 -- TEST BENCH
43 ------------------------------------------------------------------------------
44 library ieee;
45 use ieee.std_logic_1164.all;
46 use ieee.std_logic_unsigned.all;
47 use ieee.std_logic_textio.all;
48 use std.textio.all;
49
50 entity lfsr_tb is
51 end entity;
52 architecture test of lfsr_tb is
53
54 signal clk :std_logic := '0';
55 signal rst :std_logic := '1';
56 signal lfsr_1 :std_logic_vector (7 downto 0);
57 signal lfsr_2 :std_logic_vector (7 downto 0);
58
59 component lfsr_implement is
60 port (
61 clk :in std_logic;
62 rst :in std_logic;
63 lfsr_1 :out std_logic_vector (7 downto 0);
64 lfsr_2 :out std_logic_vector (7 downto 0)
65 );
66 end component;
67 begin
68
69 -- Generate clock
70 clk <= not clk after 10 ns;
71 rst <= '0' after 3 ns;
72
73 Inst_lfsr : lfsr_implement
74 port map (
75 clk => clk,
76 rst => rst,
77 lfsr_1 => lfsr_1,
78 lfsr_2 => lfsr_2
79 );
80
81 -- Display the time and result
82 process (clk)
83 variable wrbuf :line;
84 begin
85 if (clk = '1') then
86 write(wrbuf, string'("Time: ")); write(wrbuf, now);
87 write(wrbuf, string'("; lfsr_1: ")); write(wrbuf,
conv_integer(lfsr_1));
88 write(wrbuf, string'("; lfsr_2: ")); write(wrbuf,
conv_integer(lfsr_2));
89 writeline(output, wrbuf);
90 end if;
91 end process;
92
93 end architecture;
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