Question

no. Question Statement Option 1 Option 2 Option 3 Option 4

1 Convert the number with the indicated

(580)10 base to
(680)
decimal
10
(4310)
(780)510 (880)10
2 Convert the number with the indicated
(260)10 base to
(360)
decimal
10
(198)
(250)
1210
(300)10
3 Convert the number with the indicated
(447)10 base to
(477)
decimal
10
(735)
(460)
8 10
(457)10
4 Convert the number with the indicated
(187)10 base to
(197)
decimal
10
(525)
(193)
6 10
(185)10

5 Determine the base of the numbe 6 8 5 2

6 Determine the base of the numbe 6 8 5 2
7 Determine the base of the numb 11 10 12 16

8 The solutions to the quadratic e 8 10 6 3

9 Express in decimal (10110.0101)2 22.1325 22.3125 22.2225 22.1234
10 Express in decimal (16.5)16 22.1325 22.3125 22.2225 22.1234
11 Express in decimal (26.24)8 22.1325 22.3125 22.2225 22.1234
12 Express in decimal (FAFA)16 64250.6875 64,255.89 64,350.69 63350.6875
13 Express in decimal 1010.10102 10.625 10.666 10.525 10.622
14 Obtain the 1 's and 2's comple 01111111 and11111111 a10111111 a11111111 and 10000000
15 Obtain the 1 's and 2's comple 00100101 and10100101 a11100101 a00100111 and 00100110
16 Obtain the 1 's and 2's comple 1000_1001 an1001_1001 1011_1001 1000_1001 and 1011_10
17 Obtain the 1 's and 2's comple 0111_1010 an0111_1110 0111_1111 0111_1010 and 0101_11
20 Obtain the 1 's and 2's comple 0000_0000 an0000_0001 1111_1111 0000_0000 and 1111_11
21 find the 9's and the 10's compl 47,215,369 an47,215,339 47,325,369 57,215,396 and 57,215,3
22 find the 9's and the 10's compl 36,674,399 an36,674,388 36,688,399 38,674,399 and 38,674,4
23 find the 9's and the 10's compl 74,999,999 an74,999,888 74,999,888 74,999,999 and 75,000,1
24 find the 9's and the 10's compl 99,999,999 an11,111,111 99,999,999 00,000,000 and 99,999,9
25 Find the 16's complement of BZ4D06 4B06 5D06 4D26
26 Convert B2FA to binary 1011_0010_111011_1111_1111_1110_1011_0010_1111_1111
27 convert decimal 8723 to BCD 1000_0111_001000_0111_1111_0111_1000_0111_1110_0011
28 convert decimal 8723 to ASCII 0_011_1000_00_011_10000_011_10001_111_1000_011_0111_0
29 Convert 5137 into BCD 0101_0011_010101_1111_0101_1111_1101_0111_0111
30 Convert 5137 into Excess-3 1000_0100_011000_0100_1011_1100_1000_0111_0111_1010
31 What bit must be complemented bit 6 from righbit 6 from lebit 1 from lebit 1 from right
32 The octal equivalent of the bin 327 656 423 535
33 when two n-bits binary numbersn-bit n+1 bits n-1 bits n+n bits
34
44

combinational logic
33
34
35
36
37
38
39
40
41 MOS family includes PMOS and CMEMOS,PMOSPMOS,NMOS PMOS and NMOS
42 Propagation delay refers to the time taken the time takethe time takthe time taken for the ou
43
 Correct
Option 5 Answer-1 Tag isShuffle State Level Author Provider

(580)10 binary conversion

(260)10 binary conversion
(477)10 binary conversion
(197)10 binary conversion

6 base
8 base
11 base

8 base
22.3125 binary conversion
22.3125 binary conversion
22.3125 binary conversion
64250.6875 binary conversion
10.625 binary conversion
111111 and 10000000 01111111 andcomplement
100111 and 00100110 00100101 andcomplement
00_1001 and 1011_10 1000_1001 ancomplement
11_1010 and 0101_110111_1010 ancomplement
00_0000 and 1111_11 0000_0000 ancomplement
,215,396 and 57,215,347,215,369 ancomplement
,674,399 and 38,674,4 36,674,399 ancomplement
,999,999 and 75,000,1 74,999,999 ancomplement
0,000,000 and 99,999,999,999,999 ancomplement
4D06 complement
11_0010_1111_1111 1011_0010_1111_1010
00_0111_1110_0011 1000_0111_00BCD conersion
111_1000_011_0111_00_011_1000_0ASCII conversion
01_0111_0111 0101_0011_01BCD conersion
00_0111_0111_1010 1000_0100_01Excess-3
1 from right bit 6 from righASCII conversion
327 binary conversion
n+1 bits
 M
M
H
E
M
M
E
MOS and NMOS PMOS,NMOS acombinational circuit M
e time taken for the ou the time taken combinational circuit M
 1 Simply the y x x' y' y
2 Simply the (x⊕y)+(x⊕(x z ⊕y)'+(x⊕(x⊕y)+(x⊕(x z ⊕z)+(x⊕z)'+(y⊕z)' (x⊕y)+(x⊕z
3 Simply theB A A' B' B
4 Simply thex(w+y) x(w'+y') x'(w+y) xw+y x(w+y)
5 Simply the 0 AB A+B A+B+C+D 0
6 Simply the Z'+X'Y' Z'+X'+Y' Z'+XY ZX+Y Z'+X'Y'
7 Find the c (w' + x')(y' (w + x)(y' +(w' + x')(y'+(w+ x)'(y' + z') (w' + x')(y'
8 Express th ∑(1,3,5,7,9,11,13,15)
∑(0,2,4,6,8Either None of these ∑(1,3,5,7,9
9 Express th ∏(1,3,5,7,9,11,13,15) Either
∏(0,2,4,6,8,10,12,14) None of these ∏(0,2,4,6,8,10,12,14)
10 Convert intAB + BC A(B+C) AB+C A+C AB + BC
11 covert intoB(A+C) BA+BC AB+C A(B+C) B(A+C)
12 Simplify thexyequation
+ x’z' xy'
F(X,Y,Z)=
+ x’z' x'y + x’z' (x+y ) x’z' xy + x’z'
13 Simplify thez' equation
+ x'y z'F(X,Y,Z)=
+ xy z + x'y z' (x'+y) z' + x'y
14 Simplify thex'equation
+ yz x'F(X,Y,Z)=
+ y'z' x' + y+z x'+ y+z x' + yz
15 Simplify thexy+yz+xz
equation x'y'+yz+xz
F(X,Y,Z)= xy+y'z'+xz xy+yz+x'z' xy+yz+xz
16 Simplify thex'y'
equation
+ xz x'y'
F(X,Y,Z)=
+ xz' xy + xz x+y + xz x'y' + xz
17 Simplify th y + x'z y + x'z' y' + x'z y' + x'z; y + x'z
18 Simplify thx'y' + xy x'y' + x'y x'y' + xy' xy' + xy x'y' + xy
19 Simplify thy' + x'z y+ x'z y' + x'z' (y' + x')z y' + x'z
20 Simplify thz z' x+y'+z y+z z
21 Simplify thx + y' z x + y' z' x' + y' z x'+ y' z' x + y' z
22 Simplify theBCD + A' B B'CD' + A' BCD'' + A' B+CD + A' BD' BCD + A' B
23 Simplify theCDequation
+ ABD +CD
F(A,B,C,D)=
+ ABD +CD + AD + ACD + ABD + ABC CD + ABD +
24 Simplify thw'x'y +wx w'x'y +wx' wx'y +wx w'x' +wx w'x'y +wx
25 Simplify thw'x + w'y'zw'x + w'yz'w'x + w'y'z'w'x' + w'y'z' w'x + w'y'z
26 Simplify thx'y' + w'y'z'x'y' + w'y'zxy + w'y'z xy + wyz x'y' + w'y'z
27 Simplify the equation xz' + w'y'z xz' + w'y'z+x'z' + w'y'z+ w'xy xz' + w'y'z

A'C + A'
C'D' +
B'C'D'
28 Simplify theA'C
equation
+ A' C' A'C'
F(A,B,C,D)=∑(1,5,9,10,11,14,15)
+ A' C'A'C' + AC'D A'C + A' C'
29 Simplify thw'y' + wx' w'y' + w'x' w'y + wx' ywy + wx y + w'xy w'y' + wx'
30 Simplify thBD + B'D' +BD + A'B + Either Both are correct Both are co
31 simplify th B' D' +A'B B D' +ABD B' D' +A'B B' D' +A'BD'+ A'BC' B' D' +A'B
32 simplify th xy' +x'z + wxy' +x'z' + xy' +x'z' + x'y' +x'z' + wx'y xy' +x'z + w
33 simplify th B'D' + BCD B'D' + BCD B'D' + B'C' B'D'( B+C) + A'BD + A'B'D' + BCD

A'B'D' +
BC'D +
ACD' +
AB'C
34 simplify th A'BD + BC' AB'D' + BC A'B'D + AC'D + ACD' +A'B'D' + BC
35 Simplify thA'B'D' + ADABD' + AD'EA'B'D' + ADA'B'D+ B'D'E + B'C'D' A'B'D' + AD
36 simply the given
x'z' + w'x'y
SOP Fx'z'
= + w'x'y x'z' + wxy' x'z + w'xy' + w'y'z x'z' + w'x'y
37 Simplify toxy+z' x'y+z' x'y'+z' xy+z xy+z'
38 Simplify to(x + z ')(y + (x' + z ')(y' (x' + z ')(y +(x + z ')(y'+ z ') (x + z ')(y +
39 Simplify t AC' + AD + AC' + AD + AC' + A'D +AC' + A'D + C'D' + AB'CAC' + AD +
40 Simplify t (A + D)(A +(A' + D')(A (A' + D)(A' (A + D')(A' + C')(B + C' (A + D)(A +
41 Simplify wi[(y + z)' + ( [(y + z)' + ( [(y + z)+ (w'[(y + z)' + (w + x) + (w [+(y + z)' + (
42 Simplify wi(w +x')' + (w (w +x') + (w'(w +x') + (w' (w +x') + (w'(w +x')' + (w
(w +x')' + (w
43 Simplify wit[(x + y)' + (x(x + y)' + (x[(x + y) + (x'[(x + y)+ (x' + z)]' [(x + y)' + (x
44 What is the(00,01,10,1(00,01,11,1(01,00,11,1(11,00,01,10) (00,01,11,1
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simplification
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k-map
 Questio
n Correct
Questio Stateme Answer-
n no. nt Option 1 Option 2 Option 3 Option 4 Option 5 1
1 How many AN 1 2 3 4 2
2 the NOR gat Both are 0 Both are 1 One is 1 analways high Both are ze
3 The gates rEX-OR gateEX-OR gateEX-OR gateEX-OR gate and EX-NOEX-OR gate
4 Exclusive-OAND , OR , AND , OR GOR,NOR,EXonly OR gates AND , OR ,
5 The AND fiEnable andDisable an SynchronizDetect and invert Enable and
6 The dependOR AND EXOR NAND OR
7 If we use aLOW inverted disabled HIGH LOW
8 Logic gate Outputs Inputs Pre-state Post-state Inputs
9 How many N 1 2 3 4 4
10 Which of thS-TTL AS-TTL HS-TTL HCMOS AS-TTL
11 Logic circu A greater cuGreater inpA smaller oGreater the input andA greater c
12 which of thOR agte AND gate ExOR gate NOT gate ExOR gate
13 An AND willAll inputs tAll inputs tEIther of thAll inputs and outpu All inputs
14 An OR gate 6 32 64 128 64
15 a debouncin an astable a stable M a ,onostab a latch a latch
16 NAND is prAny gate c low power faster less area Any gate c
17 The fan put2TTL 4TTL 8TTL 10TTL 10TTL
18 Excess-3 coweighted ccyclic red Self-complAlgebraic code Self-compl
19 How many N 2 3 4 5 2
Tag
gates
gates
gates
gates
gates
gates
gates
gates
gates
gates
gates
gates
gates
gates
gates
gates
gates
gates
 Questio
n Correct
Questio Stateme Answer-
n no. nt Option 1 Option 2 Option 3 Option 4 Option 5 1
1 AS-TTL logi50MHz 105MHz 150MHz 200MHz 105MHz
2 maximum cl S-TTL AS-TTL HS-TTL HCMOS AS-TTL
3 Maximum ch over 3000020000v 10000v 0v over 30000
4 What causeThe schot a large valuusing NANDNone of these a large valu
5 Which statThe devicesAll tools, The devicesAll the statement are All the sta
6 What a trutDescribes adescribes aoperation oAny of the statement describes a combinational ci
7 What a statDescribes adescribes aoperation oAny of the statement Describes a sequential circui
8 What a char Describes adescribes aoperation oAny of the statement operation of filpflop
9 What is SSIShort scalesmall scalesmall set i None of these small scale integration
10 how many Lessga than between 10more than None of these less than 10
11 what is MSIMedium Sca merged scalMass scalemain scale integrationMedium Scale integration
12 how many Lessga than between 12more than None of these between 12 to 100
13 What is LSILong Scale large scale long short None of these large scale integration
14 how many Lessga than Between 10Greater th None of these Between 100 to 5000
15 Integarted Lcarge, Sma Very Large, Linear and None of these Linear and digital
16 logic famili RTL and TTHTL and C ECL and DTBipolar and MOS Bipolar and MOS
17 The full fo Dual-In-Li Double-In-Double Int Double-In-Long packaDual-In-Line package
18 LCC refers tLeadless ChLongest ChiLeaded Chip Carrier Leadless Chip Carrier
19 PGA refers Pin Grid ArPlastic Gri Pin Greate Pin Greater Array Pin Grid Array
20 The code wh Binary BCD Excess 3 Gray Gray
21 The maximum Noise MargNoise immu white nois None of these Noise immunity
22 Fanin and FRegister logic famil flipflop combinational circuit logic family

23 What referRegister-TrReal-Time Real-Time LNone of these Register-Transistor Logic

24 In RTL NOR Logic
g is zerlogic is one10V None of these Logic is zero
25 Resistor–trResistors, bCapacitor, bCapacitor, rNone of these Resistors, bipolar junction tran
26 Main drawb current hogvoltage ho power hogboth current and volt current hogging
27 Which of thRTL ECL TTL CMOS RTL
28 Which elemecollector rebase resistcommon em transistor collector resistor
29 The disadvit uses ma high powerhigh noise propagation delay high power dissipation
30 The minimum 2 3 4 5 2

MOS
31 Which insulaluminiumsilicon nitr silicon dio aluminium nitrate silicon dioxide
32 Which of thdielectric threshold vpower suppdrain to gate voltage threshold voltage
33 A techniq Use of comUses of Sil using filim use of silicon nitride use of silicon nitride
34 What is usepoly silico ceramic gasilicon nitr silicon dioxide poly silicon gate
35 Why MOSFET MOSFET hasMOSFET hasMOSFET hasMOSFET has no packingMOSFET has low packing dens
36 Critical def HIGH LOW NEUTRAL UNPREDICTABLE LOW
37 MOS is beinLSI VLSI MSI both LSI and VLSI both LSI and VLSI
38 CMOS techn inveter digital logi microproceboth digital logic and both digital logic and microp
39 Two importhighnoise low static high resistihighnoise immunity ahighnoise immunity and low
40 CMOS behainverter comparatoradder substractor inverter
41 An important noise immusymmitricitduality None of these duality
42 CMOS logicmore less equal depends on applicati less
43 In CMOS cirstatic dissi dynamic disboth None of these dynamic dissipation
44 In high noise margindriven
receiving (NMH), the difference
both in of
None magnitude
these between
receivingthe maximum HIGH
45 Which factoLoad capacsupply voltgain facto All the statement are All the statement are true
46 For compleSeries Parallel Both seriesNone of these parallel
47 In pull-up network, PMOS
1 transistors
0 both of CMOS areofconnected
1 andNone these in parallel with
1 the provision of
48 n CMOS inv highest lowest averege None of these averege
49 In DIBL, whsubthreshogate leaka junction leAll the statement are All the statement are true
50 In enhancement
increases
MOSFET,
decreases
the magnitude
remain conNone
of output
of these
current __________
increasesdue to an increase in
51 Which typedepletion EnhancemeBoth None of these enhancement MOSFET
 Tag
logic family
logic family
logic family
logic family
CMOS
describes a combinational circuit
Describes a sequential circuit
operation of filpflop
small scale integration
less than 10
Medium Scale integration
between 12 to 100
large scale integration
Between 100 to 5000
Linear and digital
Bipolar and MOS
Dual-In-Line package
Leadless Chip Carrier
Pin Grid Array
Code
Noise immunity
logic family

Register-Transistor Logic
Logic is zero
Resistors, bipolar junction transistors (BJTs)
current hogging

collector resistor
high power dissipation

silicon dioxide
threshold voltage
use of silicon nitride
poly silicon gate
MOSFET has low packing density

both LSI and VLSI

both digital logic and microprocessor
highnoise immunity and low static power consuption

dynamic dissipation

All the statement are true

All the statement are true

enhancement MOSFET
 Correct
Questio Answer-
n no. Question Statement Option 1 Option 2 Option 3 Option 4 Option 5 1
The following switching
functions are to be
implemented using a
decoder:
f1 = ∑m(1, 2, 4, 8, 10,
14) f2 = ∑m(2, 5, 9, 11)
f3 = ∑m(2, 4, 5, 6, 7)
The minimum
configuration of
1 decoder will be 2 to 4 line 3 to 8 line 4 to 16 line5 to 32 line 4 to 16 line
x'y' + x'z'
2 obtain output for a cobin xy + x'z' x'y' + xz xy + xz x'y' + x'z'
3 how many gates required2 AND & 1 2OR and 1 2OR & 2ANnone of these 2 AND & 1OR
4 obtain output for a cobinZ X Y XY Z

A = x'y + A = x'y +
yz, B=x'y' A = xy + A = x'y + A = xy + yz, B=x'y'
+ y'z + yz, B=x'y' yz, B=xy+ yz, B=xy + + y'z +
xyz' + y'z + yz + xyz' y'z + xyz' xyz'
, C=x'z + xyz' , C=x'z + , C=x'z + , C=x'z +
xz' , C=xz + xz xz' xz' xz'
5 Design a cobinational log
6 Controlled inverter is als Controlled NOT both contrnone of these both contr
7 Why XOR gate is called anIt behaves Because ofBecause ounone of these It behaves like a NOT gate
8 Controlled buffer can beTo control in compariin increasi all the above mentio To control circuit output in
9 A logic circuit that pro OR AND EXOR EXNOR EXNOR
10 What is major differenceFull adder half adder full adder full adder is made of Full adder have carry inpu
11 The binary substraction difference difference difference difference=1,borrow=difference=0,borrow=0
12 How many basic subtracti 2 4 8 16 4
13 When perfoming substrac The minuenThe minuend The minuendThe minuend and the subtrahend are both change
14 What are the two typesof Sum and caHalf adder Asynchronuone and twos compleHalf adder and full adder
15 Which of the following isIn a paralleFull adder Full adder Full adders are limited In a parallel full adder, the
16 The selector inputs to a Selection oArithmetic data word clock frequency to beArithmetic or logic functio
17 Indicate which of the folOR gate NAND gateNOR gate Both NAND and NOR Both NAND and NOR
18 The number of boolean fu 22n 22n-1 2n-1 2n 22n
19 A two bit multiplier can 2 input AN2 input XORTwo input XOR gates and shift re2 input XOR gate and 2 inp
20 Fast-look-ahead carry cirReduce proAdd a 1 to determine increase ripple delay Reduce propagation delay
21 One way to make a four-b Inverting t Grouding thInverting t inverting the carry-in Inverting the B inputs
22 what distinguishes the It is fast t it easily t it is slowe it requires advance k It is fast than a ripple carr
23 Carry look ahead adder uinverting t inverting t genertaingripple factor genertaing and propagatin
24 what is one disadvantageThe interc More stages It is slow all the above mentio It is slow due to propagati
25 The carry propagation del Is cumulatiIs normallyDecreases Iincreases in direct ratIs cumulative for each stag
26 What is Manchester carrIs a chain Variation oVariation onone of these Variation of a carry-look a
27 The main disadvantage oRipple factPropagatioCapacitive Both propagation delaBoth propagation delay an
28 The summing outputs ofOmega theeta lambda sigma sigma
29 why is a fast-look-ahead to decreaseto make it to speed upto make it compactiblto speed up the circuit
30 Inverter can be represe 1 2 4 3 1
31 One positive pulse with tThe exclusiThe exclusiThe exclusiThe exclusive-OR outpu The exclusive-OR output i
32 The carry look ahead addAddend,MiMinuend,SAddend,MIAugend, addend Augend, addend
33 What are carry generateIf all the If all of t If all the none of these If all of the output are ind
34 In serial addition, the ad3 bits per byte by bytbit by bit none of these bit by bit
35 How many shift registers 2 3 4 5 2
36 A D flip-flop is used in a It is used it is used t it is used t none of these It is used to store the carr
37 What is ripple carry add The carry oThe carry i The carry onone of these The carry output of the lo
38 If minuend = 0, subtrahe 0 1 not possiblnone of these 1
39 A serial subtractor can b1's comple2's comple9's comple10's complement 2's complement
40 The hexadecimal number444ns ( 444s 355ns 355s 444ns
41 Internally, a computer’s parallel bu data bus address buserial bus data bus
42 What is the frequency of8KHz .8KHz .8MHz 8MHz .8MHz
43 Why is parallel data tranIt is much it is cheapeit is compafabrication easy It is much faster
44 With surface-mount techUtilize tra Mount direHave parallRequire holes and pa Mount directly
45 In the most applications,They consuThey are faThey are quall the above mentio all the above mentioned
46 What can a relay provid Total isolatFaster Higher currTotal isolation and Hi Total isolation and Higher
47 The serial format for tra A single c multiple c Infraredte fibre optics A single conductor
48 Serial communication caUsing silveUsing high Adjusting tUsing silver or gold c Using high speed clock sig
49 The decimal number systOctal decimal Decimal Binarycoded Binarycoded
50 29 input circuit will have total of256 512 1024 2048 512
51 BCD adder can be constr2bit 3bit 4bit 8bit 4bit
52 The output sum of two de Gray code Excess 3 c BCD Hexadecimal BCD
53 The addition of two deciBCD adderFUll adder Ripple carrCarry look ahead BCD adder
54 3 bit full adder contain 4 combinati8 combinati16 combinat 32 combination logic c8 combination logic circui
55 The simplified expressionC=xy+yz+xzC=x+y+z C=xyz C=xy+z C=xy+yz+xz
56 Complement of F' gives F' F FF FF' F
57 Decimal digit of BCD can1 input lin 2 input lin 3 input lin 4 input line 4 input line
58 The number of logic gateLogical netsystem netcircuit net Gate network Logical network
59 what are the minimum num 4NOT and 2NOT and 1NOT and 2 NOT and 3OR 2 NOT and 3OR
60 If segments of a to g are g=p
considered
1
'+p2, d=c+e
g=p'
as functions
1
+p'2, d=c+e
g=p'of1+p'
P 1 2,and
d=c+b
g=p
P21,+p
the
2,
d=c+e
which of theg=p
following
1
+p2, d=c+e
is correct?
61 The output Z of a2-bit co 8 10 6 16 6
62 A bulb in a staircase has two switches,
 Tag

Decoder

2 AND & 1OR

inverter
It behaves like a NOT gate
To control circuit output into the bus

Full adder have carry input capability

difference=0,borrow=0

e subtrahend are both changed orginal position

Half adder and full adder
In a parallel full adder, the first stage may be a half adder
Arithmetic or logic function
Both NAND and NOR

2 input XOR gate and 2 input AND gate only

Reduce propagation delay
Inverting the B inputs
It is fast than a ripple carry adder
genertaing and propagating carries
It is slow due to propagation time
Is cumulative for each stage and limits the speed at which arithmetic operations are performed
Variation of a carry-look ahed adder
Both propagation delay and capacitive load

to speed up the circuit

The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, followed by a 40 s pulse

Augend, addend
If all of the output are independent of the inputs

It is used to store the carry output of the full adder

The carry output of the lower order stage is connected to the carry input of the next higher order stage

2's complement

It is much faster
Mount directly
all the above mentioned
Total isolation and Higher current rating
A single conductor
Using high speed clock signal
Binarycoded

BCD adder
8 combination logic circuit
C=xy+yz+xz

4 input line
Logical network
2 NOT and 3OR
g=p1+p2, d=c+e
 Questio
n Correct
Questio Stateme Answer-
n no. nt Option 1 Option 2 Option 3 Option 4 Option 5 1 Tag
1 What is a mIt is a typ A multiplexIt takes on None of the mention A multiplexer is a device which convert
2 Which combi Data selectData distri Both Data sNone of the mention Data selector
3 It is possi Input Output Selection l All of the mentioned Inputs
4 multiplexinDecoding tGenerationGenerationAll of the mentioned Generation of selected path between m
5 What is theTo apply VcTo connectTo active t To active one half of To active the entire chip
6 One multiplSeveral SSI combination several ExnSeveral SSI logic gatesSeveral SSI logic gates or combinational
7 A digital mOne digitalMany digitMany decim None of the mention One digital information from several so
8 the selecti Data controSelected li Logic gatesBoth data controller aSelected lines
9 If the number of n selected
2m inputnlines is equal
Nonetoof
2^the
m
then
mention
it requires
m _____ select lines.
10 How many se 2 3 4 5 3
11 A basic mulSingle-poleDPST switcRotatry swiLinear stepper Rotatry switch
12 For the im 2 3 4 5 2
13 AND gate adecoder encoder full adder ripply carry adder decoder
14 a 2n-to- 1 -line
2n input
multiplexer
lines
2n-1toinput
isit constructed
lines
2n output
to it from
lines
2n-1 an
output
ton-to-2"
it linesdecoder
to it 2nby
input
adding
lines to it
15 A multiplexData selectData distri Both Data sNone of the mention Data selector
16 A combinatiEncoder decoder multiplexe demultiplexer multiplexer
17 Which of thEncoder decoder multiplexe demultiplexer multiplexer
18 A combinatiInput combinput combInput combpresent input and preInput combination at the time
19 Without any Some but no All functio All functio All functions of 4 vari All functions of 4 variables
20 The inputs/BidirectionUnidirectioeven paritybinary coded decimalBidirectional
21 if enable i enable disable saturation None of the mention disable
22 What is a dIt spreads It can be u It is an ap Both it can be used toBoth it can be used to route data and it
23
demux
24 The word dmany to onone to mandistributorone to many as well asone to many as well as distributor
25
exer is a device which converts many signals into one

on of selected path between multiple sources and a single destination

the entire chip
SI logic gates or combinational logic circuits
al information from several sources and transmits the selected one

H
H

mbination at the time

ons of 4 variables

an be used to route data and it is an application of multiplexer

any as well as distributor

 Questio
n Correct
Questio Stateme Answer-
n no. nt Option 1 Option 2 Option 3 Option 4 Option 5 1 Tag
1 example for serial synchronous input reading from CD or harddisk
2 example foreading fr writing to Keyboard co output from printer writing to flash memory using SDIP card
3 example forreading fr writing to Keyboard co output from printer Keyboard controller data in
4 example foreading fr writing to Keyboard co output from printer output from printer
5 example forPWM outpu filling a li Encoder inpstepper motor coil driPWM output for a DAC
6 example forPWM outpu filling a li Encoder inpstepper motor coil drifilling a liquid up to a fixed level
7 example forPWM outpu filling a li Encoder inpstepper motor coil driEncoder inputs for bit for angular positi
8 example forPWM outpu filling a li Encoder inpstepper motor coil dristepper motor coil driving output bits
9 from the foSerial Parallel Cross Both serial and paralleBoth serial and parallel
10 Synchronoumaster slave master-sla none master-slave
11 ........... HDLC UART USART DTR HDLC
12 Which of thSPI SDIO SCI All of these All of these
13 What is th High Level High and LoHigh Level High and Low Data LinHigh Level Data Link Control Protocol
14 which of thCAN I2C HDLC ISA CAN
15 which of thCAN I2C HDLC ISA I2C
16
 rom CD or harddisk
o flash memory using SDIP card
d controller data in

tput for a DAC

quid up to a fixed level
inputs for bit for angular position of a rotating shaft
motor coil driving output bits
al and parallel

el Data Link Control Protocol

 1 The memory A = 13 D = 16
2 The memory A = 31 D = 8
3 The memory A = 24 D = 32
4 The memory A = 18 D = 64
5 Give the n2^13
6 Give the 2^31
7 Give the 2^24
8 Give the 2^18
9 A 16K X 4 m256 AND gates, each with 7 inputs
10 A 16K X 4 mx = 46 y = 112
11 How many 83 chips
12 How many 18li address lines for memory and 15 address pins / chip
13 how many 3li lines and 3X8 decoder
14 A DRAM chi25 address lines and 2^25 words
15 Given the 80001 1011 1011 1
16 Generate 1101 110 011 001 010
17 A 12bit Ham0101 1010
18 A 12bit Ham1 1 0 0 0 1 1 0
19 A 12bit Ham1 1 1 1 0 1 0 0

20 The following is a truth table of a three-input, four-output combinational circuit. Obtain PAL programmi

A = yz' +
xz' + x'y'z
B= x'y' +
xy + yz
C= A + xyz
D= z + x'y
21 PLA circuit 6
22 PLA circuit 2
23 Following are specification of schotky TTL 74S00 quadraple two-input NAND gate, Calculate the fanout

24 Following are specification of schotky TTL 74S00 quadraple two-input NAND gate, Calculate the power d

25 Following are specification of schotky TTL 74S00 quadraple two-input NAND gate, Calculate the propaga
26 Following are specification of schotky TTL 74S00 quadraple two-input NAND gate, Calculate the noise m

27 The FET is Unipolar trBipolar tra Acts as botNone follows

28 The regionChannel Drain Source Gate
29 The ....... Gate Channel Drain Source
30 As the magn ConductivitConductiviConductiviConductivity first decreses then increases
31 The advantTransistor Inverter resistor both transistor and resistor
32 Determine the gate from the figure shown below

Fig1-inverter, Fig2-NAND, Fig3- NOR

33 In this inverter circuit transistor Q1 and Q2 act as

 Q1 as load Q1 as activBoth as actBoth as load resistor
34 In CMOS fa both n-ch n-channel aonly two n-only two p-channel can be fabricate in same s
35 In a inverteone p-channboth are nboth are pNone follows
36 The n-cha gate-to-sougate-to-sougate-to-sougate-to-source voltage is either positive or neg
37 The p-cha gate-to-sougate-to-sougate-to-sougate-to-source voltage is either positive or neg
38 The figure Inverter NAND AND NOR

39 The figure Inverter NAND AND NOR

40 The figure Inverter NAND AND NOR

41 The instantnmos(drainnmos(sourcnmos(gate,nmos(gate,drain,source)
42 The statemsupply1 P supply0 P supply0 P supply1 POR
43 The statemsupply0 G supply0 G supply1 G supply0 GRD
44 The switch level code for CMOS inverter for the figure

module inverter (Y, A); Input A; output y; supply1 PWR; suppl

45 The switch level code for CMOS NAND for the figure

module NAND2( Y, A, B); lnput A, B; output Y; supply1 PWR; s

cuit. Obtain PAL programming table for the circuit
gate, Calculate the fanout

Fanout=10mA

gate, Calculate the power dissipation

power dissipation=75mW

gate, Calculate the propagation delay

propagation delay=3ns
gate, Calculate the noise margin

Noise margin=0.3V

Unipolar trMos
Channel Mos
Gate Mos
ConductivitMos
Transistor Mos
Mos

Mos
Q1 as load Mos
both n-ch CMOS
one p-channCMOS
gate-to-souCMOS
gate-to-souCMOS
Inverter CMOS

NAND CMOS

NOR CMOS
 nmos(drain,source,gate)
supply1 P supply1 POR
supply0 GRD

utput y; supply1 PWR; supply0 GRD; pmos (Y, PWR, A); nmos(Y, GRD, A); endmodule

B; output Y; supply1 PWR; supply0 GRD; wire W1;pmos (Y, PWR, A);pmos (Y, PWR, B); nmos (Y, W1, A); nmos (W1 , GRD, B); endmodule
(W1 , GRD, B); endmodule
1 what is sysThe specifiThe behavio Functional Conversion of booleanThe specifiE
2 what is funThe specifiThe behavio Functional Conversion of booleanThe behavio E
3 what is logThe specifiThe behavio Functional Conversion of booleanFunctional E
4 what is cir The specifiThe behavio Functional Conversion of booleanConversionE
5 The circuit Logic desigcircuit des physical deFunctional design physical deM
6 The main pu To minimizeTo minimizeTo increaseBoth minimization of Both minimi M
7 what are thA set of bloPin locatio A netlist All of these All of thes M
8
1 The command shown below will produce what output?

fprintf('
The
value of
pi =
%4.2f',
pi) The valueThe valueThe valueinvalid syntax The value of pi = 3.14

What is
the value
in y2
when the
code
show
below
executes?
x1 = [ 5 3
1 7 9];
[y1 y2] =
2 min(x1); 3 5 1 7 3

After the
code
below
executes,
what
does the
variable
x1
contain?
aa =
linspace(0
,pi,10)
x1 =
cos(aa(10
))
3 -1 0 1 error not possible -1
y= y=
linspac linspac
4 Which statee(1,7,4) y = od y = 1:4for y=1:2:7 e(1,7,4)
 What is
the value
of JJ after
the
Matlab
code
below
executes?
JJ=0;
for
II=1:2:5
JJ=JJ+1
5 end 3 12 11 6 3

How
many
values
(terms)
will be in
the
variable
coef?
x = [1 3
5 7 9 11]
y = [15 17
16 15 16
17]
coef =
polyfit(x,y
6 ,2) 3 4 5 6 3
 What
value
does the
variable jj
contain
after the
Matlab
code
below
executes?
clear all
jj = 1
while jj
<= 2

my_list(jj)
= jj.^3
jj = jj + 1
7 end 3 2 4 6 3

Determin
e the
value of
a.
x=[01 2
34]
y=[02 0
-2 0 ]
a=
8 trapz(x,y) 0 2 1 -1 0
 What
value
does the
variable x
and q
contain
after the
Matlab
code
below
executes?
x = 7;
if x <= 3
q = 0;
elseif x >
10
q = 5;
else
q = 2.5;
9 end x=0;q=2.5 x=7;q=2.5 x=5;q=2.5 x=0;q=5 x=7;q=2.5

What
value
does the
variable q
contain
after the
Matlab
code
below
executes?
for q =
1:1:100
c=
q^0.5;
end
10 q = c + 5; q=15 q=5 operation nc q=15
 What
value
does the
variable q
contain
after the
Matlab
code
below
executes?
a=[135
];
q = a.*a; [3 11 [3 11
11 q = q + 2; 27] [1 9 25] 41 35 27]

After
execution
of the
following
code,
what will
the value
of z be?
x = 1;
y = 2;
while y <
4;
z(x) =
2 .* y;
x = x + 1;
y = y + 2;
12 end 4 [4 8] 1 2 4

S = 0; S=0 S = 0;
for for for for for
ii=1:1:13 ii=1:1:13 ii=1:1:13 ii=1:1:13 ii=1:1:13
S = S + 1; S(ii) = ii S(ii) = 13 S = S + ii S = S + 1;
13 Which set oend end end end end
 What
value
does the
variable q
contain
after the
Matlab
code
below
executes?
A=[135
];
B=[133
];
q=
14 dot(A,B); 25 [1 9 15] 5 [1 1 5/3] 25

What
value
does the
variable q
contain
after the
Matlab
code
below
executes?
A=[135
];
B=[246
];
q = diff(A)
15 ./ diff(B); [1 1] [1 1 1] [2 2] [-1 -1 -1] [1 1]
 What is
the final
value of
Q?
Q = 0;
A = 2;
B = 3;
if (A == B)
Q = 1;
elseif (A
<= B)
Q = 2;
elseif (A
>= B)
Q = 3;
else
Q = 4;
16 end 2 5 4 3 2

What
value
does the
variable q
contain
after the
Matlab
code
below
executes?
A=[135
];
B=[246
];
q=
17 diff(A); [2 2] 2 [1 1] [2 2 2] [2 2]
inline('
d./25.4'
18 Which inlini2m = i,'d'); i2m = ifunction i2m i2m
= = inline('d.*25.4','d
hat output?

ue of pi = 3.14
= inline('d.*25.4','d');
 1 The capcit (2^n)*m (2^m)*n (2^m)/n (2^n)/m (2^n)*m M
2 The number n 2^n n^2 2n n M
3 Assining adMemory ma Memory drMemory allmemory assignment Memory ma M
4 To increaseparallel series Any of the Memory cannot be inparallel M
5 To obtain four 1024X2 four 1024X2eight1024X2both four 1024X8 in sfour 1024X2 M
6 Time requirAccess timAccess rateAccess modRandom time Access timM
7 The accesssum of seekproduct of Difference None of these sum of seekM
8 What is accsum of seekReciprocal product of None of these Reciprocal M
9 Memory who ROM's RAM'S Both RAM PROM's ROM's M
10 The memory volatile m non volati Both volatiNone of these volatile m M
11 The memory volatile m non volati Both volatiNone of these non volati M
12 which requiDRAM SRAM EPROM PROM DRAM M
13 Package denDRAM SRAM EPROM PROM DRAM M
14 Reason forpackage depackage intpackage coall of these package deM
15 Which of thDRAMs areSRAMs areDRAMs areNone of these SRAMs areM
16 Semiconduc Bipolar MOS both bipol None of these both bipol E
17 For a DRAM0.5µS 5µS 1µS 1µS 0.5µS M
18 The refresh1/t 1/2t 2t t 1/2t M
19 The requiresingle por one addresEmpty/Fullall of these all of theseM
20 the procescycling block size deletion recovering cycling M
21 The number Block size cycling deletion formatting Block size M
22 The processerase adding inserting triggering erase M
23 The processProgram Erase formattingtriggering Program M
24 The capabilEnduranceProgram Erase Cycling EnduranceM
25 The capabilRetention EnduranceProgram Erase Retention M
26
 1 A semiconductor
10^20e-h
is irradiated
p10^10e-h with
p10^30e-h
light such
pData
thatinsufficent
carries a uniformly
Datagenerated
insufficentthroughout its volume.T
2 A long specis positvel is negativeacts as a d has an electricfield di acts as a dipole
3 If an intri decrease increase remain uncdecrease and increasedecrease and increase respectively
4 Under highthe mobilitthe mobilitthe velocit the velocity of chargethe velocity of charge carriers saturates
5 A small concentration
1000 of minority
2000 carriers
5000is injected
10000into a homogenous 5000
semiconductor crystal at one po
6 As the ferm1.39X10^63.3X10^6m6.65X10^60.24X10^6m/s 1.39X10^6m/s
7 electron mobility
1.77mm and 3.77mm
life-time in5.77mm
a semi conductor
9.77mmare at room temperature
1.77mm are respectively 0.36m^2/V
8 The conduct the mobiliteffictive d electronic surface state in the surface state in the semi conductor
9 The unit ofm^2V^-1s^Vm^2s^-1 Vm^-2s^-1m^2S^1V^-1 m^2V^-1s^-1
10 In an extri Increases wdecreases is indepen changes with effect ofdecreases with decrease in tempertaur
11 Assertion (A):
BothThe
A and
concentration
Both A andAmesured
is true buby
A isHall
false
effect
but doesnot
R is trueBoth
have Amuch
and Rif are
the true.
semiconductor
R is not correct
is home
12 The mobilitDiffusion veDiffusion vDrift veloc Drift velocity per unit Drift velocity per unit electric field
13 The free el 10^-4Ωm 10^-4Ωcm 1.6X10^-2Ωcm 1.6X10^-4Ωcm 10^-4Ωcm
14 The intrini 10^9cm^-310^19cm^-10^6cm^-310^4cm^-3 10^9cm^-3
15 Assertion (A):
BothThe
A and
concentration
Both A andAmesured
is true buby
A isHall
false
effect
but doesnot
R is trueBoth
have Amuch
and Rif are
the true.
semiconductor
R is correctisexpla
hom
16 Assertion (A):
BothThe
A and
concentration
Both A andAmesured
is true buby
A isHall
false
effect
but doesnot
R is trueBoth
have Amuch
and Rif are
the true.
semiconductor
R is not correct
is home
17 The elctronFor all semFor direct For non-deFor degenerate semicFor non-degenerate semiconductor und
18 An intrinsi The mobilitThe mobilitThe hole deThe mobility of holes The mobility of both electrons and hol
19 Assuming th 40cm^2/s 4cm^2/s 4000cm^2/400cm^2/s 40cm^2/s
20 An intrinsi 1/3eV 3eV 9eV 9/2eV 1/3eV
Which of the following device transmits power by friction ?

(A) Spur gears

 and increase respectively
ity of charge carriers saturates

tate in the semi conductor

s with decrease in tempertaure

nd R are true. R is not correct explanation of A
city per unit electric field

nd R are true. R is correct explanation of A

nd R are true. R is not correct explanation of A
degenerate semiconductor under thermal equilibrium condition
ility of both electrons and holes decreases