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A71d PDF
A71d PDF
Abstract
We have designed, fabricated and tested the second-generation (2G) design
of a high-resolution, dynamically programmable analog-to-digital converter
(ADC) for radar and communications applications. The ADC chip uses the
phase modulation–demodulation architecture and on-chip digital filtering.
The 2G ADC design has been substantially enhanced. Both ADC front-end
modulator and demodulator, as well as decimation digital filter, have been
redesigned for operation at 20 GHz. Test results of this 6000 Josephson
junction 2G ADC chip at clock frequencies up to 19.6 GHz are described.
These test results were compared to the results of ADC functional
simulation using MATLAB.
Figure 1. A 15-bit 2G ADC chip with a two-channel synchronizer. The inset shows the ADC front-end (modulator). The 6000-junction
1 cm2 chip was fabricated using HYPRES’ standard 1 kA cm−2 process with a 3 µm minimum junction size.
3. Test results Figure 4 shows the dynamic range of the 2G ADC chip
operating at an 18.6 GHz clock frequency and a comparison
We tested the first sample of the 2G ADC using our ADC with its operation at 11.2 GHz. As expected, the increased
test set-up described in detail in [3]. The new ADC chip was clock frequency produced a better performance both in terms
able to operate up to 19.6 GHz clock frequency, which is very of signal-to-noise ratio and distortion (SINAD) and spur-free
close to the target 20 GHz. The ADC output data was acquired dynamic range (SFDR). However, the peak SINAD and SFDR
to a computer running our custom ‘ADCtools’ ADC analysis performances of the 2G ADC chip still did not exceed the
software. We performed an FFT analysis with ‘Blackman’ previously demonstrated performance of the 1G ADC design
windowing on 8192-point and 16 384-point acquisitions. reported in [3]. In order to compare both ADC designs, we
For evaluation of the ADC chip at Nyquist sampling rate conducted tests of both ADCs at the same conditions. Figure 5
(at ×2 input tone), we performed additional off-chip shows comparative performance of these two ADC chips
low-pass filtering in software, if necessary, since ADC operating at 11.2 GHz and 10 MHz input tone. Both chips
chip has the maximum decimation ratio not exceeding demonstrated the expected linear growth of dynamic range
1:128. with amplitude over several orders of magnitude. The 2G
Figure 2 shows typical measured FFT spectra for 10 MHz ADC chip was designed to be more sensitive, and indeed,
input sine wave sampled at an 18.6 GHz clock frequency. Up it exhibited a greater SINAD and SFDR than the 1G ADC
to this clock frequency, the ADC chip demonstrated excellent chip for a given voltage input in the ranges they overlap.
stability—about 90% of all 16K-point FFT acquisitions were But the lower slew rate limited the maximum dynamic range
good, i.e. they did not contain any glitches (digital errors). available. This suggested that some excess noise affected the
This is substantially better than it was with the 1G ADC performance of the 2G ADC chip.
chip even at 11.2 GHz. The stability was somewhat lower
at the highest operational clock frequency of 19.6 GHz.
Figure 3 shows the results of the 19.6 GHz operation with 4. Simulation and comparison with measurements
a 40 kHz unfiltered input tone. While the reconstructed
40 kHz signal (the inset to figure 3) was visually fine, FFT In order to understand and correct this problem, we carried out
analysis showed some excessive noise content. Therefore, MATLAB functional simulations of the ADCs in addition to
we concluded that this ADC chip has its peak performance at the experimental measurements. Figure 6 shows a MATLAB
18.6 GHz. functional model of the ADC architecture that we used in our
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High-resolution ADC operation up to 19.6 GHz clock frequency
145 MS/s
SINAD = 63 dB
36 MS/s
SINAD = 68.5 dB
-25dBc
ENOB = 11.1
SFDR = -86.4 dBc
(190 mV rms
10 MHz sinewave)
-50dBc
-100dBc -75dBc
MATLAB program. Details of this ADC architecture can be line (with a slope of one) on this log–log plot corresponds to a
found elsewhere [1, 3]. noise floor which is independent of amplitude from very small
One way to model all sources of excess noise is to add a to the slew rate limit, assuring that the ADC is ideally linear
single random (white) noise source to the input signal. This and does not generate harmonics that impact the frequency
was done in the MATLAB program simply by adding one sine spectrum.
wave component (of fixed amplitude, but with random phase) We also used the slew rate limit, above which the
for each output frequency of the digital Fourier transform. In performance of the ADC falls sharply, as a calibration point.
this way, we could compare the theoretical model directly with It assures the exact conversion between input signal amplitude
the measurements, although the results are slightly different presented in fluxons 0 in simulations and the experimentally
each time due to the random number generator. As one can measured signal amplitude in millivolts. For our ADC
see from the figures 7 and 8, the agreement is excellent for architecture, the slew rate limit corresponds to an amplitude of
both ADCs for the SINAD and SFDR. the signal derivative of one-half flux quantum per clock period,
There is only one adjustable parameter for each chip, or a signal amplitude Amax = (0 /2)fclk /2πf , where f is the
which is the rms amplitude of the noise. The fit to a straight signal frequency. For a typical clock frequency of 11.2 GHz
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O A Mukhanov et al
5000
-125dBc -100dBc -75dBc -50dBc -25dBc
0
-5000
-15000 -10000
0 1000 2000 3000 4000 5000 6000 7000 8000
Figure 4. Measured SINAD and SFDR for a 2G ADC chip running Figure 5. Measured SINAD and SFDR for a 1G and a 2G ADC
at 11.2 GHz and 18.6 GHz clock for a 10 MHz input sine wave. The chip running at 175 MS/s (11.2 GHz clock with a 1:64 output
selected 1:128 decimation ratio in the digital filter provides decimation) and a 10 MHz input sine wave.
87.5 MS/s and 145 MS/s output sample rate, respectively.
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High-resolution ADC operation up to 19.6 GHz clock frequency
Level
m-level
Crossing Decimator
Encoder
Detector
output
d NDRO DRO
x(t) + dt + Accumulator + + Accumulator
input T/m
T
R(t) = t/2T Amplitude
T/m
Quantizer fclk=1/T –m fclk/N
T/m
90
80
70
60
SINAD and SFDR (dB)
50
40
30
10
Input
Input flux
flux noise
noise added
added to simulation:22 µΦ
to simulation: µΦ00//rt-Hz
rt-
rt-Hz
0
1 10 100 1000 10000
r.m.s. amplitude (mV)
Figure 7. Comparison of measured and simulated data for the 1G ADC chip running at 11.2 √ GHz clock, 175 MS/s output sampling rate
(1:64 decimation), and 10 MHz input sine wave. In order to achieve a close fit, a 2 µ0 / Hz input flux noise was added.
80
70 measured data
SINAD and SFDR (dB)
60
50
40
30
simulated data
20
10
Input
Input flux
flux noise
noise added
added to
to simulation: µΦ00//rt-Hz
simulation: 10µΦ
10
10µΦ rt-
rt-Hz
0
1 10 100 1000
r.m.s. amplitude (mV)
Figure 8. Comparison of measured and simulated data for the 2G ADC chip running at 11.2 √ GHz clock, 175 MS/s output sampling rate
(1:64 decimation), and 10 MHz input sine wave. In order to achieve a close fit, a 10 µ0 / Hz input flux noise was added.
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O A Mukhanov et al
√ √
Nex = 1.8 µ0 / (Hz) for the 1G and 7.9 µ0 / (Hz) for the Acknowledgments
2G chip. Again, this is generally consistent with the MATLAB
simulations. This work was sponsored in part by the Office of Naval
Research under contract no N00014-99-C-0089. The authors
thank the HYPRES fabrication team for fabricating the ADC
5. Conclusions
chips, Sergey Rylov for valuable discussions and Wenquan Li
The first sample of a 6000-junction 2G ADC chip showed for help in testing.
correct operation up to 19.6 GHz: to our knowledge, this is the
world’s fastest operation of the most complex superconductive References
digital chip to date. We have completed the measurement and
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evaluation of the first 2G ADC chip and found its excellent high-resolution A/D converter based on phase modulation
stability at high-speed operation. and multichannel timing arbitration IEEE Trans. Appl.
We also found that the 2G ADC chip exhibited some Supercond. 5 2260
excessive noise limiting its performance. For better [2] Mukhanov O A, Semenov V K, Brock D K, Kirichenko A F,
understanding, we performed MATLAB simulation of this Li W, Rylov S V, Vogt J M, Filippov T V and Polyakov Y A
1999 Progress in the development of a superconductive
ADC and compared it with the experimental data. The high-resolution ADC Extended Abstracts of ISEC’99
excellent fit was achieved assuming the presence of an (Berkeley, CA, 1999) pp 13–16
excess noise about five times higher than that of the 1G [3] Mukhanov O A, Semenov V K, Li W, Filippov T V, Gupta D,
ADC design. We believe that this noise is associated Kadin A M, Brock D K, Kirichenko A F, Polyakov Yu A
with the non-optimal input circuitry and/or fabrication. and Vernik I V 2001 A superconductor high-resolution
ADC IEEE Trans. Appl. Supercond. 11 601
Further testing of other ADC samples and comparison with [4] Filippov T V, Pflyuk S, Semenov V K and Wikborg E 2001
the MATLAB model should enable the correction of this Encoders and decimation filters for superconductor
problem. oversampling ADCs IEEE Trans. Appl. Supercond. 11 545
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