Low Power 4-Bit Arithmetic Logic Unit

Using Full-Swing GDI Technique

Abstract—Power dissipation and area of the circuit are the main issues in the electronics
industry, this paper provides a design of 4-Bit Arithmetic Logic Unit (ALU) using Full-Swing
GDI Technique, which considered an effective method for low power digital design while
reducing the area of the circuit compared to other logic styles. The proposed ALU design
consists of 2x1 Multiplexer, 4x1 Multiplexer and low power Full Adder cell to realize the
arithmetic and logic operations. The simulation carried out using Cadence Virtuoso using 65nm
TSMC process. The results show that the proposed design consume less power using less
number of transistors, while achieving full swing operation compared to previous work.
 Chapter 1
Introduction

In our daily life, we use a lot of portable electronic devices; these devices basically are low
power high speed VLSI circuits works simultaneously. One of these circuits is the Arithmetic
logic unit (ALU) which considered an essential component in many applications such as
Microprocessor, digital signal processing, image processing, etc.
Addition considered essential part of the arithmetic unit and almost all other arithmetic
operations includes addition therefore any improvement in the adder cell is reflected as a major
improvement in the ALU. In this paper a 4-Bit ALU is designed using a low power adder cell
realized by the Full- Swing GDI technique and compared to previous work in terms of power
dissipation and transistor count. Simulation environment is cadence virtuoso using TSMC 65nm
process.

ARITHMETIC LOGIC UNIT

Arithmetic Unit:
Employing fast and efficient adders in arithmetic logic unit will aid in the design of low power
high performance system. Other operations such as subtraction and multiplication also employ
addition in their operations, and their internal hardware is almost similar though not identical to
addition hardware. Various adder families have been proposed in the past to trade-off power,
area and speed for possible use in ALUs. The performance criticality of the ALU demands a
dynamic adder implementation. Dynamic logic family of adders is the most efficient in terms of
transistor-count, speed and power dissipation. This work covers the design of 3 bit adder using
Complementary logic. This same Adder unit is used for the implementation of subtractor unit.
This reuses the current hardware we made for adder and saves area.
 Fig. Internal Architecture of ALU

GDI (Gate Diffusion Input)

A new technique of low power digital circuit design is described in this .This
technique allows reducing power consumption, delay and area of digital circuits, while
maintaining low complexity of logic design. Performance comparison with traditional CMOS
and various PTL design techniques is presented, with respect to the layout area, number of
devices, delay and power dissipation, showing advantages and drawbacks of GDI as compared to
other methods. A variety of logic gates have been implemented in 0.35 / spl mu/m technology to
compare the GDI technique with CMOS and PTL. A prototype test chip of 8-bit CLA adder has
been fabricated based on GDI and CMOS cell libraries, showing up to 45% reduction in power-
delay product in GDI. Properties of implemented circuits are discussed, simulation results are
reported and measurements of a test chip are presented.
GATE DIFFUSION TECHNIQUE
Gate diffusion input is a new Technique of reducing power dissipation, area and delay and
achieving high speed and high performance. The combinational circuits also implemented by
using this technique. So that, the total circuit area reduction and power reduction is achieved.
GDI Technique is a two transistor designing technique, is a two transistor technique, by this the
complex logic and arithmetic functions can be determined

Figure: Basic GDI Cell

GDI Cell is constructed by using three inputs i.e, G (Gate), A (PMOS device source or drain), B
(NMOS device source or drain). Where PMOS is not connected to VDD and NMOS is not
connected to VSS.
Figure: GDI Circuit Representation of 2-bit multiplexer

Figure: Block Representation of 2-bit multiplexer

Figure shows the 2 bit multiplexer, where the output is determined by the select lines. Suppose,
if select line is zero then I0 input will be getting as output across output. If select line is one, then
I1 input will be getting as output across the output terminal.

Table: 2-bit Multiplexer

Below Figure shows the Full adder circuit constructed using GDI Technique and Table 2 shows
the Full adder truth table.
 Figure: Boolean Representation of Full Adder Figure

Figure: GDI Circuit Representation of Full Adder

Table: Full Adder
 Chapter 2
Literature Survey

[1] A. Morgenshtein, A. Fish, and I. Wagner, “Gate-diffusion input (GDI): a

power-efficient method for digital combinatorial circuits,” IEEE Transactions
on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst., vol.
10, no. 5, pp. 566–581, 2002

WHIS rapid development of portable digital applications, the demand for increasing
speed, compact implementation, and low power dissipation triggers numerous research efforts.
The wish to improve the performance of logic circuits, once based on traditional CMOS
technology, resulted in the development of many logic design techniques during the last two
decades. One form of logic that is popular in low-power digital circuits is pass-transistor logic
(PTL). Formal methods for deriving pass-transistor logic have been presented for nMOS. They
are based on the model, where a set of control signals is applied to the gates of nMOS transistors.
Another set of data signals are applied to the sources of the n-transistors. Many PTL circuit
implementations have been proposed in the literature. Some of the main advantages of PTL over
standard CMOS design are

1) High speed, due to the small node capacitances;

2) Low power dissipation, as a result of the reduced number of transistors; and

3) Lower interconnection effects, due to a small area. However, most of the PTL
implementations have two basic problems. First, the threshold drop across the single-channel
pass transistors results in reduced current drive and hence slower operation at reduced supply
voltages; this is particularly important for low-power design since it is desirable to operate at the
lowest possible voltage level. Second, since the “high” input voltage level at the regenerative
inverters is not, the PMOS device in the inverter is not fully turned off, and hence direct-path
static power dissipation could be significant. There are many sorts of PTL techniques that intend
to solve the problems mentioned above.

1) Transmission gate CMOS (TG) uses transmission gate logic to realize complex logic
functions using a small number of complementary transistors. It solves the problem of low logic
level swing by using pMOS as well as nMOS.

2) Complementary pass-transistor logic (CPL) features complementary inputs/outputs using

nMOS pass-transistor logic with CMOS output inverters. CPL’s most important feature is the
small stack height and the internal node low swing, which contribute to lowering the power
consumption. The CPL suffers from static power consumption due to the low swing at the gates
of the output inverters. To lower the power consumption of CPL circuits, LCPL and SRPL
circuit styles are used. Those styles contain pMOS restoration transistors or cross-coupled
inverters (respectively).

3) Double pass-transistor logic (DPL) uses complementary transistors to keep full swing
operation and reduce the dc power consumption. This eliminates the need for restoration
circuitry. One disadvantage of DPL is the large area used due to the presence of pMOS
transistors. An additional problem of existing PTL is top-down logic design complexity, which
prevents the pass transistors from capturing a major role in real logic LSIs. One of the main
reasons for this is that no simple and universal cell library is available for PTL-based design.

[2] A. Morgenshtein, I. Shwartz, and A. Fish, “Gate Diffusion Input (GDI) logic in
standard CMOS Nanoscale process,” 2010 IEEE 26th Convention of Electrical and
Electronics Engineers in Israel, 2010.

Among the forceful investigation in the field of low power, high speed digital applications due
to the growing demand of systems like phones, laptop, palmtop computers, cellular phones,
wireless modems and portable multimedia applications etc has directed the VLSI technology to
scale down to nano-regimes, allowing additional functionality to be incorporated on a single
chip. The designer’s novel purpose in the field of multifaceted digital circuit design is
minimization of power consumption. These investigations are responsible for special design
techniques for digital circuits distant from conventional CMOS design style.

A large body of investigate has been performed to expand and advance conventional
Complementary Metal Oxide Semiconductor (CMOS) techniques for the fabrication of ULTRA
low power integrated circuits (ICs). The purpose of this study is to expand a faster, lower power,
and reduced area substitute to standard CMOS logic circuits. Mod-GDI technique is one such
new technique for minimization of power consumption in the digital circuit design field.

MODIFIED GATE DIFFUSION INPUT LOGIC STYLE (Mod-GDI)

Power dissipation becomes most important restriction in high performance applications.

Optimizations for basic logic gates are fundamental constraint in order to get better the
performance of [6] a variety of low power and high performance devices. Morgenshtein et al.
investigated a high-speed and multipurpose logic style for low power electronics design, known
as Gate Diffusion Input (GDI),[7] with reduced area and power necessities, and proficient of
implementing a broad variety of logic functions. Basic GDI logic cell, which is used for
implementing verity of logic functions and circuits at low power and high speed design where G,
P and N are three inputs and output is taken from D terminal. Represents the logic functions
which can be implemented with the help of this basic GDI cell. But this basic Gate Diffusion
Input (GDI) logic style suffers from some practical limitations like swing degradation,
fabrication complexity in standard CMOS process and bulk connections. These limitations can
be overcome by modified gate diffusion input (Mod-GDI) logic style.

[3] A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky, and A. Fish, "Fullswing gate

diffusion input logic—Case-study of low-power CLA adder design," Integration, the VLSI
Journal, vol. 47, no. 1, pp. 62–70, Jan. 2014.

Power consumption and area reduction of logic and memory have become primary focuses of
attention in VLSI digital design. Power is the limiting factor in both high performance systems
and portable applications. Die area directly affects the device size and cost. Since the
introduction of the standard CMOS Logic in early 80s, many design solutions have been
proposed to improve power dissipation, area and performance of digital VLSI chips. Gate
Diffusion Input (GDI) design methodology was introduced as a promising alternative to Static
CMOS Logic.

Originally proposed for fabrication in Silicon on Insulator (SOI) and twin-well CMOS
processes, GDI methodology allowed implementation of a wide range of complex logic
functions using only two transistors. It was shown, that area and dynamic power of GDI
combinatorial and sequential logic were significantly reduced, as compared to standard CMOS
implementations. Similarly to existing alternatives to CMOS, such as Pass Transistor Logic
(PTL), the GDI gates presented reduced voltage swing at their outputs due to threshold drops.
These drops usually cause degradation in performance and increased short circuit power.
However, since the GDI circuits were implemented with much less transistors, a significant
power overall power reduction was observed, while maintaining minimal performance penalty
Recently, it was shown that any GDI circuit can be implemented in a standard CMOS process.
The efficiency of the GDI method for both combinatorial and sequential logic was shown by
many groups. Various combinatorial circuits, such as adders, multipliers, comparators, and
counters, were implemented in processes from 0.8 mm down to 65 nm. GDI Flip-Flops were also
presented, showing improvements in both area and power, compared to existing Flip Flop styles.

[4] M. Shoba, R. Nakkeeran, "GDI based full adders for energy efficient arithmetic
applications", Engineering Science and Technology, an International Journal, vol. 19, no.
1, pp. 485–496, Mar. 2016.

Power delay product or energy consumption per operation has been introduced to accomplish
optimal design tradeoffs. The performance of digital circuits can be optimized by proper
selection of logic styles. Gate Diffusion Input (GDI) is a lowest power design technique which
offers improved logic swing and less static power dissipation. This method is suitable for design
of fast, low-power circuits, using a reduced number of transistors. In this paper, an efficient
methodology for digital circuit such as AND, OR, and XOR gates with full swing is
implemented. After that, three full adders are proposed based on the full swing gates in a
standard 45 nm technology. Methodology for digital circuit such as AND, OR, and XOR gates
with full swing is implemented. After that, three full adders are proposed based on the full swing
gates in a standard 45 nm technology.

[5] Chandra Srinivasan, “Arithmetic Logic Unit (ALU) Design Using

Reconfigurable CMOS Logic,” M.S. Thesis, Dept. of Electr. & Compute. Eng.,
Louisiana State Univ., Baton Rouge, LA, USA 2003.

Advancement in VLSI technology has allowed following Moore’s law for doubling component
density on a silicon chip after every three years. Though MOS transistors have been scaled
down, increased interconnections have limited circuit density on a chip. Furthermore, the size of
transistor is limited by hot-carrier phenomena and increase in electric field that lead to
degradation of device performance and device lifetime. It has become essential to look into other
methods of adding more functionality to a MOS transistor, such as, the multiple-input floating
gate MOS transistor structure. An enhancement in the basic function of a transistor has, thus,
allowed for designs to be implemented using fewer transistors and reduced interconnections. In
published literature, many integrated circuits have been reported which are using multi-input
floating gate MOSFETs in standard CMOS process.

The arithmetic logic unit (ALU) is the core of a CPU in a computer. The adder cell is the
elementary unit of an ALU. The constraints the adder has to satisfy are area, power and speed
requirements. Some of the conventional types of adders are ripple-carry adder, carry-look ahead
adder, carry-skip adder and Manchester carry chain adder.

[6] S. Usha, M. Rajendiran, A. Kavitha, “Low Power Area Efficient ALU with Low Power
Full Adder” IEEE International Conference on Computing for Sustainable Global
Development (INDIACom), pp. 1500- 1505, 2016
In the era of growing technology and scaling of devices up to nanometer regime, the arithmetic
logic circuits are to be designed with compact size, less power and propagation delay. Arithmetic
operations are indispensable and basic functions for any high speed low power application digital
signal processing, microprocessors, image processing etc. Addition is most important part of the
arithmetic unit rather approximately all other arithmetic operation includes addition. Thus, the
primary issue in the design of any arithmetic logic unit is to have low power high performance
adder cell. There are various topologies and Methodologies proposed to design full adder cell
efficiently
 Chapter 3
Existing system

Logic Gates

Logic gates are the basic building blocks of any digital system. It is an electronic circuit having
one or more than one input and only one output. The relationship between the input and the
output is based on certain logic. Based on this, logic gates are named as AND gate, OR gate,
NOT gate etc.

AND Gate
A circuit which performs an AND operation is shown in figure. It has n input (n >= 2) and one
output.

Logic diagram

Truth Table
OR Gate
A circuit which performs an OR operation is shown in figure. It has n input (n >= 2) and one
output.

Logic diagram

Truth Table

NOT Gate
NOT gate is also known as Inverter. It has one input A and one output Y.

Logic diagram
Truth Table

Half adder:
An adder is a digital circuit that performs addition of numbers. The half adder adds two
binary digits called as augends and addend and produces two outputs as sum and carry; XOR is
applied to both inputs to produce sum and AND gate is applied to both inputs to produce carry.

Truth table:
Logical Expression

Sum = A XOR B
Carry = A AND B

Implementation

Full Adder:
Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs
are A and B and the third input is an input carry as C-IN. The output carry is designated as C-
OUT and the normal output is designated as S which is SUM.
Full adder logic is designed in such a manner that can take eight inputs together to create a byte-
wide adder and cascade the carry bit from one adder to another.
Logical Expression for SUM:
= A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN
= C-IN (A’ B’ + A B) + C-IN’ (A’ B + A B’)
= C-IN XOR (A XOR B)
= (1,2,4,7)

Another form in which C-OUT can be implemented:

= A B + A C-IN + B C-IN (A + A’)
= A B C-IN + A B + A C-IN + A’ B C-IN
= A B (1 +C-IN) + A C-IN + A’ B C-IN
= A B + A C-IN + A’ B C-IN
= A B + A C-IN (B + B’) + A’ B C-IN
= A B C-IN + A B + A B’ C-IN + A’ B C-IN
= A B (C-IN + 1) + A B’ C-IN + A’ B C-IN
= A B + A B’ C-IN + A’ B C-IN
= AB + C-IN (A’ B + A B’)
Therefore COUT = AB + C-IN (A EX – OR B)
Implementation of Full Adder using Half Adders
2 Half Adders and a OR gate is required to implement a Full Adder. With this logic circuit, two
bits can be added together, taking a carry from the next lower order of magnitude, and sending a
carry to the next higher order of magnitude.

Multiplexer

Multiplexing is the property of combining one or more signals and transmitting on a single
channel .This is achieved by the device multiplexer. A multiplexer is the most frequently used
combinational circuits and important building block in many in digital systems.

What is a Multiplexer?

The multiplexer or MUX is a digital switch, also called as data selector. It is a combinational
circuit with more than one input line, one output line and more than one select line. It allows the
binary information from several input lines or sources and depending on the set of select lines ,
particular input line , is routed onto a single output line.

The basic idea of multiplexing is shown in figure below in which data from several sources
are routed to the single output line when the enable switch is ON. That is how the multiplexers
are also called as ‘many to one’ combinational circuits.
The below figure shows the block diagram of a multiplexer consisting of n input lines, m
selection lines and one output line. If there are m selection lines, then the number of possible
input lines is 2m. Alternatively we can say that if the number of input lines is equal to 2m, then
m selection lines are required to select one of n (consider 2m = n) input lines.

This type of multiplexer is referred to as 2n × 1 multiplexer or 2n -to-1 multiplexer. For example,

if one of the 4 input lines has to be selected, then two select lines are required. Similarly, to
select one of 8 input lines, three select lines are required. Generally the number of data inputs to
a multiplexer is a power of two such as 2, 4, 8, 16, etc. Some of the mostly used multiplexers
include 2-to-1, 4-to-1, 8-to-1 and 16-to-1 multiplexers.

2-to-1 Multiplexer

A 2-to-1 multiplexer consists of two inputs D0 and D1, one select input S and one output Y.
Depends on the select signal, the output is connected to either of the inputs. Since there are two
input signals only two ways are possible to connect the inputs to the outputs, so one select is
needed to do these operations. If the select line is low, then the output will be switched to D0
input, whereas if select line is high, then the output will be switched to D1 input. The figure
below shows the block diagram of a 2-to-1 multiplexer which connects two 1-bit inputs to a
common destination.

The truth table of the 2-to-1 multiplexer is shown below. Depending on the selector switching
the inputs are produced at outputs , i.e., D0 , D1 and are switched to the output for S=0 and S=1
respectively . Thus, the Boolean expression for the output becomes D0 when S=0 and output is
D1 when S=1.

Truth table:
From the above output expression, the logic circuit of 2-to-1 multiplexer can be implemented
using logic gates as shown in figure. It consists of two AND gates, one NOT gate and one OR
gate. When the select line, S=0, the output of the upper AND gate is zero, but the lower AND
gate is D0. Thus, the output generated by the OR gate is equal to D0. Similarly, when S=1, the
output of the lower AND gate is zero, but the output of upper AND gate is D1. Therefore, the
output of the OR gate is D1. Thus, the above given Boolean expression is satisfied by this circuit.

4:1 Multiplexer:
Truth table :

Circuit diagram :
ALU:

An arithmetic logic unit is a combinational digital electronic circuit that performs arithmetic and
bitwise operations on integer binary numbers. This is in contrast to a floating-point unit, which
operates on floating point numbers.
 Chapter 4
Proposed Method
GDI Technique was first proposed by Arkadiy Morgenshtein, Idan Shwartz and Alexander Fish
this technique allows implementation of various complex logic functions using only two
transistors. The original GDI was based on using a simple cell, as shown in Fig.

Fig. GDI cell (a) originally proposed. (b) Standard CMOS compatible

However, it was proposed for fabrication in twin-well CMOS or silicon on insulator (SOI)
processes, it allowed improvement in power consumption, delay and area of digital circuits
compared to CMOS and PTL techniques. The drawback in GDI cell was it suffered from reduced
voltage swing due to threshold drops, which leads to performance degradation and increasing
static power dissipation. To improve the output of the GDI cells Swing restoration circuits
utilized. Morgenshtein et al.Proposed the Modified-GDI approach, shown in Fig (b) where the
substrate terminals of NMOS and PMOS transistors connected permanently to GND and VDD,
respectively. This modification enables fabrication of GDI cell in standard CMOS processes
which is cost efficient compared to twin well and (SOI) processes.
 In Full-Swing GDI cells proposed as an alternative for swing restoration buffers
in this technique, swing restoration transistor utilized to improve the output swing of F1
and F2 gates (universal gates used to realize any logical expression) through this
technique full swing operation can be achieved using additional transistors but when
compared to CMOS realization it uses less transistors which leads to reduce the area,
improve the power and delay of the circuits.

ARITHMETIC LOGIC UNIT

In this the Full-Swing GDI technique is used to realize the circuits required to design the
ALU as follows:
A. 2x1 Multiplexer
A multiplexer is a digital switch chooses the output from several inputs based on a select
signal, shown in Fig. 2 a 2x1 multiplexer consists of 6 transistors.

Fig. full swing GDI 2:1 multiplexer

B. 4x1 Multiplexer
Using the previously discussed 2x1 multiplexer a 4x1 multiplexer realized as shown in Fig.
consists only of 16 transistors.

Fig. full swing GDI 4:1 multiplexer

C. Full Adder

A full adder is a combinational circuit that performs the arithmetic sum of three input
bits. It consists of three inputs and two outputs. The adder cell used in this design realized using
full-swing AND, OR, and XOR gates. This design was chosen among 3 designs to maintain low
power operation, it has the lowest delay among the three designs, and with some modifications it
performs the logic operations as well, these modifications will save large area of the ALU
design.
 Fig. full-swing full adder cell

D. Design of Arithmetic Logic Unit

An ALU is a key component in the Central Processing Unit (CPU) of any computer; even
the simplest microprocessors contain one. It performs arithmetic operations such as addition,
subtraction, increment, decrement and logic operations such as AND, OR, XOR and XNOR. The
proposed design of the 4-Bit ALU consists of 4 stages, each stage is an 1-Bit ALU realized using
the previously discussed circuits as follows: Each 1-Bit ALU stage consists of two 2x1
multiplexers, two 4x1 multiplexers and one full adder cell, this design requires 48 transistors as
depicted in Fig. Any desired operation can be performed based on the selection line S0, S1, S2
code; Table II summarizes the truth table of the proposed ALU.
The 4x1 multiplexer at the input responsible for the B input based on the values of S0 and S1
selection lines it selects from logic 1, B, And logic 0 to perform the Decrement, Addition,
Subtraction and the Increment operations respectively, S2 chooses between the arithmetic and
the logic operations.

Fig.5.Schematic of 1 bit ALU Stage

To realize the 4-Bit ALU four stages were used as shown in Fig. While the carry input of ALU0
connected to selection line S1 to obtain logic 1 which needed for subtraction and increment
operations, however the other values don’t affect the results of the logic operations.
Fig. proposed 4-bit ALU Design
 CHAPTER 5
XILINX AND VERILOG HDL
HISTORY OF VERILOG

Verilog was once began in the 365 days 1984 by the use of Gateway Design
Automation Inc as a proprietary hardware modeling language. It can be rumored
that the usual language used to be designed via utilizing taking elements from
essentially the most preferred HDL language of the time, referred to as HiLo, as
well as from typical computer languages similar to C. At that time, Verilog used to
be no longer standardized and the language modified itself in almost all the
revisions that got here out inside of 1984 to 1990.

Verilog simulator first utilized in 1985 and increased appreciably via 1987.
The implementation of Verilog simulator supplied via Gateway. The first foremost
extension of Verilog is Verilog-XL, which delivered a couple of aspects and
implemented the notorious "XL algorithm" which is an awfully efficient system for
doing gate-degree simulation.

Later 1990, Cadence Design system, whose major product on the moment
integrated skinny film procedure simulator, decided to accumulate Gateway
Automation approach, together with other Gateway merchandise., Cadence now
emerge because the owner of the Verilog language, and persevered to market
Verilog as each a language and a simulator. Whilst, Synopsys was as soon as
promoting the top-down design methodology, utilizing Verilog. This was as soon
as a powerful blend.
In 1990, Cadence organized the Open Verilog global (OVI), and in 1991
gave it the documentation for the Verilog Hardware Description Language. This
was once the occasion which "opened" the language.

BASIC CONCEPTS
Hardware Description Language
Two matters distinguish an HDL from a linear language like “C”:
Concurrency:
• The capacity to do a number of matters simultaneously i.E. One of kind code-
blocks can run at the same time.
Timing:
• Capacity to symbolize the passing of time and sequence routine accordingly

VERILOG Introduction

• Verilog HDL is a Hardware Description Language (HDL).

• A Hardware Description Language is a language used to describe a digital
procedure; one may describe a digital system at a few levels.
• An HDL could describe the design of the wires, resistors and transistors on an
constructed-in Circuit (IC) chip, i.e., the swap level.
• it could describe the logical gates and flip flops in a digital system, i.e., the gate
level.
• an first-rate greater measure describes the registers and the transfers of vectors of
knowledge between registers. This is called the Register swap degree (RTL).
• Verilog helps all of those stages.
• A strong operate of the Verilog HDL is that you need to use the equal language
for describing, trying out and debugging your procedure.

VERILOG Features

• Powerful history:
Supported through utilizing OVI, and standardized in 1995 as IEEE STD 1364
• Industrial help: Speedy simulation and amazing synthesis (eighty five% were
used in ASIC foundries via EE events)
• Universal: makes it possible for entire approach in a single design surroundings
(together with evaluation and verification)
• Extensibility: Verilog PLI that makes it viable for for extension of Verilog
capabilities
Design Flow
The typical design flow is shown in figure,

Design Specification
• Requirements are written first-Requirement/desires concerning the task
• Describe the performance total structure of the digital circuit to be designed.
• Specification: phrase processor like phrase, Kwriter, AbiWord and for drawing
waveform use tools like wave former or scan bencher or phrase.
RTL Description
• Conversation of Specification in coding format using CAD Tools.

Coding Styles:
• Gate Level Modeling
• Data Flow Modeling
• Behavioral Modeling

• RTL Coding Editor: Vim, Emacs, conTEXT, HDL TurboWriter

VLSI Design Flow
Functional Verification &Testing

• evaluating the coding with the requisites.

• trying out the procedure of coding with corresponding inputs and outputs.
• If trying out fails – as soon as again determine the RTL Description.
• Simulation: Modelsim, VCS, Verilog-XL, Xilinx.
Logic Synthesis

• Dialog of RTL description into Gate level -web list kind.

• Description of the circuit in phrases of gates and connections.

• Synthesis: Design Compiler, FPGA Compiler, Simplify professional, Leonardo

Spectrum, Altera and Xilinx.

Logical Verification and Testing

• Sensible Checking of HDL coding by simulation and synthesis. If fails – examine

the RTL description.

Floor Planning Automatic Place and Route

• Construction of design with the corresponding gate measure net report.

• arrange the blocks of the web record on the chip
• Function& Route: For FPGA use FPGA' companies P&R instrument. ASIC
instruments require steeply-priced P&R tools like Apollo. Students can use LASI,
Magic

Physical Layout
• Bodily design is the system of reworking a circuit description into the bodily
design, which describes the role of cells and routes for the interconnections
between them.

Layout Verification

• Verifying the bodily layout constitution.

• If any change –as soon as once more investigate ground Planning automated
location and Route and RTL Description.
Implementation

• Final stage within the design method.

• Implementation of coding and RTL in the form of IC.
Comments
Comments can be inserted in the code for readability and documentation. There
Are two varieties to introduce comments?
• Single line feedback start with the token // and end with a carriage
Return
• Multi line feedback start with the token /* and finish with the token */
Identifiers and Keywords
Identifiers are names used to gift an object, similar to a register or a perform or a
module, a reputation so that it could be referenced from different areas in a
description.
Key words are reserved to stipulate the language constructs.
• Identifiers ought to start with an alphabetic personality or the underscore persona
(a-z A-Z )
• Identifiers might contain alphabetic characters, numeric characters, the
underscore, and the buck sign (a-z A-Z 0-9 _ $)
• Identifiers will also be as a lot as 1024 characters lengthy.
• Keyword phrases are in lowercase.

Examples of keywords
• Always
• begin
• End

MODULES
A module in Verilog contains exotic factors as proven in check. A module
definition endlessly starts off evolved with the important thing phrase module. The
module title, port record, port declarations, and no longer obligatory parameters
have got to come first in a module definition. Port list and port declarations are
present supplied that the module has any ports to engage with the outside
atmosphere. The five add-ons inside a module are;
• Variable declarations,
• Dataflow statements
• Instantiation of cut back modules
• Behavioral blocks
• Duties or aspects.
These add-ons can be in any order and at any function within the module
definition.
The end module assertion has to continuously come final in a module definition.
All components apart from module, module title, and end module are non-
obligatory and may also be mixed and matched as per design wants. Verilog makes
it possible for a few modules to be outlined in a single file. The modules will also
be outlined in any order inside the file.

Example Module Structure:

Module<module name>(<module_terminals_list>);
…..
<module internals>
….
End module

Instances
A module presents a template from which that you'd be able to create precise
objects. When a module is invoked, Verilog creates an exceptional object from the
template. Every object has its possess establish, variables, parameters and i/O
interface. The method of creating objects from a module template is often called
instantiation, and the objects are referred to as occasions. In illustration under, the
very best-stage block creates four occasions from the Tflip- flop (T_FF) template.
Every T_FF instantiates a D_FF and an inverter gate. Each example have to take
delivery of a specific identify.

PORTS
Ports furnish the interface in the course of which a module can preserve up a
correspondence with its atmosphere. For illustration, the enter/output pins of an IC
chip are its ports. The atmosphere can engage with the module easiest through its
ports. The internals of the module customarily will not be seen to the atmosphere.
This presents an awfully powerful flexibility to the fashion designer. The internals
of the module can also be modified without affecting the atmosphere as long as the
interface shouldn't be modified. Ports are additionally referred to as terminals.

Port Declaration
All ports in the list of ports must be declared in the module. Ports can be declared
as follows
Verilog Keyword Type of Port
Input Input port
Output Output port
inout Bidirectional port
Each port in the port list is defined as input, output, or in out, based on the
direction of the port signal.

Port Connection Rules

You'll be able to visualize a port as which includes two models, one unit that's
inside to the module yet another that is outside to the module. The inner and
outside models are linked. There are ideas governing port connections when
modules are instantiated inside exceptional modules. The Verilog simulator
complains if any port connection rules are violated.

Inputs:
• Internally must be of net data type (e.g. wire)
• Externally the inputs may be connected to a reg or net data type
Outputs:
• Internally may be of net or reg data type
• Externally must be connected to a net data type
Inouts:
• Internally must be of net data type (tri recommended)
• Externally must be connected to a net data type (tri recommended)

MODELING CONCEPTS
Verilog is each and every a behavioral and a structural language. Internals of each
module to be outlined at four stages of abstraction, relying on the wishes of the
design. The module behaves identically with the external atmosphere without
reference to the level of abstraction at which the module is described. The internals
of the module hidden from the environment. As a consequence, the extent of
abstraction to explain a module can also be transformed with none trade inside the
surroundings. The phases are defined under

• Behavioral or algorithmic level

This is the superb measure of abstraction offered by utilising Verilog HDL. A
module may also be carried out in phrases of the preferred design algorithm
without situation for the hardware implementation small print. Designing at this
degree is similar to C programming

• Dataflow level

At this stage the module is designed via specifying the data go with the flow. The
designer is conscious of how knowledge flows between hardware registers and the
best way the information is processed within the design.
• Gate level
The module is implemented in phrases of customary feel gates and
interconnections between these gates. Design at this stage is just like describing a
design in phrases of a gate-degree just right judgment diagram.

• Switch level

That's the bottom stage of abstraction offered via Verilog. A module can be applied
in phrases of switches, storage nodes, and the interconnections between them.
Design at this measure requires expertise of switch-degree implementation
fundamental facets. Verilog allows the fashion dressmaker to mix 'n match all 4
phases of abstractions in a design. Inside the digital design group, the time period
register swap measure (RTL) is most likely used for a Verilog description that
makes use of a blend of behavioral and dataflow constructs and is right to original
sense synthesis devices. If a design involves four modules, Verilog makes it
possible for every of the modules to be written at a different degree of abstraction.
Because the design matures, most modules are changed with gate-stage
implementations.

Probably, the higher the extent of abstraction, the additional bendy and science
impartial the design. As one goes decrease towards trade-stage design, the design
becomes science centered and rigid. A small modification can purpose a enormous
quantity of changes within the design. Evaluating the analogy with C programming
and meeting language programming. It can be less difficult to application in bigger
stage language akin to C. The applying can even be quite simply ported to any
laptop. On the other hand, if the design on the assembly stage, the application is
designated for that pc and aren't equipped to be conveniently ported to an
additional computing device.

GATE LEVEL MODELING

Verilog has developed in primitives like gates, transmission gates, and switches.
These are rarely utilized in design (RTL Coding), however are used in submit
synthesis world for modeling the ASIC/FPGA cells; these cells are then used for
gate degree simulation. Also the output netlist structure from the synthesis tool,
which is imported into the place and route instrument, can also be in Verilog gate
degree primitives.
Gate Types
A usual experience circuit can also be designed with the support of use of common
experience gates. Verilog helps excellent judgment gates as predefined primitives.
Theses primitives are instantiated like modules besides that they're predefined in
Verilog and should not have a module definition. All circuit may also be designed
by way of utilizing common gates. There are two classes of typical gates: and/or
gates and buf/now not gates.

BEHAVIORAL AND RTL MODELING

Verilog supplies designers the potential to explain design effectivity in an

algorithmic method. In certain words, the trend clothier describes the habits of the
circuit. Thus, behavioral modeling represents the circuit at an extraordinarily
immoderate stage of abstraction. Design at this measure resembles C programming
higher than it resembles digital circuit design. Behavioral Verilog constructs are
similar to c program language constructs in plenty of tactics. Verilog is rich in
behavioral constructs that furnish the clothier with a high-exceptional amount of
flexibility.
Operators
Verilog provided many different operators types. Operators can be,
• Arithmetic Operators
• Relational Operators
• Bit-wise Operators
• Logical Operators
• Reduction Operators
• Shift Operators
• Concatenation Operator
• Replication Operator
• Conditional Operator
• Equality Operator

Arithmetic Operators
• These perform arithmetic operations. The + and - can be utilized as each unary (-
z) or binary (x-y) operators.
• Binary: +, -, *, /, % (the modulus operator)
• Unary: +, - (that's used to specify the sign)
• Integer division truncates any fractional phase
• The effect of a modulus operation takes the signal of the major operand
• If any operand bit worth is the unknown rate x, then the entire have an effect on
price is x
• Register know-how forms are used as unsigned values (poor numbers are saved
in two's complement form)
Relational Operators
Relational operators evaluate two operands and return a single bit 1or zero. These
operators synthesize into comparators. Wire and reg variables are positive
therefore (- three’b001) = = 3’b111 and (-3d001)>3d1 10, nonetheless for integers
-1< 6

• The outcome is a scalar worth (illustration a < b)

• Zero if the relation is fake (a is higher than b)
• 1 if the relation is true ( a is smaller than b)
• X if any of the operands has unknown x bits (if a or b includes X)
Be aware: If any operand is x or z, then the result of that experiment is handled as
false (zero)

Bit-wise Operators

Bitwise operators perform just a little of intelligent operation on two operands.

This takes every bit in a single operand and participates within the operation with
the corresponding bit inside the different operand. If one operand is shorter than
the other, it's going to be accelerated on the left phase with zeroes to verify the size
of the longer operand.
• Computations include unknown bits, in the following way:
• -> ~x = x
• -> 0&x = 0
• -> 1&x = x&x = x
• -> 1|x = 1
• -> 0|x = x|x = x
• -> 0^x = 1^x = x^x = x
• -> 0^~x = 1^~x = x^~x = x
• When operands are of unequal bit length, the shorter operand is zero-filled in the
most significant bit positions.
Logical Operators
Legitimate administrators give back a solitary piece 1 or zero. They're the
equivalent as bit-canny administrators only for single piece operands. They can
take a shot at expressions, whole numbers or organizations of bits, and deal with
all qualities which may likewise be nonzero as "1". Coherent administrators are
without uncertainty utilized as a part of contingent (if ... Else) explanations seeing
that they work with expressions.
• Expressions connected with the backing of are assessed from left to appropriate

• Assessment stops as fast when you consider that the impact is noted

• The impact is a scalar esteemed at:

• - > zero if the connection is false

• - > 1 if the connection is correct

• - > x if any of the operands has x (obscure) bits

Reduction Operators
Rebate administrators work on the greater part of the bits of an operand vector and
return a solitary piece cost. These are the unary (one contention) kind of the bit-
astute administrators.

• Reduction administrators are unary.

• They play out somewhat insightful operation on a solitary operand to deliver a
solitary piece result.
• Reduction unary NAND and NOR administrators work as AND as well as
separately, yet with their yields nullified.
• - > Unknown bits are dealt with as portrayed some time recently
Shift Operators
Shift administrators move the primary operand by the quantity of bits determined
by the second operand. Emptied positions are loaded with zeros for both left and
right moves
(There is no sign augmentation).

• The left operand is moved by the quantity of bit positions given by the right
operand.
• The cleared piece positions are loaded with zeroes
Concatenation Operator
The link administrator joins two or more operands to shape a bigger vector.
• Concatenations are communicated utilizing the prop characters {and}, with
commas isolating the expressions inside.
• - >Example: + {a, b[3:0], c, 4'b1001}/if an and c are 8-bit numbers, the outcomes
has 24 bits
• Unsized consistent numbers are not permitted in connections.
Operator Precedence

Procedural Blocks
Verilog behavioral code is inside strategy pieces, yet there is a special case: some
behavioral code additionally exist outside method squares. We can see this in
subtle element as we gain ground. There are two sorts of procedural squares in
Verilog:
• introductory: beginning squares execute just once at time zero (begin execution at
time zero).
• Dependably: dependably squares circle to execute again and again; at the end of
the day, as the name proposes, it executes dependably.
In a dependably square, when the trigger occasion happens, the code inside start
and end is executed; then by and by the dependably piece sits tight for next
occasion activating. This procedure of holding up and executing on occasion is
rehashed till reproduction stops.

Xilinx Verilog HDL Tutorial

Getting started
 On the off chance that you wish to take a shot at this instructional exercise
and the research facility at home, you should download and introduce Xilinx and
ModelSim. These apparatuses both have free understudy forms. It would be ideal if
you perform Appendix B, C, and D in a specific order before proceeding with this
instructional exercise. Moreover in the event that you wish to buy your own
particular Spartan3 board, you can do as such at Digilent's Website. Digilent offers
scholastic evaluating. If you don't mind take note of that you should download and
introduce Digilent Adept programming. The product contains the drivers for the
board that you require furthermore gives the interface to program the board.

1. Introduction
Xilinx Tools is a suite of programming devices utilized for the outline of
advanced circuits actualized utilizing Xilinx Field Programmable Gate Array
(FPGA) or Complex Programmable Logic Device (CPLD). The outline method
comprises of (a) configuration passage, (b) blend and execution of the outline, (c)
useful reenactment and (d) testing and confirmation. Advanced outlines can be
entered in different ways utilizing the above CAD devices: utilizing a schematic
section instrument, utilizing an equipment portrayal dialect (HDL) – Verilog or
VHDL or a mix of both. In this lab we will just utilize the configuration stream that
includes the utilization of Verilog HDL.
The CAD devices empower you to outline combinational and consecutive
circuits beginning with Verilog HDL plan determinations. The progressions of this
outline strategy are recorded beneath:
1. Make Verilog outline information file(s) utilizing format driven editorial
manager.
2. Accumulate and execute the Verilog outline file(s).
 3. Make the test-vectors and recreate the outline (useful reenactment) without
utilizing a PLD (FPGA or CPLD).
4. Allot info/yield pins to execute the configuration on an objective gadget.
5. Download bit stream to a FPGA or CPLD gadget.
6. Test plan on FPGA/CPLD gadget
A Verilog information document in the Xilinx programming environment
comprises of the accompanying portions:
Header: module name, rundown of information and yield ports.
Announcements: info and yield ports, registers and wires.
Rationale Descriptions: conditions, state machines and rationale capacities.
End: end module

All your designs for this lab must be specified in the above Verilog input
format. Note that the state diagram segment does not exist for combinational logic
designs.
2. Programmable Logic Device: FPGA
On this lab digital designs will also be implemented within the Basys2 board
which has a Xilinx Spartan3E –XC3S250E FPGA with CP132 package deal deal.
This FPGA phase belongs to the Spartan cherished ones of FPGAs. These
contraptions are available in a type of programs. We can be utilizing devices that
are packaged in 132 pin bundle care for the next phase wide variety: XC3S250E-
CP132. This FPGA is a gadget with about 50K gates. Specific information on this
device is on hand on the Xilinx internet site.
3. Creating a New Project
Xilinx instruments can also be started by clicking on the assignment
Navigator Icon on the home windows computer. This must open up the
 assignment Navigator window on your display. This window indicates the
last accessed project.

Xilinx Project Navigator window (snapshot from Xilinx ISE software)

3.1 Opening a project

Choose File->New venture to create a new undertaking. This will likely deliver
up a new assignment window on the laptop. Refill the crucial entries as follows:
 New Project Initiation window (snapshot from Xilinx ISE software)

Project title: Write the name of your new undertaking

Task vicinity: The listing the place you want to retailer the brand new venture
(note: do not specify the undertaking vicinity as a folder on desktop or a folder
within the Xilinx bin listing. Your H: pressure is the high-quality situation to place
it. The challenge place direction is not to have any spaces in it eg: C:NivashTAnew
labsample exerciseso_gate will not be for use)
go away the highest degree module form as HDL.
Instance: If the assignment title have been “o_gate”, enter “o_gate” because the
task identify and then click on “subsequent”.
 Clicking on NEXT should bring up the following window:

Device and Design Flow of Project (snapshot from Xilinx ISE software)

For each of the properties given below, click on the ‘value’ area and select
from the list of values that appear.

• Device household: household of the FPGA/CPLD used. On this laboratory

we will be making use of the Spartan3E FPGA’s.
• Gadget: The range of the distinctive gadget. For this lab you can also enter
XC3S250E (this will also be placed on the hooked up prototyping board)
• Package deal deal: The style of package handle the quantity of pins. The
Spartan FPGA used on this lab is packaged in CP132 bundle.
• % Grade: The velocity grade is “-4”.
• Synthesis instrument: XST [VHDL/Verilog]
• Simulator: The instrument used to simulate and confirm the performance of
the design. Modelsim simulator is integrated within the Xilinx ISE. As a end result
select “Modelsim-XE Verilog” as the simulator or even Xilinx ISE Simulator can
be used.
• Then click on subsequent to avoid wasting tons of the entries.

All undertaking files reminiscent of schematics, net lists, Verilog documents,

VHDL files, and many others, will likely be stored in a subdirectory with the
assignment title. A task can only have one top degree HDL source file (or
schematic). Modules will also be delivered to the venture to create a modular,
hierarchical design.
With a purpose to open an existing mission in Xilinx instruments, decide on
File->Open mission to show the list of tasks on the laptop. Pick the undertaking
you need and click ok.
Clicking on NEXT on the above window brings up the following window:
Create New source window (snapshot from Xilinx ISE software) If creating a new
source file, Click on the NEW SOURCE.

1.1 Creating a Verilog HDL input file for a combinational logic design

In this lab we can enter a design making use of a structural or RTL description
using the Verilog HDL. Which you can create a Verilog HDL enter file (.V file)
making use of the HDL Editor available within the Xilinx ISE tools (or any text
editor).

Within the previous window, click on the new supply

A window pops up as proven in figure 4. (Observe: “Add to task” choice is

selected with the aid of default. If you don't decide upon it then you'll have to add
the new supply file to the challenge manually.)
Creating Verilog-HDL source file (snapshot from Xilinx ISE software)

Prefer Verilog Module and inside the “File determine:” area, enter the
determine of the Verilog supply file you're going to create. Moreover make
targeted that the alternative Add to project is chosen so that the supply needn't be
delivered to the venture again. Then click on subsequent to take delivery of the
entries. This pops up the following window.
Define Verilog Source window (snapshot from Xilinx ISE software)

Within the Port identify column, enter the names of all input and output pins
and specify the path thus. A Vector/Bus will also be outlined by way of getting
into right bit numbers in the MSB/LSB columns. Then click on subsequent> to get
a window showing all of the new supply information. If any changes are to be
made, simply click on <Back to go back and make changes. If everything is
acceptable, click on Finish > next > next > finish to proceed.

New Project Information window (snapshot from Xilinx ISE software)

Whilst you click on conclude, the deliver file will most likely be displayed
inside the sources window within the mission Navigator.
 If a source has to be eliminated, without problems appropriate click on the
supply file inside the Sources in mission window within the challenge Navigator
and opt for dispose of in that. Then choose mission -> Delete Implementation
understanding from the challenge Navigator menu bar to dispose of any associated
records.

1.2 Editing the Verilog source file

The source file will now be displayed in the task Navigator window. The supply
file window can be utilized as a textual content editor to make any vital alterations
to the supply file. The entire input/output pins will likely be displayed. Save your
Verilog application periodically through settling on the File->saves from the menu.
You can also edit Verilog applications in any textual content editor and add them
to the undertaking directory utilizing “Add replica source”.
 Verilog supply code editor window in the task Navigator (from Xilinx ISE
utility) together with good judgment within the generated Verilog supply code
template:

A short Verilog Tutorial is to be had in Appendix-A. As a result, the language

syntax and development of logic equations may also be pointed out Appendix-A.

The Verilog supply code template generated suggests the module name, the
report of ports and likewise the declarations (input/output) for each and every port.
Combinational common feel code can be delivered to the verilog code after the
declarations and earlier than the end module line.

For example, an output z in an OR gate with inputs a and b will even be b; take
into account that the names are case sensitive.
 Other constructs for modeling the great judgment perform: A given excellent
judgment function can also be modeled in lots of approaches in verilog. Correct
right here is another illustration where the good judgment operate, is applied as a
fact desk utilizing a case announcement:

2. Synthesis and Implementation of the Design

The design wants to be synthesized and utilized earlier than it could be checked
for correctness, by means of going for walks practical simulation or downloaded
onto the prototyping board. With the highest-measure Verilog file opened (can also
be completed through double-clicking that file) inside the HDL editor window
inside the correct half of the task Navigator, and the view of the venture being
within the Module view , the put into effect design option will also be obvious
within the procedure view. Design entry utilities and Generate Programming File
options can also be seen inside the strategy view. The former can be utilized to
include person constraints, if any and the latter may also be mentioned later.

To synthesize the design, double click on the Synthesize Design choice inside
the approaches window.

To put into effect the design, double click on the enforce design substitute
inside the strategies window. It will go via steps like Translate, Map and role &
Route. If any of these steps would now not be completed or executed with
blunders, it is going to location a X mark in front of that, or else a tick mark can be
positioned after each of them to indicate the optimistic completion. If the entire
factor is finished effectually, a tick mark will also be put before the put in force
Design substitute. If there are warnings, you can be competent to peer mark in
entrance of the alternative indicating that there are some warnings. That you would
be able to nonetheless seem on the warnings or mistakes inside the Console
window reward at the backside of the Navigator window. At any time when the
design file is saved; all these marks disappear soliciting for a contemporary
compilation.

Implementing the Design (snapshot from Xilinx ISE software)

The schematic diagram of the synthesized verilog code can be considered by

means of double clicking View RTL Schematic below Synthesize-XST menu in
the approach Window. This is competent to be a useful procedure to debug the
code if the output just isn't assembly our requirements inside the proto kind board.
 Via utilizing double clicking it opens the easiest stage module displaying
handiest input(s) and output(s) as proven under.

Top Level Hierarchy of the design

By double clicking the rectangle, it opens the realized internal logic as shown
below.

Realized logic by the XilinxISE for the verilog code

CONCLUSION

This work presents a 4-Bit ALU designed in TSMC 65nm CMOS process using the
Full-Swing GDI technique and simulated using the Cadence Virtuoso simulator. Simulation
results showed an advantage of the proposed ALU design in terms of power consumption and
transistor count, while maintaining Full-Swing Operation. The proposed design consists of 192
transistors and operates under 1V supply voltage.
REFERENCES:

[1] A. Morgenshtein, A. Fish, and I. Wagner, “Gate-diffusion input (GDI): a power-efficient

method for digital combinatorial circuits,” IEEE Transactions on Very Large Scale Integration
(VLSI) Systems IEEE Trans. VLSI Syst., vol. 10, no. 5, pp. 566–581, 2002.
[2] A. Morgenshtein, I. Shwartz, and A. Fish, “Gate Diffusion Input (GDI) logic in standard
CMOS Nanoscale process,” 2010 IEEE 26th Convention of Electrical and Electronics
Engineers in Israel, 2010.
[3] A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky, and A. Fish, "Fullswing gate diffusion
input logic—Case-study of low-power CLA adder design," Integration, the VLSI Journal, vol.
47, no. 1, pp. 62–70, Jan. 2014.
[4] N. Weste, D. Harris, CMOS VLSI Design a Circuits and Systems Perspective, 4th Ed,
Addison-Wesley, 2011.
[5] M. Shoba, R. Nakkeeran, "GDI based full adders for energy efficient arithmetic
applications", Engineering Science and Technology, an International Journal, vol. 19, no. 1, pp.
485–496, Mar. 2016.
[6] Chandra Srinivasan, “Arithmetic Logic Unit (ALU) Design Using Reconfigurable CMOS
Logic,” M.S. Thesis, Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA,
USA 2003.
[7] Vivechana Dubey, Ravimohan Sairam, “An Arithmetic and Logic Unit Optimized for Area
and power” IEEE Fourth International Conference on Advanced Computing & Communication
Technologies.,pp.330-334, 2014.
[8] G. Sree Reddy, K. V. Koteswara Rao,“32-Bit Arithmetic and Logic Unit Design With
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of Research In Computer Applications and Robotics, Vol.3 Issue.4, pp. 51-66, April 2015.
[9] S. Usha, M. Rajendiran, A. Kavitha, “Low Power Area Efficient ALU With Low Power Full
Adder” IEEE International Conference on Computing for Sustainable Global Development
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