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Zroute Technical Tutorial v2 03 024524
Zroute Technical Tutorial v2 03 024524
Zroute Technical Tutorial v2 03 024524
Future
t re of Ro
Routing
ting in
IC Compiler: Zroute
Technical Tutorial
B-2008.09-SP4/A-2007.12-SP5-2+
Presenter Info
1- 1
CONFIDENTIAL INFORMATION
The following material is being disclosed to you pursuant to a
non-disclosure agreement between you or your employer and
Synopsys. Information disclosed in this presentation shall be
used only as permitted under such an agreement.
agreement
LEGAL NOTICE
Information contained in this presentation reflects Synopsys
plans as of the date of this presentation. Such plans are subject to
completion and are subject to change. Products shall be offered
and purchased only pursuant to an authorized quote and
purchase order. Synopsys is not obligated to develop the
software with the features and functionality discussed in the
materials.
1- 2
Agenda
Multi-Threaded Routing
Example Scripts
Summary
1- 3
Introducing Zroute
Architected From The Ground Up For New Challenges
1
State-of-the-art routing
technology
IC Compiler
C il 2
Concurrent DFM optimizations
Z
Zroute
t
3
Multi-threaded throughout
10X Speed-
Speed-up,
up higher QoR
QoR,, better manufacturability
1- 4
1. State-of-the-Art Routing Technology
Dynamic
Grid
Virtual Wire
0.6S X Y
S Z
0.6S
S
W
S
Faster runtimes,
runtimes improved design closure
1- 5
2. Concurrent DFM Optimizations
S T
S T Spacing
Metal 2
Via1 Via1
Metal 1 Metal 1
Gate
Faster runtimes,
runtimes improved manufacturability
1- 6
3. Multi-Threaded Throughout
Global Routing
X Speedup
Track Assignment
Detail Routing
# of cores
Native
Memory
Ready to go
Simple set
set-up
up
# of cores
Faster runtimes,
runtimes near linear scalability
1- 7
10X Speed-Up On Mainstream Hardware
10X Speed Up
1- 8
10X Speed-Up On Mainstream Hardware
3-4X 3X
Multi-threaded
X Speedup # of Cores
1- 9
Fewer Wires, Fewer Total Number of Vias
1-2% 10--15%
10
Wire Length # of Total Vias
40nm, 225K 45nm, 374K
40nm, 60K 65nm, 845K
45nm, 170K 65nm, 593K
65nm, 845K 65nm, 545K
65nm, 593K 65nm, 356K
65nm, 545K 80nm, 2777K
65nm, 356K 90nm, 2313K
0 1 2 3 0 10 20
Improvement % Improvement %
1- 10
Fewer Non-Optimized Single Vias
30--50%
30
Remaining Non-Optimized Single Vias
40nm, 225K
40nm, 93K
40nm, 60K
45nm, 374K
45nm, 170K
65nm, 1000K
65nm, 68K
0 10 20 30 40 50 60 70
Improvement %
1- 11
Fewer Jogs and Notches,
Improved Lithography
Litho-Friendly Routing
No Scenic Routes
Fewer Jogs
Fewer Notches
1- 12
Zroute Results on Customer Designs
3X 3% 11%
1- 13
Zroute Is GA in IC Compiler B-2008.09!
Also available in
A-2007.12-SP5-1
Multiple on-going
tape-outs
tape outs
1000+
Multiple planned
hits test chips at 32nm
1- 14
Zroute Users Tell The Story …
1- 15
Zroute Technology Summary
Architected From The Ground Up For New Challenges
Available 1
B-2008.09
State of of
Part theICartCompiler
technology
IC Compiler
C il 2
Concurrent
Co-
Co DFMcurrent
-exists with optimizations
router
Z
Zroute
t
3
Multi-threaded
Single throughout
license for 4 cores
10X Speed-
Speed-up,
up higher QoR
QoR,, better manufacturability
1- 16
Agenda
Multi-Threaded Routing
Example Scripts
Summary
1- 17
Currently Supported Design Rules
1- 18
Zroute Input and Output
Same inputs as classic router
z Milkyway design library
Technology file
Standard cell and macro cell FRAM view
route_opt –skip_initial_route
Postroute Optimizations route_opt
p –incremental
Chip Finishing
signoff_opt
1- 20
Enabling Zroute
1- 21
More on report_route_opt_strategy
Default
D f lt It
Iterations
ti are 10 and
d 4 ffor Zroute-based
Z t b d
route_opt
z Zroute converges
g q quicker
z Zroute is more intelligent, stopping on nonconvergence
1- 22
Zroute Versus Classic Router Commands
* Î common|detail|global|track
1- 24
Intelligent DRC Convergence
1- 27
verify_zrt_route: Summary
Verify Summary:
1- 28
Switching to Zroute in the GUI
1- 29
Different Route Menu in IC Compiler GUI
1- 30
Has Design Been Routed by Zroute?
Multi-Threaded Routing
Example Scripts
Summary
1- 32
Multi-Threaded Routing Throughout
Designed from ground up as a multi-threaded router
z Most route engines run multi-threaded tasks
z Great threadability – close to upper bounds without QoR loss
Need multi-CPU or multi-core machines to run
multi-threading
z Number of threads ≤ total number of cores
1- 34
Example: Runtime Improvement
90nm, 2.3M Instances, 578 Macros
QoR
classic
Classic versus Zroute Zroute
Memory reduction
8.0 2.1X
7.0
z 21.6GB vs. 16.9GB
6.0
1 5X
1.5X z 21 6%
21.6%
5.0
Wire length improvement
me: Hours
4.0
2.0
Via reduction
1.0
z 11.6%
0.0
route_auto
t t i
insert_redundant
t d d t viasi verify_route
if t
Redundant via rate
improvement
Single CPU/Thread z 72.7% vs 93%
1- 35
Example: Multi-Threading Speed-Up
90nm, 2.3M Instances, 578 Macros
200.0
5.2X
150.0 2.8X 1
Runtime: Mi nutes
2
4
100.0 4.7X 8
50.0
0.0
route auto
route_auto insert redundant vias
insert_redundant verif y_route
y route
120.0
6.9X
100 0
100.0
1
80.0
Runtime: Minutes
5.1X 2
4
60.0 3.3X 8
40.0
R
20.0
0.0
global track detail
Multi-Threaded Routing
Example Scripts
Summary
1- 38
Parameter Translator Example
See the parameter translator guide (SolvNet 024478)
for more info
##Run
##R n classic ro
router
ter script up
p to point of r
running
nning classic ro
router
ter
##Translate parameters
translate_zrt_parameters
1- 39
route_opt With Zroute Example
##Enable
##E bl Zroute
Z t inside
i id route_opt
t t
set_route_mode_options -zroute true
##Turn on multi-threading
set_route_zrt_common_options
t t t ti -max_number_of_threads
b f th d 2
##Perform
##P f postroute
t t optimizations
ti i ti
route_opt –skip_initial_route
1- 40
route_zrt_auto: SI and Timing Driven
##Set signal integrity options
set_route_zrt_common_options -threshold_noise_ratio 0.25
set_route_zrt_global_options -crosstalk_driven true
set route zrt track options –crosstalk
set_route_zrt_track_options crosstalk_driven
driven true
1- 41
ICGR Flow With Zroute Example
##
##Verify
y routing
g – antenna checking
g on by
y default
verify_zrt_route
define_zrt_redundant_vias
define zrt redundant vias \
-from_via { VIA12 VIA23 VIA34 VIA45 VIA56 VIA12_OPTI VIA23_OPTI VIA34_OPTI \
VIA45_OPTI VIA56_OPTI VIA12_OPTI_SQ VIA23_OPTI_SQ VIA34_OPTI_SQ VIA45_OPTI_SQ \
VIA56_OPTI_SQ VIA67 VIA78 } \
-to_via { VIA12 VIA23 VIA34 VIA45 VIA56 VIA12 VIA23 VIA34 \
VIA45 VIA56 VIA12 VIA23 VIA34 VIA45 \
VIA56 VIA67 VIA78 } \
-to_via_x_size { 2 2 2 2 2 2 2 2 \
2 2 2 2 2 2 \
2 2 2 } \
-to_via_y_size
to via y size { 1 1 1 1 1 1 1 1 \
1 1 1 1 1 1 \
1 1 1 } \
1- 44
Prioritizing Double and Single VIA for DFM
Hidden 2008.09-SP2
Un-Hidden 2008
2008.09-
09-
SP4
1- 45
Insert Redundant Vias
1- 46
Insert Redundant Vias
Concurrent Flow
##Define redundant via sets (optional)
define zrt redundant vias …
define_zrt_redundant_vias Optional
##Route design
set_route_mode_options –zroute true
Redundant
edu da vias as
route_opt –initial_route_only
will be inserted
##Perform postroute optimizations at end of
route_opt –skip_initial_route routing phases
Sett after
S ft iinserting
ti DVDVs so th
thatt DV rate
t remains
i
nearly constant through rest of flow
With setting
setting, the eco route during route_opt
route opt will
re-double the vias on routing changed nets
z Extraction and timing
g effects are seen before and after
route_opt
z route_opt optimizations are based on these effects
set_route_zrt_common_options
z -post_detail_route_redundant_via_insertion
{ off | low | medium | high
g }
Include define_zrt_redundant_vias, if used, in
any script the automatic option may apply in 1- 48
Soft Concurrent Double Via
Hidden 2007.12-SP5-2
Soft rules to increase DV rate Unhidden 2008.09-SP4
Multi-Threaded Routing
Example Scripts
Summary
1- 50
Summary
Zroute is IC Compiler’s brand new, super-fast,
DFM-friendly router
z Fully multi-threaded
multi threaded for near
near-linear
linear scalability of runtime
z Concurrent DRC, antenna rules, wire and via optimization
z Concurrent redundant via insertion for higher
g yyield
z Soft rule support for lithography-friendly routing
z Signal-integrity-driven and timing-driven detail routing
z Simplified flow for ease-of-use
Zroute is available in version B-2008.09 to all
IC Compiler users
z Co-exists with the classic IC Compiler router
z Single IC Compiler license allows up to 4 threads
More info: https://solvnet.synopsys.com/zroute
1- 51
Predictable Success
1- 52
Appendix
1- 53
Technology File Details
1- 54
Default Vias and Via Regions
1- 55
Translation Example: ignoreNotchDRC
1- 56
Translation Example: runTimingMode
1- 57
Translation Example:
Migration to Technology File
TSMC fat wire via enclosure rule (VIA1.EN.3.1)
DesignRule {
layer1 = "Metal1"
layer2 = "Via1"
fatWireViaKeepoutParallelLengthThreshold = PL1
fatWireViaKeepoutMaxSpacingThreshold = S1
f tWi Vi K
fatWireViaKeepoutTblSize
tTblSi = 1
fatWireViaKeepoutMinSize = (R)
fatWireViaKeepoutWidthThreshold = (W)
fatWireViaKeepoutEnclosure = (G)
}
Starting in version A
A-2007.12-SP2,
2007 12 SP2 the classic router
warns you to move these to the technology file
1- 58
Parameter Translator – Verification
set_route_mode_options -zroute true
##Run Zroute
route_zrt_auto
1- 59
Independently Verifying Routing Results
1- 64
Script Conversion Tip – Redundant Vias
1- 65
Script Conversion Tip – Wire Spreading
1- 66