CMOS Static RAM IDT71256S

256K (32K x 8-Bit) IDT71256L

Features Address access times as fast as 20ns are available with power
◆
High-speed address/chip select time consumption of only 350mW (typ.). The circuit also offers a reduced power
– Military: 25/35/45/55/70/85/100ns (max.) standby mode. When CS goes HIGH, the circuit will automatically go to and
– Commercial/Industrial: 20/25/35ns (max.) low power only remain in, a low-power standby mode as long as CS remains HIGH. This
◆
Low-power operation capability provides significant system level power and cooling savings.
◆
Battery Backup operation – 2V data retention The low-power (L) version also offers a battery backup data retention
◆
Produced with advanced high-performance CMOS capability where the circuit typically consumes only 5μW when operating
technology off a 2V battery.
◆
Input and output directly TTL-compatible The IDT71256 is packaged in a 28-pin (300 or 600 mil) ceramic DIP,
◆
Available in standard 28-pin (300 or 600 mil) ceramic DIP, a 28-pin 300 mil SOJ providing high board level packing densities.
28-pin (300 mil) SOJ The IDT71256 military RAM is manufactured in compliance with the
◆
Military product compliant to MIL-STD-883, Class B latest revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance and
Description reliability.
The IDT 71256 is a 262,144-bit high-speed static RAM organized as
32K x 8. It is fabricated using high-performance, high-reliability CMOS
technology.

Functional Block Diagram

A0 VCC

262,144 BIT GND

ADDRESS
DECODER MEMORY ARRAY

A14

I/O0
I/O CONTROL
INPUT
DATA
CIRCUIT
I/O7

CS ,
OE CONTROL
CIRCUIT 2946 drw 01
WE

SEPTEMBER 2013
1
©2013 Integrated Device Technology, Inc. DSC-2946/13
 IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

Pin Configurations Truth Table(1)

WE CS OE I/O Function
A14 1 28 VCC
X H X High-Z Standby (ISB)
A12 2 27 WE
A7 3 26 A13 X VHC X High-Z Standby (ISB1)
A6 4 25 A8
H L H High-Z Output Disabled
A5 5 24 A9
A4 6 D28-3 23 A11 H L L DOUT Read Data
A3 7 D28-1 22 OE
A2 8 SO28-5 21 A10 L L X DIN Write Data
A1 9 20 CS 2946 tbl 02
NOTE:
A0 10 19 I/O7 1. H = VIH, L = VIL, X = Don't care.
I/O0 11 18 I/O6
I/O1 12 17 I/O5
I/O2 13 16 I/O4
GND 14 15 I/O3
2946 drw 02 Absolute Maximum Ratings(1)
DIP/SOJ Symbol Rating Com'l. Ind. Mil. Unit

Top View VTERM Terminal Voltage -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 V
with Respect
to GND

TA Operating 0 to +70 -40 to +85 -55 to +125 o

C
Pin Descriptions Temperature

Name Description TBIAS Temperature -55 to +125 -55 to +125 -65 to +135 o
C
Under Bias
A0 - A14 Address Inputs
Storage
TSTG -55 to +125 -55 to +125 -65 to +150 o
C
I/O0 - I/O7 Data Input/Output Temperature
Power
CS Chip Select PT
Dissipation
1.0 1.0 1.0 W

WE Write Enable IOUT DC Output Current 50 50 50 mA

OE Output Enable 2946 tbl 03
NOTE:
GND Ground 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
VCC Power functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
2946 tbl 01
to absolute maximum rating conditions for extended periods may affect
reliability.

Capacitance (TA = +25°C, f = 1.0MHz)

Symbol Parameter(1) Conditions Max. Unit
CIN Input Capacitance VIN = 0V 11 pF

CI/O I/O Capacitance VOUT = 0V 11 pF

2946 tbl 04
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.

2
 IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

Recommended Operating Recommended DC Operating

Temperature and Supply Voltage Conditions
Grade Temperature GND Vcc Symbol Parameter Min. Typ. Max. Unit
Military -55OC to +125OC 0V 5V ± 10% VCC Supply Voltage 4.5 5.0 5.5 V
Industrial -40OC to +85OC 0V 5V ± 10% GND Ground 0 0 0 V
Commercial 0 C to +70 C
O O
0V 5V ± 10% VIH Input High Voltage 2.2 ____
6.0 V
2946 tbl 05
VIL Input Low Voltage -0.5(1) ____
0.8 V
2946 tbl 06
NOTE:
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.

DC Electrical Characteristics(1,2) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
71256S/L20 71256S/L25 71256S/L35 71256S/L45

Power Com'l. Com'l Mi l . Com'l. Mi l . Mi l .

Symbol Parameter & Ind & Ind & Ind Unit
____ ____ ____
ICC Dynamic Op e rating Curre nt S 150 140 135 mA
CS < VIL, Outp uts Op e n
VCC = Max., fMAX(2) L 135 125 130 115 120 115
____ ____ ____
ISB Stand b y Po we r Sup p ly Curre nt S 20 20 20 mA
(TTL Le ve l), CS > VIH, VCC = Max.,
Outp uts Op e n, f = fMAX(2) L 3 3 3 3 3 3
____ ____ ____
ISB1 Full Stand b y Po we r Sup p ly Curre nt S 20 20 20 mA
(CMOS Le ve l), CS > VHC,
VCC = Max., f = 0 L 0.6 0.6 1.5 0.6 1.5 1.5
2946 tb l 07

71256S/L55 71256S/L70 71256S/L85 71256S/L100

Symbol Parameter Power Mi l . Mi l . Mi l . Mi l . Unit

ICC Dynamic Op e rating Curre nt S 135 135 135 135 mA

CS < VIL, Outp uts Op e n
VCC = Max., fMAX(2) L 115 115 115 115

ISB Stand b y Po we r Sup p ly Curre nt S 20 20 20 20 mA

(TTL Le ve l), CS > VIH, VCC = Max.,
Outp uts Op e n, f = fMAX(2) L 3 3 3 3

ISB1 Full Stand b y Po we r Sup p ly Curre nt S 20 20 20 20 mA

(CMOS Le ve l), CS > VHC,
VCC = Max., f = 0 L 1.5 1.5 1.5 1.5
2946 tb l 08
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, all address inputs are cycling at fMAX; f = 0 means no address pins are cycling.

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 IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

AC Test Conditions
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2
2946 tbl 09

5V 5V

480Ω 480Ω
DATA OUT DATA OUT
255Ω 30pF* 255Ω 5pF*

, ,
2946 drw 04 2946 drw 05

Figure 1. AC Test Load Figure 2. AC Test Load

(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
*Includes scope and jig capacitances

DC Electrical Characteristics (VCC = 5.0V ± 10%)

IDT71256S IDT71256L

Symbol Parameter Test Conditions Min. Typ. Max. Min. Typ. Max. Unit

|ILI| Input Leakage Current VCC = Max., MIL. ____ ____

10 ____ ____
5 µA
VIN = GND to VCC COM"L & IND. ____ ____
5 ____ ____
2

|ILO| Output Leakage Current VCC = Max., CS = VIH, MIL. ____ ____
10 ____ ____
5 µA
VOUT = GND to V CC COM"L & IND. ____ ____
5 ____ ____
2

VOL Output Low Voltage IOL = 8mA, VCC = Min. ____ ____
0.4 ____ ____
0.4 V

IOL = 10mA, VCC = Min. ____ ____

0.5 ____ ____
0.5

VOH Output High Voltage IOH = -4mA, VCC = Min. 2.4 ____ ____
2.4 ____ ____
V
2946 tbl 10

Data Retention Characteristics Over All Temperature Ranges

(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
Typ.(1) Max.
VCC @ VCC @

Symbol Parameter Test Condition Min. 2.0V 3.0V 2.0V 3.0V Unit
VDR VCC for Data Retention ____
2.0 ____ ____ ____ ____
V

ICCDR Data Retention Current MIL. ____ ____ ____

500 800 μA
COM'L. & IND. ____ ____ ____
120 200
tCDR Chip Deselect to Data CS > VHC 0 ____ ____ ____ ____
ns
Retention Time

tR(3) Operation Recovery Time tRC(2) ____ ____ ____ ____

ns
2946 tbl 11
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.

4
 IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

Low VCC Data Retention Waveform

DATA
RETENTION
MODE
VCC 4.5V 4.5V

tCDR VDR ≥ 2V tR

CS VIH VIH
VDR
2946 drw 06

AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)

71256S25(3) 71256S35(3) 71256S45(3)
71256L20(1) 71256L25 71256L35 71256L45(3)
Symbol Parameter Min. Max. M i n. Max. M i n. Max. Min. Max. Unit

Read Cycle
____ ____ ____ ____
tRC Re ad Cycle Time 20 25 35 45 ns
____ ____ ____ ____
tAA Ad d re ss Acce ss Time 20 25 35 45 ns
____ ____ ____ ____
tACS Chip Se le ct Acce ss Time 20 25 35 45 ns

tCLZ(2) Chip Se le ct to Outp ut in Lo w-Z 5 ____

5 ____
5 ____
5 ____
ns

tCHZ(2) Chip De se le ct to Outp ut in Hig h-Z ____

10 ____
11 ____
15 ____
20 ns
____ ____ ____ ____
tOE Outp ut Enab le to Outp ut Valid 10 11 15 20 ns

tOLZ(2) Outp ut Enab le to Outp ut in Lo w-Z 2 ____

2 ____
2 ____
0 ____
ns

tOHZ(2) Outp ut Disab le to Outp ut in Hig h-Z 2 8 2 10 2 15 ____

20 ns
____ ____ ____ ____
tOH Outp ut Ho ld fro m Ad d re ss Chang e 5 5 5 5 ns

Write Cycle
____ ____ ____ ____
tWC Write Cycle Time 20 25 35 45 ns
____ ____ ____ ____
tCW Chip Se le ct to End -o f-Write 15 20 30 40 ns
____ ____ ____ ____
tAW Ad d re ss Valid to End -o f-Write 15 20 30 40 ns
____ ____ ____ ____
tAS Ad d re ss Se t-up Time 0 0 0 0 ns
____ ____ ____ ____
tWP Write Pulse Wid th 15 20 30 35 ns
____ ____ ____ ____
tWR Write Re co ve ry Time 0 0 0 0 ns
____ ____ ____ ____
tDW Data to Write Time Ove rlap 11 13 15 20 ns

tWHZ(2) Write Enab le to Outp ut in Hig h-Z ____

10 ____
11 ____
15 ____
20 ns
____ ____ ____ ____
tDH Data Ho ld fro m Write Time 0 0 0 0 ns

tOW(2) Outp ut Active fro m End -o f-Write 5 ____

5 ____
5 ____
5 ____
ns
2946 tb l 12
NOTES:
1. 0° to +70°C or -40° to +85°C temperature range only.
2. This parameter is guaranteed by device characterization, but is not production tested.
3. –55°C to +125°C temperature range only.

6.42
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 IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

AC Electrical Characteristics (VCC = 5.0V ± 10%, Military Temperature Ranges)

71256S55(1) 71256S70(1) 71256S85(1) 71256S100(1)
71256L55(1) 71256L70(1) 71256L85(1) 71256L100(1)
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

Read Cycle
tRC Read Cycle Time 55 ____
70 ____
85 ____
100 ____
ns
tAA Address Access Time ____
55 ____
70 ____
85 ____
100 ns

tACS Chip Select Access Time ____

55 ____
70 ____
85 ____
100 ns

tCLZ(2) Chip Select to Output in Low-Z 5 ____

5 ____
5 ____
5 ____
ns

tCHZ(2) Chip Desele ct to Output in High-Z ____

25 ____
30 ____
35 ____
40 ns

tOE Output Enable to Output Valid ____

25 ____
30 ____
35 ____
40 ns

tOLZ(2) Output Enab le to Output in Low-Z 0 ____

0 ____
0 ____
0 ____
ns

tOHZ(2) Output Disab le to Output in High-Z 0 25 0 30 ____

35 ____
40 ns

tOH Output Hold from Address Change 5 ____

5 ____
5 ____
5 ____
ns

Write Cycle
tWC Write Cycle Time 55 ____
70 ____
85 ____
100 ____
ns
tCW Chip Select to End-of-Write 50 ____
60 ____
70 ____
80 ____
ns

tAW Address Valid to End-of-Write 50 ____

60 ____
70 ____
80 ____
ns

tAS Address Set-up Time 0 ____

0 ____
0 ____
0 ____
ns

tWP Write Pulse Width 40 ____

45 ____
50 ____
55 ____
ns
tWR Write Recovery Time 0 ____
0 ____
0 ____
0 ____
ns

tDW Data to Write Time Overlap 25 ____

30 ____
35 ____
40 ____
ns

tWHZ(2) Write Enab le to Output in High-Z ____

25 ____
30 ____
35 ____
40 ns

tDH Data Hold from Write Time (WE) 0 ____

0 ____
0 ____
0 ____
ns

tOW(2) Output Active from End-of-Write 5 ____

5 ____
5 ____
5 ____
ns
2946 tbl 13
NOTES:
1. -55° to +125°C temperature range only.
2. This parameter is guaranteed by device characterization, but is not production tested.

6
 IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

Timing Waveform of Read Cycle No. 1(1)

tRC

ADDRESS

tAA tOH

OE
tOE
tOHZ(5)
tOLZ (5)

CS
tACS tCHZ(5)
tCLZ (5)
DATAOUT

2946 drw 07

Timing Waveform of Read Cycle No. 2(1,2,4)

tRC

ADDRESS

tAA
tOH
tOH

DATAOUT
,

2946 drw 08

Timing Waveform of Read Cycle No. 2(1,3,4)

CS
tACS tCHZ(5)
tCLZ (5)
DATAOUT

2946 drw 09
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.

6.42
7
 IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4,6)

t WC

ADDRESS

tOHZ (5)

OE

tAW

CS
(6)
t AS t WP t WR

WE

tWZ (5) t OW

DATAOUT (3) (3)

tDW tDH

DATAIN

2946 drw 10

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,4)

tWC

ADDRESS
tAW

CS
t AS tCW(6) t WR
WE
t DW tDH2

DATA IN
2946 drw 11

NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width can be as short
as the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW.

8
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

Ordering Information — Commercial & Industrial

71256 X XX XXX X X X
Device Power Speed Package Process/
Type Temperature
Range

Blank Tube or Tray

8 Tape and Reel

Blank Commercial (0°C to +70°C)

I Industrial (-40°C to +85°C)

G Green

Y 300 mil SOJ (SO28-5)

20
25 Speed in nanoseconds
35

L Low Power Only

2946 drw 13

Ordering Information — Military

71256 X XXX XXX X
Device Power Speed Package Process/
Type Temperature
Range

B Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B

TD 300 mil CERDIP (D28-3)

D 600 mil CERDIP (D28-1)

25
35
45
55 Speed in nanoseconds
70
85
100

S Standard Power
L Low Power 2946 drw 12

6.42
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