Cadence Digital and Custom/Analog Tools

Achieve TSMC Certification for 16FF+

Process, Companies Collaborate on 10nm
FinFET
Cadence Design Systems, Inc. - September 26, 2014

Cadence Digital and Custom/Analog Tools

Achieve TSMC Certification for 16FF+
Process, Companies Collaborate on 10nm
FinFET
10nm FinFET Process Collaboration Enables Immediate
Early Customer Design Starts
PR Newswire

SAN JOSE, Calif., Sept. 26, 2014

SAN JOSE, Calif., Sept. 26, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a
leader in global electronic design innovation, today announced that its digital and custom/analog
tools have achieved V0.9 Design Rule Manual (DRM) and SPICE certification from TSMC for its
16FF+ process, enabling systems and semiconductor companies to take advantage of the 15 percent
speed improvement with the same total power compared to 16nm FinFET, or 30 percent total power
reduction at the same speed compared to 16nm FinFET. 16FF+ V1.0 certification is on track to be
concluded by November 2014. Cadence® also collaborated with TSMC to make several
enhancements to its Custom Design Reference Flow (CDRF) for the 16FF+ process. Additionally,
Cadence and TSMC are collaborating on the 10nm FinFET process, and Cadence solutions are ready
to support 10nm early customer design starts.
The Cadence custom/analog and digital implementation and signoff tools have been validated by
TSMC on high-performance reference designs in order to provide customers with the fastest path to
design closure. Cadence tools certified for 16FF+ include Encounter® Digital Implementation
System, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Quantus™ QRC
Extraction Solution, Virtuoso® custom design platform, Spectre® simulation platform, Physical
Verification System, Litho Physical Analyzer and CMP Predictor.

Enhancements to the CDRF include an exclusive TSMC application programming interface (API)
incorporated into Virtuoso Analog Design Environment GXL that speeds up statistical simulation
flow, a new design methodology leveraging module generator (ModGen) technology for designing
FinFET arrays to avoid density gradient effects, and the introduction of the electrically aware design
(EAD) platform to extract and analyze real-time parasitics and electromigration (EM) violations
during design implementation. Cadence tools in the flow include Virtuoso custom design platform,
Integrated Physical Verification System, Physical Verification System, Quantus QRC Extraction
Solution, Spectre simulation platform, Voltus-Fi Custom Power Integrity Solution and Litho
Electrical Analyzer.

Cadence also announced today a broad portfolio of intellectual property (IP) for TSMC's 16nm
FinFET Plus (16FF+) process. Click here for more information.

"We worked closely with Cadence to certify tools for customers to enjoy the benefits of higher
performance and lower power consumption of TSMC's 16nm FinFET Plus process," said Suk Lee,
TSMC senior director, Design Infrastructure Marketing Division. "The design tools and
manufacturing process have been tested to ensure they work seamlessly together so that customers
can achieve reduced iterations and improved predictability. Moreover, we are actively collaborating
with Cadence on the 10nm FinFET process, and the joint flow is ready for early customer designs."

"Innovation is at the core of our business, and that's why we continue to invest in our partnership
with TSMC and the development of 16nm and 10nm FinFET technologies," said Dr. Chi-Ping Hsu,
senior vice president, chief strategy officer, EDA and chief of staff to the CEO at Cadence. "TSMC
and Cadence work closely together to drive advancements that help our customers stay at the
forefront of silicon technology. Customers that create chips for the world's newest mobile devices
are already tapping into the benefits of the 16nm FinFET Plus design flows and can start to adopt
10nm FinFET solutions to overcome design complexity and get to market faster."

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of
today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and
services to design and verify advanced semiconductors, consumer electronics, networking and
telecommunications equipment, and computer systems. The company is headquartered in San Jose,
Calif., with sales offices, design centers, and research facilities around the world to serve the global
electronics industry. More information about the company, its products, and services is available
here.

© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo,
Encounter, Spectre, and Virtuoso are registered trademarks and Liberate, Quantus, Tempus, and
Voltus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All
other trademarks are the property of their respective owners.

For more information, please contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com

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SOURCE Cadence Design Systems, Inc.