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Scan Insertion Lab Observation (K.S.K.S.sarma)
Scan Insertion Lab Observation (K.S.K.S.sarma)
Scan Insertion Lab Observation (K.S.K.S.sarma)
LAB OBSERVATION
SUBMITTED BY
K.S.K.S.SARMA
TEST CASE – 1
PROBLEM DEFINITION: Design has S1 violations and it should be on all inputs (clk, set, and
reset) of the flop. Fix the violation using command and also by manual edits to the netlist.
INPUTS:
Synthesis Netlist
Library Model
Dofile Commands
OUTPUTS:
Design is having S1 violations. S1 violation is one in which the clocks (sets and resets included)
of non scan elements cannot be turned to off state.
How it is resolved?
It can be fixed by adding a MUX which selects between clocks in test mode and functional
mode.
OBSERVATIONS:
1 clock domain
2 resets
4 scan chains
No clock mixing.
It is Top-Down approach.
4 non-scan flops
S1 violations:
D5 violations:
Issue: Non-scan
scan memory element
INPUTS:
Synthesis Netlist
Library model
Dofile commands
OUTPUTS:
Design is having S2 violation. S2 violation is one in which the data at input of flop cannot be
captured with the clock due to some conditions like when the clock pin is tied to some value.
How it is resolved?
It can be fixed by connecting the clock input of flop to output of mux which selects test clock
when test enable is high and the functional clock when it is low.
OBSERVATIONS:
1 clock domain
2 resets
4 scan chains
No clock mixing.
It is Top-Down approach.
4 non-scan flops
C7 violations:
D5 violations:
Issue: Non-scan
scan memory element
S2 violations:
INPUTS:
Synthesis Netlist
Library model
Dofile commands
OUTPUTS:
Design has Bus Contention violation. Bus contention arises when there are multiple drivers
(usually with tristate buffers) disabling all drivers of the bus except 1 of the drivers.
How it is resolved?
With the command “insert test logic –tristate on” it can be resolved. This command will make
any two tristate buffers enabled with gating.
OBSERVATIONS:
1 clock domain
3) How many resets?
1 resets
2 scan chains
No clock mixing.
It is Top-Down approach.
18 non-scan flops
5 DRC violations which includes E4 and E10. E10 can’t be fixed and it won’t affect the design.
12) Write diagram with issues
E4 violation:
E10 violation:
These
ese violations can be ignored.
TEST CASE – 5
PROBLEM DEFINITION: Design has 1 clock domain with DFFs and latches and insert 2 scan
chains in the design.
INPUTS:
Synthesis Netlist
Library model
Dofile commands
OUTPUTS:
How it is resolved?
Usually if the design is having latches, it is advisable to go for LSSD style. In this case latches are
ignored.
OBSERVATIONS:
2 clock domains
1 reset
2 scan chains
5) Clock mixing or not clock mixing?
clock mixing.
It is Top-Down approach.
56 non-scan flops are available in the design and 2 non-scan flops are ignored for scannable
check.
34 DRC violations which include C8, C9 and D5 but these violations can be ignored.
INPUTS:
Synthesis Netlist
Library model
Dofile commands
OUTPUTS:
How it is resolved?
OBSERVATIONS:
1 clock domain
3) How many resets?
1 reset
3 scan chains
No clock mixing.
It is Top-Down approach.
INPUTS:
Synthesis Netlist
Library model
Dofile commands
OUTPUTS:
The design has no ATPG model for a Flip-Flop used in the netlist.
How it is resolved?
The library team should provide the library model files. Then the problem can be resolved.
OBSERVATIONS:
1 clock domain
2 scan chains
No clock mixing.
It is Top-Down approach.
14 non-scan flops
INPUTS:
Synthesis Netlist
Library model
Dofile commands
OUTPUTS:
The shift register should be added in the scan chain with converting it into scan Flip-Flop.
How it is resolved?
If the entire design is a shift register with no combo logic then the scan insertion chain and only
continuity has to be verified in this case.
OBSERVATIONS:
1 clock domain
3) How many resets?
1 reset
2 scan chains
No clock mixing.
It is Top-Down approach.
INPUTS:
Synthesis Netlist
Library model
Dofile commands
OUTPUTS:
How it is resolved?
OBSERVATIONS:
1 clock domain
0 resets
4) Number of scan chains
2 scan chains
No clock mixing.
Zero lock-up
up latches were added during scan insertion.
7) Is it top-down or bottom-up
up approach?
It is Top-Down approach.
9) Number of non-scan
scan flops in the desig
design?
77 non-scan flops
77 D7 DRC violations.
INPUTS:
Synthesis Netlist
Library model
Dofile commands
OUTPUTS:
How it is resolved?
Specify the sub chains (with add subchains) which are already present in the modules with their
length, scan-in, scan-out so that tool won’t touch these chains and just include them in the new
scan chains.
OBSERVATIONS:
1 clock domain
3) How many resets?
2 resets
4 scan chains
clock mixing.
It is Bottom-Up approach.
17 non-scan flops
D5 violations:
Top
|___block1
|___block2
INPUTS:
Synthesis Netlist
Library model
Dofile commands
OUTPUTS:
How it is resolved?
By using the command “add nonscan instance –module [module name]”, it can be resolved.
OBSERVATIONS:
1 clock domain
0 resets
4 scan chains
No clock mixing.
It is Bottom-Up approach.
4 D5 DRC violations.
12) Write diagram with issues
D5 violations:
INPUTS:
Synthesis Netlist
Library model
Dofile commands
OUTPUTS:
For 12(a): Normal scan insertion should be done for the given netlist.
For 12(b): The clock domains should be mixed and the scan should be done.
For 12(c): Along with clock mixing and inserting scan, edge mixing should also be done.
For 12(d): With single clock, all the 4 scan chains should be stitched.
How it is resolved?
For 12(a): By using the command, “set test logic -set on -reset on -clock on -ram on -bidi off”,
the scan insertion was done.
For 12(b): By using the commands, “set lockup latch on “and “insert test logic -ram on -clock
merge” clock mixing was done.
For 12(c): By using the commands, “set lockup latch on” and “insert test logic -ram on -clock
merge -edge merge”, clock mixing and edge mixing are done.
For 12(d): By using a single clock for the whole design and with the command, “insert test logic
–number 4”, all the 4 scan chains were stitched.
OBSERVATIONS:
For 12(a):
For 12(b):
For 12(c):
For 12(d):
2) How many clock domains?