Low Power Design

Cadence Design Systems, Inc.
RAPID ADOPTION KIT
Timing Signoff Optimization

Using
TEMPUS & Innovus
Lab Instruction Document
Tool Version
TEMPUS 16.20
Innovus 16.20
Nov – 2016
Tempus Timing Signoff Optimization
Table of Contents
I. INTRODUCTION .................................................................................................................................... 3
A. How to get the RAK Database .................................................................................................... 4
B. Directory Structure ..................................................................................................................... 4
C. Tools and Scripts ......................................................................................................................... 5
D. Terminology and Typographical Conventions ............................................................................ 5
E. Design ......................................................................................................................................... 6
F. Lab Flow ...................................................................................................................................... 6
Lab 1: MMMC SignOff at block level ....................................................................................................... 8
A. Lab1.1 : Fixing Hold timing violations ......................................................................................... 8
B. Lab1.2 : Fixing Hold timing violations with customizations...................................................... 17
C. Lab1.3 : Fixing Design Rule violations ....................................................................................... 20
D. Lab1.4 : Fixing DRV, Hold and Setup in one session ................................................................. 22
Lab 2 : Hierarchical Chip Finishing with Tempus ECO in Master/Clone mode ...................................... 26
A. Lab2.1 : Timing closure on Hierarchical design in Tempus....................................................... 26
Lab 3: Optimize Leakage/Timing with PBA ........................................................................................... 35
A. Lab3.1 : Optimizing Leakage in PBA mode ............................................................................... 35
Lab 4: Running Tempus ECO in Innovus ................................................................................................ 39
A. Lab4.1 : Optimizing DRV/Hold in PBA mode ............................................................................ 39
B. Lab4.2 : Optimizing Leakage in PBA mode ............................................................................... 42
COPYRIGHT © 2016, CADENCE DESIGN SYSTEMS, INC.

ALL RIGHTS RESERVED. PAGE 2
Tempus ECO - LABS

I. INTRODUCTION
In the following labs, you will learn how to perform ECOs for solving Hold, Setup and DRV timing
violations on a Dual Tone Multi Frequency (DTMF) design using Cadence Tempus and the Innovus
Digital Implementation System.
One Lab will cover Tempus ECO fixing on a block level design, the second Lab will cover Hierarchical
Chip finishing using Tempus ECO, the third Lab will show how to optimize Leakage/Timing in Path
Based Analysis mode and the fourth Lab will illustrate how to run Tempus ECO from Innovus cockpit.
It is recommended to run the Labs in the order they are described in this document, but since they
are each independent, you can directly jump to the one you are interested in.
At the end of the session, you will be able to:
 Explain how to investigate timing in an SignOff STA environment
 Understand and explain the timing ECO methodology
 Understand and perform all the steps required before starting the ECO process
 Perform Hold, Setup and DRV timing fixes through ECOs
 Report and analyze ECO results
 Implement the ECOs in Innovus Digital Implementation
 Verify final SignOff STA
 Assemble a Hierarchical design in Tempus for STA and ECO fixing
 Perform Hierarchical aware Chip Finishing with timing ECOs
 Time the design in Path Based Analysis mode
 Optimize leakage/timing in Path Based Analysis mode
 Run Tempus Eco from Innovus cockpit
NOTE: The Tempus ECO feature does require a Tempus ECO license.

_____________________________________________________________________
A. How to get the RAK Database
The RAK testcase database, Scripts and References can be found at ‘Attachments’ and ‘Related
Solutions’ sections below the PDF.
This pdf can also be searched with the document 'Title' on https://support.cadence.com
B. Directory Structure
The lab directory structure is as follows:
<my_dir>/
design/
design_hier/
design_PBA/
docs/
libs/
scripts/
scripts_hier/
scripts_PBA/
scripts_SOD/
work/
work_hier/
work_PBA
work_SOD
The docs/ directory contain the Tempus ECO Lab Instructions and Presentation documents:
Tempus162_MMMC_ECO_RAK_Labs.pdf
Tempus162_MMMC_ECO_RAK_slides.pdf
Review this presentation before starting the labs, and use them as a reference throughout the
labs.
_____________________________________________________________________

C. Tools and Scripts
This lab uses Tempus and the Innovus Digital Implementation. Make sure you have the following
versions installed:
TEMPUS 16.20
Innovus 16.20
Note: You must use the same tool version and environment (scripts, libraries, constraints, and so
on) throughout the design cycle (in other words, in the tapeout flow and for the ECO).
_____________________________________________________________________
D. Terminology and Typographical Conventions
Please note the follow key acronyms:
ECO = Engineering Change Order
Tempus = Cadence SignOff STA tool
Innovus = Cadence Implementation tool
AAE = Name of the delay calculation engine (Advanced Analysis Engine)
MMMC = Multi Mode Multi Corner
view = Combination of a corner and a timing mode
DB = Database
GTD = Global Timing Debug environment available in the Tempus Graphical Interface under the
Analysis tab.
D-MMMC = Distributed MMMC timing analysis environment in Tempus
DRV = Design Rule Violation, such as max_cap and max_tran.
STA = Static Timing Analysis
PBA = Path Based Analysis
Throughout this lab, anything to be typed as shown is in bold italics, along with a typical
command prompt. For instance,
 cd $WS_DIR/work/
Also, during this lab, anything printed in ”blue Courier font style” is representing
information that can be visible in a file (either a script or a log file)

_____________________________________________________________________
E. Design
The sample testcase is a generic DTMF design, it contains:
 Approximately 10k instances
 Sequential, combinational, and state machine logic
 The following hard macros: PLL, RAM, and ROM.
 Seven clocks
 36 Views ( 2 libraries x 6 corners x 3 modes ) :
o Libraries are : Worst and Typical
o Corners are : Cmax, RCmax, Rmax, Cmin, RCmin, Rmin
o Modes are : Functional, Test, Scan
Note: This design is mapped on Cadence open source Libraries, so this explains why the clock
period and cell delay are probably larger than usual.
_____________________________________________________________________
F. Lab Flow
The following describes the overall Tempus ECO methodology for the labs when Tempus is the
main cockpit; this is also described in the Tempus ECO presentation document:
1. Generate the ECO Timing DB:
Tempus ECO is able to load and optimize timing on previously generated ECO Timing DB.
This allows keeping current D-MMMC SignOff STA environment to generate timing
information per views on an unlimited amount of views. In this session, user will
generate those ECO Timing DBs and can debug the timing using GTD feature.
2. Run Tempus ECO timing fixing session:
Once the ECO Timing DB are generated, you can load all (or just some) of them in a
single session in order to perform timing fixing. The tool will automatically generate an
ECO file containing all the netlist change needed to close timing on the design.
3. Implement the ECOs using Innovus Digital Implementation tool:
The ECOs must be applied in an implementation tool in order to update the physical
context, meaning doing ECO routing. No placement refinement is needed because the

ECOs generated are fully legal since Tempus ECO is Physical-Aware. At the end of that
phase a new Verilog/DEF set will be generated and new SPEF files will be dumped.
4. Perform SignOff STA on the new DB containing the ECOs:
With the new set of Verilog/DEF/SPEF containing the ECOs, user will perform a final
round of SignOff STA in D-MMMC mode and investigate the resulting timing in GTD
feature.
In the last Lab, when Innovus in the main cockpit, only one script is provided and it will run the
full flow.

Lab 1: MMMC SignOff at block level

_____________________________________________________________________
A. Lab1.1 : Fixing Hold timing violations
Overview: Demonstrate the automated ECO timing closure flow using Tempus and Innovus
Digital Implementation tools.
Timing violations: The initial design contains some Hold timing violations that should be fixed
before going to TapeOut.
Goal: The Hold timing violations must be fixed without impacting Setup timing and without
creating any Design Rule Violations.
Location:
 cd <MY_DIR>/work/
Steps:
1. Generate ECO Timing DB
 cat ../scripts/run_session1.tcl
You can see that this file contains the minimum and standard required commands to perform a
D-MMMC SignOff timing analysis run on 36 actives views.
set_distribute_host -local
set_multi_cpu_usage -localCpu 16 –remoteHost 4 –cpuPerRemoteHost 4
distribute_read_design -design_script
../scripts/loadDesign_DMMMC.tcl -outdir sta
distribute_views -views [list func_slow_CMAX func_fast_CMAX

func_slow_RCMAX func_fast_RCMAX func_slow_RMAX func_fast_RMAX
func_slow_CMIN func_fast_CMIN func_slow_RCMIN func_fast_RCMIN
func_slow_RMIN func_fast_RMIN scan_slow_CMAX scan_fast_CMAX
scan_slow_RCMAX scan_fast_RCMAX scan_slow_RMAX scan_fast_RMAX
scan_slow_CMIN scan_fast_CMIN scan_slow_RCMIN scan_fast_RCMIN
scan_slow_RMIN scan_fast_RMIN test_slow_CMAX test_fast_CMAX
test_slow_RCMAX test_fast_RCMAX test_slow_RMAX test_fast_RMAX
test_slow_CMIN test_fast_CMIN test_slow_RCMIN test_fast_RCMIN
test_slow_RMIN test_fast_RMIN] -script ../scripts/sta.tcl
 cat ../scripts/loadDesign_DMMMC.tcl
This file contains the design data that must be loaded to perform a D-MMMC SignOff timing
analysis. This one also is a standard file, except that LEF/DEF data are being loaded.

read_lib -lef {../libs/lef/FreePDK45_lib_v1.0.lef

../libs/MACRO/LEF/pllclk.lef ../libs/MACRO/LEF/ram_256X16A.lef
../libs/MACRO/LEF/rom_512x16A.lef}
read_view_definition ../design/viewDefinition.tcl
read_verilog
"../design/ECO_INIT_11_optSetup.enc.dat/dtmf_recvr_core.v.gz"
set_top_module dtmf_recvr_core -ignore_undefined_cell
read_def "../design/full.def"
Note: The LEF/DEF data are not needed to time the design or to generate the ECO Timing DB,
but since we will use the same script to load the design in all the sessions: STA and ECO,
therefore loading of physical data was added.
 cat ../scripts/sta.tcl
This file contains the SPEF files location and the SignOff SI timing analysis settings/reporting
commands. At the end of the file, the only needed command to generate an ECO Timing DB is
write_eco_opt_db.
source ../scripts/spef.tcl
set_delay_cal_mode -SIAware true
report_constraint -all_violators > rep.vio.gz

report_analysis_coverage > rep.coverage
report_timing -path_type end_slack_only \
-max_slack 0 > setup.rpt
report_timing -path_type end_slack_only \
-max_slack 0 -early > hold.rpt
report_timing -late -max_slack 0.0 -max_paths 1000 \

-machine_readable > design_before_late.mtarpt.gz
report_timing -early -max_slack 0.0 -max_paths 1000 \
-machine_readable > design_before_early.mtarpt.gz
write_eco_opt_db
 tempus -init ../scripts/run_session1.tcl -log LOG_session1.log
This will run Tempus to perform SignOff SI timing analysis, then dump a Timing ECO DB per view
and ends by opening up GTD for timing investigation. Once the run is completed, please go to
the “Analysis” tab to have a complete view of the initial timing.

From this analysis form, please answer the following questions:
- Are there Hold timing violations in all the views? __________________
- Which timing view has the most Hold timing violations? __________________
- Which timing view has the least Hold timing violations? __________________
In MMMC SignOff timing analysis environment some timing violations are in every timing views
and some are only in a few views. The goal is to fix every timing violation without creating any
new timing violations in any of the views.
There are some IO paths Hold violations and some register-to-register paths Hold violations. The
range of the Hold violations are quite high on this technology but the Tempus ECO feature will
insert the right number of ECO buffers to fix them all at the minimum area cost.
Now, go back to the shell and type “Resume” in order to load the Setup timing analysis in the
“Analysis” tab.

- Are there Setup timing violations? __________________
- How many views are violated in Setup out of the 36 total views? __________
- How many violated paths are there in the worst view? __________________
You can exit the TEMPUS session.
 ls ecoTimingDB/
In the current working directory you can see that a new directory was created and it contains the
ECO Timing DB per view. Those are the one needed for the next step.
2. Run Tempus ECO timing fixing session
This is the file containing the necessary commands to load the design with physical data, to load
the MMMC environment settings and to set up the Tempus ECO fixing feature command called
eco_opt_design.

source ../scripts/loadDesign_DMMMC.tcl
source ../scripts/spef.tcl
set_eco_opt_mode -verbose true

set_eco_opt_mode -load_eco_opt_db ecoTimingDB
eco_opt_design -hold -analysis_script ../scripts/spef.tcl
You can note that the location of the SPEF files must be provided before running
eco_opt_design command since that is mandatory to perform precise timing evaluation during
the fixing process.
 tempus -tso -init ../scripts/run_session2.tcl –log LOG_session2.log
This will execute the script that runs Signoff ECO timing fixing.
 more LOG_session2.log
This is the log file of the fixing SignOff ECO timing fixing session. By browsing through it please
provide answers to the following questions:
- What are the initial Hold timing WNS; TNS; No. of Viol paths? _________________
- What are the initial Setup timing WNS; TNS; No. of Viol paths? _________________
- What is the initial DRV count? _________________
- Is the final Hold timing met? _________________
- Do you see any degradation in the final Setup timing or DRV? _______________
- How many buffers were inserted to fix the Hold timing violations? ____________
Open up the Graphical User Interface by typing the “start_gui” command and click on the
“Layout” tab. On this form you can see that TEMPUS has a full view of the placement and the
routing. You can remove the net visibility, by unselecting the left check box next to “Net” in the
“Layer Control” menu.

The ECO buffers have been highlighted in white. You can verify that all of them are located in
fully legal locations.
You can exit the TEMPUS session and check what ECOs are being done in the ECO file.
 cat eco_innovus.tcl
This file contains the ECO instruction that will be sourced in Innovus in the next step. You can
scan over it and find out that it contains a list of ecoAddRepeater commands, with physical
information, which are natively supported by Innovus release.
3. Implement the ECOs in Innovus
 cat ../scripts/run_PlaceAndRoute.tcl
This is the file containing the necessary commands to load the design in Innovus, to source the
ECO file and to run ECO routing.
source ../design/ECO_INIT_11_optSetup.enc
setExtractRCMode -coupled true -engine postRoute -effortLevel low

setMultiCpuUsage -localCpu 8

extractRC
source eco_innovus.tcl
ecoRoute
extractRC
 innovus -nowin -init ../scripts/run_PlaceAndRoute.tcl –log \
LOG_Innovus_PlaceAndRoute.log
This will perform the ECO implementation in Innovus.
 cat LOG_Innovus_PlaceAndRoute.logv
By browsing the Innovus log file you can see the ECO buffers being inserted and at the end of
that process the tool is calling placement refinement.
Do you see any instance movement? _________________
Statistics of distance of Instance movement in detailed placement:

maximum (X+Y) = 0.00 um
mean (X+Y) = 0.00 um
Total instances moved : 0
*** cpu=0:00:00.4 mem=485.4M mem(used)=15.5M***
Indeed there is no instances movement because the ECO buffers location in the ECO file is all
fully legal.
From this session we do also generate the final Verilog/DEF and dump new SPEFs.
4. Perform SignOff STA on the DB containing the ECOs implemented
This file is very similar to “run_session1.tcl” which we have reviewed earlier. Here again the
purpose is to run a D-MMMC SignOff STA. It will load the new Verilog/DEF/SPEFs to generate
timing reports and we will then be able to investigate the final timing in the graphical interface.
set_distribute_host -local
set_multi_cpu_usage -localCpu 16 –remoteHost 4 –cpuPerRemoteHost 4
distribute_read_design \
-design_script ../scripts/loadDesign_DMMMC_postECO.tcl \
-outdir sta_postECO
distribute_views -views [list func_slow_CMAX func_fast_CMAX

func_slow_RCMAX func_fast_RCMAX func_slow_RMAX func_fast_RMAX
func_slow_CMIN func_fast_CMIN func_slow_RCMIN func_fast_RCMIN
func_slow_RMIN func_fast_RMIN scan_slow_CMAX scan_fast_CMAX

scan_slow_RCMAX scan_fast_RCMAX scan_slow_RMAX scan_fast_RMAX

scan_slow_CMIN scan_fast_CMIN scan_slow_RCMIN scan_fast_RCMIN
scan_slow_RMIN scan_fast_RMIN test_slow_CMAX test_fast_CMAX
test_slow_RCMAX test_fast_RCMAX test_slow_RMAX test_fast_RMAX
test_slow_CMIN test_fast_CMIN test_slow_RCMIN test_fast_RCMIN
test_slow_RMIN test_fast_RMIN] -script ../scripts/sta_postECO.tcl
 tempus -init ../scripts/run_session3.tcl -log LOG_session3.log
Once the run is completed, please go to the “Analysis” tab to have a complete view of the Hold
timing.
- Are there any remaining Hold timing violations? __________________
- What is the worst Hold slack? __________________

From the Slack histogram you can also see that the Hold timing violations were not over fixed
since there are still a few Hold timing slack close to +0ps. This is because the tool is fixing the
timing violations to meet the target slack with the least impact on area increase.
Now, go back to the shell and type “Resume” in order to load the Setup timing views in the
“Analysis” tab.
- Are there any new Setup timing violations compared to the initial Setup timing measured
earlier in this lab? __________________
Tempus ECO was able to fix the Hold violations in many different timing views while not creating
any new Setup violations among all the Setup timing views. The fact that this feature is Physical-
Aware does provide higher timing predictability. You can see that the worst Setup path has some
large slews, which explains that any slight routing change may cause timing difference on it.
Once this path gets optimized in Setup timing, slews will be better and timing more stable.
You can exit the TEMPUS session. You now know how to run a complete loop of ECO timing
closure using ECO fixing feature.

_____________________________________________________________________
B. Lab1.2 : Fixing Hold timing violations with customizations
Overview: Demonstrate the automated Signoff ECO timing closure flow using Tempus and
Innovus Digital Implementation tools.
Timing violations: The initial design contains some Hold timing violations that should be fixed
before going to TapeOut. In addition, the user wants to apply some customization on top of the
default tool settings.
Goal: The Hold timing violations must be fixed without impacting Setup timing and without
creating any Design Rule Violations. Also the tool should honor the extra constraints/options
provided by the user.
Location:
Steps:
1. Run Tempus ECO Hold fixing session with positive Hold target slack
The customer methodology, for this slow process node, is to achieve a Hold target slack of
+500ps. In that context, all that is needed to honor this extra rule is to add the following option
in the scripts that calls eco_opt_design : ”set_eco_opt_mode -hold_target_slack 0.5”
So out of the different scripts/step from the LAB1, the only one that must be updated is:
../scripts/run_session2.tcl
You should copy the ../scripts/run_session2.tcl script to ../scripts/run_session2_extra.tcl and

then edit it to add the option mention above before the eco_opt_design command.
 tempus -tso -init ../scripts/run_session2_extra.tcl –log \
LOG_session2_extra.log
This will execute the script that runs Tempus ECO Hold fixing with extra constraints.
 more LOG_session2_extra.log
This is the log file of the fixing SignOff ECO Hold fixing session. By browsing through it and by
comparing it to the previous Hold fixing run, please provide answers to the following questions:
- Was the tool able to meet the +500ps Hold target slack? _________________
- Did this extra constraint lead to Setup timing degradation? _________________
- How many buffers were inserted to fix the violations? ____________

------------------------------------------------------------
Final Hold Summary
------------------------------------------------------------
+--------------------+-----------+
| Hold mode | all |
+--------------------+-----------+
| WNS (ns):| 0.502 |
| TNS (ns):| 0.000 |
| Violating Paths:| 0 |
+--------------------+-----------+
In this sub-section we could verify that on this design the tool was able to fix the Hold timing
violations up to a positive 502ps target slack without any negative side effect on Setup timing.
2. Run Tempus ECO Hold fixing session on register to register paths only
In addition to the positive Hold target slack of +500ps, the design team is willing to fix only the
register to register violated paths since the IO paths might not have accurate Hold timing
constraints.
In that context, all that is needed to honor this extra rule is to add the following command in the
scripts that calls eco_opt_design :
“set_eco_opt_mode –optimize_core_only true”
Please update the ../scripts/run_session2_extra.tcl script by adding the command mention

above before the eco_opt_design command.
 tempus -tso -init ../scripts/run_session2_extra.tcl –log \
LOG_session2_extra2.log
This will execute the script that runs Tempus ECO Hold fixing with extra constraints on Hold
target slack and focusing only on register to register paths.
 more LOG_session2_extra2.log
This is the log file of the fixing SignOff ECO Hold fixing session. By browsing through it and by
comparing it to the previous Hold fixing run, you will see that the initial Hold timing report is
now mentioning that Hold timing reported is on register to register only :
+--------------------+-----------+
| Hold mode | reg2reg |
+--------------------+-----------+
| WNS (ns):| -0.485 |
| TNS (ns):| -3.288 |
| Violating Paths:| 17 |
+--------------------+-----------+

The same will be for final Hold timing. On the other hand, the initial and final Setup timing will be
reported on the “all” path_group since while fixing Hold timing on register to register, tool will
ensure no Setup degradation on the entire design.

_____________________________________________________________________
C. Lab1.3 : Fixing Design Rule violations
Overview: Demonstrate the automated ECO timing closure flow using Tempus and Innovus
Digital Implementation tools.
Timing violations: The initial design contains one max_cap violation that should be fixed before
going to TapeOut and also some max_tran violations.
Goal: The max_cap violation must be fixed and the max_tran violation count must be reduced,
without impacting Setup timing and without creating any other Design Rule Violations.
Location:
Steps:
The same ECO Timing DB can be used to fix the DRV violations. So out of the different
scripts/step from the LAB1, the only one that must be updated is: ../scripts/run_session2.tcl
You should copy that script to ../scripts/run_session2_DRV.tcl and then edit it to only replace
the –hold by –drv option for the eco_opt_design command.
In addition, to be able to insert buffers along the routing, which is very helpful for DRV fixing,
you will need to load parasitic data through RCDB (since that will contain segment coordinates)
instead of SPEF, and enable the along route buffering feature. Here are the two commands:
restoreRC ../design/ECO_INIT_11_optSetup.enc.dat/dtmf_recvr_core.rcdb.d
set_eco_opt_mode -along_route_buffering true
Then run Tempus:
 tempus -tso -init ../scripts/run_session2_DRV.tcl –log \
LOG_session2_DRV.log
This will execute the script that runs Tempus ECO DRV fixing.
 more LOG_session2_DRV.log
This is the log file of the fixing SignOff ECO DRV fixing session. By browsing through it please
- What is the initial Signal Nets max_cap violation ? _________________
- What is the initial Signal Nets max_tran violation ? _________________
- Did the tool also reduce the max_tran violation count? _________________

- How many instances were resized to fix the violations? ____________
- How many buffers were inserted to fix the violations? ____________
At the end of the fixing process, there is a detailed diagnostic report explaining the reasons why
the remaining violations were not fixed.
---------------------------------------------------
ECO DRV Fixing Violated Nets Summary
---------------------------------------------------
*info: Total 4 net(s) have violated drvs
*info: 3 net(s): Could not be fixed because they are clock nets.
*info: The tool is not allowed to insert a buffer on a
clock net.
m_ram_clk__L5_N0
m_clk__L3_N0
m_dsram_clk__L1_N0
*info: 1 net(s): Could not be fixed because

no max_tran violation improving moves were
found.
*info: These nets have DRV but
inserting a buffer would further degrade the
max_tran violation.
*info: You should check the
topology of those nets and probably enlarge the
list of
*info: available buffer/delay
cells that are allowed to be used.
p_addrs[2]
Tempus ECO is not allowed to touch the clock nets so the DRV on
those nets remain at the end of this process. That’s for the 3 nets
from the first category.
The single net from the second category remain unfixed because
the tool was not able to find a solution through buffering/resizing
to reduce the max_tran violations. Indeed, when highlighting that
“p_addrs[2]” net on the floorplan, using selectNet command,
you will see that this net is entirely over a placement blockage area
before connecting to the RAM.

_____________________________________________________________________
D. Lab1.4 : Fixing DRV, Hold and Setup in one session
Overview: Demonstrate the incremental timing closure feature of Tempus ECO flow using
Tempus and Innovus Digital Implementation tools.
Timing violations: The initial design contains some DRV violations, some Hold timing violations
and also some Setup timing violations. Those must be fixed as much as possible before going to
TapeOut.
Goal: All those DRV/Hold/Setup violations must be fixed in one single session without having to
for full ECO loop after each fixing stage. This can be done using the incremental timing closure
feature available in Tempus.
Location:
Steps:
The same ECO Timing DB generated earlier can be used for this exercise too. So out of the
different scripts/step from the LAB1, the only two that must be updated are:
../scripts/run_session2_DRV.tcl and ../scripts/run_PlaceAndRoute.tcl
You should copy that first script to ../scripts/run_session2_incr.tcl and then edit it to replace the
eco_opt_design -drv command by this list of commands executing the incremental timing
closure flow:
set_eco_opt_mode -allow_multiple_incremental true

set_eco_opt_mode -eco_file_prefix DRV
eco_opt_design -drv
set_eco_opt_mode -eco_file_prefix SETUP

eco_opt_design -setup
set_eco_opt_mode -eco_file_prefix HOLD

eco_opt_design –hold
Note: The DRV/Setup/Hold optimizations can be called in any order, since timing is incrementally
updated. But it is recommended to run first DRV fixing because it can impact Setup and Hold
timing, then it is usually better to continue with Setup optimization as it can help Hold
optimization by creating extra Setup timing margin.

Then run Tempus :
 tempus -tso -init ../scripts/run_session2_incr.tcl –log \
LOG_session2_incr.log
This will execute the script that runs Tempus ECO for DRV/Hold/Setup fixing in the same session.
 more LOG_session2_incr.log
This is the log file for that ECO session. By browsing through it please provide answers to the
following questions:
- At the end of the flow, is the Setup timing met? _________________
- Did the tool fix all the Hold violations? _________________
- Can you confirm that the DRV violations were reduced too? ____________
The conclusion is that the tool was able to fix all the Setup timing violations while still fixing the
Hold and DRV violations as it was happening in standalone during the earlier labs.
2. Run ECOs implementation and final SignOff STA
The other steps of the flow, to complete the full ECO loop, remain the same whether Tempus
ECO was called in regular or incremental mode except that you need to source each ECO file in
the order they were generated. So let’s run implementation of the ECOs and retime the new
Verilog/DEF/SPEF database.
You should copy the ../scripts/run_PlaceAndRoute.tcl script to

../scripts/run_PlaceAndRoute_incr.tcl and then edit it to ensure that each incremental ECO file
is correctly sourced and in the right order, like shown below:
source DRV_eco_Innovus.tcl
source SETUP_eco_Innovus.tcl
source HOLD_eco_Innovus.tcl
Then run Innovus followed by Tempus:
 innovus -nowin -init ../scripts/run_PlaceAndRoute_incr.tcl –log \
LOG_Innovus_PlaceAndRoute_incr.log
 tempus -init ../scripts/run_session3.tcl -log LOG_session3_incr.log
timing.

“Analysis” tab.

From this analysis form, you can see that there are no more Setup violations and the worst path
is now at +121ps.
Now, you know how to run a complete loop of ECO timing closure using Tempus ECO feature in
incremental mode in order to fix DRV/Setup/Hold timing violation in one single session.
You can exit the Tempus session.

Lab 2 : Hierarchical Chip Finishing with Tempus

ECO in Master/Clone mode
_____________________________________________________________________
A. Lab2.1 : Timing closure on Hierarchical design in Tempus
Overview: Demonstrate the capability of Tempus to assemble the logical and physical data of
Hierarchical design in order to perform full flat STA and physical hierarchy-aware timing closure
in a scenario where some hierarchical instances are replicated (aka Master/Clone).
Goal: The design contains two partitions which are clones because the two modules are pointing
to the same cell name. The top level netlist was implemented in parallel of the partitions. The
design must be assembled to perform full flat STA and ECO timing closure.
Location:
 cd <MY_DIR>/work_hier/
Steps:
1. Load the full flat netlist to time the design
To time the full flat netlist, all you need to provide is the complete list of Verilog for top level and
blocks. No need to load any physical data.
 cat ../scripts_hier/loadDesign_DMMMC.tcl
You can see that this file contains the recommended flow and commands to laod the full flat
netlist in Tempus.
read_view_definition ../design_hier/viewDefinition.tcl
read_verilog "../design_hier/dtmf_recvr_core.v.gz
../design_hier/results_conv.v.gz"
set_top_module dtmf_recvr_core -ignore_undefined_cell
2. Generate the ECO timing DB
The generation on the ECO timing DB is identical as for a block level design. Once the hierarchical
design is assembled, Tempus will see a full flat netlist and can perform full flat STA.
The following scripts are therefore very similar as the one reviewed in Lab 1 :
 cat ../scripts_hier/run_session1.tcl
 cat ../scripts_hier/loadDesign_DMMMC.tcl
 cat ../scripts_hier/sta.tcl

To run full flat STA and ECO timing generation, here is what must be done:
 tempus -init ../scripts_hier/run_session1.tcl -log LOG_session1.log
This will run Tempus to assemble the hierarchical design, then perform SignOff SI timing analysis
and finally dump a Timing ECO DB per view. In order to investigate the initial timing this session
ends by opening up the graphical interface. Once the run is completed, please go to the
“Analysis” tab to have a complete view of the initial Hold timing.
From this analysis form, please answer the following question:
- Are there Hold violations on paths starting/ending in the partitions? _______
In this design there are two partitions RESULTS_CONV_INST and RESULTS_CONV_INST2, pointing
to the same cell (results_conv).
From the “Analysis” tab, which does a hierarchical timing analysis, you can see that there are a
few violations on paths starting/ending in RESULTS_CONV_INST.
Those violations were seen when loading only the top level netlist or the block level netlist. It is
only when assembling the design and timing the full flat netlist that those timing violations can
be measured. This is also why there is a need to have a timing closure solution for Hierarchical
design to optimize the full flat timing view while honoring the physical hierarchies.
On the other hand, the second partition, named RESULTS_CONV_INST2, pointing to the same
cell (results_conv) is not violated in Hold. This is a typical situation of replicated modules not
having the same timing environment. The timing optimization engine will need to optimize
timing in RESULTS_CONV_INST while replicated all the change in RESULTS_CONV_INST2 and
checking that no netlist change would create negative side effects in both modules.


Now, go back to the shell and type “Resume” in order to load the Setup timing analysis in the
“Analysis” tab. This will allow you to investigate the Setup timing on the full flat netlist.
- Are there Setup timing violations? __________________
- Are there Hold violations on paths starting/ending in the partitions? _______
As for Hold timing, here we can see that some Setup timing violations are on timing paths ending
in the partitions. Either those were not well fixed at top or block level, or those paths were not
seen as violated. Once the design is assembled, the full flat STA can catch all those type of
violations and ECO fixing can find the right places to fix them, either at top level or at block level.
You can exit the Tempus session.
 ls ecoTimingDB/
In the current working directory you can see that a new directory was created and it contains the

This is the file containing the necessary commands to load the top level design with physical
data, assemble the block, apply the MMMC environment settings and run ECO timing closure
using incremental calls of eco_opt_design.
In the script you will see one new option, named “-partition_list_file”, which is to point to a file
containing the cell name of the modules that should be considered as a partition. In other words,
when a module is defined in the partition list file, all the ECOs done in that module will be
separated from the top level ECOs and a unique ECO file will be generated for it. In case of
replicated modules, like in this lab where both RESULTS_CONV_INST and RESULTS_CONV_INST2
modules are pointing to cell “results_conv”, you only need to provide the common cell name.
In this exercise we will run incremental timing closure feature in order to clean up all possible
DRV, Hold and Setup violations.
source ../scripts_hier/loadDesign_DMMMC.tcl
source ../scripts_hier/spef.tcl

set_eco_opt_mode -load_eco_opt_db ecoTimingDB
## Uncomment to get Master/Clone aware timing optimization
#set_eco_opt_mode -optimize_replicated_modules true
set_eco_opt_mode -partition_list_file ../scripts_hier/partition.txt
set_eco_opt_mode -allow_multiple_incremental true
set_eco_opt_mode -eco_file_prefix DRV

eco_opt_design -drv
set_eco_opt_mode -eco_file_prefix SETUP
eco_opt_design -setup
set_eco_opt_mode -eco_file_prefix HOLD
eco_opt_design -hold
 tempus -tso -init ../scripts_hier/run_session2.tcl –log LOG_session2.log
This will execute the script that runs Tempus ECO flow for DRV/Hold/Setup timing optimization
on a hierarchical design with two partitions.
 more LOG_session2.log
This is the log file of the fixing SignOff ECO timing fixing session. By browsing through it please
- At the end of the last call of eco_opt_design, what are the Hold timing WNS; TNS; Nb of Viol
paths? _________________

- At the end of the last call of eco_opt_design, what are the Setup timing WNS; TNS; Nb of Viol
paths? _________________
- Do you see any improvement on the DRV count ? _______________
By investigating in more details the reason for the remaining Hold violations not being fixed you
will see the following:
Hold fixing:
*info: 3 net(s): Could not be fixed because they are in or

around non-unique modules.
*info: You should apply "set_eco_opt_mode -

optimize_replicated_modules true" at the start of your ECO timing
closure flow.
FE_OFN288_n_165 (critical end point

RESULTS_CONV_INST/clear_flag_reg/SI)
RESULTS_CONV_INST/FE_OFN307_DFT_sdi (critical end point

RESULTS_CONV_INST/lower770/dout_reg[0]/SI)
RESULTS_CONV_INST/FE_OFN299_DFT_sdi_1 (critical end point

RESULTS_CONV_INST/clear_flag_reg/SI)
By default Tempus, like any other tools, would apply a don’t_touch on all replicated modules.
Tempus ECO supports Master/Clone timing optimization so let’s enable this to allow timing
optimization on the replicated modules too.
In the script “../scripts_hier/run_session2.tcl”, please uncomment the following line before the
first eco_opt_design call :
set_eco_opt_mode -optimize_replicated_modules true
Once this small script modification is done, you should make a new run of ECO timing closure
using the following command:
 tempus -tso -init ../scripts_hier/run_session2.tcl –log LOG_session2_bis.log
By investigating the log file you will see that Setup and Hold timing are now met after the
incremental timing optimization.
 more LOG_session2_bis.log
You can exit the Tempus session and check what are the ECOs being done in the ECO file. For
each optimization phase, an ECO file was generated for top level and for the cell of the
partitions.
 cat DRV_dtmf_recvr_core_eco_innovus.tcl
 cat DRV_results_conv_eco_innovus.tcl
 cat HOLD_dtmf_recvr_core_eco_innovus.tcl
 cat HOLD_results_conv_eco_innovus.tcl

 cat SETUP_results_conv_eco_innovus.tcl
 cat SETUP_dtmf_recvr_core_eco_innovus.tcl
Those file contains the ECO instruction that will be sourced in Innovus in the next step. You can
scan over them and find out that it contains a list of ecoAddRepeater/ecoChangeCell
commands, with physical information, which are natively supported by Innovus release.
3. Implement the ECOs in Innovus
 cat ../scripts_hier/run_PlaceAndRoute.tcl
 cat ../scripts_hier/run_PlaceAndRoute_block.tcl
Those two files contain the necessary commands to load the design in Innovus, either the top
level only or the block level only, then to source their respective ECO files and finally to run ECO
routing, parasitic extraction and DEF/Verilog/SPEF dump out.
 innovus -nowin -init ../scripts_hier/run_PlaceAndRoute.tcl \

-log LOG_Innovus_PlaceAndRoute.log
 innovus -nowin -init ../scripts_hier/run_PlaceAndRoute_block.tcl \

-log LOG_Innovus_PlaceAndRoute_block.log
This will perform the ECOs implementation in Innovus on top level and partition independently.
 cat LOG_Innovus_PlaceAndRoute.log
 cat LOG_Innovus_PlaceAndRoute_block.logv
By browsing the Innovus log files you can see the ECO buffers being inserted and the cell being
resized.
Do you see any instance movement? _________________
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 0.00 um
mean (X+Y) = 0.00 um
Total instances moved : 0
Indeed there is no instances movement because the ECO buffers location in the ECO files are all
fully legal both at top level and block level.
From those sessions we do also generate the final Verilog/DEF and dump new SPEFs.

4. Perform SignOff STA on the DB containing the ECOs implemented
purpose is to assemble the hierarchical design and run a D-MMMC SignOff STA. It will load the
new Verilog/DEF/SPEFs to generate timing reports and we will then be able to investigate the
final timing in the graphical interface.
 tempus -init ../scripts_hier/run_session3.tcl -log LOG_session3.log
timing.
As you could see, all Hold violations are fixed, even though those were in cloned modules.

“Analysis” tab.
- Are there remaining Setup violations? __________________
Tempus ECO was able to fix the Hold/Setup/DRV violations in many different timing views,
including replicated modules, while not creating any new Setup violations among all the Setup
timing views. The fact that this feature is Physical-Aware does provide higher timing
predictability
You can exit the Tempus session. Now you know how to run a complete loop of ECO timing
closure using Tempus ECO feature on a hierarchical design which may contained replicated
hierarchies.

Lab 3: Optimize Leakage/Timing with PBA

_____________________________________________________________________
A. Lab3.1 : Optimizing Leakage in PBA mode
Overview: Demonstrate the automated ECO leakage reclaim flow in PBA mode using Tempus
and Innovus Digital Implementation tools.
Power optimization: The initial design contains too much leakage and that must be reduced
before going to TapeOut. At signoff stage, the Path Based Analysis mode is selected, which
means that overall timing is less pessimistic, and this gives new opportunities to recover power.
Goal: The leakage power must be reduced without impacting Setup timing and without creating
any Design Rule Violations.
Location:
 cd <MY_DIR>/work_PBA/
Steps:
1. Generate ECO Timing DB in PBA mode
 cat ../scripts_PBA/run_session1.tcl
D-MMMC SignOff timing analysis run on 12 actives views.
 cat ../scripts_PBA/loadDesign.tcl
This file contains the design data that must be loaded to perform a D-MMMC SignOff timing
analysis. This one also is a standard file, except that LEF/DEF data are being loaded.
 cat ../scripts_PBA/sta.tcl
This file contains the SPEF files location and the SignOff SI timing analysis settings/reporting
commands. At the end of the file, the only needed command to generate an ECO Timing DB is
write_eco_opt_db.
In this exercise we will generate ECO Timing DB in PBA mode for both Setup and Hold timing.
### PBA Setup and Hold ECO Timing DB generation
set_eco_opt_mode -check_type both
set_eco_opt_mode -retime aocv_path_slew_propagation
set_eco_opt_mode -nworst 1000
set_eco_opt_mode -save_eco_opt_db ECO-PBA
write_eco_opt_db

There are 4 main options for PBA mode:
-retime : to choose which kind of retiming you are enabling
-check_type : to choose whether retiming should be done for early or late paths, or both.
-max_slack : to choose up to which path slack the retiming should happen. By default this
option is at 0, but when optimizing Hold or Leakage, it is recommended to set it to a large value
(like +10ns) for Setup views to make sure that even positive setup slack paths get retimed.
-nworst : to choose how many paths per endpoint should be retimed. It is important to set a
high value to ensure that enough paths are retimed.
-max_paths : to choose a maximum amount of total paths to be retimed
 tempus -init ../scripts_PBA/run_session1.tcl -log LOG_session1.log
This will run TEMPUS to perform SignOff SI timing analysis in PBA mode, generate Timing ECO DB
per view in PBA mode and ends by opening up GTD for timing investigation. Once the run is
completed, please go to the “Analysis” tab to have a complete view of the initial timing.
The script will print timing in this order:
1) Setup in GBA mode

2) Setup in PBA mode
3) Hold in GBA mode
4) Hold in PBA mode
Note: You need to type “resume” to move to the next timing report
From those four timing analysis forms, you should see that:
- Setup timing is met in GBA mode

- Setup timing is met in PBA mode and timing is slightly better than in GBA mode
- Hold timing is violated in GBA mode
- Hold timing is violated in PBA mode and timing is slightly better than in GBA mode
You can exit the TEMPUS session.
 ls ECO-PBA/
In the current working directory you can see that a new directory was created and it contains an
2. Run Tempus ECO for Leakage optimization
 cat ../scripts_PBA/run_session2_leakage.tcl
This is the file containing the necessary commands to load the design with physical data, to load
the MMMC environment settings and to set up the Tempus ECO fixing feature command called
eco_opt_design.

source ../scripts_PBA/loadDesign.tcl
source ../scripts_PBA/spef_new.tcl
set_analysis_mode -aocv true -cppr both

set_eco_opt_mode -load_eco_opt_db ECO-PBA
set_eco_opt_mode -swap_inst true -optimize_sequential_cells true
set_eco_opt_mode -optimize_core_only true
eco_opt_design –leakage
For leakage optimization it is recommended to allow sequential cell optimization.
 tempus -tso -init ../scripts_PBA/run_session2_leakage.tcl –log LOG_session2_leakage.log
This will execute the script that runs Signoff ECO Leakage optimization.
 more LOG_session2_leakage.log
This is the log file of the SignOff ECO Leakage optimization session. By browsing through it please
- What is the initial leakage power? _________________
- What are the initial Setup timing WNS; TNS; No. of Viol paths? _________________
- What is the initial DRV count? _________________
- Do you see any degradation in the final Setup timing or DRV? _______________
(The setup target slack is 0ns, so tool is allowed to degrade positive path slack down to 0ns when
recovery leakage)
- How many instances were swapped? ____________
- What is the final leakage power? ____________
You can exit the TEMPUS session and check the ECOs being done in the ECO file.
 cat eco_innovus.tcl
This file contains the ECO instruction that can be sourced in Innovus to implement the ECOs
done during leakage recovery. In this Lab we will skip that step and directly retime the design
with the ECOs since leakage optimization does only Vth swapping, so no change in placement
and routing.
3. Perform SignOff STA on the DB containing ECOs from leakage optimization
 cat ../scripts_PBA/run_session3_leakage.tcl
purpose is to run a D-MMMC SignOff STA in PBA mode. It will load the Verilog/DEF/SPEFs, then

source the ECO file generated during leakage optimization and then generate timing reports in
PBA mode to investigate the final timing in the graphical interface.
 tempus -init ../scripts_PBA/run_session3_leakage.tcl -log LOG_session3_leakage.log
timing.
The script will print timing in this order:
1) Setup in GBA mode

2) Setup in PBA mode
3) Hold in GBA mode
4) Hold in PBA mode
Note: You need to type “resume” to move to the next timing report
From those four timing analysis forms, you should see that:
- Setup timing is now violated in GBA mode. This is expected and it proves that the leakage
recovery engine took advantage of the lesser pessimistic PBA timing when optimizing
leakage.
- Setup timing is still met in PBA mode. This is mandatory since leakage recovery engine had
to ensure that no Setup violations would be created in PBA mode.
- Hold timing is still violated in GBA mode, but lesser than initially
- Hold timing is still violated in PBA mode, but lesser than initially
You can exit the TEMPUS session. You now know how to run leakage optimization in PBA mode.

Lab 4: Running Tempus ECO in Innovus

_____________________________________________________________________
A. Lab4.1 : Optimizing DRV/Hold in PBA mode
Overview: Demonstrate the usage of Tempus ECO inside Innovus cockpit. In this first section,
we will go over a basic Hold fixing flow.
Timing violations: The initial design contains a few Hold timing violations that must be fixed
before going to TapeOut. At the same time we will fix the remaining DRV violations.
Goal: Fixing Hold timing violations without impacting Setup timing or creating any Design Rule
Violations. All timing reports and optimization must be done in PBA mode.
Location:
 cd <MY_DIR>/work_SOD/
Steps:
1. Run DRV/Hold fixing in PBA mode in Innovus cockpit
 cat ../scripts_SOD/run_SOD.tcl
setDistributeHost -local -timeout 3000

setMultiCpuUsage -localCpu 16 -remoteHost 4 -cpuPerRemoteHost 4
restoreDesign ../design_SOD/forSOD.enc.dat dtmf_recvr_core
setExtractRCMode -coupled true
extractRC
setAnalysisMode -aocv true

setSignoffOptMode -retime aocv_path_slew_propagation -check_type both
-max_paths 10000000 -nworst 100
setSignoffOptMode -alongRouteBuffering true
setSignoffOptMode -routingCongestionAware true
setSignoffOptMode -saveEcoOptDb ecoTimingDB_PBA

signoffTimeDesign -reportOnly -outDir RPT_PBA
setSignoffOptMode -loadEcoOptDb ecoTimingDB_PBA
signoffOptDesign -noEcoRoute -drv

signoffOptDesign -noEcoRoute -hold
ecoRoute
extractRC
signoffTimeDesign -reportOnly -outDir RPT_PBA_final -noEcoDb

signoff Timing analysis in Innovus using signoffTimeDesign command and signoff Timing
optimization using signoffOptDesign command.
Innovus will use the Tempus executable pointed in the PATH environment variable.
Once ready, run the following command in your shell :
 innovus -init ../scripts_SOD/run_SOD.tcl -log LOG_SOD.log
This will load the initial DB, run parasitic extraction, then call signoffTimeDesign to perform
SignOff SI timing analysis in PBA mode (and generate Timing ECO DB per view in PBA mode),
then call signoffOptDesign to fix DRV/Hold violations. After that the script will run ECO routing
and parasitic extraction, then ends with a final signoffTimeDesin to perform SignOff SI timing
analysis in PBA mode.
##### Initial timing summary from signoffTimeDesign

----------------------------------------------------------------------------------
signoffTimeDesign Summary
----------------------------------------------------------------------------------
+--------------------+-----------+-----------+-----------+-----------+-----------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out |
+--------------------+-----------+-----------+-----------+-----------+-----------+
| WNS (ns):| 1.383 | 1.383 | N/A | N/A | N/A |
| TNS (ns):| 0.000 | 0.000 | N/A | N/A | N/A |
| Violating Paths:| 0 | 0 | 0 | 0 | 0 |
+--------------------+-----------+-----------+-----------+-----------+-----------+
+----------------+-------------------------------+------------------+
| | Signal nets | Clock nets |
| DRVs +------------------+------------+------------------+
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 ( 0) | 0 | 0 ( 0) |
| max_tran | 1 ( 1) | -0.002 | 3 ( 3) |
| max_fanout | 0 ( 0) | 0 | 0 ( 0) |
+----------------+------------------+------------+------------------+
+--------------------+-----------+-----------+-----------+-----------+-----------+
| Hold mode | all | reg2reg | in2reg | reg2out | in2out |
+--------------------+-----------+-----------+-----------+-----------+-----------+
| WNS (ns):| -0.058 | -0.058 | N/A | N/A | N/A |
| TNS (ns):| -0.124 | -0.124 | N/A | N/A | N/A |
| Violating Paths:| 4 | 4 | 0 | 0 | 0 |
+--------------------+-----------+-----------+-----------+-----------+-----------+
##### Final timing summary from signoffTimeDesign

+--------------------+-----------+-----------+-----------+-----------+-----------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out |
+--------------------+-----------+-----------+-----------+-----------+-----------+
| WNS (ns):| 1.383 | 1.383 | N/A | N/A | N/A |
| TNS (ns):| 0.000 | 0.000 | N/A | N/A | N/A |
| Violating Paths:| 0 | 0 | 0 | 0 | 0 |
+--------------------+-----------+-----------+-----------+-----------+-----------+
+----------------+-------------------------------+------------------+
| | Signal nets | Clock nets |

| DRVs +------------------+------------+------------------+
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 ( 0) | 0 | 0 ( 0) |
| max_tran | 0 ( 0) | 0 | 3 ( 3) |
| max_fanout | 0 ( 0) | 0 | 0 ( 0) |
+----------------+------------------+------------+------------------+
+--------------------+-----------+-----------+-----------+-----------+-----------+
| Hold mode | all | reg2reg | in2reg | reg2out | in2out |
+--------------------+-----------+-----------+-----------+-----------+-----------+
| WNS (ns):| 0.007 | 0.007 | N/A | N/A | N/A |
| TNS (ns):| 0.000 | 0.000 | N/A | N/A | N/A |
| Violating Paths:| 0 | 0 | 0 | 0 | 0 |
+--------------------+-----------+-----------+-----------+-----------+-----------+
From those reports, you should see that:
- Initial Setup timing is met in PBA mode but there are half a dozen Hold violations and some
small DRV violations.
- After running Tempus ECO in Innovus, all DRV/Hold violations are be fixed and Setup timing
remains unchanged
You can exit the Innovus session.

_____________________________________________________________________
B. Lab4.2 : Optimizing Leakage in PBA mode
Overview: Demonstrate the usage of Tempus ECO inside Innovus cockpit. In this second section,
we will go over a basic Leakage recovery flow.
Goal: Recovering leakage power in PBA mode with not creating any timing violations in PBA
mode.
Location:
 cd <MY_DIR>/work_SOD/
Steps:
1. Run Leakage recovery in PBA mode in Innovus cockpit
 cat ../scripts_SOD/run_SOD_leakage.tcl
setDistributeHost -local -timeout 3000

setMultiCpuUsage -localCpu 16 -remoteHost 4 -cpuPerRemoteHost 4
restoreDesign ../design_SOD/forSOD_power.enc.dat dtmf_recvr_core
setExtractRCMode -coupled true
extractRC
setSignoffOptMode -retime aocv_path_slew_propagation -check_type both

-max_paths 10000000 -nworst 100
setSignoffOptMode -maxSlack 10 -pbaEffort high
setSignoffOptMode -optimizeSequentialCells true
setSignoffOptMode -setupTargetSlack 0
setSignoffOptMode -saveEcoOptDb ecoTimingDB_PBA_leakage

signoffTimeDesign -reportOnly -outDir RPT_PBA_leakage
setSignoffOptMode -loadEcoOptDb ecoTimingDB_PBA_leakage
report_power -leakage
signoffOptDesign -noEcoRoute -leakage
signoffTimeDesign -reportOnly -outDir RPT_PBA_leakage_final -noEcoDb
report_power –leakage
signoff Timing analysis in Innovus using signoffTimeDesign command and Leakage optimization
on signoff Timing optimization using signoffOptDesign command.
The main two differences compared to the DRV/Hold fixing flow is earlier section are:
1) The PBA retiming is applied to positive GBA slack paths by using

“-maxSlack 10” option. This will create even more positive slack paths which
can be then used for extra Leakage recovery.

2) In order to ensure highest PBA coverage in the timing see by signoffOptDesign,

the option “-maxSlack 10” is applied.
Once ready, run the following command in your shell:
 innovus -init ../scripts_SOD/run_SOD_leakage.tcl -log LOG_SOD_leakage.log
This will load the initial DB, run parasitic extraction, then call signoffTimeDesign to perform
SignOff SI timing analysis in PBA mode (and generate Timing ECO DB per view in PBA mode) in
high effort PBA mode with positive GBA slack path retiming, then call signoffOptDesign to
recover leakage. After that the script ends with a final signoffTimeDesin to perform SignOff SI
timing analysis in PBA mode.
By looking at the log file you will see that “report_power –leakage“ command is showing
the following improvement:
Before Leakage optimization: Total leakage power = 0.00706167 mW
Afer Leakage optimization : Total leakage power = 0.00648306 mW
From those steps, you should see that:
- No PBA Setup timing violations are created during Leakage optimization. All DRV/Hold
violations are be fixed
- Leakage power reduction is ~8%
You can exit the Innovus session.


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Cadence Design Systems, Inc.

RAPID ADOPTION KIT

Timing Signoff Optimization

Lab Instruction Document

COPYRIGHT © 2016, CADENCE DESIGN SYSTEMS, INC.

Tempus ECO - LABS

At the end of the session, you will be able to:

 Explain how to investigate timing in an SignOff STA environment

 Understand and explain the timing ECO methodology

 Perform Hold, Setup and DRV timing fixes through ECOs

 Report and analyze ECO results

 Implement the ECOs in Innovus Digital Implementation

 Verify final SignOff STA

 Assemble a Hierarchical design in Tempus for STA and ECO fixing

 Perform Hierarchical aware Chip Finishing with timing ECOs

 Time the design in Path Based Analysis mode

 Optimize leakage/timing in Path Based Analysis mode

 Run Tempus Eco from Innovus cockpit

COPYRIGHT © 2016, CADENCE DESIGN SYSTEMS, INC.

A. How to get the RAK Database

The lab directory structure is as follows:

COPYRIGHT © 2016, CADENCE DESIGN SYSTEMS, INC.

C. Tools and Scripts

D. Terminology and Typographical Conventions

Please note the follow key acronyms:

ECO = Engineering Change Order

Tempus = Cadence SignOff STA tool

Innovus = Cadence Implementation tool

AAE = Name of the delay calculation engine (Advanced Analysis Engine)

MMMC = Multi Mode Multi Corner

view = Combination of a corner and a timing mode

D-MMMC = Distributed MMMC timing analysis environment in Tempus

DRV = Design Rule Violation, such as max_cap and max_tran.

STA = Static Timing Analysis

PBA = Path Based Analysis

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The sample testcase is a generic DTMF design, it contains:

 Approximately 10k instances

 Sequential, combinational, and state machine logic

 The following hard macros: PLL, RAM, and ROM.

 36 Views ( 2 libraries x 6 corners x 3 modes ) :

o Libraries are : Worst and Typical

o Corners are : Cmax, RCmax, Rmax, Cmin, RCmin, Rmin

o Modes are : Functional, Test, Scan

1. Generate the ECO Timing DB:

2. Run Tempus ECO timing fixing session:

3. Implement the ECOs using Innovus Digital Implementation tool:

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4. Perform SignOff STA on the new DB containing the ECOs:

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Lab 1: MMMC SignOff at block level

A. Lab1.1 : Fixing Hold timing violations

1. Generate ECO Timing DB

set_multi_cpu_usage -localCpu 16 –remoteHost 4 –cpuPerRemoteHost 4

distribute_views -views [list func_slow_CMAX func_fast_CMAX

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read_lib -lef {../libs/lef/FreePDK45_lib_v1.0.lef

report_constraint -all_violators > rep.vio.gz

report_timing -late -max_slack 0.0 -max_paths 1000 \

 tempus -init ../scripts/run_session1.tcl -log LOG_session1.log

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From this analysis form, please answer the following questions:

- Are there Hold timing violations in all the views? __________________