IEEE 1999 International Conference on Power Electronics and Drive Systems, PEDS’99, July 1999, Hong Kong.

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PLECS Piece-wise Linear Electrical Circuit Simulation for Simulink
Jost H. Allmeling and Wolfgang P. Hammer
Power Electronics and Electrometrology Laboratory
Swiss Federal Institute of Technology (ETH) Zurich
8092 Zurich, Switzerland

Abstract - In this paper a new toolbox, PLECS, for the fast
simulation of power electronic circuits under Simulink is present-
ed. This toolbox provides the means for modeling large power
electronic systems containing both electrical circuits and control-
lers. The program is based on a state-space formulation for cir-
cuits that consist of linearelements (RLC), transformers, sources,
meters, and ideal switches. Diodes,thyristors, IGBTs and other
nonlinear elements such as saturable inductors can be assembled
by combining linear elements and switches. Thus, a piece-wise
linear model is attained which leads to a stable and fast simula-
tion. An attached benchmark simulation demonstrates the capa-
bility of PLECS.
I. INTRODUCTION
The development of power electronic systems usually in-
volves the design of both the electrical circuit and the control
algorithms. To study the behavior of these systems thoroughly
simulation is essential.
For the simulation of purely electrical circuits powerful pro-
grams like Spice and Saber exists. They allow the user to enter
the circuits as netlists or schematics. However, incorporating
complex control structures requires a thorough knowledge of
the specific program.
Simulink, an extension to Matlab, is a program for simulat-
ing dynamic systems. It is widely used for the simulation of
control systems, since even complex structures can be built
easily and Matlab provides powerful evaluation of the simula-
tion results. Therefore, Simulink is also convenient for the de-
sign of closed loop controlled power electronic systems.
However, systems containing electrical circuits cause difficul-
ties, in that they cannot be modeled in a straightforward way.
Simulink accepts neither schematics nor netlists for electrical
circuits. Instead they must be represented by mathematicalfor-
mulae - be it state-space equations or nodal formulation -
which must be set up individually for every topology. This pro-
cess is time-consuming and error-prone.
Since summer 1998 the Power System Blockset is available
[l]. This toolbox allows the user to combine the electrical sys-
tem and the controller in one system model by entering the cir-
cuit diagram at Simulink block level. Although the Power
System Blockset also contains components such as diodes and
GTOs the extensive use of these elements leads to very long
simulation times. Furthermore, ideal elements like switches re-
quire snubber circuits to make the simulation converge. Thus,
this toolbox is not well suited for simulating large power elec-
tronic systems.
The Power System Blockset models semiconductors and
switches as inductances in parallel with current sources to
make the simulation continuous even during switching actions.
When simulating complex power electronic systems, however,
the processes during switching are of little interest. Here, the
use of ideal instantaneous switches is more appropriate. Firstly
this yields systems that are linear between two switching in-
stances. Secondly, to handle the discontinuities at the switch-
ing instances only two integration steps are required. Both
speed up the simulation considerably. The application of ideal
switches in circuit simulation programs has been described in
[2]-[4]. To achieve the goal of improving simulations under
Simulink by the use of ideal switches, a new tool had to be de-
veloped.
11. USING PLECS
This paper presents PLECS, a toolbox for piece-wise linear
simulation of electrical circuits within the Simulink environ-
ment. Circuits to be simulated with PLECS may consist of ide-
al resistors, inductors, capacitors, transformers, voltage and
current sources, meters, and switches. These latter elements -
sources, meters, and switches - form the interface between the
electrical circuit and the control system. This points towards
modeling the electrical circuit as one single Simulink sub-
system. Its inputs are the commands for controlled sources and
switches. Measurements taken by the volt- and ammeters are
provided as the subsystem’s outputs.
Circuits are defined by an input file which has a format sim-
ilar to the Saber input file format. They can be arbitrarily as-
sembled using the built-in ideal components or user-defined
templates. Templates are compound components or sub-cir-
cuits that in turn consist of templates or built-in components.
PLECS provides linear elements and switches. At any time
the switches in PLECS are either short or open circuits. This
means that before and after the instant of switching the circuit
is purely linear and hence its overall behavior is piece-wise lin-
ear.
Nonlinear components, e.g. a saturable inductor, may be ap-
proximated as piece-wise linear by combining linear elements
and switches. True nonlinearities must be modelled by voltage
controlled current sources (or vice versa), the characteristics of
which are computed in an external feedback loop. This meth-
od, however, reduces the performance and should therefore be
used minimally.
Switches are also the basis for power electronic compo-
nents. They can be controlled externally or internally or a com-

355
 bination of both. External in this context means that the control
signal does not directly depend on voltages or currents in the
circuit but is instead supplied by the overlaying control system.
Examples for externally controlled switches are breakers and
half-bridges of VSIs. Internal control variables are voltages or
currents that can be measured in the circuit. The simplest ex-
ample of a purely internally controlled switch is a diode, which
is switched on by a positive voltage and off by a negative cur- Fig. 1: Buck converter
rent. Power electronic components such as thyristors, GTOs
and IGBTs operate according to a logical combination of ex-
ternal and internal switching conditions.

Example: Buck Converter

As an example, Fig. 1 to Fig. 3 show the schematic of a buck
converter, its implementation model in PLECS, and the corre- grid I I
sponding netlist. The voltage source v-src between the Fig. 2: Implementation model of the buck converter
nodes nl and gnd is controlled by the signal input-1
which is imported from Simulink. The transistor is modelled as v.v-src nl gnd << input-1
the ideal switch s-T controlled by the imported signal s . s-T nl n2 <% (gate-1 ! = 0)
gate-1. The switch is closed when the first condition is true, (gate-1 == 0)
i.e. gate-1 is not equal zero. The second condition opens am. am-D n3 n2 >> i-D
the switch. vm .vm-D gnd n3 >> v-D
The ammeter am-D and the voltmeter m - D measure s. s-D gnd n3 <% (v-D > 0 )
the current through and the voltage across the diode. Their out- (i-D < 0)
puts are used in the switching conditions of the internally con- am. am-L n2 n4 >> output-1
trolled switch s-D. When the voltage across the diode l.L n4 n5 = .1
becomes positive the diode starts conducting. The diode blocks r.R n5 n6 = . 0 5
when the current becomes negative. c.c n6 gnd = le-3
The current measured by the meter am-L is exported back r.G n6 gnd = 10
to Simulink. There, it can be viewed with a scope or used in a Fig. 3: Netlist for the buck converter
control loop, e.g. a hysteresis type control (Fig. 4).

III. STATE-VARIABLE EQUATIONS

10 -
T
-
v src
4 U
PLECS y
A. Setting up the Equation System
i-ref + i-L
The algorithm of PLECS is based on state-variable equa- Sum Relay: +/-O.!j Buck converter
tions, where the states represent storage components i.e. induc-
Fig. 4: Sirnulink model of the controlled buck converter
tors and capacitors. A circuit containing only linear
components can be described mathematically by one set of dif-
ferential equations: law. A circuit with e arbitrary elements, i.e. branches, and n
nodes has e - ( n- 1) independent mesh equations and n - 1
x = Ax+Bu (1)
independent node equations. In these equations the voltages
y = Cx+Du (2) and currents of switch elements are left undetermined. After
the elimination of dependent variables, e.g. by applying Ohm's
If the circuit contains one or more switches every combina- law to resistors, the reduced generic equation system describ-
tion (3 of switch positions yields a different linear circuit to-
ing the circuit is obtained. It is valid for any combination of
pology and therefore a different set of equations characterized
switch positions. The variables are ordered as follows:
by the matrices A , , B , , C , ,and D , .Having n switches the
system could have 2" different topologies. Thus, even if not T
all of the 2"topologies are needed in a simulation, the state [x Y I s x U] (3)
space approach is only practical if the matrices can be generat- where:
ed automatically.
For this purpose the independent mesh and node equations
must be set up according to Kirchhoff s voltage and current
i= [.vc e']
1L
T
(state derivatives) (4)

356
 T For example, for a conducting transistor (i.e. vT = 0 ) and a
y = [vout iouJ (output variables) (5) blocking diode (i.e. i, = 0 ) the specific equation system has
the following form, where the matrices A , , B , , C , , D , are
s = [vs idT (undetermined switch variables) (6) indicated:

x = [vc idT (state variables) (7) 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0
U = [v,, isrJT (input variables) (8)

In order to derive the matrices A , , B , , C , ,and D , for a

specific topology from this generic equation system the voltag-
es across closed switches and the currents through open
switches are set to zero. Then the equation system is trans- 0 0 0 0 0 0 1 0 0 0 0 1
formed to the reduced row echelon form using Gauss Jordan 0 0 0 0 0 0 0 1 0 0 - 1 0 -
elimination with partial pivoting. In the reduced row echelon
form A , , B , , C , ,and D , appear as sub-matrices:

1 0 0 0 0 0 0 0 0
(9)

0 1 0 0 0 0 0 0 0
I represents the identity matrix. The rows marked with X 0 0 1 0 0 0 0 0 0
contain additional information about the switch variables
0 0 0 1 0 0 0 0 0
which is of no further interest here.
0 0 0 0 1 0 0 0 0
Example: Buck Converter 0 0 0 0 0 1 0 0 0
10 0 0 0 010 0 0 1 0 -1 o]
This method is illustrated using the example of the buck
converter. The independent mesh and node equations are:
B. Implementation in Simulink
0 = VT-VD-V,, (10) The state-space equations are embedded in Simulink by
means of an S-Function which is entirely programmed in C.
iL.L = -vD-vC-iL. R (11) The interaction between this S-Function and Simulink is out-
lined in Fig. 5. At any integration step the actual states x and
0 = iT+iD-iL (12)
inputs U are fetched from the model workspace. The state de-
rivatives iare then computed according to (1) and passed on
vc.C = -vc.G+iL (13) to the Simulink solver. There, they are integrated along with
The output variables are: the control system. The user has the choice between various
solving algorithms offered in Simulink’s simulation parame-
ters menu.
At the same time, the system outputs y are calculated ac-
This yields the generic equation system: (15) cording to (2) and written back to the model workspace. The
switch manager decides which set of matrices has to be used.
This decision is based on the system outputs and the gate in-
puts g .
0 0 0 0 0 1 - 1 0 0 0 0 - 1
IV. CONTROL OF IDEAL SWITCHES
O L O O O 0 -1 0 0 -1 -R 0
0 0 0 0 0 0 0 1 1 0 - 1 0 The switch manager constantly monitors the system output
c o o o o 0 0 0 0 - G 1 0 and the gate signals and compares them with the thresholds
0 0 1 0 0 0 1 0 0 0 0 0 given in the switching conditions. The switching conditions
0 0 0 1 0 0 0 0 1 0 0 0 form the boundary of a specific topology’s validity. If any
boundary condition is violated the switch manager toggles the
0 0 0 0 1 0 0 0 0 0 1 0
respective switch(es).

357
 It has been pointed out in section I11 that the number of pos-
sible topologies increases exponentially with the number of
switches used in the circuit. However, not all of these topolo-
gies are actually needed. Therefore it is not practical to calcu-
late all of them in advance. Instead, they are computed as they
are encountered during the simulation. The most recently used
matrices are cached in order to further reduce the computation-
al effort.

A. Dirac Impulses in Switched Circuits

As has been described in detail in [2]-[4] the toggling of ide-

al switches may lead to Dirac impulses due to inconsistent ini-
tial conditions in the new topology. As an example consider
the buck converter in Fig. 1. The transistor T is conducting and
hence the diode D blocks. The inductor current iL builds up
until a time t, when T is opened. In the new topology (T and given x, U ,g,d
D open) iL would be forced to zero resulting in an impulsive
voltage across the inductor. The total voltage vD across the di-
ode can then be calculated as
r i f l

The positive impulsive part of vD indicates that the diode

must become conducting regardless of the non-impulsive part.
In the following topology (T open and D closed) the initial
conditions are consistent and the simulation can be continued.
In order to represent (20) on a computer the system output is
split into two parts. In addition to the non-impulsive part given
by (2), an output impulse-multiplier can be defined which is violated?
implicitly associated with the Dirac impulse:
Simulink

Fig. 6: Flow chart of the switch manager

The individual matrices C:' and 0:' for each topology

are derived using an approach similar to that described in sec-
tion III. After toggling one or more switches y") can easily be
checked for the presence of Dirac impulses. If y @ ) is non-zero
it will overrule y in the evaluation of the switching conditions.
This procedure of finding a new topology with consistent
initial conditions is outlined in Fig. 6. If during this process any
topology is encountered twice, this indicates that the iteration
over t s has become an infinite loop since no topology satisfy-
ing the boundary conditions could be found. In such a case the
simulation is aborted.
B. Tracking the Switching Instants
For an accurate simulation it is vital to find the exact in-
stances at which the boundary conditions are violated and
therefore a switching occurs. Consider for example a diode
connected in series with an inductor. The diode may open only
when the inductor current is zero within machine precision. If
this instant is missed the non-zero current will produce a Dirac
voltage across the inductor which may lead to false results or
an aborted simulation.
In order to hit the exact switching instants PLECS employs
Simulink's zero crossing detector. The boundary conditions
are formulated as continuous functions in which zero repre-
sents the boundary. These functions are constantly monitored
by the Simulink solver. If the sign of any function changes be-
tween two integration steps, i.e. a boundary has been over-
stepped, the solver automatically steps back and performs a
bisection style search to track the exact instant of the zero
crossing.
V. APPLICATION EXAMPLES
In this section, two examples will be discussed that show the
ease of use, the accuracy, and the speed of PLECS. The first
example is a simple switched network which has been used al-
ready in [2] because its response can be calculated analytical-
ly. The second example contains thyristors as switches that are

358
controlled both by internal and external conditions. For com-
parison both examples are also simulated with the Power Sys-
tem Blockset and with Saber. All simulations have been
performed on a Sun Ultra 1C/200 MHz.

A. Example I : Switched RC network

Fig. 7: Switched RC network
Fig. 7 shows the schematic of a RC network. The switches
s s
S and operate in anti-phase. When S is closed and open the
capacitor C is charged via the resistors RI and R2. When S is
open and 5 closed C is discharged through R2. The capacitor U
PLECS y
voltage vc is used in a control loop as shown in Fig. 8. Sim- 9
ulink generates a repeating sequence in which the signal rises Switched RC
linearly from 0 to 10 V in 4.9 ms and falls back to 0 in 0.1 ms.
This ramp is compared with VC. As long as vc is greater than Fig. 8: Simulink model of the switched RC example
the ramp signal switch S is closed, otherwise open. The closed
form steady state solution for the circuit is easily determined
(121).
When S has been closed at t = t l ,the capacitor voltage is
L

When S has been opened at t = t 2 , the capacitor voltage is

1 - I,
5 104-.. . . . . . . ... . _ .. _. . .
5
!
The resulting capacitor voltage in steady state operation and
the ramp signal are depicted in Fig. 9(a). Fig. 9(b) shows the
relative error of the simulated capacitor voltage with respect to
the analytical solution. The corresponding simulation times for
a time span of 0.1 s are listed in Table I. Of course, in all pro-
'
0 2 4 6 8 10
time (ms)
grains there is a trade-off between the requested accuracy and
the resulting speed. The poor accuracy of the Power System Fig. 9: (a) Capacitor voltage and ramp signal. (b) Relative errors
of the simulation results compared to the exact solution
Blockset stems from the snubber circuits that have to be used
with any kind of switch. TABLE I
Simulation times for the circuit in Fig. 7 for a time span of 0.1 s
B. Example 2: 6-Pulse Controlled Rect$er Simulation Program CPU time
The schematic of a 6-pulse rectifier is outlined in Fig. 10. Simulink / Power System Blockset 33.49 s
The 3-phase grid is modelled by the 170V/50Hz voltage Saber 6.58 s
sources Va,b,c and the impedance LN = 0.001 H. The DC load is Simulink / PLECS 0.34 s
represented by the resistor RL = 1 4 the inductance LL =
0.02 H, and the voltage source vL = 120 V.
The thyristors of the rectifier exemplify switches controlled In order to ensure a proper start-up of the valve group the
by both external and internal conditions: A thyristor can be reference signal for the DC current iref is kept equal to zero for
fired only if there is a positive voltage from anode to cathode the first 10 ms until the pulse generator is synchronized. After
and will extinguish when the current becomes negative. this period it ramps up linearly to 10 A within 20 ms. At t =
The DC current id is controlled in a feedback loop according 60 ms irefsteps to 25 A.
to Fig. 11. The difference between the reference current i,f The simulation results for id and the DC voltage Vd are given
and id is fed into a PI-controller. Its output is used as the alpha in Fig. 12. For this model an analytical solution can not be ob-
order to generate the firing pulses for the thyristors. The pulse tained easily so that the accuracy cannot be determined. How-
generation is synchronized with the line to line voltage at the ever, all three results show good accordance. The simulation
rectifier input. times for a time span of 0.1 s are listed in Table 11.

3 59
C. Other Applications

PLECS has been extensively used in various projects of the

Power Electronics and Electrometrology Laboratory. In these

-
projects, hard- and soft-switching converter and rectifier sys-
tems are investigated. Special interest is taken in the develop-
ment of fast control algorithms.
The largest of the simulation models consists of 24 switches
and 20 state variables. However, this is not a limit for the size
of systems that can be simulated with PLECS.
Fig. 10: 6-pulse controlled rectifier

VI. CONCLUSIONS

PLECS has been proven as a useful tool for the simulation line to line voltages
of arbitrary electric, especially power electronics circuits in a
Simulink control environment. Circuits are entered as netlists out@g
U
PLECS y d ?
c DC current
and seamlessly integrated into Simulink as S-functions. Thus, v-1-1
full benefit can be taken from Simulink’s highly accurate inte- 6-Pulse Rectifier
gration algorithms. alpha

Pulse
Switches are modeled as short and open circuits, the actual generator
state of which may depend on internal and external conditions.
The use of Simulink’s zero crossing detection ensures that the alpha i-en
exact switching instants are hit.
For models where ideal switches are to be simulated PLECS Pl-controller
i-ref
is superior to both circuit simulation programs such as Saber
and the existing Power System Blockset regarding speed, ac-
curacy and stability.
.
Fig. 11: Sirnulink model of the 6-pulse conuolled rectifier

30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REFERENCES

1. P. Barnard, “New Power System Blockset Enables You to

Model Electrical Power Systems”, Matlab Newsletter, 0‘
pp. 1&11, Summer 1998 .............................

2. D.Bedrosian and J. Vlach, “Time-Domain Analysis of

Networks with Internally Controlled Switches”, IEEE
Transactions on Circuits and Systems - I, vol. 39, no. 3,
pp. 199-212, Much 1992
3. R. J. Dirkman, “The Simulation of Circuits Containing
Ideal Switches”, IEEE Power Electronics Specialists
Conference, pp. 185-194, June 1987 ”
0 0.02 0.04 0.06 0.08 0.1
4. A. Massarani, U. Reggiani and M. K. Kazimierczuk, time (s)
“Analysis of Networks with Ideal Switches by State
Fig. 12: Simulation results for the circuit in Fig. 10
Equations”, IEEE Transactions on Circuits and
Systems - I, vol. 44,no. 8, pp. 692-697, August 1997 TABLE 11
Simulation times for the circuit in Fig. 10 for a time span of 0.1 s

CPU time

Saber 39.30 s

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