Research Article

A low power 10 bit SAR ADC with variable threshold technique

for biomedical applications
Kiran Kumar Mandrumaka1 · Fazal Noorbasha1

© Springer Nature Switzerland AG 2019

Abstract
This paper presents two low power design techniques used for successive approximation registers (SAR) analog-to-digital
converter (ADC) for transmission of Physiological signal: Dual split switching; set and reset phase. Dual split switching
is used in one sided charge scaling digital-to-analog converter (DAC) to edge of the switching energy by reducing the
leakage in dual transmission gate. The set and reset phase defines the amplification and comparison phase of the com-
parator. The delay time of the comparator is profoundly reduced with folded cascoded pre amplifier and a regenerative
latch. A Serial In Parallel Out (SIPO) N bit register and SAR are designed with negative edge triggered D Flip-Flop (DFF).
For power optimization the supply voltage of SAR ADC is designed with 500 mV. The Variable threshold concept has
been utilized in the entire design to operate the SOC with 500 mV supply voltage. The designed SAR ADC is capable of
supporting the sampling rate of 1 Msps. The circuit is designed using standard UMC 180 nm technology. The simulation
results show that the power consumption of the SAR ADC is 13.99 μW and achieved 68.54 dB SFDR with ENOB value 7.69
bits. The DNL (max) is + 0.9/− 0.82 LSB and INL 1.06/− 1.31 LSB.

Keywords  Low power · Dual split switching · Physiological signals · SAR ADC · Variable threshold · Negative edge
triggered DFF

1 Introduction is edged off and operates with lower threshold voltages,

In the recent years the development of biomedical appli-
cations in wireless communication has become very pop-
ular [1, 2]. The research on Electrocardiogram (ECG) and
Electroencephalogram (EEG) acquisition boards are giving
impeccable results in the biomedical applications [1, 2].
The role of bio signal acquisition board is to collect bio
signals from the human body which are weak in amplitude
and frequency and transmit in digital form after amplifi-
cation. So, for continuous transmission of physiological
signals, a battery life is required to prolong the work time
and the device size should get reduced to be implanted
on the human body. Most importantly, high data accu-
racy should be maintained [3–10]. While going towards
advanced CMOS processes, the benefits are: feature size
but leakage currents will play dominant role in the power
consumption. Therefore, besides accommodating a small
supply voltage, we need to minimize the leakage power
to achieve better power efficiency. While transmitting the
physiological signals through wireless, high data accuracy
should be required because the neural signals are weak
in amplitude (< 100 μV) and weak in frequencies (few Hz
to below 100 Hz) [7, 8]. Physiological signals are the pure
analog signals which are captured from the human body
with transducers. The successive approximation register
(SAR) type analog-to-digital converter (ADC) is an essential
part in the analog signal processing [11–18]. SAR ADCs are
available from 8 to 18 bits resolution with sampling rates
up to 50 Msps [11, 12]. So SAR ADC is well suited when
compared to other ADC architectures for transmission

*  Kiran Kumar Mandrumaka, kirankumarece@cvsr.ac.in; Fazal Noorbasha, fazalnoorbasha01@gmail.com | 1Department of ECE, Koneru
Lakshmaiah Education Foundation, Vaddeswaram, Guntur, A.P., India.

SN Applied Sciences (2019) 1:918 | https://doi.org/10.1007/s42452-019-0940-3

Received: 9 November 2018 / Accepted: 17 July 2019

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Research Article SN Applied Sciences (2019) 1:918
Fig. 1  Proposed SAR ADC architecture
of physiological signals [7, 8] as shown in the Fig. 1. The
charge redistribution DAC with charge scaling single
ended spilt capacitor array is designed with small capaci-
tance values so that switching speed increases and area
is reduced. DAC operates in two modes, one is sampling
phase and second is conversion phase by additional con-
trolling as proposed in references [14], This paper also
proposes a novel comparator which is designed to oper-
ate in the sub threshold region to have very low power
consumption. An adjustable body bias is arranged in the
regenerative latch phase to operate the transistor in weak
inversion region so that leakage current is reduced for
500 mV Supply voltage. Few optimization technologies are
adopted in the ADC blocks to reduce power consumption
[1–30]. To implement the low power multi-channel signal
processing system, a 0.5 V bulk-driven folded-cascoded
operational trans conductance amplifier is proposed in
references [31].The digital data from SAR ADC is stored in
the proposed design of low power 16 × 16 SRAM array in
references [32].
This paper is organized as follows: In Sect. 2, the pro-
posed SAR ADC is described. Section  3 describes the
detailed circuit design of the ADC’s blocks. Low power
optimized techniques discussed in Sect. 4 The measure-
ment results and comparison with previous works are
shown in Sect. 5 followed by conclusion.
2 SAR architecture
As shown in Fig. 1 the architecture of SAR ADC resembles
the general ADC architecture only, but the essential blocks
which are used in SAR ADC is designed with low power
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optimized techniques. Such as low power Comparator and
single ended switched capacitor and the SAR control logic,
which controls the DAC switches based on the compara-
tor output. In the overall power consumption of the sys-
tem, Comparator and DAC plays the major role because
of switching between ­Vref and ­Vin, so we opted dual trans-
mission gate based switching method instead of static
CMOS inverter. The additional privilege in the proposed
design is Variable threshold CMOS technique (VTCMOS).
It is adopted for operating transistor under sub threshold
region while minimizing leakage current. The working of
the ADC is as shown in the Fig. 2 the complete operation
of the ADC divided into three stages. The first stage is sam-
pling stage, Second stage is conversion stage and finally
recycling stage. During the initial stage the bottom plates
of all the capacitors are connected to ground. The upper
plates of the capacitors are connected to the inverting ter-
minal of the comparator. Non inverting input of the com-
parator is connected to the sampled output. Based on the
comparator output and control signals of switches, sam-
pled signal is converted into digital form during second
and third stages. The input signal is sampled by a sample
and hold circuit which was explained in the Sect. 3.2. A
Start
Intial: V+= Vsample(Vin);V-=Gnd;N=10
D[9:0]=0000000000
Conversion: V+= Vsample(Vin);V-=Vref;i=1
No Yes
V+>V -
Vin>V-;MSB=1 Vin<V-;MSB=0
i.e D[9:0]=1000000000 i.e 0100000000
D[9:0]>>1'b1 D[9:0]>>1'b1
V- Vref(D02-1+D12-2 - - -DN-12-(N-1))
i=i+1
i=N-1
No
Stop
Fig. 2  Flowchart of proposed ADC
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detailed design process of all the blocks are explained in
the next sections.
3 Design details of SAR ADC
3.1 Comparator
The low power regenerative comparator circuit is the
essential block in the ADC and many electronic devices.
The main goal is to design a high speed and low power
preamplifier regenerative comparator circuit [28, 29].
Figure 3 shows the schematic of proposed preamplifier
regenerative comparator circuit. The operation of the com-
parator is divided into pre-amp phase (reset) stage and
dynamic comparison phase (set) stage with additional low
on resistance switches S1 and S2 with non-overlapping
clock signals as shown in Fig. 3. During the reset phase
switch S1 will be open and S2 will be closed then the sin-
gle stage folded amplifier, amplifies the voltage difference
between the two input signals with voltage gain 40.4 dB
(1). During the set phase S1 will close and S2 opens dur-
ing the time regenerative comparator circuit compares
between two input signals during the opted sampling
intervals. Because of this set and reset phases the nonlin-
ear error and offset error at comparator are reduced during
analog to digital conversion. When Vin > Vref the output
signal exhibits logic high means level 1 and Vin < Vref the
output signal exhibits logic low means level 0.
gm2
Adm = (1)
gds2 + gds6
The preamplifier is a single stage operational trans con-
ductance amplifier (OTA) [32] as shown in Fig. 3. The cur-
rent scaling technique is implemented by the transistors
M5–M6 with higher widths. Transistors Mb1, Mb2, Mb3
form a current mirror which delivers the differential cur-
rents. These differential currents are feed to output stage,
for voltage to current conversion. Transistors M1 to M6 are
operated in weak inversion region with appropriate W/L
ratio. The drain to source current ­IDS (2) in weak inversion
region depends on reverse saturation current I­S, T is the
ambient temperature, n is the inclination of the curve in
weak inversion, K is the Boltzmann constant, q the charge
of the electron or hole. The total power consumption of
the comparator is 1.8 μW with 500 mV rail to rail supply
voltage.
( )[ ( )]
W
( ) VGS − Vth VDS
IDS = IS exp q 1 − exp −q (2)
L nKT KT
Current scaling is achieved by increasing the output
impedances and thereby ensuring current scaling. The
source degenerated current mirrors are formed by transis-
tors Mc1, M5 and M6, set the currents in the regenerative

Substrate
Bias
Control
Mb3 Mb2 Mb1 Comp+
-

V+ V-
IB M1 M2
S1
S1

M3 M4

Vo - S2 S2
Vo +
M5 M6
CLK_B Mc1

Vi V0

CLK

PMOS NMOS

Fig. 3  Proposed schematic of the preamplifier regenerative comparator circuit with low on-resistance transmission gate based switches

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circuit (the difference between the currents in M3–M4
and M5–M6). In order to save the power, the bias circuit
is designed in such a way that the currents of transistors
in the regenerative circuit are only a small portion of the
input pair. The current scaling ratio between Mb1 and Mb2
is 7:1(2ID/14). The currents in the regenerative transistors
are ­ID/7; this is 1/3rd of the differential input pair current.
Using the bias circuit formed by Mb2 and Mc1, we set the
current in the M5 and M6 to be ­8ID/7 [31] (Table 1).
The Transmission gate based switch is used for switch-
ing between set and reset operations, but to avoid glitches
during switching and without voltage drops while passing
through the channel, on-resistance should be reduced. The
parallel combination of one low and high on-resistance of
the transistors results low on-resistance. So on-resistance
Table 1  Design summary of pre-amplifier
Devices W (μm)/L (nm) ID (nA) Operating region
of the transmission gate is reduced while connecting one
low W: L ratio pMOS transistor with high W:L ratio pMOS
transistor and similarly for nMOS transistor.
3.2 Sample and hold
A simple sample and hold circuit is designed with CMOS
Transmission gate and a sampling capacitor. To avoid
charge injection error, a dummy switch is arranged as
shown in the Fig. 4. The dummy switch is driven by an
inverted clock which absorbs the charge injection from
sampling switch. The unwanted glitches are also elimi-
nated by using this dummy switch. The minimization of
DNL and INL for better ADC design can be possible by
connecting a buffer at the end of the sample and hold
circuit.
3.3 Digital to analog converter (DAC)

M1:M2 20/180 393 Sub threshold A 10 bit charge scaling capacitive DAC is designed with a
M3:M4 50/180 393 Sub threshold combination of two 5 bit charge scaling sub-DACs with a
M5:M6 10.02/200 505 Sub threshold scaling capacitor Cs as shown in the Fig. 5. The operation of

CLK_B CLK

Vin Vout

CLK CLK_B

(a) (b)

Fig. 4  a Sample and hold circuit with dummy switch. b Simulation result with sampling rate 5 Ksps

VSample
`

CS +
Comparator Vout
-

C C 2C 4C 8C 16C C 2C 4C 8C 16C

Fig. 5  Digital to Analog Converter with proposed regenerative comparator

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Case: 1000000000 Case: 1100000000 Case: 1110000000 Case: 0111000000 Case: 0011100000

Vin Vin Vin Vin

Vin + 1 + 1 + 0 + 0
+ 1 Vin>3Vref/4 Vin>7Vref/8 Vin<7Vref/8 Vin<7Vref/8
Vin>Vref/2 - - - -
-
C 2C C 2C 4C C 2C 4C 4C 8C 16
C 2C C
Vref Vref Gnd Vref Vref Vref Gnd Gnd Vref Vref G G Gnd Vref Vref Vref
Vref Gnd Gnd nd nd

Fig. 6  Switching procedure of proposed ADC with an example of 5 levels shifting

The high performance of the DAC is defined from the

Power(uW)
DAC Comparator SAR
5%
30% 40%
25%
Fig. 7  Power analysis of ADC blocks
the DAC with example of five levels of shifting is explained
with the help of the Fig. 6. The series combination of scal-
ing capacitor starts with LSB array and terminates with
MSB array. The accuracy of the DAC depends upon the
scaling capacitor Cs as it is the terminating capacitor
between LSB and MSB array.
The area of the DAC is proportional to the size of the
unit capacitor. From the simulation test results the unit
capacitance whose value is 62.5 fF. The operational ampli-
fier which is discussed in the previous section is utilized
in the DAC as a buffer to increase the linearity and to
decrease comparator offset error [31].Total capacitance
on the right of the scaling capacitor 1.937 pF and left of
the scaling capacitor is 2 pF. DAC plays almost 40% in the
total power consumption of ADC because dynamic power
consumption and switching event capacitances, charge up
phase dissipates more heat in the circuit. Dual split switch-
ing minimizes the switching energy by reducing on resist-
ance of the transmission gate that could be explained in
later sections. The power analyses of all the modules are
as shown in the Fig. 7.
calculations of differential nonlinearity (DNL) and inte-
gral nonlinearity (INL). In this paper, DAC design is carried
out for low frequency applications such as Physiological
S&H
signals so there is no much importance for DNL and INL.
However, all the performance metrics are carried out for
proposed ADC as shown in the simulation results. DNL
is the difference between an actual step width and ideal
value of 1 LSB (Least Significant Bit).
VFSR
1LSB =
2N
VFSR is the full scale range and N is the resolution of
the ADC. Resolution of proposed ADC is 10  bit and
VFSR = 100 mV , so 1 LSB value is 100 μV.
VD+1 − VD
[ ]
DNL = − 1 , where0 < D < 2N−2
VLSBIDEAL
3.4 SAR control logic
The advantage of Successive approximation register is
to give zero latency compared to remaining ADC archi-
tectures. The circuit schematic of SAR Control logic is
considered from Ref. [29] but the basic cell which is
used in SAR control is DFF, it is designed with low on-
resistance transmission gate with VTCMOS technique
explained in previous sections. The gate level circuit is
shown in Fig. 8.
4 Proposed low power techniques
4.1 Variable threshold CMOS (VTCMOS)
In this paper, MOS transistor substrate bias voltage is
dynamically varied to control the threshold voltage as
shown in Fig. 9 and followed equations. The substrate

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CLK_B
CLK_B
D Q
CLK
CLK
CLK
CLK_B
Fig. 8  Gate level circuit of D Flip-Flop in SAR control logic
voltages of nMOS and pMOS transistors are generated by
the variable substrate bias control circuit. The transmis-
sion gate using VTCMOS technique is shown in Fig. 3 The
circuit operates with low-power dissipation (due to low
VDD ) and a high switching speed (due to a low VTH ). When
the circuit is in the standby mode, the substrate bias con-
trol circuit generates a lower substrate bias voltage for the
nMOS transistor and a higher substrate bias voltage for the
pMOS transistor. As a result, the magnitudes of the thresh-
old voltages ( VTHn and VTHp ) increase in the standby mode
due to the body bias effectively. Since the sub thresh-
old leakage current drops exponentially with increasing
threshold voltage, the leakage power dissipation in the
standby mode can be significantly reduced with this circuit
design technique. However, with technology scaling, the
effectiveness of the VTCMOS technique reduces the chan-
nel length becomes smaller [33].
R4 R2
where V1b = Vin R +R Similary V2b = Vin R +R .
3 4
4.2 Dual split switching
Dual Spilt switching is done with 2:1 MUX design. In
charge scaling DAC, 2:1 Mux is used to switch between
Vin to Vref and at the Sect. 3 in Preamplifier regenerative
comparator design also dual spilt switching is used to
V2b
R1
R2
Vin Out
V1b
R3
R4
Fig. 9  VTCMOS technique
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switch between amplifier and comparator. The primary
element used in the dual splitting design is a trans-
mission gate [34]. In the proposed transmission gate,
another set of NMOS and PMOS transistors are connected
in parallel, so that the on resistance and sampling distor-
CLK tion are maintained as low as possible. The length and
widths are in 2:1 ratio. As mentioned in previous section
transmission gate is operated with VTCMOS technique
CLK_B
refer Fig. 10.
5 Test simulation results
The schematic of ADC was designed in the UMC 180 nm
CMOS process. Chip fabrication was not carried out, but
Simulation test results are verified with the theoretical.
The performance of ADC is characterised by differential
nonlinearity(DNL) and integral nonlinearity(INL) calcula-
tions. The simulated DNL and INL are 0.9/− 0.82 LSB and
1.06/− 1.31 LSB respectively as shown in Figs. 11 and 12.
The input signal is a sinusoidal signal with frequency
100 Hz sampled at 1 MS/s with effective number of bits
7.69 bit. The power supply voltage is 0.5 V. Figure 13
shows positive level shifting for positive analog cycle
and negative level shifting for negative analog cycle
and Fig.  14 shows the measured 10 bit DAC divides
the input range up to 1024 levels. Figure 15 shows the
regenerative comparator output. The simulated SNDR
and SFDR and ENOB results are shown in the Fig. 16 and
Tables 2, 3.
1 2
CLK_B
Vin
V0
CLK
Vref
CLK_B
Fig. 10  2:1 Mux with dual transmission gates with on-resistance
reducing method
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Fig. 11  Simulated DNL 1.5 DNL=0.9/-0.82 LSB

1
0.5
0 LSB

109
145
181
217
253
289
325
361
397
433
469
505
541
577
613
649
685
721
757
793
829
865
901
937
973
1009
1
37
73
-0.5
-1
-1.5

Fig. 12  Simulated INL 2
INL=1.06/-1.31LSB
1

0 LSB

491

701
106
141
176
211
246
281
316
351
386
421
456

526
561
596
631
666

736
771
806
841
876
911
946
981
1
36
71

1016
-1

-2

Fig. 13  Simulated ADC output for 100 Hz sine wave input

Fig. 14  Simulated 10 bit DAC dividing input range (100 mV) to 1024 levels

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Fig. 15  Regenerative comparator output waveform

Table 3  Comparison of low power ADCs

This work [5] [6] [8]

Architecture SAR SAR SAR SAR

VDD (V) 0.5 1.2 1 0.5
Power dissipation 13.99 μW 0.826 mW 820 μW 1.8 μW
Technology (nm) 180 130 65 90
Resolution (bits) 10 10 10 10
Fsample 1 Msps 50 Msps – 1.25 Msps
DNL (max) (LSB) + 0.9/− 0.82 0.91/− 0.63 – 0.34
INL (LSB) 1.06/− 1.31 1.27/− 1.36 – 0.62
SFDR (dB) 68.54 65.9 75.2 80.4
SINDR (dB) 61.96 57 56.9 55.6
ENOB 7.69 9.18 9.16 8.94

Fig. 16  Simulated FFT for a 100  Hz sine wave with sampling rate 6 Conclusion
1 MS/s
A 10 bit SAR ADC with a 100 mV ­Vref input range using
Table 2  Key parameters of proposed SAR ADC dual split switching network in DAC is presented. A regen-
erative comparator operating in the sub threshold region
Architecture SAR
with low offset is used, along with low power SAR logic
VDD (V) 0.5 with negative edge triggered flip-flop at a 500 mV supply
Power dissipation (μW) 13.99 μW voltage. The proposed ADC consumes 13.99 μW power.
Technology (nm) 180 The ENOB around 7.69 bits.
Resolution (bits) 10
Fsample Up to 1 Msps Acknowledgements  The authors are highly thankful to the Chairman
of ANURAG group of institutions Dr. P. Rajeshwar Reddy M. L. C for
DNL (max) + 0.9/− 0.82 LSB his constant encouragement and also providing all the necessary
INL 1.06/− 1.31 LSB resources to carry out this work. They are also thankful to Dr. K. S. R.
SFDR (dB) 68.54 Krishna Prasad, Professor, NIT, Warangal and Dr. K. S. Rao, Director,
SINDR (dB) 61.96 Anurag Group of Institutions for their valuable suggestions during
this work. The authors deeply express their gratitude Department
ENOB 7.69 of ECE, K L. University.

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