Ade Final Manual PDF

BANGALORE INSTITUTE OF TECHNOLOGY
K.R. ROAD, V.V PURAM, BANGALORE – 560 004
DEPARTMENT OF
INFORMATION SCIENCE AND ENGINEERING
(AFFILIATED TO VTU, BELAGAVI)
CODE: 18CSL37
ANALOG AND DIGITAL ELECTRONICS LABORATORY
As per Choice Based Credit System Scheme (CBCS)
FOR III SEMESTER CSE/ISE AS PRESCRIBED BY VTU
Academic year 2019-2020
Prepared By:
Prof. C.S JAYASHEELA
Assistant Professor
Dept. of ISE, BIT
ANALOG AND DIGITAL ELECTRONICS LABORATORY (18CSL37)
Bangalore Institute of Technology

K R Road, VV puram, Bangalore 560004
Department of Information Science and Engineering
Pre-requisite
• Basic Mathematics
• Knowledge of Basic Electronics.
• Knowledge of Analog and Digital Principles.
Course objectives
After studying this course, students will be able to:

This laboratory course enable students to get practical experience in design , assembly and
evaluation/testing of
• Analog components and circuits including Operational Amplifier, Timer, etc.

• Combinational logic circuits.
• Flip-Flops and their operations.
• Counters and registers using flip-flops.
• Synchronous and Asynchronous sequential circuits.
• A/D and D/A converters.
Course Outcomes
Students should be able to
Understand the applications of Electronic components, ICs and tools to design

CO1
and test Electronic circuits.
Design, implement and evaluate the different Analog & Digital circuits with
CO2
proper input test conditions.
Analyze the working principle and functions of different Analog & Digital
CO3
circuits.
Compile and present a laboratory journal which depicts the various activities of
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the laboratory.
Design and implement a given Analog/Digital circuit with specified
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application. (Case study- Group Activity).
Dept of ISE, BIT Page 2

CO’S & PO’S MAPPING
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2 2 2
ADE
Lab CO2 3 3 3 2 2 2 1
18CSL37
CO3 3 3 3 2 2 2 1
CO4 2 2 2 2 1
CO5 3 3 3 2 3 3 1
PSO1 PSO2
CO1 2 3
ADE Lab CO2 2 3
18CSL37
CO3 2 3
CO4 2 3
CO5 2 3
Guidelines given by the University for Conduction of laboratory:

• Simulation packages preferred: Multisim, Modelsim, PSpice or any other relevant.
• For Analog Electronics circuit students must trace the wave form on Tracing
sheet/Graph sheet and label trace.
• Continuous evaluation by the faculty must be carried by including performance of the
student in both hardware implementation and simulation for the given circuits.
• A batch not exceeding 4 must be formed for conducting the experiment. For
simulation individual student must execute the program.

Analog and Digital Electronics Laboratory

Semester- III
Course Code: 18CSL37 CIE Marks : 40

Hours/Week: 0:2:2 SEE Marks : 60
Total Hours: 36 Exam Hours: 3
List of Programs
Sl.
Name of Experiment
No
PART A ( Analog Electronics Circuits)
Design an astable multivibrator circuit for three cases of duty cycle (50%, <50% and
1 >50%) using NE 555 timer IC. Simulate the same for any one duty cycle.
Using ua 741 Opamp, design a 1 kHz Relaxation Oscillator with 50% duty cycle. And
2 simulate the same
Using ua 741 opamap, design a window comparator for any given UTP and LTP. And
3 simulate the same.
PART B( Digital Electronics Circuits)

Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using basic
4 gates. And implement the same in HDL.
Given a 4-variable logic expression, simplify it using appropriate technique and realize the
5 simplified logic expression using 8:1 multiplexer IC. And implement the same in HDL.
Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table. And
6 implement the same in HDL.
Design and implement code converter I) Binary to Gray (II) Gray to Binary Code using
7 basic gates.
Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs and
8 demonstrate its working.
Design and implement an asynchronous counter using decade counter IC to count up from
9 0 to n (n<=9) and demonstrate on 7-segment display (using IC-7447).

Analog & Digital Electronics Laboratory

Evaluation Rubrics

Daily Conduction rubrics (Max: 20 marks)
Write-up &
Implementation Analysis & Execution Results & Tabulation Record/Journal
5Marks 5Marks 5Marks 5Marks
Test rubrics (Max: 15 marks)
Write-up &
Implementation Execution & Results Viva
4Marks 6Marks 5Marks
Group Activity rubrics (Max: 5 marks)
A Group of students will be designing and demonstrating the given Analog/Digital Circuit in
Hardware or Software. Based on their work marks will be allocated.
GROUP ACTIVITY
Design Implementation Presentation Total
2Marks 2Marks 1Mark 5Marks

Analog & Digital Electronics Laboratory

Lesson Planning / Schedule of Experiments
Sl. To be
Name of Experiment
No completed
Vision, Mission of college and department, course objective and
course outcomes of ADE Laboratory.
1 Introduction to trainer kit, Basic Gates ICs, Verification of truth Week1
tables. Introduction to signal generators, CROs, checking input and
output waveforms.
Design and implement Half adder, Full Adder, Half Subtractor, Full Week2
2 Subtractor using basic gates. And implement the same in HDL.
Design and implement code converter I) Binary to Gray (II) Gray Week3
3 to Binary Code using basic gates.
Given a 4-variable logic expression, simplify it using appropriate
4 technique and realize the simplified logic expression using 8:1 Week4
multiplexer IC. And implement the same in HDL.
Realize a J-K Master / Slave Flip-Flop using NAND gates and Week5
5 verify its truth table. And implement the same in HDL.
TEST-I Week6
Design and implement an asynchronous counter using decade

6 counter IC to count up from 0 to n (n<=9) and demonstrate on 7- Week7
segment display (using IC-7447).
Design and implement a mod-n (n<8) synchronous up counter Week8

7 using J-K Flip-Flop ICs and demonstrate its working.
Design an astable multivibrator circuit for three cases of duty cycle

8 (>50%,< 50%,50%) using NE 555 timer IC. Simulate the same Week9
for any one duty cycle.
Using ua 741 Opamp, design a 1 kHz Relaxation Oscillator with Week10

9 50% duty cycle. And simulate the same.

Using ua 741 opamap, design a window comparator for any given Week11
10 UTP and LTP. And simulate the same.
TEST-II Week 12
11 Repetitions Week13
12 Repetitions Week14

Introduction
Basics Gates & its implementation using NAND

Pin diagrams of Logic gates

Cathode-Ray Oscilloscope and Signal Generator used in Analog Experiments
Pin Diagram of OPAMP 741
Pin Diagram of 555 Timer

Analog Electronics Circuits -PART A

1. Design an astable multivibrator circuit for three cases of duty cycle (50%,<50% and
>50%) using NE 555 timer IC. Simulate the same for any one duty cycle.
AIM:
To design and implement an astable multivibrator using 555 Timer for a given frequency and
duty cycle.
COMPONENTS REQUIRED:
Sl.no Name of Component No.’s Sl.no Name of Component No.’s

1 555 Timer IC 1 6 Probes 2
2 Resistors of 3.3KΩ, 1 7 Single Strand wires 4
6.8KΩ 8 Patch Chords 15
3 Capacitors of 0.1 μF, 1 9 Spring Board 1
0.01 μF
4 Regulated power supply 1
5 CRO 1
THEORY:
Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output waveform
is rectangular. The multivibrators are classified as
i) Astable or free running multivibrator: It alternates automatically between two states

(low and high for a rectangular output) and remains in each state for a time dependent upon
the circuit constants. It is just an oscillator as it requires no external pulse for its operation.
ii) Monostable or one shot multivibrators: It has one stable state and one quasi stable. The
application of an input pulse triggers the circuit time constants and the output goes to the
quazi stable state, after a period of time determined by the time constant, the circuit returns to
its initial stable state. The process is repeated upon the application of each trigger pulse.
iii) BistableMultivibrators: It has both stable states. It requires the application of an external
triggering pulse to change the output from one state to other. After the output has changed its
state, it remains in that state until the application of next trigger pulse. Flip flop is an
example.
Timer IC 555 is a general purpose integrated circuit, widely used to configure monostable
and astable multivibrator circuits around.

CIRCUIT:
+VCC
4,8
RA
7
V0
555 3
RB +
V0 CRO
2,6
5 1
+ -
Vc 0.1μF
-
0.01µf
DESIGN:
Design 1: Given frequency (f) = 1 KHz and duty cycle = 60% (=0.6)
The time period T =1/f = 1ms = tH + tL
Where tH is the time the output is high and tL is the time the output is low.
From the theory of astable multivibrator using 555 Timer (refer Malvino), we have
tH = 0.693 RB C ------(1)
tL = 0.693 (RA + RB)C ------(2)
T = tH + tL = 0.693 (RA +2 RB) C
Duty cycle = tH / T = 0.6. Hence tH = 0.6T = 0.6ms and tL = T – tH = 0.4ms.
Let C=0.1μF and substituting in the above equations,
RB = 5.8KΩ (from equation 1) and RA = 2.9KΩ (from equation 2 & RB values).
The Vcc determines the upper and lower threshold voltages (observed from the capacitor
2 1
voltage waveform) as VUT = VCC & VLT = VCC .
3 3
Note: The duty cycle determined by RA & RB can vary only between 50 & 100%. If RA is
much smaller than RB, the duty cycle approaches 50%. Since charging and discharging is via
RB, ignoring RA
Design 2: 50% Duty Cycle Astable Oscillator
50% Duty Cycle Frequency Equation
f= 1 Hz
0.693 (2R2) .C

EXPECTED OUTPUT:
PROCEDURE:
• Before making the connections, check the components using multimeter.

• Make the connections as shown in figure and switch on the power supply.
• Observe the capacitor voltage waveform at 6th pin of 555 timer on CRO.
• Observe the output waveform at 3rd pin of 555 timer on CRO (shown below).
• Note down the amplitude levels, time period and hence calculate duty cycle.
APPLICATIONS:
Astable multivibrators are used in pulse position modulation, frequency modulation, etc.
To Flash LEDs, it acts as Frequency divider, ramp generators etc.
RESULT:
Astable Multivibrator was designed and implemented using 555 timer with three cases and
the given frequency was verified with the output graph obtained.

SIMULATION CIRCUIT FOR ASTABLE MULTIVIBARTOR:
OUTPUT WAVEFORM:

2. Using ua 741 Opamp, design a 1 kHz Relaxation Oscillator with 50% duty cycle. And
simulate the same.
AIM:
To implement a Op-Amp relaxation oscillator for the frequency of 1 kHz.

1 Op-amp μA 741 1 5 Probes 2
Resistor of 1KΩ,10KΩ, 6 CRO 1
2 20 kΩ(based on design) 1 7 Single Strand wires 4
8 Patch Chords 15
Capacitors (based on
3 1 9 Trainer Kit 1
design)
4 VDC, GND earth -
THEORY:
Oscillator is an equipment produces oscillated output (Sine,Square or Rectangular) without any input
except the bias voltage (DC). The type of feedback is positive. The main components required are
Amplifier.(opamp is used here) Tank circuit, Positive Feed Back network. The condition for
oscillation is Av = -1 (loop gain) and Total phaseShift arround loop is 0 or 3600 (since positive
feedback). Av is open loop gain of Opamp, is Feedback factor.
Relaxation oscillator is an oscillator circuit that produces a non sinusoidal output where
time period is depend on charging time of a capacitor connected as a part of the oscillator circuit. Op-
amp adopts very well for construction of relaxation oscillator that produces a square and rectangular
output. The time period of output may be conventionally vary by varying the value of resistor R
which is a part of tank circuit. The resistances R1and R2 make the feedback circuit (positive) that
compress the loss of R C circuit.
When the output is in positive saturation, the voltage at non-inverting input of op-amp is
+Vsat this forces output to stay in positive saturation as the capacitor ‘C’ is initially
discharged. It starts charging towards +Vsat through R. The moment capacitor voltage
exceeds the voltage appearing at non- inverting input, the output switches to –Vsat. The
voltage at non inverting input also changes to –Vsat ( The capacitor starts discharging
and after reaching zero, it begins to discharge towards –Vsat. As it becomes more –ve than the –ve
threshold appearances at non inverting input, the output switches to +Vsat and cycle repeats.

CIRCUIT:
R1 R
12V
3
7 6
µA741
C 2 -
4 +
- CRO
+ 12V CRO
VC VOUT
-
R2
DESIGN:
For frequency 1khz. i.e.
where
when R1= R2, T =2RC ln (3)
If we choose R2=1.16 R1, T =2RC
For a frequency of design 1 kHz means, T = 1/f
T = 1/103 or T = 10-3 ms, Hence, T = 1ms
Let R1 =10KΩ, then R2=11.6 KΩ (use a 20 KΩ potentiometer) Choosing a suitable value of
C, the value of R can be calculated . Let C = 0.1µF, then R = T/2C
R = (1x 10-3 )/ (2 x 0.1 x 10-6 ) Therefore, R = 5 KΩ. Based on the hardware design,

EXPECTED OUTPUT:
PROCEDURE:
1. Before making the connections check the working conditions of all the components.
2. Make the connections as shown in figure and switch on the power supply.
3. Observe the waveform across the capacitor on CRO and measure its amplitude.
4. Also observe the output waveform on CRO. Measure its amplitude and frequency.
APPLICATIONS:
• Used as an oscillator to produce Square or Rectangular wave.
• The Square wave can be used as a frequency generator in CPU.
RESULT:
The designed frequency is verified from the waveforms obtained on CRO and duty cycle is
measured.

SIMULATION CIRCUIT
R1 R
12V
3
7 6 V
V +
VC µA741
-
C 2 VOUT
4
12V
R2
EXPECTED OUTPUT:
Waveforms from simulation T= 1ms f = 1 kHz
20V
10V
0V
- 10V
- 20V
0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms
V(C1:2) V(R3:2)
Time
Type of analysis: TIME DOMAIN (TRANSIENT), Run to time: 10ms, Step size: 0.01ms
PROCEDURE:
• Get the required components.

• Select Draw → Get new part→ Type the part name →Select the component→ Place&
Exit.
• Make the connections with wires as given in circuit diagram.
• Place the Voltage meter & label it as shown in circuit.
• Set print & final step in setup analysis based on the frequency & number of
waveforms to see on output graph.
• Enable skip initial transition in the Setup Analysis.
• Click Simulate, on the output graph measure the frequency.
RESULT:
Relaxation oscillator was designed for 1khz using 741 Opamp and the output waveforms
were verified.

3. Using µa 741 opamp, design a window comparator for any given UTP and LTP. And
simulate the same.
AIM:
To design and implement a window comparator using µa 741 op-amp for the given UTP and
LTP values.

1 IC μA 741 1 6 Probes 3
2 Resistor of 7 Single Strand wires 4
10KΩ,100KΩ,1 1 8 Patch Chords 15
KΩ(based on design) 9 Spring Board 1
3 DC regulated power 1
supply
4 Signal generator 1
5 CRO 1
THEORY:
A Window Comparator is basically the inverting and the non-inverting comparators above
combined into a single comparator stage. The window comparator detects input voltage
levels that are within a specific band or window of voltages, instead of indicating whether a
voltage is greater or less than some preset or fixed voltage reference point.
This time, instead of having just one reference voltage value, a window comparator will have
two reference voltages implemented by a pair of voltage comparators. One which triggers an
op-amp comparator on detection of some upper voltage threshold, VREF(UPPER)and one which
triggers an op-amp comparator on detection of a lower voltage threshold level, VREF(LOWER).
Then the voltage levels between these two upper and lower reference voltages is called the
“window”, hence its name.
Using our idea above of a voltage divider network, if we now use three equal value resistors
so that R1 = R2 = R3 = R we can create a very simple window comparator circuit as shown.
Also as the resistive values are all equal, the voltage drops across each resistor will also be
equal at one-third the supply voltage, 1/3Vcc. Then in this simple example, we can set the
upper reference voltage to 2/3Vcc and the lower reference voltage to 1/3Vcc.

CIRCUIT:
Design Steps 1. Define the upper (VH) and lower (VL ) window voltages. 2. Choose
resistor values to achieve the

PROCEDURE:
1. Before making the connections check the working conditions of all the components.
2. Make the connections as shown in figure and switch on the power supply.
3. Give the input waveform with required frequency and amplitude.
4. Also observe the output waveform on CRO. Measure its amplitude and frequency.
APPLICATIONS:
• Acts as switching device.

• To synchronize sampling to an external frequency source.
RESULT:
The window comparator is implemented and the output waveform is observed.

PART B ( Digital Electronics Circuits)
4. Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using
basic gates. And implement the same in HDL.
AIM:
To realize Half Adder, Full Adder, Half Subtractor, Full Subtractor using basic gates.
Sl.no Name of Component No.’s
1 IC7404 1
2 IC 7408 2
3 IC 7432 1
4 Patch chords 30
5 Trainer kit 1
HALF ADDER:
THEORY:
Half Adder is a combinational circuit is used to perform addition of 2 bits in the form of sum
and carry.
DESIGN (TRUTH TABLE):
i/p’s o/p’s
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
SIMPLIFICATION:
Sum= A B + A B
Carry= A B

CIRCUIT:
A B
7404
7408
7432
Sum
Carry
FULL ADDER:
THEORY:
Full Adder is a combinational circuit, is used to perform addition of 3 bits. It returns 2 bits of
output in the form of sum and carry.
i/p’s o/p’s
A B Cin Sum Carry
0 0 0 0 0
0 1 0 1 0
0 0 1 1 0
0 1 1 0 1
1 0 0 1 0
1 1 0 0 1
1 0 1 0 1
1 1 1 1 1

SIMPLIFICATION:
Expression:- Sum = AB Cin + A B Cin + A B Cin + A B Cin
= Cin (A B +A B) + Cin(AB +AB)
Sum = Cin + Cin
Carry = A B Cin + A B Cin + A B Cin + A B Cin
= Cin(A B+ A B) + A B (Cin + Cin)
= Cin +AB
CIRCUIT DIAGRAM:
HALF SUBTRACTOR:
THEORY:
Half Subtractor is a combinational circuit, is used to perform subtraction

of 2 bits. It returns two bits of output in the form of difference and borrow.

i/p’s o/p’s
A B Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
SIMPLIFICATION:
Diff= A B + A B
Borrow = A B
CIRCUIT:
A B
7404
7408
Borrow
Diff
7432
FULL SUBTRACTOR:
THEORY:
Full Subtractor is a combinational circuit, is used to perform subtraction of 3 bits. It returns

two bits of output in the form of difference and borrow.

i/p’s o/p’s
A B Bin Diff Borrow
0 0 0 0 0
0 1 0 1 1
0 0 1 1 1
0 1 1 0 1
1 0 0 1 0
1 1 0 0 0
1 0 1 0 0
1 1 1 1 1
SIMPLIFICATION:
Difference :- A B Bin + A B Bin + A B Bin + A B Bin
= Bin(A B +A B) + Bin(A B +A B)
Borrow :- A B Bin + A B Bin + A B Bin + A B Bin
= Bin(A B +A B) + A B (Bin + Bin)
= Bin + AB
Comparison b/w Full Adder and Full Subtractor
Sum = Diff = Cin + Cin
Borrow= Cin +AB
CIRCUIT:

PROCEDURE:
• Collect the required ICs and required other components.

• Connect the different components according to their design.
• For different combinations of input find the output and verify the truth table.
• Carry out these steps for all Adders and Subtractors (HA,FA,HS & FS)
APPLICATIONS:
To perform arithmetic operation (add, sub, mul, div) and also to produce 2’s complement for
a given input
RESULTS:
The truth table for Half Adder, Full Adder, Half Subtractor and Full Subtractor has been
verified.
SIMULATION:
VHDL to describe the functions of a Full Adder

Block Diagram
Truth Table
a b c Sum Carry e=sc

0 0 0 0 0 00
0 0 1 1 0 10
0 1 0 1 0 10
0 1 1 0 1 01
1 0 0 1 0 10
1 0 1 0 1 01
1 1 0 0 1 01
1 1 1 1 1 11

a) DATA FLOW
i) VHDL code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fad is --Define the entity;

Port (a, b, c: in std_logic;-- Define input and output ports;
sum, carry: out std_logic);
end fad;
-- end the entity body;
architecture Behavioral of fad is-- Define the architectural body;
begin
sum<=(a xor b) xor c;--Assign sum and carry using assignment operator;
carry<=(a and b) or (b and c) or (c and a);
end Behavioral;-- end the architectural body;
b) BEHAVIORAL
i) VHDL code
library IEEE;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fab is--Define the input and output ports inside the entity;
Port ( d : in std_logic_vector(2 downto 0);
e : out std_logic_vector(1 downto 0));
end fab;--End the entity;
architecture Behavioral of fab is
begin
process(d)-- process statement represents
beginthe behavior of some portion of the design;
if (d="000") then e<="00"; --Defining differnt input conditions using
elsif (d="001") then e<="10";conditional statements;
elsif (d="010") then e<="10";
elsif (d="011") then e<="01";
elsif (d="100") then e<="10";
elsif (d="101") then e<="01";
elsif (d="110") then e<="01";
else e<="11";
end if; --Ending conditional & process statements;
end process;
end Behavioral; --End the architectural body;

Subprogram for Halfadder

Entity Halfadder is
Port (A, B: in std_logic;
S, C: out std_logic);
endHalfadder;
Architecture dataflow of Halfadder is
begin
S<=A xor B;
C<=A and B;
end dataflow;
Note: Students should write the code for Half and Full Subtractor and execute.
EXPECTED SIMULATION OUTPUT:

5. Given a 4-variable logic expression, simplify it using appropriate technique and

realize the simplified logic expression using 8:1 multiplexer IC. And implement the
same in HDL.
AIM:
To simplify Boolean expression using Entered Variable Map method and realize the
simplified expression using 8:1 MUX
4variable expression→ MEV (can used D as variable)→ Simplified expression→ implement

table→ final diagram using 74151

1 IC74151/IC74153 1
2 IC7404 1
3 Patch chords 20
4 Trainer kit 1
THEORY:
The term multiplex means “many to one”. A multiplexer (MUX) has n inputs. Each
line is used to shift digital data serially. There is a single output line. One of the data stored in
the n input line is transferred to the output based on the valued of control bits. An n to 1
multiplexer requires m control bits where n<= 2m
To construct an 4 variable function we require a 16(24) to 1 multiplexer, whereas using an

entered variable map method a 4 variable expression can be realized using 8(23) to 1
multiplexer.
Pin Diagrams: IC 74LS151
Example:

Simplify the following function using EVM technique

f(a,b,c,d)=∑m(2,3,4,5,13,15)+dc(8,9,10,11)
Decimal ABCD f MEV map entry Data I/P
0 0000 0 0 Do
1 0001 0
2 0010 1
3 0011 1 1 D1
4 0100 1
5 0101 1 1 D2
6 0110 0
7 0111 0 0 D3
8 1000 X
9 1001 X X D4
10 1010 X
11 1011 X X D5
12 1100 0
13 1101 1 D D6
14 1110 0
15 1111 1 D D7
ABC
D 000 001 010 011 100 101 110 111
0 2 4 6 8 10 12 14
0 0 1 1 0 X X 0 0
1 3 5 7 9 11 13 15
1
0 1 1 0 X X 1 1
D0 D1 D2 D3 D4 D5 D6 D7
D0 = D3 = 0
D1 = D2 = D4 = D5 = 1 (Don’t cares considered as 1)
D6 = D7 = D·

Circuit Diagram
PROCEDURE:
• Connect the input to mux by using any one variable say LSB or MSB (Say D) and use
other lines ABC as select lines to MUX.
• Check output Pin no 5(Y) as per Truth table or Boolean Expression.
APPLICATIONS:
To select any one channel from many channels of microwave.

To select any one output device for display say Monitor, File, CRO etc.
To implement any Boolean Expression with minimum number of gates.
RESULTS:
The given 4-variable logic expression is realized using 8:1 multiplexer and verified.

Implementation in HDL
BLOCK DIAGRAM:
MULTIPLEXER
I 8 TO 1 Zout
8
3
SEL
TRUTH TABLE:
INPUTS OUTPUTS
SEL(2) SEL(1) SEL (0) Zout
0 0 0 I(0)
0 0 1 I(1)
0 1 0 I(2)
0 1 1 I(3)
1 0 0 I(4)
1 0 1 I(5)
0 1 1 I(6)
1 1 1 I(7)
VHDL CODE:
library IEEE;
entity mux1 is
Port ( I : in std_logic_vector(7 down to 0);
sel : in std_logic_vector(2 downto 0);
zout : out std_logic);
end mux1;
architecture Behavioral of mux1 is

begin
zout<=I(0) when sel="000" else
I(1) when sel="001" else
I(7);
end Behavioral;
OUTPUT/GRAPH:
RESULTS:
The output graph is obtained by giving different set of combinations of input and the
multiplexer output is observed.

6. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table.
And implement the same in HDL.
AIM:
To realize a J-K Master/Slave FF using NAND gates and verifies its functioning.

1 IC7410 three input 1
NAND gate
2 IC7400 (Q -1) two input 2
NAND gate
3 Patch chords, 25
4 Trainer kit 1
THEORY:
A flip-flop is a device very much like a latch in that it is a bitable multivibrator, having two
states and a feedback path that allows it to store a bit of information. The difference between
a latch and a flip-flop is that a latch is asynchronous, and the outputs can change as soon as
the inputs do (or at least after a small propagation delay). A flip-flop, on the other hand, is
edge-triggered and only changes state when a control signal goes from high to low or low to
high.
Master Slave Flip Flop:
The control inputs to a clocked flip flop will be making a transition at approximately the
same times as triggering edge of the clock input occurs. This can lead to unpredictable
triggering. A JK master flip flop is positive edge triggered, whereas slave is negative edge
triggered. Therefore master first responds to J and K inputs and then slave. If J=0 and K=1,
master resets on arrival of positive clock edge. High output of the master drives the K input
of the slave. For the trailing edge of the clock pulse the slave is forced to reset. If both the
inputs are high, it changes the state or toggles on the arrival of the positive clock edge and the
slave toggles on the negative clock edge. The slave does exactly what the master does.

TRUTH TABLE:
Clk J K Q Q bar comment

0 0 Q0 Q0bar No change
0 1 0 1 Reset
1 0 1 0 Set
1 1 Q Q0 Toggle
CIRCUIT:
7400 7400
7410 7400
7410
7400 7400
7400
7400
PROCEDURE:
• Verify all the components and patch chords whether they are in good condition or not.
• Make connections as shown in the circuit diagram.
• Give power supply to the trainer kit.
• Provide the input data to the circuit via switches.
• Record and verify the output sequence for each combination of the select lines.
APPLICATIONS:
To generate clock pulse for CPU.

To demonstrate Racing and method to avoid racing.
It is used as an input to T FF which is used to divide the clock input by a scaling factor of
2,3,4 etc.
RESULT:
The Master Slave JK Flip-flop was implemented using Nand gates and verified.

VHDL CODE:
entity jkff is
Port ( clk,j,k : in std_logic;
q : inout std_logic:='0';
qb : out std_logic);
end jkff;
architecture Behavioral of jkff is
begin
process(clk)
begin
if(j='0' and k='0')then q<=q;
elsif(j='0' and k='1')then q<='0';
elsif(j='1' and k='0')then q<='1';
elsif(j='1' and k='1')then q<=not q;
end if;
end process;
qb<= not q;
end Behavioral;
OUTPUT/GRAPH:
RESULT:
The JK flip-flop was implemented using VHDL code and output graph was observed.

7. Design and implement code converter I) Binary to Gray (II) Gray to Binary Code
using basic gates.
AIM:
To design and implement 4-bit
a. Binary to gray code converter
b. Gray to binary code converter

1 IC7408 1
2 IC 7404 1
3 IC 7432 1
4 Patch chords 45
5 Trainer kit 1
THEORY:
Binary to gray code conversion is a very simple process. There are several steps to
do this types of conversions. Steps given below elaborate on the idea on this type of
conversion.
The M.S.B. of the gray code will be exactly equal to the first bit of the given binary number.
Now the second bit of the code will be exclusive-or of the first and second bit of the given
binary number, i.e if both the bits are same the result will be 0 and if they are different the
result will be 1.
The third bit of gray code will be equal to the exclusive-or of the second and third bit of the
given binary number. Thus the Binary to gray code conversion goes on. One example given
below can make your idea clear on this type of conversion.

BINARY TO GRAY
TRUTH TABLE:
BINARY INPUT GRAY CODE OUTPUT

D
D B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1 1
2 0 0 1 0 0 0 1 1 3
3 0 0 1 1 0 0 1 0 2
4 0 1 0 0 0 1 1 0 6
5 0 1 0 1 0 1 1 1 7
6 0 1 1 0 0 1 0 1 5
7 0 1 1 1 0 1 0 0 4
8 1 0 0 0 1 1 0 0 12
9 1 0 0 1 1 1 0 1 13
10 1 0 1 0 1 1 1 1 15
11 1 0 1 1 1 1 1 0 14
12 1 1 0 0 1 0 1 0 10
13 1 1 0 1 1 0 1 1 11
14 1 1 1 0 1 0 0 1 9
15 1 1 1 1 1 0 0 0 8
SIMPLIFICATION:
BINARY TO GRAY
G3
B1B0
B3 B2 00 01 11 10
00
01
11 1 1 1 1
1 1 1 1
10
Simplification:
G3=B3

G2
B1B0
B3 B2 00 01 11 10
00
01 1 1 1 1
11
1 1 1 1
10
Simplification:
G2=B3 B2 + B3 B2
G1
B1B0
B3 B2 00 01 11 10
1 1
00
01 1 1
11 1 1
10 1 1
Simplification:
G1=B2 B1 + B2 B1

G0
B1B0
B3 B2 00 01 11 10
1 1
00
01 1 1
11 1 1
10 1 1
Simplification:
G0=B1 B0 + B1 B0
CIRCUIT:

GRAY TO BINARY
Gray code to binary conversion is again very simple and easy process. Following step scan
make your idea clear on this type of conversions.
The M.S.B of the binary number will be equal to the M.S.B of the given gray code. Now if
the second gray bit is 0 the second binary bit will be same as the previous or the first bit. If
the gray bit is 1 the second binary bit will alter. If it was 1 it will be 0 and if it was 0 it will be
1. This step is continued for all the bits to do Gray code to binary conversion. One example
given below will make your idea clear.
TRUTH TABLE:
Decimal GRAY CODE INPUT BINARY OUTPUT

No G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
3 0 0 1 1 0 0 1 0
2 0 0 1 0 0 0 1 1
6 0 1 1 0 0 1 0 0
7 0 1 1 1 0 1 0 1
5 0 1 0 1 0 1 1 0
4 0 1 0 0 0 1 1 1
12 1 1 0 0 1 0 0 0
13 1 1 0 1 1 0 0 1
15 1 1 1 1 1 0 1 0
14 1 1 1 0 1 0 1 1
10 1 0 1 0 1 1 0 0
11 1 0 1 1 1 1 0 1
9 1 0 0 1 1 1 1 0
8 1 0 0 0 1 1 1 1

SIMPLIFICATION:
B3
G1G0
G3 G2 00 01 11 10
00
01
11 1 1 1 1
10 1 1 1 1
Simplification:
B3=G3
B2
G1G0
G3 G2 00 01 11 10
00
01 1 1 1 1
11
10 1 1 1 1
Simplification:
B2=G3 G2 + G3 G2

B1
G1G0
G3 G2 00 01 11 10
00
1 1
01 1 1
11 1 1
10 1 1
Simplification:
B1=G3 G2 G1 + G3 G2 G1 + G3 G2 G1 + G3 G2 G1
= G1(G3 G2 + G3 G2) + G1(G3 G2 + G3 G2)
B0
G1G0
G3 G2 00 01 11 10
00
1 1
01 1 1
11 1 1
10 1 1
Simplification:
B0=G3 G2 G1 G0 + G3 G2 G1G0 + G3 G2 G1 G0 + G3 G2 G1G0 +

G3 G2 G1G0 + G3 G2 G1G0 + G3 G2 G1G0 + G3 G2 G1G0
= G3 G2 (G1 G0 + G1 G0) + G3 G2 (G1 G0 + G1 G0) +

G3 G2 (G1 G0 + G1 G0)+ G3 G2 (G1 G0 + G1 G0)
= (G1 G0 + G1 G0) (G3 G2 + G3 G2) + (G1 G0 + G1 G0)
(G3 G2 + G3 G2)

CIRCUIT:
G3 G2 G1 G0
B3 = G3
B2= G3 G2 +G3 G2
B1= B2 G1 + B2 G1
B0= B1 G0 + B1 G0
PROCEDURE:
• Check for the working condition and Patch cords.

• Connect the components as shown in circuit diagram.
• Observe the logical output and verify truth table.
• Repeat these steps for both binary to gray & gray to binary.
APPLICATIONS:
It used in labeling the cells of K-Maps.

It plays a vital role in error correction in digital communications.
RESULTS:
Binary to Gray and Gray to Binary converters are verified with basic gates.

8.Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop
ICs and demonstrate its working.
AIM:
To Design and implement a mod n (a<8) synchronous up counter using JK FF IC’s and
demonstrate its working.
THEORY:
The ripple (Asynchronous) counter requires a finite amount of time for each flip flop to
change state. This problem can be solved by using a synchronous parallel counter where
every flip flop is triggered in synchronism with the clock and all the output which are
scheduled to change do so simultaneously.
The counter progresses counting upwards in a natural binary sequence from count 000 to
count 111 advancing count with every clock transition and get back to 000 after this cycle.
In synchronous counter, all of the FF’s are clocked at the same time. Before each clock pulse,
the J and K inputs of each FF must be at the correct level to ensure that each FF goes to the
correct state.
TRUTH TABLE:
Present State Next State

Q2 Q1 Q0 Q2+1 Q1+1 Q0+1 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1
EXCITATION TABLE
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

K-Map
J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q1*Q0

CIRCUIT: Mod 8
Q0 Q1 Q2
Vcc +Vcc
PRE
J1 PRE Q1 J2 PRE Q2
J0 Q0
Clk
Clk
K2 Q2
K1 Q1
K0 Q0
CLR CLR
CLR
+Vcc
Clk
PROCEDURE:
APPLICATIONS:
Used to generate desired frequency for oscillator.
RESULT:
Mod-8 Counter was designed and implemented using JK Flip-Flop.

9. Design and implement an asynchronous counter using decade counter IC to count up

from 0 to n (n<=9) and demonstrate on 7-segment display (using IC-7447).
AIM:
To design and implement an asynchronous counter using decade counter IC to count up from
0 to n (n≤9)

1 IC7490 1
2 Patch chords
3 Trainer kit
4 IC7447 1
THEORY:
Asynchronous counter is a counter in which the clock signal is connected to the clock
input of only first stage flip flop. The clock input of the second stage flip flop is triggered by
the output of the first stage flip flop and so on. This introduces an inherent propagation delay
time through a flip flop. A transition of input clock pulse and a transition of the output of a
flip flop can never occur exactly at the same time. Therefore, the two flip flops are never
simultaneously triggered, which results in asynchronous counter operation.
Pin Diagram: 74LS90 / 74LS47

Pin Names Description of 7447:

A0–A3 =BCD Inputs
RBI =Ripple Blanking Input (Active LOW) LT= Lamp Test Input (Active LOW)
RBO =Ripple Blanking Output (Active LOW) a –g =Segment Outputs (Active LOW)
Pin Names Description of 7490:
R1 and R2-clear all flip-flop (high active and low for not active) S1 and S2- set all flip flop
(high active and low for not active) CLKA-clock pulse to first flip flop
CLKB-clock pulse to second flip flop (output of first flip flop clock for second filp flop)
Circuit Diagram
DESIGN FOR DECADE COUNTER

TRUTH TABLE:
CLK QD QC QB QA
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 0 0 0 0
1 1 0 0 1
For mod 9
connect Q0 and Q3 to reset(clear) through an AND gate. Reset should not be connected to the
switch
For mod8
Connect Q3 to reset
For mod7
Connect Q2, Q1,Q0 to reset through an And Gate
For Mod 6
Connect Q2 and Q1 to reset through an AND gate
For mod 5
For Mod 4
Connect Q2 to reset
For mod 3
For mod 2
Connect Q1 to reset

PROCEDURE:
APPLICATIONS:
To count the number of pulses at the input and to check lexico graphical errors in
programming language.
RESULT:
Decade Counter was realized using 7490 and 7447(7-Segment Display).

STEPS FOR SIMULATION

Introduction to Xilinx ISE
Xilinx ISE means Xilinx® Integrated Software Environment (ISE), i.e. programmable logic design tool
in electronics industry. This Xilinx ® design software suite allows taking design from design entry
through Xilinx device programming. The ISE Project Navigator manages and processes design through
several steps in the ISE design flow. These steps are Design Entry, Synthesis, Implementation,
Simulation/Verification, and Device Configuration. Xilinx is one of most popular software tool used to
synthesize VHDL code.
Tool Procedure:
1. Double click on Project Navigator Icon.
2. Select new project in file menu.
3. Enter the project name and location as shown below and press NEXT.
4. Select the Family, Device, Package and speed as per the requirements and press NEXT.
5. Create a new source by using new source icon or right click on the device/project folder to create
new source.
6. Select the appropriate source type and enter the file name in New Source Wizard window and
press NEXT

7. Enter the architecture name – dataflow/behavioral/structural, port name and select the direction.
This will create .v source file. Press NEXT and finish the initial project creation.
8. Write complete VHDL/Verilog code implementation and save.
9. Click on implementation and check for syntax using “Check syntax” option under synthesize
tab. If any error, edit and correct VHDL/Verilog code and repeat check syntax until zero errors.
CPLD reports will be generated.
10. After CPLD report is generated go to source window in the top and select behavioral
simulation.
11. Go to processes window below the source window, select your file and click on
simulate behavioral model. We will get Modelsim XE III/starter 6.0a-custom Xilinx
version.
12. Default wave window will appear maximize the window.
13. Click on RESTART button to delete the unwanted waveforms.
14. Select and right click on the variable you want to give inputs and click force. Give input value
in value box(either 0 or 1 or x).
15. Once the required number of input is given click on RUN. We will get the output waveform in
the modelisim window. Click on the waveforms to see the input and output value in data
column.

PSPICE SIMULATION TOOL
In order to ensure a successful circuit design and mitigate costly and potentially dangerous design
flaws, careful planning and evaluation must occur at every stage of the circuit design process. Circuit
simulation provides a cost-effective and efficient method for identifying faults before moving to the
more expensive and time-consuming prototyping stage. Including simulation in the design process
reduces design errors and speeds the design cycle by allowing you to predict and better understand
circuit behavior. The main purpose of simulation is to predict and understand the behavior of
electronic circuits. PSpice is a program that simulates electronic circuits on your PC.
Limitations of simulation:
While a prototype helps you to verify and validate your design in the real world, simulation helps you
catch design errors before spending money and time on prototyping.
Orcad 9.2 Lite Edition Installation:

Insert Cadence CD into CD-ROM drive
Select Products to install
Capture – Schematic entry application – it must be installed

Capture CIS – Should be grayed out.
PSpice – For conducting mixed-signal analog and digital simulations
Layout– For creating PC Board layouts from schematics
Then follow the instructions as it appears on the monitor and complete the installation
The steps to simulation:

Create a simulation project
Draw schematic to simulate
Establish a simulation profile
Set up simulation type
Simulate circuit
Analyze results in Probe
General procedure for all experiments:

Select the required components from the menu.
Place all the required components in the schematic.
Simulate the circuit using RUN option from the menu.
Observe the waveforms form the output
To start a simulation session:

1. On the start menu select ORCADFAMILY RELEASE 9.2 LITE EDITION - CAPTURE LITE
EDITION
2.Once the capture window appears, select FILE - NEW – PROJECT. The following window appears:
3.Give the project a descriptive name (spaces can be included).
4.Select ANALOG OR MIXED-SIGNAL CIRCUIT WIZARD.
5.Specify a location where the project is to be stored

6. Click OK.
The following window appears:
7. Select Create a blank project and click OK. The following window appears:

8.To place parts, click PLACE PART (Shift+P). Then the following window appears:
If Libraries are not appearing in the window then click Add Library. The library files will generally be
available in the following path by default.
C:\Program Files\Orcad_Demo \Capture \ Library\Pspice. Select all Library files by pressing Ctrl A
and then press Open. All the
Library files will appear in the window.
9. Select the part you wish to place in the schematic. Insert as many as needed
10. Right Click and select END MODE to stop inserting parts
11. To wire parts together, click Place Wire Icon from the Right hand side vertical Icons list
(Shift+W). Place cursor over boxes at ends of parts and draw wires connecting parts. When done,
right click and select End Wire.
12. To insert a ground node, click Place – Ground Icon. Window appears with caption Place Ground
with only ground nodes available for selection.

Always select 0/SOURCE for the ground node of an analog circuit – every analog circuit must
contain at least one 0 ground. This is not a requirement for digital circuits.
13. To change component values that are displayed. Double click the displayed value· Change the
desired value in the dialog box that appears.
To set up a simulation profile:
Select PSPICE ---NEW SIMULATION PROFILE from the menu.
Give a descriptive name to the type of simulation.
Select the desired parameters for the particular circuit and then click OK.
Place voltage, current, and power markers from the PSPICE --- MARKERS menu where needed.
Click PSPICE – RUN

Sample Viva Questions

1) Why operational amplifier is called by its name?
2) Explain the advantages of OPAMP over transistor amplifiers.
3) List the OPAMP ideal characteristics.
4) Give the symbol of OPAMP
5) Explain the various applications of OPAMP
6) Define UTP and LTP
7) Mention the applications of window comparator
8) What is a bipolar and unipolar devices? Give examples
9) Define resolution
10) What is a multivibrator?
11) What is a bistable multivibrator?
12) Give the applications of monostable and astablemultivibrator
13) Explain the working of 555 timer as astable and monostable multivibrator
14) Why astable multivibrator is called as free running multivibrator
15) Define duty cycle.
16) List the applications of 555 timer
17) Explain 555 timer as astable multivibrator to generate a rectangular wave of duty cycle of less
than 0.5
18) Define a logic gate.
19) What are basic gates?
20) Why NAND and NOR gates are called as universal gates?
21) State De morgans theorem
22) Give examples for SOP and POS
23) Explain how transistor can be used as NOT gate
24) Realize logic gates using NAND and NOR gates only
25) List the applications of EX-OR and EX~NOR gates
26) What is a half adder?
27) What is a full adder?
28) Differentiate between combinational and sequential circuits. Give examples
29) Give the applications of combinational and sequential circuits
30) Define flip flop
31) What is an excitation table?
32) What is race around condition?
33) How do you eliminate race around condition?
34) What is minterm and max term?
35) Define multiplexer/ data selector
36) What is a demultiplexer?
37) Give the applications of mux and demux
38) What is a encoder and decoder?
39) Compare mux and encoder
40) Compare demux and decoder
41) What is a priority encoder?
42) What are counters? Give their applications.
43) Compare synchronous and asynchronous counters
44) What is modulus of a number?
45) What is a shift register?
46) What does LS stand for, in 74LSOO?
47) What is positive logic and negative logic?
48) What are code converters?
49) What is the necessity of code conversions?
50) What is gray code?
51) Realize the Boolean expressions for Binary to gray code conversion Gray to binary code
conversion?

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BANGALORE INSTITUTE OF TECHNOLOGY

K.R. ROAD, V.V PURAM, BANGALORE – 560 004

(AFFILIATED TO VTU, BELAGAVI)

ANALOG AND DIGITAL ELECTRONICS LABORATORY

As per Choice Based Credit System Scheme (CBCS)

FOR III SEMESTER CSE/ISE AS PRESCRIBED BY VTU

Academic year 2019-2020

Bangalore Institute of Technology

• Knowledge of Basic Electronics.

• Knowledge of Analog and Digital Principles.

After studying this course, students will be able to:

• Analog components and circuits including Operational Amplifier, Timer, etc.

Understand the applications of Electronic components, ICs and tools to design

Dept of ISE, BIT Page 2

CO’S & PO’S MAPPING

Guidelines given by the University for Conduction of laboratory:

Dept of ISE, BIT Page 3

Analog and Digital Electronics Laboratory

Course Code: 18CSL37 CIE Marks : 40

PART A ( Analog Electronics Circuits)

PART B( Digital Electronics Circuits)

Dept of ISE, BIT Page 4

Analog & Digital Electronics Laboratory

Course Code: 18CSL37 CIE Marks : 40

Daily Conduction rubrics (Max: 20 marks)

5Marks 5Marks 5Marks 5Marks

Test rubrics (Max: 15 marks)

4Marks 6Marks 5Marks

Group Activity rubrics (Max: 5 marks)

2Marks 2Marks 1Mark 5Marks

Dept of ISE, BIT Page 5

Analog & Digital Electronics Laboratory

Course Code: 18CSL37 CIE Marks : 40

Design and implement an asynchronous counter using decade

Design and implement a mod-n (n<8) synchronous up counter Week8

Design an astable multivibrator circuit for three cases of duty cycle

Using ua 741 Opamp, design a 1 kHz Relaxation Oscillator with Week10

Dept of ISE, BIT Page 6

Dept of ISE, BIT Page 7

Basics Gates & its implementation using NAND

Dept of ISE, BIT Page 8

Pin diagrams of Logic gates

Dept of ISE, BIT Page 9

Cathode-Ray Oscilloscope and Signal Generator used in Analog Experiments

Pin Diagram of OPAMP 741

Pin Diagram of 555 Timer

Dept of ISE, BIT Page 10

Analog Electronics Circuits -PART A

Sl.no Name of Component No.’s Sl.no Name of Component No.’s

i) Astable or free running multivibrator: It alternates automatically between two states

Dept of ISE, BIT Page 11

Design 2: 50% Duty Cycle Astable Oscillator

50% Duty Cycle Frequency Equation

Dept of ISE, BIT Page 12

• Before making the connections, check the components using multimeter.

Dept of ISE, BIT Page 13

SIMULATION CIRCUIT FOR ASTABLE MULTIVIBARTOR:

Dept of ISE, BIT Page 14

To implement a Op-Amp relaxation oscillator for the frequency of 1 kHz.

Sl.no Name of Component No.’s Sl.no Name of Component No.’s

Dept of ISE, BIT Page 15

For frequency 1khz. i.e.

Dept of ISE, BIT Page 16