RFIC Notes PDF

RF Circuits –
Design & Analysis
Dr. T K Bhattacharyya
E & ECE Dept.

IIT Kharagpur.
Dr. T. K. Bhattacharyya,Dept. of E&ECE

Basics of RF

What is RF?
•Why Lumped parameters models failed ……………….
• Kirchoff's to Maxwell’s…….
• Failure of two port circuit parameter (Z, Y,ABCD) ……..
• Scattering parameter( S-parameter) on the basis of

Maxwell equation comes in …

Application area of the RF-IC designer
•Wireless communication
•Radar
•Navigation
•Remote sensing
•RF identification
•Automobile and Highways
•Sensors:
•Medical
•Radio- astronomy and space exploration

Beauty of RF- IC Design:
Link between Microwave Engineer and Design Engineer
kirchoff’s law
No net current build Total voltage around a
up at any node(KCL) loop is zero( KVL)
•If ε & μ =0, (c α ) i.e infinitely fast wave

propagation of wave gives KVL and KCL
•As the physical dimension of circuit element & sub-circuit in a IC chip is very less
th
(even less than 1/10 of λ [ 30 cm in air at 1 GHz] ) , so finiteness of the speed of
light is not noticeable inside chip, so a full transmission line ( Microwave) for on-
chip design and analysis is generally unnecessary. Kirchoff’s law is well suited for
on-chip design
•But for interfacing the RF signals in / out of the chip, we need connectors, boards,
cables etc. Where transmission-line effects cannot be ignored
Comparison of Analog and RF/MW
1. On Discrete PCB component
( Analog [Low frequency<100MHz] ) ( RF/MW[ High frequency>100MHz] )
Conductor Simple Microstrip

wire line
Ceramic
Capacitor Thin Film
SMD comp.
Resistor Carbon Thin Film

SMD comp.
Inductor Wire Thin Film

Wound SMD comp.

Comparison of Analog and RF/MW
1. On Performance Based
( Analog [Low frequency<100MHz] ) ( RF/MW [High frequency>100MHz] )
A. Small signal AC equivalent A. Small signal AC equivalent circuit

circuit analysis analysis with parasitic i.e. Good circuit
Modeling
B. Linearity B. Matching
C. Stability C. Noise
D. Noise (on few cases) D. Stability
E. Linearity
F. Sensitivity
G. Dynamic range
RF Circuit & Systems – Design Issues
Phase shift of the signal is significant over the extent of the component
because it’s size is comparable with the wavelength.
The reactance of the circuit must be accounted for, particularly those associated
with the parasitic of the active devices.
Circuit losses causes degradation of Q, reduction of frequency selectivity and noise

performance.
Noise especially arising from the circuit can be significant and it’s effect needs to
be modeled.
Electromagnetic radiation capacitive coupling and substrate coupling significantly alter

the performance of the circuit.
Reflection issues, because circuit size is of the order of a wavelength.
Circuit design should take care to ensure reflections do not cause any loss of gain,
power, or failure of components.
Nonlinearity which causes distortion and unwanted frequency components is

undesirable, but it may become essential part of the circuit operation, as in mixing or
local oscillators.
High Frequency Device
modeling
Silicon Technologies
Bipolar BiCMOS MOS
Junction PMOS NMOS

Dielectric
Isolated
Isolated
BJTs
CMOS
High Frequency Device modeling (contd.)
Visualization of Process Flow
Protective Overcoat
CVD Oxide
Metal-2
via
Metal-1
contact
poly Gate oxide

FOX
+ +
n n
p-epi
p-substrate

WHY CMOS FOR RF-IC?
Standard Digital CMOS is hardly the ideal
medium for RF ICs, because of :
CMOS BJT
„ Lossy Silicon substrate
ƒ Symmetric behavior. ƒ Higher gm for same
„ Large source/drain parasitics ƒ Better linearity bias.
High device noise and poor 1/f noise performance(Higher signal swing). ƒ High fT.
„ Series gate resistance ƒ Higher fT at sub- ƒ Low thermal and 1/f
micron feature size. noise, but input
ƒ Better scaling current noise.
But, properties. ƒ Lower DC offset .
„ Device scaling …faster ƒ Low power (no gate ƒ No body effect.

„ CMOS f (and f ) ….range of 60GHz doubles DC current).
T max
ƒ Lower overdrive
roughly every 3 years. (Low VCE sat).

CMOS is cost effective
Both digital & analog block can be designed on
same substrate
High linearity; Low distortion
Low power consumption
On-chip realization of passive inductors and
capacitors

R
R C C C C
poly
R sub
gs gd ds
•To calculate magnetic coupling between two adjacent metal line, interlayer capacitance ,
EMI between subcircuits & on-chip passive component (such as inductor and MIM
capacitor) , the Maxwell EM equation is required ( Challenging issue !!!)
RF CMOS MODELLING
“Standard” (digital oriented) MOS models do not allowllow forfor RFRF
Maximumm unitunit powerpower gaingain
frequencyfrequency
Maximum Cutut--offoff frequencyfrequency
In RF, Cgs ( whose effect negligible in low frequency analog) affects the matching with
successive blocks . Frequency dependence of Transconductance(g m )
RF CMOS MODELLING
Long channel effect
1 W
Id = 2 μ n C o x L ( V g s − Vt ) 2
3 μn
f = 2 ( V gs − V t )
T 2 2πL
Short channel effect
μ n ε dv
V d = ε =
ε dy
1 +
,
ε c
I = Q WV (y) 1 dv dv
I d (1 + . ) = W Q I ( y )μ n
d I d
εc dy dy
μ C
n ox W 2
Id = V ( V gs − V t )
V g s − t L
2 (1 + )
μ C ε c L
= n ox W (V − V)
2
V =μ ε
scl n c
2[1 + θ ( V g s − V t )] L gs t
2 ( V gs − V t )
1+ −1
g =WC V εcL
m ox scl
2 ( V gs − V t )
C =C 1+
c.f Lee P-68,70 gc ox C cb = Csi ε cL ,
C C
sbo dbo
C
jsb
=
V
sb 1/2
C
jdB
=
V
db 1/2
• fT independent of overdrive voltage (V − V )
ψ gs t
(1 + ψ 0 ) (1 + 0 ) • fT inversely proportional to L
Noise
Significance :The significance of noise performance of a circuit is the limitation it places on the
smallest input signals(MDS) the circuit can handle before the noise degrades the quality of output signal.
• Thermal Noise
-Brownian motion of thermally agitated charge carriers - generated in every physical resistor
- pure reactive components generate no thermal noise
Thermal Noise in MOSFET

Th most significant source of noise
Channel Noise:
In2 = 4kTγgm
• γ ~1 at a zero VDS for long channel device, 2/3 at saturation, 2-3 for short channel transistor

Gate induced noise
Thermal agitation of channel charge cause fluctuation of channel potential. This couples
capacitively with gate terminal, leading to gate noise
• this noise is negligible at low frequency, but can dominate at RF
• δ ~ 4/3 in long device

- both drain and gate noise share a common origin and they
are correlated
Shot Noise
-Gaussian white process associated with the transfer of charge across an energy barrier
- due to DC current through p-n junction, gate channel
Flicker noise in MOSFET

-random trapping of charge at oxide interface
- modeled as a voltage source in series with gate

Noise figure (cont..)
Noise figure of cascaded stages ..
For two stage case it can be shown
For m- stages
• NF of each stages is calculated with respect to the output impedance of previous stages
• The noise is contributed by each stage decreases as the gain preceding the stages increase
•That’s why the first stage of any system should have higher gain with low noise figure ( PRIME
CRITERION FOR LOW NOISE AMPLIFIER (LNA) DESIGN OF A RECEIVER)
Sensitivity

Dynamic Range

Modeling of Arbitrary Shaped
RF Spiral Inductors for Circuit Simulation
Complex field coupling between turns.
„ For on- chip spiral inductor the following difficulties arise due
to conductive substrate:
1) Eddy current in the substrate
2) Coupling between field generated by the coil and field
generated by the eddy current. This mutual coupling increases the
active part of the current and as a result Q decreases.
Proposing a New Generic Methodology of Modeling RF Spiral Inductor
for Circuit Simulation.
Developing a System Identification Algorithm for the proposed
modeling technique.

Direct Transfer-Function Estimation
from Frequency Response Data:
Dimension Numerical
and Techniques [S( ω [Y(ωk)]
Material or k)] Parameter
Property Measurement Para
meter Zin(ωk) =
1
Z ind (s) = Y (s) ; 1/Y11(ωk)
11
Model Order
1
L = ω Re[Y11−1 (s)]; &
Model Parameter
= Im[Y −1 (s)] Estimation Algorithm
Q 11 Transfer Function
Re[Y11−1
ˆ
(s)
(s)] Z
in
The basic Idea
Both model order and model parameters

are identified with PSO.
Two independent PSO has been used.
One PSO has been used for model parameter
Estimation for a given model order.
Another PSO has been used for model
order Estimation.

Case Study I
TABLE I
Dimensions Of The Inductor Used In Case Study I
Outer Diameter (μm) 120
Metal Width; Metal Spacing (μm) 5.5; 3
No. of Turns 6
Metal Layer; Under Pass M6; M5

TABLE II
Parameters Of The Estimated Transfer Function
K (Gain) 1.5771039E-10
Z1 (1st Zero) 1.0146618E+9
Z2 (2nd Zero) 1.2566E+13
P (Pole) 8.6472026E+11

TABLE III
Estimated Parameters Of The Nine-Parameter Model
LS (nH) 1.3041006
RS (Ohm) 2.385343
R
Si (Ohm) 1000
CS (fF) 6.1117785
C
OX (fF) 484.85646
C
Si (fF) 8.1567198

55 Measured Zin
Zin of 9 Parameter Model
Estimated Zin
50
Magnitude (dB) 45
40
35
30
25
20
15
10 9 10 11 12
10 10 10 10
Frequency (rad/sec)
90
Measured Zin
Zin of 9 Parameter Model
Estimated Zin
85
80
75
70
65
60
55 9 10 11 12
10 10 10 10

RF Transceiver Design

From System level to
Component level specifications (contd.)
Block Diagram of the Receiver System
Sensitivity of the Receiver

Noise Figure of the Front-end
Given
•SNRout Required = 14 dB
•Sensitivity Required( Pin,min) = -90 dBm
•Bandwidth = 2 MHz
The required Noise Figure of the receiver front-end is
calculated from the sensitivity eqn.
- 09 =- 74+1 10 log10(2x103) + NF + 14
Î NF = 7 dB

Gain, NF and IIP3 of cascaded stages
Total Gain
Ap = A p1 × A p2 × L × Apk
Total Noise Factor
N F2 − 1 N F3 − 1 N Fk − 1
N F=N F1 + A + A A + ..... + A A ...A
p1 p1 p2 p1 p2 p(k-1)
Total IIP3
A A A A A ...A
1 1 p1 p1 p2 p1 p2 p(k-1)
= + + + ..... +
IIP IIP IIP IIP IIP
3 3,1 3,2 3,3 3,k
Where NFi, Api and IIP3,i are respectively Noise Factor , Available
Power Gain and input 3rd order intercept point of the i-th stage

Example- Gain and NF calculation

RF Transceiver Design:
Low Noise Amplifiers

LOW NOISE AMPLIFIERS
Design consideration :
Characteristics :
First gain stage in receiver Noise Figure: 2~3dB
Gain: 15~20dB
Received signal very weak (~μV)
IIP3: ~ -10dBm
Gains usually moderate (10-20 dB Input/output Impedance: 50 Ohm
typical) Input/output Return Loss: -15dB
Noise Figure (NF) should be as low Reverse Isolation: >30dB
as possible (<3 dB typical) Stability Factor >1
Linearity is also an issue
Reverse Isolation should be high

Different structure of CMOS LNA
All structures are narrow-band
¾ Capacitive input impedance.

¾ Lg cancels Capacitive term.
¾ A parallel RS (50 Ω) is added to
match input source R50.
Common source LNA ac equivalent model
¾ To reduce the effect of Zout (img)
Disadvantage of this circuit : on tuning circuit, C value should
be large compared to Zout
¾Due to Rextra , the power divide by 2.
¾NF ~1+ (γ/α) * Rextra/R50 , γ & α Corresponding circuit
(=gm/gdo) are device parameter. NF~3-4 dB.
¾Due to Cgd reverse isolation(S11) Bad.
¾Cgd affects stability due to presence of zero
in transfer function (Vout/Vin)

Most popular LNA topology
Remedy ………
“ Cascode source degeneration common source”
Equation for choosing Input matching networkork ComponentComponent
¾ Choosing of device (W/L) & Vgs : determine gm &

Cgs value , then Ls and Lg can be found.
¾ Effect of channel resistance & gate resistance :
modify above equation (Fingering is done in layout
to reduce this value ).
¾ The parasitic of inductor must be considered for
calculating practical component values.
Equation for choosing output matching networketwork componentcomponent
¾ Gate of M2 is ac ground, so
output cap due to Zout is ¾ Good L, Q is 22 ––3,3, thenthen getget Rd,Rd,
Cgd2 only…. C value lesser. ¾ From Rd findd--outout equivalentequivalent LdLd

by ASITIC withith maximummaximum
¾ As impedance looking to source possible Q. thenhen calculatecalculate CC from
of M2 is 1/gm2 as a result Miller
ω0, checkk whetherwhether CC isis much
cap effect gets reduced.
larger(~1010 timestimes ofof CgdCgd))

1 V Low Noise Amplifier
9 Native MOSes used to facilitate low voltage operation

9 The input N/W consisting of LG and CGS is tuned to
900 MHz.
9 The LC load is also tuned to 900 MHz.
9 Gate induced noise is included in simulation by an
equivalent resistor.
Performance Values in the typical

Parameters corner
Supply Voltage 1 Volt
Bandwidth 825 - 975 MHz
Voltage Gain 16.53 dB
Power Consumption 4.06 mW
Noise Figure 2.327 dB
Schematic

Subthreshold RF Design:
Multiband & Wideband Applications

Introduction
¾ Major challenges in VLSI Design:
Power Consumption.
Performance (Speed/Area).
Reliability.
¾ Subthreshold region design
Weak inversion MOSFET provides
sufficient transconductance.
¾ Very low power consumption.
¾ Major RF Front-end modules
Low Noise Amplifier (LNA)
Voltage Controlled Oscillator (VCO)
Subthreshold Region:
¾ For a MOSFET:
V <V
GS TH (VGS −VTh )
I =I e ηVT
¾ Exponential Current Equation: DS on
¾ Important parameter in subthreshold:

Subthreshold Slope
dV dV
GS GS
S= ; 2.3 = 2.3ηVT
d (log I D ) d (ln ID )
Single Band LNA
¾ Input Impedance (in saturation):
I
g L out
Z = m s + sL + 1
in C s
gs sCgs
Z
in
¾ Tune gm or LS:
Real Part = 50 Ω
Imaginary Part = 0
¾ Input Matching : LNA input Device
Pad-Pin parasitics modify input impedance.
Separate off-chip matching network required.
Matching needed over a bandwidth – Q based matching.
Subthreshold Operation and Modeling
¾ Accurate input impedance modeling:

Closed Form expression of input impedance.
Automatic generation of Q-based matching
network.
¾ Effect of parasitic capacitors

Device capacitors play a major role.
Channel not fully formed.
Gate-to-Bulk & Source-to-Bulk capacitors
Subthreshold Operation and
Modeling (Contd.)
R
C
L
M
2
V
out
L L
pin bond
M1
C C R
frame pad SS
Z
in
LS
Schematic of packaged
cascode LNA
Subthreshold Operation and Modeling (Contd.)
g V C
m2 gs2 out
C
L L gd1
pin bond V1 V0 ZL
g V
m1 gs1 -
C + C V C +C +C
C C gb1 V gs1
gs2 gs2 sb2 db1
frame pad gs1
- +
Vx
C
sb1 Ls
R
S
Modified Subthreshold region model of

LNA input
Verification of Model
Effect of Cgb and Csb

Verification of Model (Contd.)
Model and simulation results coincide

Q-based input matching
¾ Matching over a bandwidth:
¾ Bandwidth defined by Quality Factor (Q)
f0
Q= f
¾ Conventional techniques:
¾ and T matching techniques.
π L L1 L2
RL RL
C1 C2 C
π match T match
π match network analysis
Variation of matching
components with frequency
π match network analysis (contd.)
Variation of matching
components with LS
π match network analysis (contd.)
Variation of Matching components

with VGS
Effect of Finite component Q
¾ Severe degradation of matching performance
S forideal case and Q=30

Dr. T. K .Bhattacharyya,Dept . ofE&ECE
11
Limitations of Conventional Approach
' Unsymmetrical profile for S11 over

the bandwidth.
' Similar problems with Real and

Imaginary part of input impedance.
' Effect prominent at lower frequency bands

[GSM band (900MHz)].

PSO Based Matching Technique
¾ Based on Particle Swarm Optimization

¾ Heuristic method.
¾ Based on flocking of birds/swarms.
¾ Reaches optimum by modifying velocity of each
particle.
¾ PSO based approach applied to Q-based matching
¾Desired Real part profile -

PSO Based Matching Technique (Contd.)
¾ Equations Optimized :
f1 =| Re(Z in @850 MHz ) −35| + | Im(Z in @850 MHz) |
f2 =| Re( Zin @950MHz ) −35 | + | Im( Zin @950MHz) |
f3 =| Re(Z in @900 MHz ) − 50 | + | Im(Z in @900 MHz) |
fopt = w1 f1 + w2 f 2 + w3 f3
Wi’s are weights of fi. Weight of function at 900MHz

was maximum
Results of PSO Based matching

Concurrent Dual-band LNA
¾ Existing technique (Hashemi): R
Cancellation of imaginary part at L

C
2 frequencies using LC
tank network M2
V
out
Lg M
1
L L
bond
R
g S
SS
m C L
gs S
Cg
Z
in
Real Part = made 50 Ω by adjusting

gm and LS.
Concurrent Dual-band LNA (Contd.)
¾ Drawbacks of existing technique:
' Pad/Pin parasitics severely influence both real

and imaginary part of input impedance.
' Input matching is only at 1 frequency, i.e. not Q-based

over a bandwidth.
' Value of LS required for input match is generally very

high at lower center frequencies.

Proposed PSO based matching
Unity Current
LNA input impedance at 2 predefined frequencies
Source
Q-based pi
Matching network value for 2 frequencies match
Select Network topology for LC tank, LC series,

each pi element combination, etc
Calculation of network
values

Results of dual-band matching
Accurate input match at both frequencies

(900MHz and 1.8GHz)
Finite Q effect
¾ Finite Q of components affect matching

performance.
¾ Individual networks have different effects

on final input match.
¾ Lseries and C1 component finite Q have

minimal effect on matching performance.

Mixers

Mixer
Mixers
Indispensable components of transceivers
Used to up-convert or down-convert a baseband signal to/from the

carrier frequency
Basic philosophy behind mixing is MULTIPLICATION
Say we have 2 frequencies f1 and f2, then
cos 2πf1t and cos 2πf2t are the 2 signals
Multiplying them gives evidently the f1-f2 and the f1+f2
components, out of which, one we select through filtering

Downconversion Mixers
The most basic Downconversion mixer is the Gilbert cell mixer
RF signal: Radio Frequency signal

LO signal: Local Oscillator signal
Vout gives the IF or the Intermediate frequency signal

Basic terms associated with mixing
Conversion Gain: Gc= VIF/VRF=> the 2 signals are evidently at 2
different frequencies
Noise Figure (in dB): S/N ratio at IF output port –S/N ratio at RF output
port
NFSSB= NFDSB + 3dB
Linearity: 1dB compression point, IIP2 and IIP3 shown as

Gilbert Mixer…… analyzed
Approximating the LO signal as a square wave

G = 2g R
c π m L
Noise figure is typically of the order of 10-15dB
The main catch, however, is in the DC offset arising from the low LO-RF
isolation as shown.

Hmmm….so?
The problem of DC offset arising out of poor LO-RF isolation can pose
serious problems by saturating the IF stage
The problem arises simply because the LO and the RF bands lie in such
close proximity in the frequency spectrum
……………..
What if we mix LO(=RF/2) with RF instead of RF with LO=RF?
This is precisely what we mean by even harmonic mixing

Even Harmonic Mixing
Harmonic mixer suppresses the fundamental mixing between the signal and
LO
It allows mixing of the signal with the harmonics of LO

Lets “even” out things!!
The basic structure is as follows:

The RF signal is amplified by the transconductor stage to generate the
RF current.
This RF current is fed to a switching stage controlled by the LO signals.
The transconductor has been designed as shown:

Let’s “even” out things (2)
The LO-controlled switching stage is as shown:
The LO signals are applied in quadrature mode i.e. each one is 90° phase-
shifted from the other.

Let’s “even” out things(3)
The quadrature LO signals are applied in an AND-OR mode as shown in the

switching stage resulting in a frequency doubling as shown diagrammatically
AND
OR

Frequency Synthesizers

Frequency Synthesizer Block Diagram
PLL-based Frequency Synthesizer consists-
¾ Phase Frequency Detector (PFD)
¾ Charge Pump (CP)
¾ Loop Filter (LF)
¾ Voltage Control Oscillator (VCO)
¾ Frequency Divider
Integer N Divider (Integer N Frequency Synthesizer)
Fractional N Divider (Fractional N Frequency Synthesizer)
REFERENCE
FREQUENCY CHARGE LOOP OUTPUT
PFD PUMP FILTER FREQUENCY
VCO
FREQUENCY
DIVIDER
Channel Control
Block Diagram of Frequency Synthesizer

Basic PLL
f
+
IN
PD VCO
w
1/s
f
OUT Open loop Kd Kv = K
- s s
Closed loop 1
1+ s / K
That is fine for small signal linear control loop
But large signal(bias) output of PD may not be directly compatible
with VCO input.
Need gain/attenuation/shift/filtering: Loop filter
Normally vp is discrete(like PWM)
Required vo is steady (DC)
vp can be converted to vo by simple LPF
f
IN + vp vo w f
vp
PD Kh VCO 1/s OUT vo
-
Kh
Discrete nature of PD (and vp) can be treated by continuous linear

loop if bandwidth of the loop is within 1/10-th of the frequency of vp
A walk around the loop
x(t)
+ y(t)
VCO 1/s
-
PD Loop filt
x(t)
y(t)
PD
output
LPF
output

Frequency step at input
w
0 w0 + Dw
x(t)
y(t)
PD
output
LPF
output
System has memory

At lock, input and output frequencies are equal

Phase Detector
XOR Phase detector
-
PD
Simple XOR PD works for a small range of Df, for a large

range it becomes nonlinear/non-monotonic
PD o/p
Kd = VDD/p
-2p -p 0 p 2p
Phase error
Steady state phase error for most useful range : ?

Phase Detector
Sequential Phase detector (SR flip-flop)
y(t) reset o/p
x(t) set
VDD
x(t)
Df
y(t)
-4p -2p 0 2p 4p
o/p
Kd = VDD/2p
Most useful range offered when Df = p : cannot use for 0 steady state phase error

Phase Frequency Detector (PFD)
up x(t) rising edge
x(t) x(t) rising edge x(t) rising edge
+
PFD
- Create All reset Create up
y(t) down pulse pulse
dn
y(t) rising edge y(t) rising edge y(t) rising edge
Three-state state machine representation
x(t) x(t)
y(t) y(t)
up up
dn dn
Output UP and DN pulses
Sequential three-state PFD provides large and linear detection range
Also it indicates sign and magnitude of frequency error since once it is set by one edge
of one clock, can only be reset by edge of the other clock
Phase error detection is sampled in nature : introduces delay in the loop
Average Voltage
RCLK UP
DFF VDD
‘1’
- 4p - 2p Phase
error
0 2p 4p
‘1’
DFF
DN
FCLK
Used PFD PFD Characteristics
PFD PFD
o/p o/p Dead zone: phase error below
Dead zone Non- the zero gain region cannot
linearity be corrected
Phase error Phase error Non-monotonic / non-linear
behavior near 0 is also a
problem
PFD dead zone and non-linearity near zero
DN
UP Dead zone problem is

eliminated by using a certain
Vfb
minimum UP and DN pulse
k under lock condition
Vref
Simulated waveform of PFD under lock condition

Charge Pump (CP)
Vdd
Charge Pump current ICP
= 24 uA
i
cp
MU
n2
UPB UPB
M1 M3
UP
d1 d3
out
d2 d4 n1
DN DNB out
M2 M4
i
bias DN
n3
MD
i
cp
gnd

Phase-Frequency Detector + Charge pump
x(t)
y(t)
x(t) + up LPF
PFD output
up
-
y(t) dn
dn
LPF
output

Phase-Frequency Detector + Charge pump
Status of UP/DOWN pulses is converted
I1 to a DC current to get PFD + CP gain
characteristic.
x(t) + VOUT
PFD average charging current = (t1/T)*I1
-
y(t) average discharging current = (t2/T)*I2
t1: on time of UP pulse
I2
t2: on time of DN pulse
T: time period
PFD & Cpump combined gain characteristic is obtained by plotting average
charging current for different phase differences between x(t) and y(t).
Average current
I
For I1 = I2 = I
-4p -2p 0 2p 4p Phase error

Integer N Frequency Divider
Divide by 2/3 cell based topology is chosen
for the divider implementation
Eight such cells are cascaded to achieve the
required division factor range of 480 – 495
DFFs of first two 2/3 cell of divider are
designed in CML logic. DFFs of remaining six
cell of divider are designed in digital logic
Current for the fastest DFF circuit is kept to
200 µA. It is halved for consecutive CML stage.
Total divider current of 1.6mA from 1.8V supply
For such n stage divider, output signal time
period (Tout) is expressed as function of input
signal time period (Tin) by the following
expression. Where pr is the division control
signal of the rth 2/3 cell.
Circuit diagram of CML DFF AND/NAND gate
T = (2n + 2n−1 p + 2n−2 p + ........ + 21 p + p )T

out n n−1 21 in
Integer N Frequency Divider
Simulated waveforms of divider for divide by 490

Layout of the chip
Die area: 1812.4um x 1965.04um

Power Amplifiers

PHASE NOISEAN ISSUE OF
CONCERN
WHAT IS PHASE NOISE ?
It is the most critical parameter in the design of a high performance

VCO or for that matter in any application requiring spectral purity
•When one talks about spectral purity he essentially means an impulse at

the frequency of interest. But phase noise causes spilling around this
central frequency of interest in the form of side bands.
•So instead of having all the energy concentrated at one single point in
the frequency domain, the energy gets distributed at and around the
central frequency leading to wastage of power

Phase noise manifests itself in the form of timing jitter (although there are other factors
that contribute to jitter as we shall see shortly) in the time domain.
Phase noise as the term suggests is addition of unwanted phase (phase angle) to any desired
frequency. Mathematically, it is defined as a zero-mean stochastic process φ(t) in the general
expression for the output voltage of an oscillator which is given by

Where the second term in the first bracket represents amplitude error while the
time dependent phase term in the second bracket, φ(t) represents the phase error. In
general the amplitude control mechanism takes care of the amplitude error and it is
the phase error that is of real concern to us. (even if not taken care of completely the
amplitude error is not of great concern to us. We are interested in the spectral purity
of the signal.

What contributes to Phase noise ?
Any oscillator circuit consists of both passive as well as active components. They both
contribute to noise. In general the noise is composed of the thermal noise, the flicker noise &
the shot noise.
Shot noise is a type of electronic noise that occurs when the finite number of particles
that carry energy, such as electrons in an electronic circuit or photons in an optical device, is
small enough to give rise to detectable statistical fluctuations in a measurement.

How To Deal With Phase Noise ?
Thus far we have dealt with phase noise in general but we will have to quantify it if we have
to make it a basis of our design implementation and so the obvious question is how to interpret it or
what kind of mathematical model do we have for it?
As such there are three mathematical models
(1) Linear Time Invariant model
(2) Linear Time Variant model
(3) Non-Linear Time Variant model
Here we will briefly present the important points of the first two models. The 3 rd model although
perfectly fine is way too complicated for us to make any use of it in practical implementation.
The first model the linear time invariant one is due to Leeson and so is often referred to as
Lesson's model. He derived an expression for the phase noise spectral density of a feedback
oscillator. The general expression is

Where F is the circuit noise factor, k is the Boltzmann’s constant, T is the temperature,
P0 is the oscillator output power, QL is the loaded quality factor of the resonator, ω0
is the oscillator fundamental frequency, ωC is the flicker noise corner frequency and ωis the offset
frequency.
In fact Leeson’s model is a correction of an already existing model that ignored the noise contribution
from the active devices. Actually if we take into account a lossless energy restoration device coupled
with an LC tank
We would get the following equation

A comparison of the oscillator phase noise vs the offset frequency w.r.t. the central
frequency for the old model and the corrected model shows the effectiveness of Leeson’s model
But the fact that neither the corrected model nor the old one can make quantitative predictions about
phase noise indicates that at least some of the assumptions used in the derivations are invalid, despite
their apparent reasonableness. To develop a theory that does not possess the enumerated deficiencies
we need to revisit, and perhaps revise these assumptions. And this was done by Lee and Hajimiri
leading to the making of time variant model.
Lee and Hajimiri suggested that although the linear assumption is more or less valid, the time
invariance would effectively mean that the irrespective of the point of time in the time
domain at which the noise or the error shows up it’s effect on the system would remain the
same. This assumption was challenged by them and they introduced something known as the impulse
sensitivity factor Γ(x).
It gives us an idea of the disturbance an impulse of error would produce depending on the time at
which it shows itself. Based on it the system could be so designed so as to ensure that the error which
if unavoidable should be minimum.
The ISF is a periodic function and has it’s maximum value at the zero crossings of a signal and
minimum value (0) at the points where the signal (required) has it’s maximum value.
The figure on the shows the output of a LC oscillator and a ring oscillator in that order. While that on
the bottom shows their impulse response in the same order.
A The impulsive phase disturbance can be written as
$ We can compute the excess phase using the superposition integral (In simple
words simply sum up the contribution due to impulsive disturbances throughout
the cycle)
A The ISF being a periodic function can be expressed as a Fourier series.
$ There isn’t exactly a healthy correlation between the various noise sources in the
above expression and so the extra phase term in the cosine expression is ignored
based on the assumption that the different noise sources are uncorrelated making
their relative phase irrelevant.

$ Now we substitute the last expression into the earlier expression for the
extra phase.
$ Considering a noise source with frequency very close to an integer
multiple of the central frequency say
$ Substituting this in place of the noise source in the equation used to calculate the
extra phase gives us a general result for a noise source with frequency close to an
integer multiple of the central frequency. In computing this expression we have
ignored contribution from product of trigonometric expressions with different
frequencies based on the assumption that their contribution would be minimal
since whenever the product of a sine and a cosine or a sine and a sine or vice
versa is computed over one full cycle for integer multiples of frequency the end
result is a zero and since here we have frequency of one term close to an integer
multiple of the other this assumption is valid
A The spectrum of has two equal side bands at even though the injection
of noise occurred at some near integer multiple of the central frequency.
$ The previous expressions simply give us an idea of excess phase but we need to
see how it affects the output voltage. To do so we consider the general
expression for the output voltage. Note that the amplitude noise or disturbance
being mentioned here in this expression is already taken are of by the nonlinear
amplitude control that exists in the oscillator.
$ Performing Phase to voltage conversion and assuming small amplitude

disturbances, results in two equal power-sidebands symmetrically disposed about
the central frequency
A Extending the above result to the general case of white noise gives us
$ It is clear from the above expression that minimizing the coefficients of ISF would
ultimately minimize the phase noise. Another very apparent observation that can
be made is that the power due to white noise sources varies as 1/ f 2 thus
explaining the middle segment of Leeson’s curve
Phase Noise Prediction
$ The ISF approach is the more accurate approach amongst the existing
methodologies. But the real problem with the ISF approach is the determination
of the ISF function. Of the existing ways to determine the ISF the one that
determines it most accurately is by carrying out transient analysis of the oscillator
by feeding it with impulses varying in their timing from the start to the end of one
cycle. The oscillator is simulated for a few cycles after the injection of the impulse.
In order to use this method one has to have the oscillator design before hand.
The simulation can be carried out in CADENCE software.
$ Once the ISF is known it needs to be expanded in a Fourier series to determine

the Fourier coefficients. One may also use Fourier analysis directly ( in order to
determine the various coefficients ) if we have the complete ISF curve (MATLAB
can be used for this purpose).
$ Apart from it we would be needing the device noise 1/f corner frequency and a
specification of the offset from the central frequency at which we wish to calculate
the phase noise
TRADE OFFS
•supply voltage
•output power,
•power efficiency
•distortion
REQUIREMENTS
•Ability to work at low supply voltages
•High operating frequencies.

CMOS PA: Related Design Issues
„ Low breakdown voltage of deep sub-micron technologies

„ Substrate interaction in a highly integrated CMOS IC
„ Low value of optimum load resistance requires higher impedance
transformation ratio
„ Low Q values of inductors
„ PA delivers large output current – parasitics in circuit may cause
performance degradation
Conventional transistor models for CMOS devices are moderately
inaccurate for RFICs.

Power Amplifier Characteristics
Function: Deliver power to antenna
Power Dissipation easily dominates the transceiver power budget
Key Specification:
Maximum Output Power
Efficiency/Power Added Efficiency
Power Gain
Linearity
Stability
Radiation Pattern
Thermal Emission

PERFORMANCE METRICS
Output Power
Efficiency
Linearity

Output Power
Power delivered to the load within the band of interest.
Load is usually an antenna with Z0 of 50Ω
Doesn’t include power contributed by the harmonics or any unwanted
spurs
Sinusoidal
Modulated Signal

Efficiency
Power Added Efficiency Most common efficiency metric
DC RF
Shows how efficiently supply DC power is converted to RF power

Drain efficiency is often used to indicate the efficiency of a single
power amplifier stage

Linearity
Linearity Requirement can be different based on modulation
Variable Envelope
Information is carried in the amplitude
∏/4 DQPSK and OQPSK
Constant Envelope
Information is carried in the phase
GMSK and GFSK

CLASSIFICATION OF RF
POWER AMPLIFIER
„Linear
„Switch mode

Linear PA: Class A,B,AB and C
transistor acts as a current source
Since certain amount of voltage must
exist to keep the device in the current
source mode, there is always certain
power dissipation on the device
Switch mode PA: Class D,E,F
Active device acts as a switch
There is either zero voltage across or
zero current through a switch
Î 100% efficiency possible

Resistor Loaded Class A Amplifier
In a Class A amplifier, the active device conducts current 100% of time
For maximum output swing (and thus output power), the quiescent output voltage is
set at VDD/2, and bias current at VDD/2RL

Other Power Efficiency Parameters
Normalized Power Output Capability PN
Ratio between power delivered to load and peak current times
peak voltage on the output device
Measure related to output device power handling
Power Added Efficiency (PAE)

Added signal power by the amplifier divided by DC biasing power
At low frequencies, PAE=η for the previous amplifier

Class A RF Power Amplifier
Inductor improves peak

amplitude, thus power efficiency
L1: Large inductor: acts as

current source
C1: DC block (prevents DC

power in RL)
L2, C2: Output tank circuit

Drain Voltage and Current Waveforms
Since L1 presents a DC short

to VDD, the drain voltage
waveform must be symmetric
around VDD. the maximum
amplitude of sinusoid at the
drain is VDD.
The drain voltage (and the

output voltage) swings to twice
the power supply! (in practice
limited by device breakdown)

Normalized Power Output Capability
Class A amplifiers are linear, but have poor efficiency!

Class B Power Amplifier
Same circuit, but Vbias is set so that M1 conducts only 50% of time

Class B Power Amplifier
Vbias is set so that M1

conducts only 50% of time
The harmonics in the output

waveform are filtered by output
tank circuit
The fundamental component
is a linear function of the input

Class B Power Efficiency, Continued
The DC component of max. iD half-sine wave is
The DC power is then
And the efficiency
Normalized Output Power Capability:
Same as Class A
Since DC power is proportional to the amplitude, η is proportional to square root of

output power: slower degradation at lower power than class A

Conduction Angle vs. Class
Conduction Angle φ :2φ is the

portion of period during
which the output transistor M1
conducts
2φ=2π: Class A
π<2φ<2π: Class AB
2φ=π: Class B
0<2φ<π: Class C
(Class AB or C output cannot be a

linear function of input)

Push-Pull Amplifier
Depending on Vbias and
Vin push- pull amplifier
can be operated as Class A,
B, AB, C, or D amplifier.
Theoretically a Class B
push- pull amplifier has
low distortion comparable
to class A because either
half will be conducting at
any time.
Real Class B is not possible
because devices do not have
abrupt turn- on
characteristic–most are
Class AB

Voltage and Current Waveforms of
Class B Push-Pull
„ Waveforms shown for maximum

amplitude output
„ typically, ‘crossover distortion’

arises at the switching point of
the two halves due to imprecise
turn-on voltages
„ Crossover distortion is reduced

by class AB operation

Class C Amplifier
Same amplifier, but biased to

conduct less than 50% of time
The output amplitude is not a

linear function of input: more
suitable for constant-amplitude
power amp (such as in PM or
FM)

Class C Amplifier Waveforms
Conduction angle
Solving for the DC bias to

achieve conduction angle
φ

Class C Power Efficiency Calculation
The average value of iD
The fundamental component of iD
Maximum output swing is reached when

Class C Power Efficiency, Continued
Maximum efficiency is then
The normalized output capability is poor at small

conduction angles
Thus, the efficiency must be sacrificed for reasonable P N

Class D Amplifier Power Efficiency
With ideal switches, Class D amplifier efficiency would be 100%
In practice, finite switch ON resistance and nonzero on-off transients limit

efficiency (use high ft device!)
In biploar Class D amplifier, the efficiency is further comprised due to charge

storage in saturation and VCE,SAT.
Normalized power capability is shown to be

Class E Power Amplifier
Finite switching speed causes v-i product at the switching instant non-zero ->
power loss
Class E amplifiers tries to make both v and I zero at the off-to-on transients (solves
only half of the problem)

Typical Voltage and Current Waveforms
Source: Shawn Kuo,’Linearization of a PulseWidth Modulated Power Amplifier,” S.B. Thesis, MIT,
June 2004

Class F Power Amplifier
Allows square wave on drain

Single-ended version of class D

Class F Power Amplifier Waveforms
The waveforms are similar to half of class D Push-Pull

Class F Power Amplifier Analysis
Refer Thomas. H. Lee’s book
Amplitude of fundamental frequency of drain voltage
Power delivered to the load

Linearization Techniques
How to linearize highly efficient PAs?

Linearization Techniques
Non-linear power amplifier can reach great efficiencies

But they lack linearity
Linearization techniques can be applied to non-linear PAs to get a good
linearity and a modest efficiency
Control is applied at
Input
Back-off
Pre-distortion
Cartesian feedback
Polar feedback
Output
Feed-forward
LINC (Linearization using Nonlinear Components)
Supply
EER (Envelope Elimination and Restoration)
Input: Back-off
Simplest and most common linearization

PAE is greatly reduced

Input: Pre-distortion
Tracking gain and change variations of amplifier is very challenging

using analog techniques
Digital Look-up tables often used
PA gain and phase response varies with bias,
temperature and supply changes

Input: Cartesian Feedback
„ Feedback is used to increase linearity

„ Large loop gain is needed to improve linearity; very difficult to
achieve at RF frequencies
„ Down-converting alleviates this problem
„ Stability is a big challenge

Supply: EER
(Envelope Elimination and Restoration)
Amplitude and phase are amplified separately
Amplitude information is fed at the output by supply
Substantial power could be dissipated in the supply modulation circuitry
providing the whole current of PA
Dc-to-dc can be used but still delivered current is quite large
Delay mismatch between two paths introduces distortion

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RF Circuits –

Design & Analysis

E & ECE Dept.

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Dr. T. K. Bhattacharyya,Dept. of E&ECE

•Why Lumped parameters models failed ……………….

• Failure of two port circuit parameter (Z, Y,ABCD) ……..

• Scattering parameter( S-parameter) on the basis of

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Dr. T. K. Bhattacharyya,Dept. of E&ECE

up at any node(KCL) loop is zero( KVL)

•If ε & μ =0, (c α ) i.e infinitely fast wave

1. On Discrete PCB component

( Analog [Low frequency<100MHz] ) ( RF/MW[ High frequency>100MHz] )

Conductor Simple Microstrip

Resistor Carbon Thin Film

Inductor Wire Thin Film

Dr. T. K. Bhattacharyya,Dept. of E&ECE

( Analog [Low frequency<100MHz] ) ( RF/MW [High frequency>100MHz] )

A. Small signal AC equivalent A. Small signal AC equivalent circuit

D. Noise (on few cases) D. Stability

 Circuit losses causes degradation of Q, reduction of frequency selectivity and noise

 Electromagnetic radiation capacitive coupling and substrate coupling significantly alter

 Reflection issues, because circuit size is of the order of a wavelength.

 Nonlinearity which causes distortion and unwanted frequency components is

Bipolar BiCMOS MOS

Junction PMOS NMOS

poly Gate oxide

Dr. T. K. Bhattacharyya,Dept. of E&ECE

„ Device scaling …faster ƒ Low power (no gate ƒ No body effect.

roughly every 3 years. (Low VCE sat).

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Maximum Cutut--offoff frequencyfrequency

- pure reactive components generate no thermal noise

Thermal Noise in MOSFET

Dr. T. K. Bhattacharyya,Dept. of E&ECE

• δ ~ 4/3 in long device

Flicker noise in MOSFET

Dr. T. K. Bhattacharyya,Dept. of E&ECE

For two stage case it can be shown

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Both model order and model parameters

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Outer Diameter (μm) 120

Metal Width; Metal Spacing (μm) 5.5; 3

Metal Layer; Under Pass M6; M5

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Z1 (1st Zero) 1.0146618E+9

Z2 (2nd Zero) 1.2566E+13

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Block Diagram of the Receiver System

 Sensitivity of the Receiver

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Dr. T. K. Bhattacharyya,Dept. of E&ECE

Circuit losses causes degradation of Q, reduction of frequency selectivity and noise

Electromagnetic radiation capacitive coupling and substrate coupling significantly alter

Reflection issues, because circuit size is of the order of a wavelength.

Nonlinearity which causes distortion and unwanted frequency components is

Both model order and model parameters

Sensitivity of the Receiver

Used to up-convert or down-convert a baseband signal to/from the

The most basic Downconversion mixer is the Gilbert cell mixer

RF signal: Radio Frequency signal

Approximating the LO signal as a square wave

The basic structure is as follows:

The LO-controlled switching stage is as shown:

The quadrature LO signals are applied in an AND-OR mode as shown in the