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Verilog123 3
Verilog123 3
Verilog123 3
1
List and describe verilog ports:
• input: the port is only an input port. In any assignment statement, the port should
appear only on RHS of it
• output: the port is an output port. The port can appear on either side of any
assignment statement
• inout: the port can be used as both an input and output. The inout port represents a
bidirectional bus
2
List and describe briefly the different styles of descriptions used in verilog
Behavioral description: it is one where the verilog module uses always and initial
construct
Data flow description: the description generally involve boolean expression for
outputs in terms of inputs
Structural description: verilog modules is designed using gates
Switch-level description: it is the lowest level of descriptions. The system is
described using switches and transistors. The verilog keywords nmos, cmos, pmos,
tranif0, tran describe the system.
Mixed-style description: it uses more than one style of previously mentioned
descriptions within a module.
3
compare VHDL and Verilog
4
Describe briefly the steps involved in simulation and synthesis.
• Choose the preferred language to describe the system. The language may verilog,
VHDL or mix language
• Choose the style or type of description
• Write the code depending on the style of description chosen
• Compile the code using the computer supplied by the HDL package. If any errors
found correct them and recompile until the code is error free
• Test or simulate the design with known inputs.
• After the simulation verified, the signal behavior is as expected, the compiled code
can be synthesized. The simulator package usually has a synthesizer. The
synthesizer converts the compiled code into a schematic and a net_list
• The net_list can be down loaded onto a chip, uasually FPGA
5
Data types
Net type:
Variable type:
• It represents an abstract data storage element. It is assigned value only within
an always statement or an initial statement
• Its value is saved from one assignment to the next.
• A variable type has a default value of x
6
Net types
wire
tri
wor
trior
wand
triand
trireg
tri0
tri1
supply0
supply1
7
Syntax for net declaration:
Net_kind [signed][msb:lsb]net1,net2,……….,netn;
where net_kind is one of nets listed above
• Keyword signed is used to declare a net that holds a signed value
• By default , a net holds an unsigned value
• msb and lsb are constant expressions that specify the range of the net
• The range specification is optional, if no range is specified , a net defaults to a size of one bit
Ex:
wire a1, a2; // two 1 bit wire nets
wand[2:0]hadder; // hadder is 3 bit vector wand net
define size 16
wire signed[size-1:0]data; // data holds signed value in two’s compliment form
8
• tri:
• The keyword wire and tri have identical syntax and function. However,
separate names are provided to indicate the purpose of net
• The keyword ‘wire’ denotes nets with single drivers and ‘tri’ denotes net that
have multiple drivers
Multiplexer defined below uses tri declaration:
module mux (out, a, b, control);
input a, b, control;
output out;
tri out;
wire a, b, control;
bufif0 b1( out, a, control);// drives a when control=0;z otherwise
bufif1 b2( out, b, control); // drives b when control=1;z otherwise
endmodule
• The net is driven by b1 and b2 in a complimentary manner. When b1 drives a,
b2 is tristated, when b2 drives b, b1 is tristated. Thus there is no logic
contention
• if there are two signals of opposite values and same strength, the resulting
value of the trinet is x
9
• trireg
• keyword trireg is used to model nets having capacitance that stores values
• The default strength for trireg net is medium
• nets of type trireg are in one of two states
Driven state:
At least one driver drives 0,1 or x values on the net. The value is
continuously stored in the trireg net. It takes the strength of the driver
Capacitive state:
All drivers on the net have high impedance (z) value. The net holds the last
driven value. The strength is small, medium or large ( default is small )
10
• tri0 and tri1
Keyword tri0 and tri1 are used to model resistive pull down and pull up
devices. A tri0 net has a value 0 if nothing is driving the net. Similarly, tri1 net has
a value 1 if nothing is driving the net. The default strength is pull
Ex:
tri0 out;
wire a, control;
bufif1 ( out , a, control); /* net out gets the value of a, when control=1, when
control=0, out gets value 0 instead of z. if out were
declared as tri1, the default value of out would be 1 instead of 0 */
11
• Supply0 and supply1:
supply1 vcc //all nets are connected to vcc are connected to power supply
12
• wor , wand, trior and triand:
When there is logic contention, if we use a trinet, we will get x. This could be
indicative of a design problem
however, sometimes the designer needs to resolve the final logic value when there
are multiple drivers on the net, without using strength levels
Keyword wor, wand, trior and triand are used to resolve such conflicts.
• Net wand performs the AND operation on multiple driver logic values. If any value
is 0, the value of wand is 0
• Net wor performs the OR operation on multiple driver values. If any value is 1, the
net wor is 1
• Nets triand and trior have the same syntax as function as the nets wor and wand
Ex:
wand out1;
wor out2;
Buf ( out1,1’b0);
Buf ( out1,1’b1); // out1 is a wand net, gets the final value 1’b0
Buf ( out2,1’b0);
Buf ( out2,1’b1); // out2 is a wor net, gets the final value 1’b1
13
• Undeclared nets:
It is possible not to declare a net. In such a case, the net defaults to a 1-bit wire
net
14
• Vectored and scalared nets:
• The keyword , scalared or vectored, can optionally be specified for a
vectored net
• if a net is declared with the keyword vectored, then bit selects and part-selects
of this vector net are not allowed, in other words, the entire net has to be assigned
Ex:
wire vectored[3:0]count;
// bit select count[2] and part-select count[3:2] are not allowed
15
• Variable types:
reg
integer
time
real
realtime
16
• reg variable:
It is declared as follows:
reg [ signed] [[ msb : lsb]] reg1, reg2,………..,regn;
Where msb and lsb specify the range and are constant-valued expressions.
The range specification is optional, if there is no range , it defaults to a 1-bit reg variable
Ex:
reg [3:0]exp; // exp is a 4-bit variable
reg test; // test is a 1-bit variable
A reg variable can be of any size. A value in a reg variable is interpreted as an unsigned
number, unless the keyword signed is used, in which the variable holds 2’s compliment
form
reg signed[1:4] a1;
a1=-2; // a1 has 14( 1110) , the two’s compliment of 2
a1=5; // a1 has 5( 0101)
Ex:
reg [0:3] mem1[0:63]; // mem1 is a array of sixty four 4-bit reg variables
reg file1[1:5]; // file1 is an array of five 1-bit reg variables
Mem1 and file1 are memories. A memory belongs to the variable data type . Arrays with
more than two dimensions and arrays of nets are allowed
A single reg declaration can be used to declare both variables and memories
Parameter ADDR_SIZE = 16, WORD_SIZE = 8;
reg [1:WORD_SIZE]mem2[ADDR_SIZE-1:0], add;
Mem2 is a memory, an array of sixteen 8-bit reg variables , while add is a 8-bit reg variable
18
A memory cannot be assigned value in one assignment, but a reg can
Ex:
reg [1:5]b1; // b1 is a 5-bit reg variable
b1 = 5’b11101; is accepted but
reg hold_gnt[1:5]; // hold_gnt is a memory of five 1-bit reg variables
Hold_gnt = 5’ b11101; is not accepted
Instead
Ex:
reg [0:3] a1[1:4];
a1[1] = 4’hA;
a1[2] = 4’hB;
a1[3] = 4’hC;
a1[4] = 4’hD;
19
To copy the content of one memory to another memory, use a for loop and copy
one word at a time.
Ex:
parameter word_length = 8, num_word = 64;
reg [word_length-1:0] mem_a[num_word-1:0],
mem_b[num_word-1:0];
integer i;
// mem_a = mem_b; is not allowed
for( i=0;i<num_word; i=i+1)
mem_a[i] = mem_b[i];
20
An alternative way to assign values to a memory is by using the system tasks:
I. $readmem : loads binary values
II. $readmemh : loads hexadecimal values
These system tasks read and load data from a specified text file into a memory
The text file must contain the appropriate form of numbers, either binary or
hexadecimal
Ex:
reg [1:4]cdn_rom[7:1];
$readmemb(“ram.patt”,cdn_rom);
Cdn_rom is a memory. The file ram.patt must contain binary values. The file may also
contain white spaces and comments.
Ex of what may be in the file
1010
1101
1111
0000
1000
1011
1110
21
If only a part of the memory is to be loaded, the range can be specified in the
$readmemb task such as
$readmemb(“ram.patt”,cdn_rom,5,4,3);
In which only cdn_rom[5], cdn_rom[4] and cdn_rom[3] words are read from the file
beginning at the top.
22
Integer variable:
• It contains integer values
• An integer variable is treated as a signed reg variable with the least significant bit index
of 0
Ex:
reg [31:0] a_reg;
integer a_int;
……
// a_int[6] and a_int[20:10] are allowed
…..
a_reg = a_int;
24
• Converting from a bit-vector to an integer can also be accomplished by using an
assignment
Ex:
integer j ;
reg [3:0] beq;
25
• Example of an array of integers , showing the declaration , assignments and its
usage
module mod_int_array;
Localparam array_size = 8;
integer int_array[0:array_size-1];
initial
begin
int_array [0] = 56;
int_array [1] = 12;
int_array [2] = int_array[0]/2;
$display(“int_array[2] is %d”, int_array[2]);
end
endmodule
26
Time variable:
Where msb and lsb are constant valued expressions that indicates the range of indices.
If no range is specified, each identifiers stores one time value which is at least 64
bits
27
Real and real time variable:
• A real variable(or a real time variable) can be declared using the following form
// real declaration
real a1,a2,…….,an;
// real time declaration
realtime b1,b2,……..,bn;
• A realtime variable is exactly identical to a real variable.
Ex:
real top_mark;
realtime current_time;
• The default value of a real variable is 0. no range, bit range or word range, is allowed for
declaring a real variable
tri [ 0:31] addr [0:1][0:3]; // two dimensional array of triwires, each element being
//32-bits wide
integer run_stats [0:15] [0:15] ; // array of 16-by-16 integer variables
• The vector size specifies the number of bits in each element of the vector, while the
range on the right of the variable specify the number of elements in each dimension
of the array
• Note one-dimensional reg variable array is called a memory
29
• An array cannot be assigned to another array using a single assignment statement.
Only an element of an array can be assigned. A bit-select or part-select of an
element of an array can also be accessed and assigned.
Ex:
smc_fifo[5] = 26; // 26 is assigned to 5th element of array
smc_fifo = req_stack; // not allowed: cannot assign a complete array
30
Difference between reg and wire:
reg wire
1. Is a variable type Is a wire type
Ex:integer, time Ex: wand, tri
31
Parameters:
• It is a constant
• It is often used to specify delays and width of variables
• It can be assigned a value only once, using a paramater declaration
• A parameter declaration is of the form:
parameter [ signed] [[ msb:lsb]] param1 = const_expt1;
Ex:
Parameter LINELENGTH = 32 // implied range of LINELENGTH is [ 31:0]
define WIDTH 16;
parameter [WIDTH-1:0] red = 0;
• A parameter value can also be changed at compile time. This is done using a defparam
statement or by specifying the parameter value in the module instantiation statement
• A parameter declaration can optionally specify a type ( integer, real, realtime or time), in
which case, no range specification or keyword “signed” is allowed
Ex:
parameter time trig_time = 10;
parameter integer count_limit = 25;
32
Difference between parameter and a define
parameter define
1. Is local to the module that Definition stays through
is declared in multiple files as they are
compiled
33
Local parameters:
• If a local parameter is defined in terms of other non-local parameter, then the local
parameter gets indirectly modified when the parameter value changes due to an
external assignment
parameter BYTE = 0;
localparam NIBBLE = BYTE/2;
If parameter BYTE gets modified during compile time, so does the local parameter
NIBBLE
34
Expression
I. Constant
II. Parameter
III. Net
IV. Variable
V. Bit-select
VI. Part-select
VII. Memory and array element
VIII.Function call
35
Constant:
• Are values that does not change during the execution of the program
Ex:
456, 6 // unsized decimal number
4’b10_11, 8’h0A // sized integer constant
‘b1, ‘hFBA // unsized integer constant
89.000005 // real constant
“ABCD” // string constant ; each character is stored as a 8-bit ASCII value
Net:
• Both scalar net ( 1-bit) and vector nets ( multi-bit) can be used in an expression
Ex:
wire [ 0:3] a_port; // a_port is a 4-bit vector net
wire intr // intr is a scalar net
wire signed [ 3:0] jch; // 4-bit signed net
assign gpio_port = -3;
gpio_port has the bit-vector 1101 assigned which is in effect the decimal value 13
assign gpio_port = 4’hA;
gpio_port has the bit-vector 1010 assigned to it which is the decimal value 10
37
Variable:
periph_id = -10 // periph_id has the bit vector 10110, which is the two’s
//compliment of 10
periph_id = ‘b1011 // periph_id has the decimal value 11
38
Bit-select:
• If the select expression evaluates to an x or z or if it is out of bounds, the value of the bit-select is an x
Ex:
mis_select[ x] is an x
39
Part-select:
• The base expression (start index) can be a variable. However the width of the part –
select must be a constant
• If either the range index is out of bounds or evaluates to an x or a z, the part-select
value is an x
40
• An indexed part-select is of the form
net_or-reg_vector [ base_expr+: const_width_expr ]
net_or-reg_vector [ base_expr-: const_width_expr ]
Ex:
integer mark;
reg [ 0:15] inst_code;
wire [ 31:0] gpio_port;
41
Memory and array element:
42
• Here is another memory declaration
reg [15:0] fill_pattern [ 0:63]; // memory of 64 words, each word of 16 bits
Examples of arrays:
reg [7:0] sense_data [15:0] [15:0];
integer three_d [255:0] [255:0] [255:0];
wire xbar [3:0] [3:0];
three_d[5][5][2] // ok
three_d[2][1:2][0] // not ok; part-select of only an element is allowed
xbar[0][2:0] // not ok
43
Function call:
• A function call can be used in an expression. It can either be a system function call
(starts with $ character) or an user defined function call
Signedness:
• An operand is either signed or unsigned.
• If all operand in an expression are signed, then the result is signed, else the result is
unsigned
Ex:
8’d2 + 8’sb0101 // result is unsigned since 8’d2 is an unsigned number
4’sb0110 – 4’sd1 // result is signed since all operands are signed
44
Operators:
I. Arithmetic operators
II. Relational operators
III. Equality operators
IV. Logical operators
V. Bitwise operators
VI. Reduction operators
VII. Shift operators
VIII.Conditional operators
IX. Concatenation and replication operators
45
The following table shows the precedence and names of all the operators
+ Unary plus
- Unary minus
! Unary logical negation
~ Unary bit-wise negation
& Reduction and
~& Reduction nand
^ Reduction xor
^~ or ~^ Reduction xnor
| Reduction or
~| Reduction nor
** Power(exponentiation)
* Multiply
/ Divide
% Modulus
+ Binary plus
- Binary minus
<<< Arithmetic left shift
>>> Arithmetic right shift
<< Logical left shift
>> Logical right shift
< Less than
<= Less than or equal to
> Greater than
>= Greater than or equal to
46
== Logical equality
!= Logical inequality
=== Case equality
!== Case inequality
& Bitwise and
^ Bit-wise xor
^~ or ~^ Bit-wise xnor
| Bit-wise or
&& Logical and
|| Logical or
?: Conditional operator
{} Concatenation
{{}} replication
47
Arithmetic operator:
48
Result size:
• The size of the result of an arithmetic expression is determined by the size of the
largest operand.
49
Unsigned and signed :
• When performing arithmetic operations and assignments, it is important to note
which operands are being treated as unsigned values and which are being treated as
signed value.
50
Ex:
reg [0:5] burst_data;
integer mtx_addr;
burst_data = -4’d12 // reg burst_data has the decimal value 52, which is the
//vector 110100
Ex:
burst_data = -2 +(-4);
mtx_addr = -2 +(-4);
burst_data gets the decimal value 58 (bit-vector 111010), while mtx_addr gets the
decimal value -6 (bit-vector 111010)
• The two system functions $signed and $unsigned can be used to convert values to
signed or unsigned forms respectively
Ex:
$signed (4’b1101) // is a signed number, value of -3
$unsigned (4’shA) // is an unsigned number, value at 10
51
• To perform only a signed operation, convert the unsigned operand to a signed
operand using the $signed system function. When signed and unsigned operators
are mixed in an single expression
Ex:
$signed (‘d2) + 4’sb1001 is -5
$unsigned (5’sb11010 +5’sh1C) – 5’b01001 is 13
52
Relational operators:
• The result of a relational operator is true (the value 1) or false (the value 0).
• Result is an x if any bit in either of the operand is an x or a z
Ex:
67 > 90 is false (value 0) while
52 < 16’hxFF is x
• If operands are not of same size and if any operand is unsigned, the smaller operand
is zero-filled on the most significant bit side (the left)
Ex:
‘b1000 >= ‘b01110
is equivalent to
‘b01000 >= ‘b01110 is false (value 0)
53
• If both operands are signed, then sign extension is performed on the smaller
operand
Ex:
4’sb1011 <= 8’sh1A
is equivalent to
8’sb11111011 <= 8’sb00011010 is true (value 1)
• If one of the operands in the expression is unsigned, the rest of the expression is
treated as unsigned as well
Ex:
( 4’sd9 * 4’d2) < 4 is false (18<4)
( 4’sd9 * 2) < 4 is true (-14 < 4)
54
Equality operators:
55
Ex:
‘b010x != ‘b11x0 is true. Even though x is present in both the operands, the
result is not ambiguous- due to the difference in the first bit
• If the operands are of unequal lengths and if either operand is unsigned, the smaller
operand is zero-filled on the most significant side, that is , on the left
Ex:
2’b10 == 4’b0010
is same as
4’b0010 == 4’b0010 which is true (value 1)
56
Logical operators:
The logical operators are:
• && ( logical and)
• || ( logical or)
• ! ( unary logical negation)
These operators operate on logical values 0 and 1. the result of a logical operation is 0,
1 or x
Ex:
‘b1 || ‘bx is 1
‘b0 && ‘bz is 0
!x is x
57
Bit-wise operator:
• ~ (unary negation)
• & (binary and)
• | (binary or)
• ^ (binary exclusive-or)
• ~^ (binary exclusive-nor)
• ~(&) (binary nand)
• ~(|) ( binary nor)
These operators operate bit-by-bit, on corresponding bits of the input operands and
produce a vector result.
58
Reduction type:
These operators operate on a single operand. The result is Boolean. The result is 0 or 1
depending on the individual bits if a single operand and reduces to single bit
Ex:
y = &x
If x = 1011
Then y = 1&0&1&1 = 0
59
Shift operators:
• The conditional operator selects an expression based on the value of the condition
expression and it is of the form:
cond_expr ? expr1 : expr2
Ex:
wire [0:2] student = marks > 18 ? Grade_a : grade_b ;
61
Concatenation and replication:
62
• Replication is performed by specifying a repetition number. It is of the form:
{ repetition_number { expr1, expr2,….., expr n}}
Ex:
abus = {3{4’b1010}}; is same as 101010101010
parameter LENGTH = 8;
{LENGTH{1’b1}} is a string of 8 1’s
63
Kinds of expressions:
64
The steps in evaluating an expression are:
• Determine its signedness. If any operand in the expression is unsigned, then the
expression is unsigned, if all the operands in the expression are signed, then the
expression is signed. The type of left hand side (target) does not determine its
signedness
• Size of each operand is extended to the size of the expression, sign extension for
signed operands and zero extension for unsigned operands
65
Gate – level modeling
66
• A gate can be used in a design using a gate instantiation. It is in the format
• Multiple instances of the same type can be specified in one construct. The syntax
is:
gate_type
[ instance_name] ( term11, term12,……, term1n),
[ instance_name] ( term21, term22,……, term2n),
……………….
[ instance_name] ( termM1, termM2,……, termMn);
67
Multiple – input gates:
• These logic gates have only one output and one or more inputs. The syntax is:
Ex:
and a1( out1, in1, in2);
68
Tristate gates:
• These gates model three state drivers. These gates have one output, one data input
and one control input. The syntax is:
• Depending on the control input, the output can be driven to high impedance state,
that is, to value z
• For a bufif0 gate, the output is z if control is 1, else data is transferred to output
• For a bufif1 gate, the output is z if control is 0, else data is transferred to output
• For a notif0 gate, the output is z if control is 1, else output is invert of data input
• For a notif1 gate, the output is z if control is 0, else output is invert of data input
Ex:
bufif1 a1( dbus, mem_data, strobe);
69
Bufif/notif
70
Pull gates:
Ex:
Pullup a1 ( data);
71
MOS switches:
• These gates model unidirectional switches, that is , data flows from input to output
and the dataflow can be turned off by appropriately setting the control input
• The pmos, nmos, rnmos and rpmos switches have one output, one input and one
control input. The basic syntax is:
gate_type [instance_name] (output A, input B, control C);
• If control is 0 for nmos and rnmos switches and 1 for pmos and rpmos switches, the
switch is turned off, that is, output has value z
• If control is 1 for nmos and rnmos swiches and 0 for pmos and rpmos switches,
data at the input passes to output
72
Bidirectional switches:
• These switches are bidirectional, that is, data flows both ways and there is no delay
when data propagates through the switches
• The last four switches can be turned off by setting a control signal appropriately.
The tran and rtran switches cannot be turned off
73
Gate delays:
• The signal propagation delay from any gate input to the gate output can be
specified using a gate delay
74
Array of instances:
• When repetitive instances are required, a range specification can optionally be specified in a
gate instantiation
• The leftbnound and rightbound values are any two constant expressions.
Ex:
wire [3:0] a,b,c;
……..
nand a0 [3:0] ( a,b,c);
75
Implicit nets:
• However the default_nettype compiler directive can be used to override the default
nettype.
• The implicit net inference can be disabled by using a value of none for the
default_nettype compiler directive. In such a case, any undeclared net is an error
76
Dataflow modeling:
• Continuous assignment
a continuous assignment assigns a value to a net (or variable). It has the
following form
assign LHS_target = RHS_expression;
77
Delays
• If no delay is specified in a continuous assignment, the assignment of the RHS
expression to the left hand side target occurs with zero delay
• A delay can be explicitly specified in a continuous assignment as shown in the
following example
assign #6 sum = a+b;
• The delay specified, #6, is the delay between the right hand side and the right hand
side.
• For each delay specification, up to three delay values can be specified
1) Rise delay
2) Fall delay
3) Turn-off delay
The syntax for specifying the three delays:
assign #(rise, fall, turn-off) LHS_target = RHS_expression;
78
Behavioral modeling:
• the primary mechanism for modeling the behavior of a design are the following two
statements
1. Initial statement
2. Always statement
Initial statement: it executes only once. It begins its execution at start of simulation
which is at time 0. the syntax for initial statement is
initial
[timing_control] procedural_statement
Where a procedural statement is one of:
Procedural_assignment (blocking or nonblocking)
Procedural_continuous_assignment
Conditional_assignment
Case_statement
Loop_statement
79
Wait_statement
Disable_statement
Event_trigger
Sequential_block
Parallel_block
Task_enable (user or system)
• The sequential block (begin…….end) is the most commonly used procedural
statement
Always statement:
• In contrast to the initial statement, an always statement executes repeatedly. Just
like the initial statement, an always statement also begins execution at time 0. the
syntax for an always statement is:
always
[timing_control] procedural_statement
80
Example:
81
82
83
Dataflow modeling
Continuous assignment:
84
Note:
Structure of verilog module
• It has a declaration of single unit declaration called module
• The verilog module has a declaration and a body
• In the declaration name, inputs, outputs of the module are listed
• The body shows the relationship between inputs and outputs
• The order of declarations of inputs and outputs is irrelevant
• More than one input or output could be written o the same line by using comma to separate
each input or output
85
List and describe verilog ports:
• input: the port is only an input port. In any assignment statement, the port should
appear only on RHS of it
• output: the port is an output port. The port can appear on either side of any
assignment statement
• inout: the port can be used as both an input and output. The inout port represents a
bidirectional bus
86
List and describe briefly the different styles of descriptions used in verilog
Behavioral description: it is one where the verilog module uses always and initial
construct
Data flow description: the description generally involve boolean expression for
outputs in terms of inputs
Structural description: verilog modules is designed using gates
Switch-level description: it is the lowest level of descriptions. The system is
described using switches and transistors. The verilog keywords nmos, cmos, pmos,
tranif0, tran describe the system.
Mixed-style description: it uses more than one style of previously mentioned
descriptions within a module.
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compare VHDL and Verilog
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Describe briefly the steps involved in simulation and synthesis.
• Choose the preferred language to describe the system. The language may verilog,
VHDL or mix language
• Choose the style or type of description
• Write the code depending on the style of description chosen
• Compile the code using the computer supplied by the HDL package. If any errors
found correct them and recompile until the code is error free
• Test or simulate the design with known inputs.
• After the simulation verified, the signal behavior is as expected, the compiled code
can be synthesized. The simulator package usually has a synthesizer. The
synthesizer converts the compiled code into a schematic and a net_list
• The net_list can be down loaded onto a chip, uasually FPGA
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Describe the logical operators in verlog
• The verilog logical operators are classified as bitwise, boolean logical and
reduction
bitwise operators: they operate on corresponding bits of two operands. The list of
bitwise operators and their meaning is shown below:
Sl. No. operation Symbol Operand type result
1. AND & Bit Bit
2. OR | Bit Bit
3. NOT ~ Bit Bit
4. NAND ~(&) Bit Bit
5. NOR ~(|) Bit Bit
6. Ex-OR ^ Bit Bit
7. EX-NOR ~^ Bit bit
Boolean logical operators: operates on two operand, the result is boolean 0(false) or
1(true). The list is shown below:
Sl.no. Operation Symbol No. of operands
1. AND && Two
2. OR || Two
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Reduction operator:
• The operators operate on a single operand. The result is boolean. The result is 0 or
1 depending on the operation on the individual bits of single operand and reduces
to a single bit. The list is shown below:
2. | Reduction OR One
3. ~ Negation One
5. ~| Reduction OR One
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Explain how signal is declared and assigned in verilog?
• In verilog, the input and output parameters of module are implicitly signals. The
explicit signal declaration is done using keyword as shown below.
• The assignment is
assign o1 = i1 & i2;
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Explain the structure of the HDL behavior mode; in verilog
• The behavioral description is a powerful tool to describe system for which the digital logic
structure (boolean expression)are not known or hard to generate
• In this description design is described interms of sequential statements rather than boolean
expressions
• Initial or always statement is used as sequential statement
• The signal assignments describe the output behavior for the input signals change
• The signal assignments are placed inside the process statement and are called sequential signal
assignments
// verilog behavioral description for halfadder
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