Intelbras I400 - Compal La-4611p KSW01 91 - Rev 0.2 PDF

You might also like

Download as pdf or txt
Download as pdf or txt
You are on page 1of 47

A B C D E

PJP1 PJP1

14W_DCIN 15W_DCIN
14W_45@ 15W_45@

1 1

Compal Confidential
2
KSW01/91 Schematics Document 2

Intel Merom Processor with SiSM672/FX + DDRII + SiS968 + SiS307ELV

2008-08-01
ZZZ9

3
PCB
REV: 0.2 3

ZZZ1 ZZZ3 ZZZ4 ZZZ5 ZZZ6

PCB LA-4611P LS-4243P LS-4244P LS-4249P


14WDAZ@ 14WDA@ 14WDA@ 14WDA@ 14WDA@

ZZZ2 ZZZ8 ZZZ10 ZZZ11 ZZZ12 ZZZ13

PCB LA-4611P LS-4243P LS-4244P LS-4245P LS-4246P


15WDAZ@ 15WDA@ 15WDA@ 15WDA@ 15WDA@ 15WDA@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/05/18 Deciphered Date 2009/05/18 Title
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 1 of 47
A B C D E
A B C D E

Compal Confidential
Thermal Sensor Clock Generator
Model Name : KSW01/91 Fan Control Intel Merom Processor
page 4 ADM1032 ICS9LPRS600C+
page 4
File Name : LA-4611P uPGA-478 Package ICS9P935
page 14,15
1
page 4,5,6 1

FSB
H_A#(3..35) 533MHz H_D#(0..63)
CRT
page 17
Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
SiS M672 /FX
Single Channel BANK 0, 1, 2, 3 page 12,13
PCI-Express
LCD Conn. SiS 307ELV TEBGA-847 1.8V DDRII 533/667
page 16 page 18

page 7,8,9,10,11

1GB/s MuTIOL IO Link USB conn x3 Bluetooth Web Camera Card Reader 3 in 1
TO I/O/B Conn page RTS5158E socket
page 34 33 page 37 page 26 page 27
2 2
PCI-Express USB
3.3V 48MHz
SiS968
3.3V 24.576MHz/48Mhz HD Audio
MII
3.3V ATA-100 IDE
PCI BUS TEBGA-570
S-ATA port 0 port 1
page 19,20,21,22,23
3.3V 33 MHz
New Card MINI Card x1 MDC 1.5 HDA Codec
IDSEL:AD22
Socket WLAN LAN (PIRQG#,PIRQH#, Conn
page 37
ALC268
page 35
page 30 page 29 RTL8201CL GNT#0, REQ#0)
page 28
S-ATA HDD CDROM
Conn.page 24 Conn.
page 24
Audio AMP
RJ45 page 36
3
page 28 LPC BUS 3

RTC CKT.
page 20 ENE KB926C
page 31

Power On/Off CKT.


page 34
Touch Pad Int.KBD
page 33 page 32

DC/DC Interface CKT.


I/O Conn. BIOS
page 39
page 33
Power /B.
Power Circuit DC/DC Function /B.
4 4
page 40,
41,43,44,45,46
LID SW page 34

CHARGER Security Classification Compal Secret Data Compal Electronics, Inc.


page 42
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 2 of 47
A B C D E
A B C D E

Voltage Rails
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Power Plane Description S1 S3 S5
External PCI Devices
1
VIN Adapter power supply (19V) N/A N/A N/A DEVICE IDSEL # REQ/GNT # PIRQ 1

B+ AC or battery power rail for power circuit. N/A N/A N/A


+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS ( Actual +0.9V ) 0.9V switched power rail for DDR terminator ON ON OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.2VS 1.2V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
EC SM Bus1 address EC SM Bus2 address
+1.8VS 1.8V switched power rail ON OFF OFF
+2.5VS 2.5V switched power rail ON OFF OFF Device Address Device Address
+3VALW 3.3V always on power rail ON ON ON* Smart Battery 0001 011X b ADI ADM1032 1001 100X b
+3VS 3.3V switched power rail ON OFF OFF EEPROM(24C16/02) 1010 000X b
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON M672 SM Bus address
2 2
Device Address

Clock Generator 1101 001Xb


SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
DDR DIMM0 1010 000Xb
Full ON HIGH HIGH HIGH HIGH ON ON ON ON DDR DIMM1 1010 001Xb

S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF

PROJECT ID Table
3 3

PROJECT_ID
SKU ID Table R311 R311 R311 R311 R311 R311
14W R424 (Pull low)
Vcc 3.3V +/- 5%
15W NA (Internal Pull High)
Ra 100K +/- 5%
8.2K_0402_5% 18K_0402_5% 33K_0402_5% 56K_0402_5% 100K_0402_5% 200K_0402_5%
14_B@ 14_C@ 14_MP@ 15_A@ 15_B@ 15_C@
Ra~ R312
Rb~ R311
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max Rb BOM Structure
0 0 0 V 0 V 0 V 14_A@
1 8.2K +/- 5% 0.217 V 0.250 V 0.288 V 14_B@
2 18K +/- 5% 0.439 V 0.503 V 0.575 V 14_C@
3 33K +/- 5% 0.721 V 0.819 V 0.926 V 14_MP@
4 56K +/- 5% 1.054 V 1.185 V 1.325 V 15_A@
5 100K +/- 5% 1.489 V 1.650 V 1.819 V 15_B@
6 200K +/- 5% 2.019 V 2.200 V 2.386 V 15_C@
4 4
7 NC 3.135V 3.300 V 3.465 V 15_MP@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 3 of 47
A B C D E
5 4 3 2 1

H_A#[3..35]
<7> H_A#[3..35] Trace length must short Place close to CPU within 500mil
H_REQ#[0..4]
<7> H_REQ#[0..4]
H_RS#[0..2] JP36A
<7> H_RS#[0..2] +1.05VS
H_A#3 J4 H1
A[3]# ADS# H_ADS# <7>

ADDR GROUP 0
H_A#4 L5 E2
H_A#5 A[4]# BNR# H_BNR# <7>
L4 A[5]# BPRI# G5 H_BPRI# <7>
H_A#6 K5 Intel :Pull-up 56ohm (Un-Mount) SiS : Pull-up 56ohm (Mount) H_PREQ# R85 1 2 @ 56_0402_5%
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# <7>
H_A#8 N2 F21 H_IERR# R115 1 2 56_0402_5%
H_A#9 A[8]# DRDY# H_DRDY# <7>
D J1 A[9]# DBSY# E1 H_DBSY# <7> D
H_A#10 N3 Intel :Pull-up 56ohm (Mount) SiS : Pull-up 54.9ohm (Mount) ITP_TMS R84 1 2 56_0402_5%
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# <7>
H_A#12 P2 ITP_TDI R83 1 2 150_0402_1%
A[12]#

CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR# H_INIT# H_PROCHOT# R113 1 56_0402_5%
H_A#15
P4 A[14]# INIT# B3 H_INIT# <20> Intel :Pull-up 56ohm (Mount) SiS : Pull-up 75ohm (Mount) 2
P1 A[15]#
H_A#16 R1 H4 ITP_TCK R69 1 2 27.4_0402_1%
A[16]# LOCK# H_LOCK# <7>
<7> H_ADSTB#0 M1 ADSTB[0]#
C1 H_RESET# Add for option ITP_TRST# R61 1 2 680_0402_5%
RESET# H_RESET# <7>
H_REQ#0 K3 F3 H_RS#0 R19 R20 Michael 2008/5/30
H_REQ#1 REQ[0]# RS[0]# H_RS#1
H2 REQ[1]# RS[1]# F4
H_REQ#2 K2 G3 H_RS#2
H_REQ#3 REQ[2]# RS[2]#
H_REQ#4
J3 REQ[3]# TRDY# G2 H_TRDY# <7> Checklist recommend 39 Ohm CRB pull 75 Ohm
L1 REQ[4]#
HIT# G6 H_HIT# <7>
H_A#17 Y2 E4 0_0402_5% 0_0402_5%
H_A#18 A[17]# HITM# H_HITM# <7> NS@ NS@
U5 A[18]#
H_A#19 R3 AD4 Add Michael 2008/5/30
A[19]# BPM[0]# 1/29 change to EMC1402 pn

ADDR GROUP 1
H_A#20 W6 AD3
H_A#21 U4
A[20]# BPM[1]#
AD1 EMC1402 U1
for second source

XDP/ITP SIGNALS
H_A#22 A[21]# BPM[2]# +3VS
Y5 A[22]# BPM[3]# AC4
H_A#23 U1 AC2 C1
H_A#24 A[23]# PRDY# H_PREQ# 0.1U_0402_16V4Z
H_A#25
R4 A[24]# PREQ# AC1
ITP_TCK
Connect SB SYS_RESET# or just left NC
T5 A[25]# TCK AC5 1 2
H_A#26 T3 AA6 ITP_TDI
H_A#27 A[26]# TDI LM95245CIMMX NOPB MSOP 8P
W2 A[27]# TDO AB3
H_A#28 W5 AB5 ITP_TMS NS@
H_A#29 A[28]# TMS ITP_TRST#
Y4 A[29]# TRST# AB6
C H_A#30 U2 C20 ITP_DBRESET# 1 U1 C
A[30]# DBR# ITP_DBRESET#
H_A#31 V4 C2 1 8
A[31]# VDD SCLK EC_SMB_CK2 <31>
H_A#32 W3 H_PROCHOT#
A[32]# H_PROCHOT# <20,46>
H_A#33 AA4 THERMAL 2200P_0402_50V7K THERMDA 2 7
H_A#34 A[33]# 2 D+ SDATA EC_SMB_DA2 <31>
AB2 A[34]#
H_A#35 AA3 D21 THERMDC 3 6 2 1 +3VS
A[35]# PROCHOT# THERMDA_R
R19 SMSC@ 100_0402_5% THERMDA D- ALERT/THERM2 R706 10K_0402_5%
<7> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 THERMDC_R
R20 SMSC@ 100_0402_5% THERMDC +3VS 1 2 4 5 FX@
H_A20M# THERMDC R18 10K_0402_5% THERM GND
<20> H_A20M# A6 A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP#
<20> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <20> EMC1402-1-ACZL-TR
H_IGNNE# C4 C114 1 2 0.1U_0402_16V4Z
<20> H_IGNNE# IGNNE#
Address:100_1100 SMSC@
H_STPCLK# D5
<20> H_STPCLK# STPCLK#
H_INTR C6 H CLK
<20> H_INTR LINT0
H_NMI B4 A22
<20> H_NMI LINT1 BCLK[0] H_CLK_DP0 <14>
H_SMI# A3 A21
<20> H_SMI# SMI# BCLK[1] H_CLK_DN0 <14>
M4 RSVD[01]
N5
T2
V3
RSVD[02]
RSVD[03]
FAN1 Conn
RSVD[04]
B2
RESERVED

RSVD[05]
C3 RSVD[06]
D2 RSVD[07]
D22 RSVD[08]
D3 RSVD[09] H_THERMDA, H_THERMDC routing together, +5VS
F6 RSVD[10] Trace width / Spacing = 10 / 10 mil C3 10U_0805_10V4Z +5VS
1 2
B B

1
Merom Ball-out Rev 1a
conn@ U2 D1
1 VEN GND 8 BAS16_SOT23-3
U1 2 7
+VCC_FAN1 VIN GND
3 6

2
VO GND
<31> EN_FAN1 1 R815 2 EN_FAN1_R 4 VSET GND 5 D2
1 2

1
330_0402_5% C769 G990P11U_SOP8
BAS16_SOT23-3
ADM1032ARMZ_MSOP8 0.047U_0402_16V7K

2
+1.05VS MX@ C4 10U_0805_10V4Z
CPU to SB interface 1 2

R120 1 2 56_0402_5% H_STPCLK# R19 R20 +3VS C5


Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount) 1000P_0402_50V7K
R141 1 2 56_0402_5% H_INIT# Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount) 1 2

1
R128 1 2 56_0402_5% H_IGNNE# Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount) R21
10K_0402_5%
R144 1 2 56_0402_5% H_SMI# Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount) 0_0402_5% 0_0402_5% 40mil
MX@ MX@ JP7

2
R148 1 2 56_0402_5% H_A20M# Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount) +VCC_FAN1 1 1
<31> FAN_SPEED1 2 2
R137 1 2 56_0402_5% H_NMI Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount) 3 3
Add for option 1
R140 1 2 56_0402_5% H_INTR Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount) Michael 2008/6/12 C6 4
1000P_0402_50V7K GND
5 GND
R127 1 2 56_0402_5% H_THERMTRIP# Intel : Pull-up 56ohm (Mount) SiS : Pull-up 56ohm (Mount)
A 2 A

R208 1 2 56_0402_5% H_FERR# Intel : Pull-up 56ohm (Mount) SiS : Pull-up 56ohm (Mount) ACES_85205-03001

+1.05VS
CONN@

R114 1 2 51_0402_1% H_BR0# Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
R136 1 @ 2 56_0402_5% H_RESET# Intel :Don't Pull-up SiS : Pull-up 56ohm (Un-Mount)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom (1/3)
R112 1 2 150_0402_1% ITP_DBRESET# Intel :Don't Pull-up SiS : Pull-up 150ohm (Mount) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 4 of 47
5 4 3 2 1
5 4 3 2 1

GTL_REF

1 1 H_D#[0..63]
H_D#[0..63] <7>
C368 C814
JP36C
1U_0603_10V4Z 220P_0402_50V7K A7 AB20
2 2 JP36B +CPU_CORE VCC[001] VCC[068] +CPU_CORE
A9 VCC[002] VCC[069] AB7
H_D#0 E22 Y22 H_D#32 A10 AC7
H_D#1 D[0]# D[32]# H_D#33 VCC[003] VCC[070]
D F24 D[1]# D[33]# AB24 A12 VCC[004] VCC[071] AC9 D
H_D#2 E26 V24 H_D#34 A13 AC12
H_D#3 D[2]# D[34]# H_D#35 VCC[005] VCC[072]
G22 D[3]# D[35]# V26 A15 VCC[006] VCC[073] AC13

DATA GRP 0
H_D#4 F23 V23 H_D#36 A17 AC15
H_D#5 D[4]# D[36]# H_D#37 VCC[007] VCC[074]
SiS Recommend H_D#6
G25 D[5]# D[37]# T22
H_D#38
A18 VCC[008] VCC[075] AC17
E25 D[6]# D[38]# U25 A20 VCC[009] VCC[076] AC18
H_D#7 E23 U23 H_D#39 B7 AD7
H_D#8 D[7]# D[39]# H_D#40 VCC[010] VCC[077]
K24 Y25 B9 AD9

DATA GRP 2
H_D#9 D[8]# D[40]# H_D#41 VCC[011] VCC[078]
G24 D[9]# D[41]# W22 B10 VCC[012] VCC[079] AD10
H_D#10 J24 Y23 H_D#42 B12 AD12
H_D#11 D[10]# D[42]# H_D#43 VCC[013] VCC[080]
J23 D[11]# D[43]# W24 B14 VCC[014] VCC[081] AD14
H_D#12 H22 W25 H_D#44 B15 AD15
H_D#13 D[12]# D[44]# H_D#45 VCC[015] VCC[082]
F26 D[13]# D[45]# AA23 B17 VCC[016] VCC[083] AD17
H_D#14 K22 AA24 H_D#46 B18 AD18
H_D#15 D[14]# D[46]# H_D#47 VCC[017] VCC[084]
H23 D[15]# D[47]# AB25 B20 VCC[018] VCC[085] AE9
<7> H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 <7> C9 VCC[019] VCC[086] AE10
<7> H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 <7> C10 VCC[020] VCC[087] AE12
<7> H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 <7> C12 VCC[021] VCC[088] AE13
C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17
H_D#16 N22 AE24 H_D#48 C17 AE18
H_D#17 D[16]# D[48]# H_D#49 VCC[024] VCC[091]
K25 D[17]# D[49]# AD24 C18 VCC[025] VCC[092] AE20
H_D#18 H_D#50
Close to CPU pin AD26 H_D#19
P26
R23
D[18]# D[50]# AA21
AB22 H_D#51
D9
D10
VCC[026] VCC[093] AF9
AF10
D[19]# D[51]# VCC[027] VCC[094]
within 500mils. H_D#20 L23 D[20]# D[52]# AB21 H_D#52 D12 VCC[028] VCC[095] AF12

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D14 AF14
H_D#22 D[21]# D[53]# H_D#54 VCC[029] VCC[096]
L22 D[22]# D[54]# AD20 D15 VCC[030] VCC[097] AF15
H_D#23 M23 AE22 H_D#55 D17 AF17 Place this cap more close to
H_D#24 D[23]# D[55]# H_D#56 VCC[031] VCC[098]
P25 D[24]# D[56]# AF23 D18 VCC[032] VCC[099] AF18
C H_D#25 P23 AC25 H_D#57 E7 AF20 B26/C26 rather than 10UF C
+1.05VS H_D#26 D[25]# D[57]# H_D#58 VCC[033] VCC[100]
P22 AE21 E9

DATA GRP 3
H_D#27 D[26]# D[58]# H_D#59 VCC[034]
T24 D[27]# D[59]# AD21 E10 VCC[035] VCCP[01] G21 +1.05VS
H_D#28 R24 AC22 H_D#60 E12 V6
H_D#29 D[28]# D[60]# H_D#61 VCC[036] VCCP[02]
L25 D[29]# D[61]# AD23 E13 VCC[037] VCCP[03] J6 1
2

H_D#30 T25 AF22 H_D#62 E15 K6


R321 H_D#31 D[30]# D[62]# H_D#63 VCC[038] VCCP[04] + C80
N25 D[31]# D[63]# AC23 E17 VCC[039] VCCP[05] M6
<7> H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 <7> E18 VCC[040] VCCP[06] J21
1K_0402_1% <7> H_DSTBP#1 M26 AF24 E20 K21 330U_D2E_2.5VM_R9
DSTBP[1]# DSTBP[3]# H_DSTBP#3 <7> VCC[041] VCCP[07] 2
<7> H_DINV#1 N24 AC20 H_DINV#3 <7> F7 M21
1

DINV[1]# DINV[3]# VCC[042] VCCP[08]


F9 VCC[043] VCCP[09] N21
Width=20 mil GTL_REF AD26 R26 COMP0 R324 1 2 27.4_0402_1% F10 N6
R111 2 GTLREF COMP[0] VCC[044] VCCP[10]
1 @ 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 R323 1 2 54.9_0402_1% F12 VCC[045] VCCP[11] R21
R98 2 1 @ 1K_0402_5% TEST2 D25 AA1 COMP2 R42 1 2 27.4_0402_1% F14 R6
TEST2 COMP[2] VCC[046] VCCP[12]
2

PAD TEST3 C24 Y1 COMP3 R44 1 2 54.9_0402_1% F15 T21


T3 TEST3 COMP[3] VCC[047] VCCP[13]
R319 C364 1 2 @ 0.1U_0402_16V4Z TEST4 AF26 F17 T6
TEST5 TEST4 VCC[048] VCCP[14]
T2 PAD AF1 TEST5 DPRSTP# E5 H_DPRSTP# <25,46> F18 VCC[049] VCCP[15] V21
2K_0402_1% TEST6 A26 B5 H_DPSLP# F20 W21
T23 PAD TEST6 DPSLP# H_DPSLP# <25> VCC[050] VCCP[16]
D24 H_DPWR#_R AA7 20mils
1

DPWR# H_PWRGOOD VCC[051]


<14> CPU_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD <7> AA9 VCC[052] VCCA[01] B26 +1.5VS
B23 D7 H_CPUSLP# AA10 C26
<14> CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# <20> VCC[053] VCCA[02]
<14> CPU_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# <46> AA12 VCC[054] 1 1
AA13 AD6 C438 C432
VCC[055] VID[0] CPU_VID0 <46>
Merom Ball-out Rev 1a Resistor placed within AA15 AF5
VCC[056] VID[1] CPU_VID1 <46>
conn@ AA17 AE5 0.01U_0402_16V7K 10U_0805_10V4Z
0.5" of CPU pin.Trace VCC[057] VID[2] CPU_VID2 <46> 2 2
AA18 VCC[058] VID[3] AF4 CPU_VID3 <46>
should be at least 25 AA20 VCC[059] VID[4] AE3 CPU_VID4 <46>
AB9 AF3 CPU_VID5 <46>
mils away from any other AC10
VCC[060] VID[5]
AE2
B VCC[061] VID[6] CPU_VID6 <46> B
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs toggling signal. AB10 VCC[062] 1 2 100_0402_1% +CPU_CORE
AB12 R27
COMP[0,2] trace width is AB14
VCC[063]
AF7 VCCSENSE
VCC[064] VCCSENSE VCCSENSE <46>
18 mils. COMP[1,3] trace AB15 VCC[065]
width is 4 mils. AB17 VCC[066]
AB18 AE7 VSSSENSE
VCC[067] VSSSENSE VSSSENSE <46>
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0
Merom Ball-out Rev 1a R24 1 2 100_0402_1%
conn@ .

133 0 0 1 H_DPWR#_R 1 @ 2 H_DPWR#


H_DPWR# <7>
R126 0_0402_5%

R131
166 0 1 1
10_0402_5%

200 0 1 0
Length match within 25 mils.
The trace width/space/other is
20/7/25.
+1.05VS

R121 1 2 56_0402_5% H_CPUSLP#


Close to CPU pin
Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount) SiS Recommend
A
R143 1
within 500mils. A
2 56_0402_5% H_DPSLP# Intel :Pull-up 56ohm (Un-Mount) SiS : Pull-up 56ohm (Mount)
R133 1 @ 2 56_0402_5% H_PWRGOOD Intel :Don't Pull-up (Connecte to ICH) SiS : Pull-up 56ohm (Un-Mount)
R119 1 @ 2 56_0402_5% H_DPWR# Intel :Don't Pull-up SiS : Pull-up 56ohm (Un-Mount)
Security Classification Compal Secret Data Compal Electronics, Inc.
C650 1 2 @ 0.1U_0402_16V4Z H_PWRGOOD Intel :Don't Pull-down SiS :Pull-down Cap (Un-Mount) 2008/05/15 2009/05/15 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom (2/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 5 of 47
5 4 3 2 1
5 4 3 2 1

+CPU_CORE +CPU_CORE
3 x 330uF(9mOhm/3) 3 x 330uF(9mOhm/3)
JP36D 1 1 1 1 1 1
A4 VSS[001] VSS[082] P6
A8 P21 C47 + C350 +
C390 + C347 + C155 + C169 +
VSS[002] VSS[083] @ @
A11 VSS[003] VSS[084] P24
A14 R2 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9
VSS[004] VSS[085] 2 2
330U_D2E_2.5VM_R9 2 2 2
330U_D2E_2.5VM_R9 2
A16 VSS[005] VSS[086] R5
A19 VSS[006] VSS[087] R22
D A23 VSS[007] VSS[088] R25 D
AF2 VSS[008] VSS[089] T1 South Side Secondary North Side Secondary
B6 VSS[009] VSS[090] T4
B8 VSS[010] VSS[091] T23
B11 T26 +CPU_CORE
VSS[011] VSS[092]
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6 CRB no stuff. Reserved!
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24 1 1 1 1 1 1 1 1
B24 V2 C394 C383 C408 C409 C410 C411 C412 C392
VSS[016] VSS[097]
C5 VSS[017] VSS[098] V5
C8 V22 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[018] VSS[099] 2 2 2 2 2 2 2 2
C11 VSS[019] VSS[100] V25
C14 W1 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[020] VSS[101]
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23 (Place these capacitors on South side,Secondary Layer)
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3
C25 Y6 +CPU_CORE
VSS[025] VSS[106]
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5 1 1 1 1 1 1 1 1
D13 AA8 C379 C378 C377 C376 C375 C385 C393 C384
VSS[030] VSS[111]
D16 VSS[031] VSS[112] AA11
D19 AA14 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[032] VSS[113] 2 2 2 2 2 2 2 2
D23 VSS[033] VSS[114] AA16
D26 AA19 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[034] VSS[115]
E3 VSS[035] VSS[116] AA22
C E6 AA25 (Place these capacitors on North side,Secondary Layer) C
VSS[036] VSS[117]
E8 VSS[037] VSS[118] AB1
E11 VSS[038] VSS[119] AB4
E14 AB8 +CPU_CORE
VSS[039] VSS[120]
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19 1 1 1 1 1 1 1 1
F5 AB23 C107 C106 C105 C104 C103 C89 C46 C90
VSS[044] VSS[125]
F8 VSS[045] VSS[126] AB26
F11 AC3 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[046] VSS[127] 2 2 2 2 2 2 2 2
F13 VSS[047] VSS[128] AC6
F16 AC8 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[048] VSS[129]
F19 VSS[049] VSS[130] AC11
F2 VSS[050] VSS[131] AC14 (Place these capacitors on South side,Primary Layer)
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 AC21 +CPU_CORE
VSS[053] VSS[134]
G1 VSS[054] VSS[135] AC24
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
H3 VSS[057] VSS[138] AD8 1 1 1 1 1 1 1 1
H6 AD11 C77 C76 C75 C74 C84 C78 C88 C85
VSS[058] VSS[139]
H21 VSS[059] VSS[140] AD13
H24 AD16 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[060] VSS[141] 2 2 2 2 2 2 2 2
J2 VSS[061] VSS[142] AD19
J5 AD22 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[062] VSS[143]
J22 VSS[063] VSS[144] AD25
B
J25 VSS[064] VSS[145] AE1 (Place these capacitors on North side,Primary Layer) B
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14 +CPU-CORE C,uF ESR, mohm ESL,nH
L3 AE16
L6
VSS[069] VSS[150]
AE19 Decoupling
VSS[070] VSS[151]
L21 VSS[071] VSS[152] AE23 SPCAP,Polymer 6X330uF 9m ohm/6 1.8nH/6
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2 32X22uF 3m ohm/32 0.6nH/32
M5 VSS[074] VSS[155] AF6 MLCC 0805 X5R
M22 VSS[075] VSS[156] AF8 32X10uF 3m ohm/32 0.6nH/32
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 A25 +1.05VS
VSS[081] VSS[162]
VSS[163] AF25

Merom Ball-out Rev 1a


conn@ . 1 1 1 1 1 1
C97 C87 C81 C96 C83 C73

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/05/15 Deciphered Date 2009/05/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom (3/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 6 of 47
5 4 3 2 1
5 4 3 2 1

+1.05VS

+1.2VS V_AVDD_PCIE_1.2V
U30C
H_D#[0..63] <5>
C1XAVDD B16 N29 H_D#0 L22 PCIEAVDD:77mA
C1XAVDD HD0#
1

1 C1XAVSS C17 M30 H_D#1 1 2


R210 C191 C1XAVSS HD1# H_D#2 MBK1608121YZF_0603
HD2# M28
C4XAVDD A17 L30 H_D#3 1 1
75_0402_1% 0.01U_0402_16V7K C4XAVSS C4XAVDD HD3# H_D#4 C201 C218
D B18 C4XAVSS HD4# L29 D
2 H_D#5
K28
2

NB_GTLREF HD5# H_D#6 0.1U_0402_16V4Z 0.01U_0402_16V7K


W24 HVREF HD6# K31
H_D#7 U30 2 2
U24 HVREF HD7# K30
1

1 1 R24 H31 H_D#8


R202 C212 C200 HVREF HD8# H_D#9
N24 HVREF HD9# G34
L21 H32 H_D#10
150_0402_1% 0.1U_0402_16V4Z HVREF HD10# H_D#11
HD11# G32
2 2 H_D#12
K32
2

PCREQ# HD12# H_D#13


T30 PAD R34 PCREQ# HD13# F34 S IC SISM672FXA1 TEBGA 847P
0.01U_0402_16V7K EDRDY# P32 F33 H_D#14
T5 PAD EDRDY# HD14#
F32 H_D#15 FX@
H_DPWR# HD15# H_D#16
<5> H_DPWR# E21 DPWR# HD16# H28
J30 H_D#17
HD17# H_D#18
HD18# H30
H_CLK_DP1 F18 G29 H_D#19
<14> H_CLK_DP1 CPUCLK HD19#
H_CLK_DN1 G18 J29 H_D#20
<14> H_CLK_DN1 CPUCLK# HD20#
G30 H_D#21
H_LOCK# HD21# H_D#22
<4> H_LOCK# L32 HLOCK# HD22# F30
H_DEFER# P30 D33 H_D#23
<4> H_DEFER# DEFER# HD23#
H_TRDY# P31 D34 H_D#24
<4> H_TRDY# HTRDY# HD24# V_AVDD_PCIE_1.2V
H_RESET# F21 B32 H_D#25
<4> H_RESET# CPURST# HD25#
H_PWRGOOD P28 B33 H_D#26 U30D
<5> H_PWRGOOD CPUPWRGD HD26#
H_BPRI# N30 C34 H_D#27 P7
<4> H_BPRI# BPRI# HD27# PCIEAVDD
H_BR0# P33 D31 H_D#28 R7 T5 PCIE_CLK_NB
<4> H_BR0# BREQ0# HD28# PCIEAVDD REFCLK+ PCIE_CLK_NB <14>
A32 H_D#29 T7 T4 PCIE_CLK_NB#
<4> H_RS#[0..2] HD29# PCIEAVDD REFCLK- PCIE_CLK_NB# <14>
H_RS#0 K34 A31 H_D#30 U7
H_RS#1 RS0# HD30# H_D#31 PCIEAVDD
M31 RS1# HD31# C31 V7 PCIEAVDD
H_RS#2 K33 B30 H_D#32
C
RS2# HD32# H_D#33 SB_PCIE_WAKE# C
HD33# C30 <21,29,30> SB_PCIE_WAKE# D7 PME#
<4> H_ADS# H_ADS# M34 A30 H_D#34 INT_N_A G16
ADS# HD34# <9,19> INT_N_A INTX#
<4> H_HITM# H_HITM# N34 D28 H_D#35
H_HIT# HITM# HD35# H_D#36
<4> H_HIT# N32 HIT# HD36# G28 E4 PERP0 PETP0 G6
<4> H_DRDY# H_DRD Y# M33 C29 H_D#37 E5 H6
H_DBSY# DRDY# HD37# H_D#38 PERN0 PETN0
<4> H_DBSY# L34 DBSY# HD38# C28 F1 PERP1 PETP1 G4
<4> H_BNR# H_BNR# M32 E28 H_D#39 G1 G5
BNR# HD39# H_D#40 PERN1 PETN1
<4> H_REQ#[0..4] HD40# E27 H3 PERP2 PETP2 J6
H_REQ#0 T34 C27 H_D#41 H2 K6
H_REQ#1 HREQ0# Host HD41# H_D#42 PERN2 PETN2
R30 HREQ1# HD42# G26 H1 PERP3 PETP3 J4
H_REQ#2 R29 E26 H_D#43 J1 J5
H_REQ#3 HREQ2# HD43# H_D#44 PERN3 PETN3
R32 HREQ3# HD44# D26 K1 PERP4 PETP4 L6
H_REQ#4 P34 B26 H_D#45 K2 PCIE M6
HREQ4# HD45# H_D#46 PERN4 PETN4
HD46# A26 L1 PERP5 PETP5 M4
C26 H_D#47 M1 M5
H_ADSTB#0 HD47# H_D#48 PERN5 PETN5
<4> H_ADSTB#0 U34 HASTB0# HD48# G22 N1 PERP6 PETP6 P6
<4> H_ADSTB#1 H_ADSTB#1 AA34 C24 H_D#49 N2 R6
HASTB1# HD49# H_D#50 PERN6 PETN6
<4> H_A#[3..35] HD50# A25 P1 PERP7 PETP7 P4
H_A#3 T32 B24 H_D#51 R1 P5
H_A#4 HA3# HD51# H_D#52 PERN7 PETN7
T28 HA4# HD52# C25 T1 PERP8 PETP8 V6
H_A#5 T31 A24 H_D#53 T2 W6
H_A#6 HA5# HD53# H_D#54 PERN8 PETN8 HDVBP2
T33 HA6# HD54# E23 U1 PERP9 PETP9(HDVBP2) W4
H_A#7 T30 E25 H_D#55 V1 W5 HDVBN2
H_A#8 HA7# HD55# H_D#56 PERN9 PETN9(HDVBN2) HDVBP1
U32 HA8# HD56# G24 W1 PERP10 PETP10(HDVBP1) Y6
H_A#9 U30 D22 H_D#57 W2 AA6 HDVBN1
H_A#10 HA9# HD57# H_D#58 PERN10 PETN10(HDVBN1) HDVBP0
V34 HA10# HD58# C22 Y1 PERP11 PETP11(HDVBP0) AA4
H_A#11 U29 E22 H_D#59 AA1 AA5 HDVBN0
H_A#12 HA11# HD59# H_D#60 PERN11 PETN11(HDVBN0)
V33 HA12# HD60# C23 AB1 PERP12 PETP12 AB6
H_A#13 V32 A23 H_D#61 AB2 AC6
B H_A#14 HA13# HD61# H_D#62 PERN12 PETN12 HDVAP2 B
V28 HA14# HD62# A22 AC1 PERP13 PETP13(HDVAP2) AC4
H_A#15 V31 B22 H_D#63 AD1 AC5 HDVAN2
H_A#16 HA15# HD63# PERN13 PETN13(HDVAN2) HDVAP1
W34 HA16# AE1 PERP14 PETP14(HDVAP1) AD6
H_A#17 Y33 AE2 AE6 HDVAN1
H_A#18 HA17# H_DINV#0 PERN14 PETN14(HDVAN1) HDVAP0
W32 HA18# DBI0# J32 H_DINV#0 <5> AF1 PERP15 PETP15(HDVAP0) AE4
H_A#19 V30 E32 H_DINV#1 AG1 AE5 HDVAN0
HA19# DBI1# H_DINV#1 <5> PERN15 PETN15(HDVAN0)
H_A#20 W30 F27 H_DINV#2
HA20# DBI2# H_DINV#2 <5>
H_A#21 Y34 F23 H_DINV#3 SISM672MX-A1_TEBGA_847P
HA21# DBI3# H_DINV#3 <5>
H_A#22 Y28
H_A#23 HA22# H_DSTBN#0
W29 HA23# HDSTBN0# H33 H_DSTBN#0 <5> MX@
H_A#24 Y32 E31 H_DSTBN#1
HA24# HDSTBN1# H_DSTBN#1 <5>
H_A#25 Y30 B28 H_DSTBN#2
HA25# HDSTBN2# H_DSTBN#2 <5>
H_A#26 Y31 D24 H_DSTBN#3 HDVBP2 C653 2 1 0.1U_0402_10V7K HDVBP2_C
HA26# HDSTBN3# H_DSTBN#3 <5> HDVBP2_C <18>
H_A#27 AA32 HDVBN2 C660 2 1 0.1U_0402_10V7K HDVBN2_C
HA27# HDVBN2_C <18>
H_A#28 AA30 H34 H_DSTBP#0 HDVBP1 C662 2 1 0.1U_0402_10V7K HDVBP1_C
HA28# HDSTBP0# H_DSTBP#0 <5> HDVBP1_C <18>
H_A#29 AA29 D32 H_DSTBP#1 HDVBN1 C654 2 1 0.1U_0402_10V7K HDVBN1_C
HA29# HDSTBP1# H_DSTBP#1 <5> HDVBN1_C <18>
H_A#30 AB33 A28 H_DSTBP#2 HDVBP0 C655 2 1 0.1U_0402_10V7K HDVBP0_C
HA30# HDSTBP2# H_DSTBP#2 <5> HDVBP0_C <18>
H_A#31 AB34 E24 H_DSTBP#3 HDVBN0 C656 2 1 0.1U_0402_10V7K HDVBN0_C
HA31# HDSTBP3# H_DSTBP#3 <5> HDVBN0_C <18>
H_A#32 AB32
H_A#33 HA32# H_PCOMP R175 10_0402_5%
AC34 HA33# HPCOMP A21
H_A#34 AB30 C21 H_NCOMP R188 110_0402_1% +1.05VS HDVAP2 C658 2 1 0.1U_0402_10V7K HDVAP2_C
HA34# HNCOMP HDVAP2_C <18>
H_A#35 AB31 HDVAN2 C657 2 1 0.1U_0402_10V7K HDVAN2_C
HA35# HDVAN2_C <18>
HDVAP1 C652 2 1 0.1U_0402_10V7K HDVAP1_C
HDVAP1_C <18>
SISM672MX-A1_TEBGA_847P HDVAN1 C651 2 1 0.1U_0402_10V7K HDVAN1_C
HDVAN1_C <18>
HDVAP0 C659 2 1 0.1U_0402_10V7K HDVAP0_C
HDVAP0_C <18>
MX@ HDVAN0 C661 2 1 0.1U_0402_10V7K HDVAN0_C
+1.8VS +1.8VS HDVAN0_C <18>
C1XAVDD:10mA C4XAVDD:12mA
L40 L31
A A
1 2 C1XAVDD 1 2 C4XAVDD
MBK1608121YZF_0603 MBK1608121YZF_0603
1 1 1 1 1 1
C454 C472 C481 C455 C470 C479

10U_0805_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 10U_0805_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K


2 2 2 2 2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 C1XAVSS 1 2 C4XAVSS 2008/05/15 2009/05/15 Title
R399 0_0402_5% R400 0_0402_5%
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M672MX (1/5)-HOST/PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 7 of 47
5 4 3 2 1
5 4 3 2 1

U30B
DDRA_SDQ[0..63] DDRA_SDQ0 AD31
<12,13> DDRA_SDQ[0..63] MD0A
DDRA_SDQ1 AD30
DDRA_SDM[0..7] DDRA_SDQ2 MD1A D1XAVDD +1.8VS
<12,13> DDRA_SDM[0..7] AG34 MD2A D1XAVDD A15
DDRA_SDQ3 AE29 B15 D1XAVSS D1XAVDD:7mA
DDRA_SMA[0..14] DDRA_SDQ4 MD3A D1XAVSS L41
<12,13> DDRA_SMA[0..14] AE32 MD4A
DDRA_SDQ5 AF34 AP11 D4XAVDD 1 2 D1XAVDD
DDRA_SDQ6 MD5A D4XAVDD D4XAVSS MBK1608121YZF_0603
AF31 MD6A D4XAVSS AP10
DDRA_SDQ7 AE30 1 1 1
DDRA_SDM0 MD7A C456 C480 C471
AD28 DQM0A
<12,13> DDRA_SDQS0 DDRA_SDQS0 AF32
DDRA_SDQS0# DQS0A 10U_0805_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
D <12,13> DDRA_SDQS0# AF33 DQS0A# D
2 2 2
DDRA_SDQ8 AF28 AH24 DDRA_SMA0 1 2 D1XAVSS
DDRA_SDQ9 MD8A MA0A DDRA_SMA1 R409 0_0402_5%
AJ34 MD9A MA1A AP25
DDRA_SDQ10 AH31 AM25 DDRA_SMA2
DDRA_SDQ11 MD10A MA2A DDRA_SMA3
AG30 MD11A MA3A AL25
DDRA_SDQ12 AF30 AP26 DDRA_SMA4
DDRA_SDQ13 MD12A MA4A DDRA_SMA5
AG32 MD13A MA5A AM26
DDRA_SDQ14 AJ32 AN26 DDRA_SMA6
DDRA_SDQ15 MD14A MA6A DDRA_SMA7 +1.8VS
AJ31 MD15A MA7A AK25
DDRA_SDM1 AH34 AP27 DDRA_SMA8 D4XAVDD:10mA
DDRA_SDQS1 DQM1A MA8A DDRA_SMA9 L52
<12,13> DDRA_SDQS1 AH32 DQS1A MA9A AP28
<12,13> DDRA_SDQS1# DDRA_SDQS1# AH33 AK24 DDRA_SMA10 1 2 D4XAVDD
DQS1A# MA10A DDRA_SBS0 MBK1608121YZF_0603
MA11A AN24 DDRA_SBS0 <12,13>
DDRA_SDQ16 AK34 AP24 DDRA_SBS1 1 1 1
MD16A MA12A DDRA_SBS1 <12,13>
DDRA_SDQ17 AH30 AM28 DDRA_SBS2 C583 C579 C578
MD17A DRAM MA13A DDRA_SBS2 <12,13>
DDRA_SDQ18 AL32 AM27 DDRA_SMA11
DDRA_SDQ19 MD18A MA14A DDRA_SMA12 10U_0805_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
AM33 MD19A MA15A AN28
DDRA_SDQ20 DDRA_SMA13 2 2 2
AK32 MD20A MA16A AP21
DDRA_SDQ21 AG29 AP29 DDRA_SMA14 1 2 D4XAVSS
DDRA_SDQ22 MD21A MA17A R473 0_0402_5%
AM34 MD22A
DDRA_SDQ23 AL31 AM23 DDRA_SRAS#
MD23A RASA# DDRA_SRAS# <12,13>
DDRA_SDM2 AJ30 AP22 DDRA_SCAS#
DQM2A CASA# DDRA_SCAS# <12,13>
<12,13> DDRA_SDQS2 DDRA_SDQS2 AK33 AJ23 DDRA_SWE#
DQS2A WEA# DDRA_SWE# <12,13>
<12,13> DDRA_SDQS2# DDRA_SDQS2# AL34 DQS2A#
DDRA_SDQ24 AM32 AK12 CLK_INT
MD24A FWDSDCLKOA CLK_INT <15>
DDRA_SDQ25 AP32 AH12 CLK_INC
MD25A FWDSDCLKOA# CLK_INC <15>
DDRA_SDQ26 AP31
C DDRA_SDQ27 MD26A C
AM29 MD27A
DDRA_SDQ28 AK30
DDRA_SDQ29 MD28A DDRA_SCS0#
AK29 MD29A CS0A# AP23 DDRA_SCS0# <12>
DDRA_SDQ30 AJ27 AH22 DDRA_SCS1#
MD30A CS1A# DDRA_SCS1# <12>
DDRA_SDQ31 AK28 AM22 DDRA_SCS2#
MD31A CS2A# DDRA_SCS2# <13>
DDRA_SDM3 AN32 AM21 DDRA_SCS3#
DQM3A CS3A# DDRA_SCS3# <13>
<12,13> DDRA_SDQS3 DDRA_SDQS3 AM30
DDRA_SDQS3# DQS3A
<12,13> DDRA_SDQS3# AM31 DQS3A#
AK22 DDRA_ODT0
ODT0A DDRA_ODT0 <12>
DDRA_SDQ32 AK20 AP20 DDRA_ODT1
MD32A ODT1A DDRA_ODT1 <12>
DDRA_SDQ33 AM20 AN22 DDRA_ODT2
MD33A ODT2A DDRA_ODT2 <13>
DDRA_SDQ34 AM19 AL21 DDRA_ODT3
MD34A ODT3A DDRA_ODT3 <13>
DDRA_SDQ35 AJ19
DDRA_SDQ36 MD35A
AN20 MD36A
DDRA_SDQ37 AJ21 AN30 DDRA_CKE0
MD37A CKEA0 DDRA_CKE0 <12>
DDRA_SDQ38 AP19 AP30 DDRA_CKE1
MD38A CKEA1 DDRA_CKE1 <12>
DDRA_SDQ39 AH20 AH26 DDRA_CKE2
MD39A CKEA2 DDRA_CKE2 <13> +1.8V
DDRA_SDM4 AK21 AK27 DDRA_CKE3
DQM4A CKEA3 DDRA_CKE3 <13>
<12,13> DDRA_SDQS4 DDRA_SDQS4 AK19
DDRA_SDQS4# DQS4A
<12,13> DDRA_SDQS4# AL19 DQS4A#

1
DDRA_SDQ40 AK18 1
DDRA_SDQ41 MD40A R276 C251
AJ17 MD41A
DDRA_SDQ42 AK17
DDRA_SDQ43 MD42A DDRVREF 1K_0402_1% 0.1U_0402_16V4Z
AP16 MD43A DDRVREF0 AD18
DDRA_SDQ44 2
AH18 AD23

2
DDRA_SDQ45 MD44A DDRVREF1 DDRVREF
AP18 MD45A
DDRA_SDQ46 AN18 MD46A

1
DDRA_SDQ47 AP17 1 1
B DDRA_SDM5 MD47A R501 C238 C233 B
DDRA_SDQS5
AM18
AL17
DQM5A
AJ25 DDRCOMP R226 36_0402_1%
Place C233
<12,13> DDRA_SDQS5 DQS5A DDRCOMP
<12,13> DDRA_SDQS5# DDRA_SDQS5# AM17 DQS5A# DDRCOMN AK26 DDRCOMN R227 36_0402_1% +1.8V 1K_0402_1%
2 2
1U_0603_10V4Z under M672MX
solder side.

2
DDRA_SDQ48 AN16
DDRA_SDQ49 MD48A 0.1U_0402_16V4Z
AK16 MD49A
DDRA_SDQ50 AN14 AH28 OCDVREFP
DDRA_SDQ51 MD50A OCDVREFP OCDVREFN
AJ15 MD51A OCDVREFN AJ29
DDRA_SDQ52 AP15
DDRA_SDQ53 MD52A
AM16 MD53A
DDRA_SDQ54 AK15
DDRA_SDQ55 MD54A +1.8V +1.8V
AP14 MD55A
DDRA_SDM6 AH16
DDRA_SDQS6 DQM6A
<12,13> DDRA_SDQS6 AL15 DQS6A

1
<12,13> DDRA_SDQS6# DDRA_SDQS6# AM15 B6 S3AUXSW#
DQS6A# S3AUXSW# S3AUXSW# <31>
R277 R511
DDRA_SDQ56 AL13
DDRA_SDQ57 MD56A 40.2_0402_1% 36_0402_1%
AM13 MD57A
DDRA_SDQ58 AM12

2
DDRA_SDQ59 MD58A OCDVREFP OCDVREFN
AJ13 MD59A
DDRA_SDQ60 AM14 MD60A

1
DDRA_SDQ61 AK14
DDRA_SDQ62 MD61A R224 R228
AN12 MD62A
DDRA_SDQ63 AH14
DDRA_SDM7 MD63A 36_0402_1% 40.2_0402_1%
AK13 DQM7A
<12,13> DDRA_SDQS7 DDRA_SDQS7 AP12

2
DDRA_SDQS7# DQS7A
<12,13> DDRA_SDQS7# AP13 DQS7A#

A A

SISM672MX-A1_TEBGA_847P

MX@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M672MX (2/5)-DDR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 8 of 47
5 4 3 2 1
5 4 3 2 1

+1.8VS Z4XAVDD:10mA
L24
1 2 Z4XAVDD
MBK1608121YZF_0603
1 1 1 U30A
C252 C250 C248 Z_CLK0 AH10 F15 NB_ENTEST R1931 2 4.7K_0402_5%
<14> Z_CLK0 ZCLK ENTEST
10U_0805_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K <19> ZDREQ ZDREQ AP8 D16
2 2 2 ZUREQ ZDREQ TESTMODE0
<19> ZUREQ AN8 ZUREQ TESTMODE1 E16
D 1 2 Z4XAVSS F16 D
R231 0_0402_5% ZSTB_DP0 TESTMODE2
<19> ZSTB_DP0 AM7 ZSTB0 TRAP0 D17
<19> ZSTB_DN0 ZSTB_DN0 AL7 E17
ZSTB_DP1 ZSTB0# TRAP1
<19> ZSTB_DP1 AP4 ZSTB1 TRAP2 F17
<19> ZSTB_DN1 ZSTB_DN1 AP5 ZSTB1#
+1.8VS ZAD0 AK10 AC32
ZAD1 ZAD0 TRAP3
AM6 ZAD1 TRAP4 AD34
ZAD2 AK11 AB28
ZAD3 ZAD2 TRAP5
AJ11 ZAD3 TRAP6 AD32
1

1 ZAD4 AP7 AD33


R232 C67 ZAD5 ZAD4 TRAP7
AJ9 ZAD5 TRAP8 AE34
ZAD6 AP6 AC30
150_0402_1% 0.1U_0402_16V4Z ZAD[0..16] ZAD7 ZAD6 TRAP9
<19> ZAD[0..16] AN6 ZAD7 TRAP10 AC29
2 ZAD8 AK9
2

Z_VREF ZAD9 ZAD8


AM4 ZAD9
ZAD10 AK6 ZAD10
1

1 ZAD11 AK8
R229 C249 ZAD12 ZAD11 AUX_PWRGD
AN4 ZAD12 AUXOK A5 AUX_PWRGD <20,31>
ZAD13 AK7 C6 SB_PWRGD
ZAD13 PWROK SB_PWRGD <20,31>
49.9_0402_1% 0.1U_0402_16V4Z ZAD14 AL5 A7 NB_RST#
2 ZAD14 PCIRST# NB_RST# <18,19>
ZAD15 AM5
2

ZAD16 ZAD15 ASL


AM8 ZAD16
Z_VREF AL9
+3VS R472 1 ZVREF
2 56_0402_5% Z_COMP_P AP9 ZCMP_P
+1.8VS R230 1 2 56_0402_5% Z_COMP_N AM9 ZCMP_N AGPSTOP#
AGPSTOP# G14 AGPSTOP# <20>
A6 AGPBUSY#
AGPBUSY# AGPBUSY# <20>
C C

1
Z4XAVDD AM10 D8 VBVSYNC
Z4XAVDD VBVSYNC VBVSYNC <18>
R178 Z4XAVSS AN10 F7 V BHSYNC
Z4XAVSS VBHSYNC VBHSYNC <18>
390_0402_5% E7 VBHCLK
VBHCLK VBHCLK <18>

1
2
R179 VGA_CRT_R D13 C8 VBCLK
<17> VGA_CRT_R ROUT VBCLK VBCLK <18>
VGA_CRT_G C12 E9 VBCAD
<17> VGA_CRT_G GOUT VBCAD VBCAD <18>
390_0402_5% VGA_CRT_B C13
<17> VGA_CRT_B BOUT
D9 H_VACLK R559 1 2 33_0402_5% VACLK
VACLK <18>

2
VGA_CRT_HSYNC R184 1 VACLK
<17> VGA_CRT_HSYNC 2 0_0402_5% A _HSYNC F12 HSYNC
VGA_CRT_VSYNC R185 1 2 0_0402_5% A_VSYNC
<17> VGA_CRT_VSYNC G12 VSYNC For SiS VB 307 use only
GMCH_CRT_CLK R183 1 2 0_0402_5% A_DDC1CLK D11
<17> GMCH_CRT_CLK VGPIO0
GMCH_CRT_DATA R182 1 2 0_0402_5% A_DDC1DAT E12 AH2
<17> GMCH_CRT_DATA VGPIO1 NC0
NC1 AG3
VCOMP D15
VVBWN VCOMP
C15 VVBWN
VRSET C14 VRSET
R196 1 2 0_0402_5% INTA# F13
<7,19> INT_N_A INTA#
R195 1 2 0_0402_5% VOSCI F11
<14> REF_CLK0 VOSCI
+1.8VS DCLKAVDD:5mA DACAVDD1 A12
L65 DACAVSS1 DACAVDD1
B12 DACAVSS1
1 2 DCLKAVDD
MBK1608121YZF_0603 DACAVDD2 A13
DACAVSS2 DACAVDD2
1 1 1 B13 DACAVSS2
B C467 C468 C469 B
5/20 reserved by Ivan DCLKAVDD B10 DCLKAVDD
10U_0805_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K DCLKAVSS A11 +3VS
2 2 2 @ DCLKAVSS
1 2 DCLKAVSS 1 2 VCOMP AGPBUSY# R258 1 2 4.7K_0402_5%
R396 0_0402_5% C166 0.1U_0402_16V4Z ECLKAVDD A9
VVBWN ECLKAVSS ECLKAVDD AUX_PWRGD C180 1
1 2 B8 ECLKAVSS 2 0.1U_0402_16V4Z
C167 0.1U_0402_16V4Z
@ SB_PWRGD C181 1 2 0.1U_0402_16V4Z
+1.8VS SISM672MX-A1_TEBGA_847P
+1.8VS ECLKAVDD:5mA
L45 R177 DACAVDD2:73mA MX@
1 2 ECLKAVDD 1 2 DACAVDD2
MBK1608121YZF_0603 0_0402_5%
1 1 1 1 1 1
C491 C484 C485 C174 C490 C483

10U_0805_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 10U_0805_10V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z


2 2 2 2 2 2
1 2 ECLKAVSS 1 2 DACAVSS2
R415 0_0402_5% R406 0_0402_5%

1 2 VRSET
1 2 VCOMP R174 130_0402_5%
C178 0.1U_0402_16V4Z
+1.8VS 1 2 VVBWN
C177 0.1U_0402_16V4Z
R395
DACAVDD1 DACAVDD1:73mA
A A
3.3_0402_5%
1 1 1
C453 C461 C463 DACAVDD1 Spec.
@ @ @
10U_0805_10V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z Voltage : 1.5V +/- 5%
2 2 2
Current : 100mA
Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 DACAVSS1 2006/08/18 2007/8/18 Title
R383 0_0402_5%
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M672MX (3/5)-ASL
7/30 modified to @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 9 of 47

5 4 3 2 1
5 4 3 2 1

U30E

+1.8V W23 VCCM


Y23 VCCM IVDD M13 +1.2VS AUX1.8:1mA AUX_IVDD:92mA
AA23 VCCM IVDD M14
D AB23 M15 +1.8V VCCM:644mA +1.2VS IVDD:2024mA +1.8VALW +1.2VALW D
VCCM IVDD
AC23 VCCM IVDD M16
AC18 VCCM IVDD M17
AC20 M18 C244 1 2 1U_0603_10V4Z C225 1 2 1U_0603_10V4Z 1 1
VCCM IVDD C187 C183
AC16 VCCM IVDD M19
AD16 VCCM IVDD N16
AD17 N17 C245 1 2 1U_0603_10V4Z C227 1 2 1U_0603_10V4Z 1U_0603_10V4Z 1U_0603_10V4Z
VCCM IVDD 2 2
AD19 VCCM IVDD N18
AD20 VCCM IVDD N20
AD21 R22 C246 1 2 10U_0805_10V4Z C243 1 2 10U_0805_10V4Z
VCCM IVDD
AD22 VCCM IVDD N22
AJ22 VCCM IVDD N13
AJ24 VCCM IVDD P13
AL23 VCCM IVDD Y13
AL26 VCCM IVDD Y22
AN21 VCCM IVDD T13
+1.8VS
PVDDH/VCC1.8/VTTP/VDD1.8 +1.2VS +1.05VS
AN23 VCCM IVDD U13 /VDDVB1.8:392mA VDDPEX:876mA VTT:80mA
AN25 VCCM IVDD U22
AN27 VCCM IVDD V13
AN29 W13 C232 1 2 0.1U_0402_16V4Z C202 1 2 0.1U_0402_16V4Z C204 1 2 0.1U_0402_16V4Z
VCCM PWR IVDD
IVDD W22
+1.8VS AP3 VCC1.8 IVDD AA13
AB12 AA22 C239 1 2 1U_0603_10V4Z C195 1 2 1U_0603_10V4Z C192 1 2 1U_0603_10V4Z
VCC1.8 IVDD
AB13 VCC1.8 IVDD AB14
AC12 VCC1.8 IVDD AB15
AC13 AB16 C247 1 2 10U_0805_10V4Z C229 1 2 10U_0805_10V4Z C176 1 2 10U_0805_10V4Z
VCC1.8 IVDD
AC14 VCC1.8 IVDD AB18
AC15 VCC1.8 IVDD AB20
AH6 VCC1.8 IVDD AB22
C AH7 AF6 C
VCC1.8 IVDD
AJ4 VCC1.8 IVDD AF7
AJ5 VCC1.8 IVDD AK3
AJ6 VCC1.8 IVDD AG4
AJ7 VCC1.8 IVDD AG5
AN2 VCC1.8 IVDD AG6
AK4 VCC1.8 IVDD AG7
AK5 VCC1.8 IVDD R13
AL1
AL2
VCC1.8 IVDD AH3
AH4
Place these Cap under M672MX solder side.
VCC1.8 IVDD
AL3 VCC1.8 IVDD AH5
AL4 VCC1.8 IVDD AJ1
AM1 VCC1.8 IVDD AJ2
AM2 VCC1.8 IVDD AJ3
AM3 AK1 +1.8V +1.2VS +1.8VALW +1.2VALW
VCC1.8 IVDD
AN3 VCC1.8 IVDD AK2
AN5 VCC1.8 IVDD AC22
AN7 AC21 C230 1 2 0.1U_0402_16V4Z C226 1 2 0.1U_0402_16V4Z 1 1
VCC1.8 IVDD C190 C182
AN9 VCC1.8 IVDD AC19
IVDD AC17
+1.8VS E8 C231 1 2 0.1U_0402_16V4Z C209 1 2 0.1U_0402_16V4Z 1U_0603_10V4Z 1U_0603_10V4Z
VDDVB1.8 2 2
F9 VDDVB1.8 VTT A19 +1.05VS
F8 VDDVB1.8 VTT A20
B19 C235 1 2 1U_0603_10V4Z C213 1 2 1U_0603_10V4Z
VTT
E10 VDD1.8 VTT B20
F10 VDD1.8 VTT C19
C20 C223 1 2 1U_0603_10V4Z C220 1 2 1U_0603_10V4Z
VTT
VTT D19
+1.8VS N19 PVDDH VTT D20
B C237 1 B
N21 PVDDH VTT E19 2 4.7U_0805_10V4Z C196 1 2 4.7U_0805_10V4Z
P20 PVDDH VTT E20
P22 PVDDH VTT F19
R21 F20 C236 1 2 4.7U_0805_10V4Z C242 1 2 4.7U_0805_10V4Z
PVDDH VTT
T22 PVDDH VTT G19
U21 PVDDH VTT G20
V22 PVDDH VTT L18
VTT L19
+1.2VS M11 VDDPEX VTT L20
N11 VDDPEX VTT M20
P11 M21 +1.8VS +1.2VS +1.05VS
VDDPEX VTT
R11 VDDPEX VTT M22
T11 VDDPEX VTT M23
U11 N23 C198 1 2 0.1U_0402_16V4Z C197 1 2 0.1U_0402_16V4Z C188 1 2 0.1U_0402_16V4Z
VDDPEX VTT
V11 VDDPEX VTT P23
W11 VDDPEX VTT R23
Y11 T23 C221 1 2 1U_0603_10V4Z C240 1 2 1U_0603_10V4Z C179 1 2 1U_0603_10V4Z
VDDPEX VTT
AA11 VDDPEX VTT U23
AB11 VDDPEX VTT V23
M12 +1.8VS C193 1 2 1U_0603_10V4Z C234 1 2 1U_0603_10V4Z C184 1 2 1U_0603_10V4Z
VTTP
VTTP N12
+1.2VALW B5 AUX_IVDD VTTP P12
C5 AUX_IVDD VTTP R12
D6 AUX_IVDD VTTP T12
VTTP U12
VTTP V12
+1.8VALW G8 AUX1.8 VTTP W12
VTTP Y12
A VTTP AA12 A

SISM672MX-A1_TEBGA_847P

MX@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
M672MX (4/5)-POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 10 of 47
5 4 3 2 1
5 4 3 2 1

D D

AG31
AG33
AC31
AC33

AD29

AH29

AN11
AN13
AN15
AN17
AA16
AA17
AA18
AA19
AA20
AA21
AA31
AA33

AB29

AE31
AE33

AK31
AF29

AL10
AL12
AL14
AL16
AL18
AL20

AL28
AL30
AL33
AJ10
AJ12
AJ14
AJ16
AJ18
AJ20
AJ26
AJ28
AJ33
AG2
AC2
AC3

AD2
AD3
AD4
AD5
AD7

AH1
AB3
AB4
AB5
AB7

AE3

AF2
AF3
AF4
AF5

AL6
AL8
AJ8
U30F

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
A3 VSS
B2 VSS VSS T29
B3 VSS VSS U2
B4 VSS VSS U3
VSS U4
B21 VSS VSS U5
B23 VSS VSS U6
B25 VSS VSS U14
B27 VSS VSS U15
B29 VSS VSS U16
B31 VSS VSS U17
C1 VSS VSS U18
C2 VSS VSS U19
C3 VSS VSS U20
C4 VSS VSS U31
VSS U33
VSS V2
C9 VSS VSS V3
C10 VSS VSS V4
C11 VSS VSS V5
C16 VSS VSS V14
C18 VSS VSS V15
C32 VSS VSS V16
C C33 V17 C
VSS VSS
D1 VSS VSS V18
D2 VSS VSS V19
D3 VSS VSS V20
D4 VSS VSS V29
D5 VSS VSS AN33
D10 GND AN31
VSS VSS
D12 VSS VSS AN19
D21 VSS VSS W3
D23 VSS VSS W14
D25 VSS VSS W15
D27 VSS VSS W16
D29 VSS VSS W17
E1 VSS VSS W18
E2 VSS VSS W19
E3 VSS VSS W20
E6 VSS VSS W21
E11 VSS VSS W31
E13 VSS VSS W33
E14 VSS VSS Y2
E18 VSS VSS Y3
E29 VSS VSS Y4
E30 VSS VSS Y5
E33 VSS VSS Y7
F2 VSS VSS Y14
F3 VSS VSS Y15
F4 VSS VSS Y16
F5 VSS VSS Y17
F6 VSS VSS Y18
B B
F14 VSS VSS Y19
F22 VSS VSS Y20
F24 VSS VSS Y21
F26 VSS VSS Y29
F28 VSS VSS AA2
G2 VSS VSS AA3
G3 VSS VSS AA14
G7 VSS VSS AA15
G10 VSS VSS AB17
P21 VSS VSS AB19
T21 VSS VSS AB21
V21 VSS VSS P19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SISM672MX-A1_TEBGA_847P
G31
G33
H4
H5
H29
J2
J3
J7
J31
J33
K3
K4
K5
K29
L2
L3
L4
L5
L7
L31
L33
M2
M3
M29
N3
N4
N5
N6
N7
N14
N15
N31
N33
P2
P3
P14
P15
P16
P17
P18
P29
R2
R3
R4
R5
R14
R15
R16
R17
R18
R19
R20
R31
R33
T3
T6
T14
T15
T16
T17
T18
T19
T20
MX@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
M672MX (5/5)-GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 11 of 47
5 4 3 2 1
5 4 3 2 1

+1.8V +1.8V

JDIMM1 New Add For SiS New Add For SiS


1 2 +1.8V +1.8V
+DIMM_VREF VREF VSS +DIMM_VREF
3 4 DDRA_SDQ4
DDRA_SDQ0 VSS DQ4 DDRA_SDQ5
DDRA_SDQ1
5 DQ0 DQ5 6 20mils
7 DQ1 VSS 8 1 1

1
9 10 DDRA_SDM0 1
DDRA_SDQS0# VSS DM0 R236 C770 + C303 + C304
<8,13> DDRA_SDQS0# 11 DQS0# VSS 12 1
<8,13> DDRA_SDQS0 DDRA_SDQS0 13 14 DDRA_SDQ6 C771 C277 @ @
DQS0 DQ6 DDRA_SDQ7 1K_0402_1% 0.1U_0402_16V4Z 330U_D2E_2.5VM 330U_D2E_2.5VM
15 VSS DQ7 16
DDRA_SDQ2 0.1U_0402_16V4Z 2.2U_0603_6.3V6K 2 2 2
17 18

2
DDRA_SDQ3 DQ2 VSS DDRA_SDQ12 2
19 DQ3 DQ12 20 +DIMM_VREF
D DDRA_SDQ13 D
21 VSS DQ13 22

1
DDRA_SDQ8 23 24 1 1
DDRA_SDQ9 DQ8 VSS DDRA_SDM1 R235 C772 C773
25 DQ9 DM1 26
27 VSS VSS 28
<8,13> DDRA_SDQS1# DDRA_SDQS1# 29 30 DDR_CLK0 1K_0402_1% 0.1U_0402_16V4Z 220P_0402_50V7K
DQS1# CK0 DDR_CLK0 <15> 2 2 @
<8,13> DDRA_SDQS1 DDRA_SDQS1 31 32 DDR_CLK0#
DDR_CLK0# <15>

2
DQS1 CK0#
33 VSS VSS 34
DDRA_SDQ10 35 36 DDRA_SDQ14
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15
37 DQ11 DQ15 38
39 VSS VSS 40
DDRA_SMA[0..14]
<8,13> DDRA_SMA[0..14]
41 VSS VSS 42
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SDQ[0..63]
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21 <8,13> DDRA_SDQ[0..63]
45 DQ17 DQ21 46
47 48 DDRA_SDM[0..7]
VSS VSS <8,13> DDRA_SDM[0..7]
<8,13> DDRA_SDQS2# DDRA_SDQS2# 49 50
DDRA_SDQS2 DQS2# NC DDRA_SDM2
<8,13> DDRA_SDQS2 51 DQS2 DM2 52 Layout Note:
53 VSS VSS 54
DDRA_SDQ18 55 56 DDRA_SDQ22 Place near JP35
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ23
57 DQ19 DQ23 58
59 60 +1.8V
DDRA_SDQ24 VSS VSS DDRA_SDQ28
61 DQ24 DQ28 62
DDRA_SDQ25 63 64 DDRA_SDQ29
DQ25 DQ29
65 VSS VSS 66
DDRA_SDM3 67 68 DDRA_SDQS3#
DM3 DQS3# DDRA_SDQS3# <8,13>
EC_TX_P80_DATA 69 70 DDRA_SDQS3 C296 C774 C775 C776 C777
<13,31> EC_TX_P80_DATA NC DQS3 DDRA_SDQS3 <8,13>
71 VSS VSS 72
DDRA_SDQ26 73 74 DDRA_SDQ30 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31
75 DQ27 DQ31 76 Swap RP11,RP12 Pin 1 & 2 +0.9VS
77 VSS VSS 78
DDRA_CKE0 79 80 DDRA_CKE1
C <8> DDRA_CKE0 CKE0 NC/CKE1 DDRA_CKE1 <8> C
81 82 DDRA_SBS2 1 4
EC_RX_P80_CLK VDD VDD DDRA_CKE0
<13,31> EC_RX_P80_CLK 83 NC NC/A15 84 2 3
DDRA_SBS2 85 86 DDRA_SMA14 RP11 56_0404_4P2R_5%
<8,13> DDRA_SBS2 BA2 NC/A14 +1.8V
87 VDD VDD 88
DDRA_SMA12 89 90 DDRA_SMA11 DDRA_SMA9 1 4
DDRA_SMA9 A12 A11 DDRA_SMA7 DDRA_SMA12
91 A9 A7 92 2 3
DDRA_SMA8 93 94 DDRA_SMA6 RP12 56_0404_4P2R_5%
A8 A6
95 VDD VDD 96 1 1 1 1
DDRA_SMA5 97 98 DDRA_SMA4 DDRA_SMA8 1 4 C778 C297 C779 C295
DDRA_SMA3 A5 A4 DDRA_SMA2 DDRA_SMA5
DDRA_SMA1
99 A3 A2 100
DDRA_SMA0
Swap RP6 Pin2 & RP7 Pin 1 2 3
101 102 RP6 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A1 A0 2 2 2 2
103 VDD VDD 104
DDRA_SMA10 105 106 DDRA_SBS1 DDRA_SMA3 1 4
A10/AP BA1 DDRA_SBS1 <8,13>
DDRA_SBS0 107 108 DDRA_SRAS# DDRA_SMA1 2 3
<8,13> DDRA_SBS0 BA0 RAS# DDRA_SRAS# <8,13>
DDRA_SWE# 109 110 DDRA_SCS0# RP7 56_0404_4P2R_5%
<8,13> DDRA_SWE# WE# S0# DDRA_SCS0# <8>
111 VDD VDD 112
DDRA_SCAS# 113 114 DDRA_ODT0 DDRA_SMA10 1 4
<8,13> DDRA_SCAS# CAS# ODT0 DDRA_ODT0 <8>
DDRA_SCS1# 115 116 DDRA_SMA13 DDRA_SBS0 2 3
<8> DDRA_SCS1# NC/S1# NC/A13
117 118 RP8 56_0404_4P2R_5%
DDRA_ODT1 VDD VDD +0.9VS
<8> DDRA_ODT1 119 NC/ODT1 NC 120
121 122 DDRA_SWE# 1 4
DDRA_SDQ32 VSS VSS DDRA_SDQ36 DDRA_SCAS#
123 DQ32 DQ36 124 2 3
DDRA_SDQ33 125 126 DDRA_SDQ37 RP9 56_0404_4P2R_5%
DQ33 DQ37
127 VSS VSS 128 1 1 1 1 1
<8,13> DDRA_SDQS4# DDRA_SDQS4# 129 130 DDRA_SDM4 DDRA_SCS1# 1 4 C780 C781 C782 C744 C783
DDRA_SDQS4 DQS4# DM4 DDRA_ODT1
<8,13> DDRA_SDQS4 131 DQS4 VSS 132 2 3
133 134 DDRA_SDQ38 RP10 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ34 VSS DQ38 DDRA_SDQ39 2 2 2 2 2
135 DQ34 DQ39 136
DDRA_SDQ35 137 138
DQ35 VSS DDRA_SDQ44
139 VSS DQ44 140
DDRA_SDQ40 141 142 DDRA_SDQ45 DDRA_SMA11 1 4
DDRA_SDQ41 DQ40 DQ45 DDRA_SMA14
143 DQ41 VSS 144 2 3
B
145 146 DDRA_SDQS5# RP13 56_0404_4P2R_5% +0.9VS B
VSS DQS5# DDRA_SDQS5# <8,13>
DDRA_SDM5 147 148 DDRA_SDQS5
DM5 DQS5 DDRA_SDQS5 <8,13>
149 150 DDRA_SMA6 1 4
DDRA_SDQ42 VSS VSS DDRA_SDQ46 DDRA_SMA7
151 DQ42 DQ46 152 2 3
DDRA_SDQ43 153 154 DDRA_SDQ47 RP14 56_0404_4P2R_5% 1 1 1 1 1
DQ43 DQ47 C784 C785 C299 C308 C307
155 VSS VSS 156
DDRA_SDQ48 157 158 DDRA_SDQ52 DDRA_SMA2 1 4
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53 DDRA_SMA4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
159 DQ49 DQ53 160 2 3
EC_RX_P80_CLK R237 1 2 2 2 2 2
2 0_0402_5% 161 VSS VSS 162 RP15 56_0404_4P2R_5%
EC_RX_P80_CLK_R 163 164 DDR_CLK1
<13> EC_RX_P80_CLK_R NC,TEST CK1 DDR_CLK1 <15>
165 166 DDR_CLK1# DDRA_SBS1 1 4
VSS CK1# DDR_CLK1# <15>
<8,13> DDRA_SDQS6# DDRA_SDQS6# 167 168 DDRA_SMA0 2 3
DDRA_SDQS6 DQS6# VSS DDRA_SDM6 RP16 56_0404_4P2R_5%
<8,13> DDRA_SDQS6 169 DQS6 DM6 170
171 172 +0.9VS
DDRA_SDQ50 VSS VSS DDRA_SDQ54 DDRA_SCS0#
173 DQ50 DQ54 174 1 4
DDRA_SDQ51 175 176 DDRA_SDQ55 DDRA_SRAS# 2 3
DQ51 DQ55 RP17 56_0404_4P2R_5%
177 VSS VSS 178
DDRA_SDQ56 179 180 DDRA_SDQ60 1 1 1
DDRA_SDQ57 DQ56 DQ60 DDRA_SDQ61 DDRA_SMA13 C306 C305 C298
181 DQ57 DQ61 182 1 4
183 184 DDRA_ODT0 2 3
DDRA_SDM7 VSS VSS DDRA_SDQS7# RP18 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
185 DM7 DQS7# 186 DDRA_SDQS7# <8,13>
DDRA_SDQS7 2 2 2
187 VSS DQS7 188 DDRA_SDQS7 <8,13>
DDRA_SDQ58 189 190
DDRA_SDQ59 DQ58 VSS DDRA_SDQ62
191 DQ59 DQ62 192
193 194 DDRA_SDQ63
SDATA VSS DQ63 DDRA_CKE1
<13,14,15,20> SDATA 195 SDA VSS 196 1 2
<13,14,15,20> SCLK SCLK 197 198 R238 1 2 10K_0402_5% R241 56_0402_5%
SCL SA0 R239 1
+3VS 199 VDDSPD SA1 200 2 10K_0402_5%
Layout Note:
FOX_ASOA426-M2RN-7F Layout Note: Place one cap close to every 2 pullup
A +3VS
CONN@ Pla ce these resistor resistors terminated to +0.9VS A
closely JP35,all
trace length Max=1.5"
1
DIMM0 STD H:5.2mm (BOT)
C786 C787

0.1U_0402_16V4Z
2.2U_0603_6.3V6K 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 12 of 47
5 4 3 2 1
A B C D E

+1.8V +1.8V

JDIMM2
+DIMM_VREF 1 VREF VSS 2
3 4 DDRA_SDQ4
DDRA_SDQ0 VSS DQ4 DDRA_SDQ5
5 DQ0 DQ5 6
DDRA_SDQ1 7 8
DQ1 VSS DDRA_SDM0 +DIMM_VREF
9 VSS DM0 10
<8,12> DDRA_SDQS0# DDRA_SDQS0# 11 12 20mils
DDRA_SDQS0 DQS0# VSS DDRA_SDQ6
<8,12> DDRA_SDQS0 13 DQS0 DQ6 14
15 16 DDRA_SDQ7
DDRA_SDQ2 VSS DQ7
17 DQ2 VSS 18 1
DDRA_SDQ3 19 20 DDRA_SDQ12 C258 C255
1 DQ3 DQ12 DDRA_SDQ13 1
21 VSS DQ13 22
DDRA_SDQ8 23 24 0.1U_0402_16V4Z 2.2U_0603_6.3V6K
DDRA_SDQ9 DQ8 VSS DDRA_SDM1 2
25 DQ9 DM1 26
27 VSS VSS 28
<8,12> DDRA_SDQS1# DDRA_SDQS1# 29 30 DDR_CLK2
DQS1# CK0 DDRA_CLK2 <15>
<8,12> DDRA_SDQS1 DDRA_SDQS1 31 32 DDR_CLK2#
DQS1 CK0# DDRA_CLK2# <15>
33 VSS VSS 34
DDRA_SDQ10 35 36 DDRA_SDQ14
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15
37 DQ11 DQ15 38
39 VSS VSS 40

41 VSS VSS 42
DDRA_SDQ16 43 44 DDRA_SDQ20
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21 DDRA_SMA[0..14]
45 DQ17 DQ21 46 <8,12> DDRA_SMA[0..14]
47 VSS VSS 48
DDRA_SDQS2# 49 50 DDRA_SDQ[0..63]
<8,12> DDRA_SDQS2# DQS2# NC <8,12> DDRA_SDQ[0..63]
<8,12> DDRA_SDQS2 DDRA_SDQS2 51 52 DDRA_SDM2 Layout Note:
DQS2 DM2 DDRA_SDM[0..7]
53 VSS VSS 54 <8,12> DDRA_SDM[0..7]
DDRA_SDQ18 55 56 DDRA_SDQ22 Place near JP34
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ23
57 DQ19 DQ23 58
59 60 +1.8V
DDRA_SDQ24 VSS VSS DDRA_SDQ28
61 DQ24 DQ28 62
DDRA_SDQ25 63 64 DDRA_SDQ29
DQ25 DQ29
65 VSS VSS 66
DDRA_SDM3 67 68 DDRA_SDQS3#
DM3 DQS3# DDRA_SDQS3# <8,12>
EC_TX_P80_DATA 69 70 DDRA_SDQS3 C253 C256 C254 C264 C263
<12,31> EC_TX_P80_DATA NC DQS3 DDRA_SDQS3 <8,12>
71 VSS VSS 72
DDRA_SDQ26 73 74 DDRA_SDQ30 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31
75 DQ27 DQ31 76
77 78 +0.9VS
DDRA_CKE2 VSS VSS DDRA_CKE3
<8> DDRA_CKE2 79 CKE0 NC/CKE1 80 DDRA_CKE3 <8>
2 DDRA_SCS3# 2
81 VDD VDD 82 1 4
EC_RX_P80_CLK 83 84 DDRA_ODT3 2 3
<12,31> EC_RX_P80_CLK NC NC/A15
DDRA_SBS2 85 86 DDRA_SMA14 RP3 56_0404_4P2R_5%
<8,12> DDRA_SBS2 BA2 NC/A14 +1.8V
87 VDD VDD 88
DDRA_SMA12 89 90 DDRA_SMA11 DDRA_CKE3 1 4
DDRA_SMA9 A12 A11 DDRA_SMA7 DDRA_CKE2
91 A9 A7 92 2 3
DDRA_SMA8 93 94 DDRA_SMA6 RP5 56_0404_4P2R_5%
A8 A6
95 VDD VDD 96 1 1 1 1
DDRA_SMA5 97 98 DDRA_SMA4 DDRA_SCS2# 1 4 C266 C267 C265 C257
DDRA_SMA3 A5 A4 DDRA_SMA2 DDRA_ODT2
99 A3 A2 100 2 3
DDRA_SMA1 101 102 DDRA_SMA0 RP4 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A1 A0 2 2 2 2
103 VDD VDD 104
DDRA_SMA10 105 106 DDRA_SBS1
A10/AP BA1 DDRA_SBS1 <8,12>
DDRA_SBS0 107 108 DDRA_SRAS#
<8,12> DDRA_SBS0 BA0 RAS# DDRA_SRAS# <8,12>
DDRA_SWE# 109 110 DDRA_SCS2#
<8,12> DDRA_SWE# WE# S0# DDRA_SCS2# <8>
111 VDD VDD 112
DDRA_SCAS# 113 114 DDRA_ODT2
<8,12> DDRA_SCAS# CAS# ODT0 DDRA_ODT2 <8>
DDRA_SCS3# 115 116 DDRA_SMA13
<8> DDRA_SCS3# NC/S1# NC/A13
117 VDD VDD 118
DDRA_ODT3 119 120 +0.9VS
<8> DDRA_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDRA_SDQ32 123 124 DDRA_SDQ36
DDRA_SDQ33 DQ32 DQ36 DDRA_SDQ37
125 DQ33 DQ37 126
127 VSS VSS 128 1 1
<8,12> DDRA_SDQS4# DDRA_SDQS4# 129 130 DDRA_SDM4 C262 C261
DDRA_SDQS4 DQS4# DM4
<8,12> DDRA_SDQS4 131 DQS4 VSS 132
133 134 DDRA_SDQ38 4.7U_0805_10V4Z 4.7U_0805_10V4Z
DDRA_SDQ34 VSS DQ38 DDRA_SDQ39 2 2
135 DQ34 DQ39 136
DDRA_SDQ35 137 138
DQ35 VSS DDRA_SDQ44
139 VSS DQ44 140
DDRA_SDQ40 141 142 DDRA_SDQ45
DDRA_SDQ41 DQ40 DQ45
143 DQ41 VSS 144
3 DDRA_SDQS5# 3
145 VSS DQS5# 146 DDRA_SDQS5# <8,12>
DDRA_SDM5 147 148 DDRA_SDQS5
DM5 DQS5 DDRA_SDQS5 <8,12>
149 VSS VSS 150
DDRA_SDQ42 151 152 DDRA_SDQ46
DDRA_SDQ43 DQ42 DQ46 DDRA_SDQ47
153 DQ43 DQ47 154
155 VSS VSS 156
DDRA_SDQ48 157 158 DDRA_SDQ52
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53
159 DQ49 DQ53 160
161 VSS VSS 162
EC_RX_P80_CLK_R 163 164 DDR_CLK3
<12> EC_RX_P80_CLK_R NC,TEST CK1 DDRA_CLK3 <15>
165 166 DDR_CLK3#
VSS CK1# DDRA_CLK3# <15>
<8,12> DDRA_SDQS6# DDRA_SDQS6# 167 168
DDRA_SDQS6 DQS6# VSS DDRA_SDM6
<8,12> DDRA_SDQS6 169 DQS6 DM6 170
171 VSS VSS 172
DDRA_SDQ50 173 174 DDRA_SDQ54
DDRA_SDQ51 DQ50 DQ54 DDRA_SDQ55
175 DQ51 DQ55 176
177 VSS VSS 178
DDRA_SDQ56 179 180 DDRA_SDQ60
DDRA_SDQ57 DQ56 DQ60 DDRA_SDQ61
181 DQ57 DQ61 182
183 VSS VSS 184
DDRA_SDM7 185 186 DDRA_SDQS7#
DM7 DQS7# DDRA_SDQS7# <8,12>
187 188 DDRA_SDQS7
VSS DQS7 DDRA_SDQS7 <8,12>
DDRA_SDQ58 189 190
DDRA_SDQ59 DQ58 VSS DDRA_SDQ62
191 DQ59 DQ62 192
193 194 DDRA_SDQ63
SDATA VSS DQ63
<12,14,15,20> SDATA 195 SDA VSS 196
<12,14,15,20> SCLK SCLK 197 198 R233 1 2 10K_0402_5% +3VS
SCL SAO R234 1
+3VS 199 VDDSPD SA1 200 2 10K_0402_5%
Layout Note:
P-TWO_A5692B-A0G16-P Layout Note: Place one cap close to every 2 pullup
4 +3VS
CONN@ Pla ce these resistor resistors terminated to +0.9VS 4
closely JP34,all
trace length Max=1.5"

C259
1
C260
DIMM1 STD H:9.2mm (BOT)
2.2U_0603_6.3V6K 0.1U_0402_16V4Z
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
DDRII-SODIMM1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 13 of 47
A B C D E
5 4 3 2 1

+CPU_CORE +3VS +3VS


+3VS
L3

1
1 2 CLKGEN_VDD R32 R58 R57
FSL4 FSL3 FSL2 FSL1 FSL0 CPU PCIE PCI ZCLK
KC FBM-L11-201209-221LMAT_0805 1
@
10K_0402_5%
@
10K_0402_5%
@
10K_0402_5%
MHz MHz MHz MHz
1 1 1 1 1 1 1 1 1
C100 C664 C69 C70 C71 C72 C98 C79 C99 C405

2
VTTPWRGD 0 1 0 0 1 133 100 33.3 133

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
10U_0805_10V4Z 10U_0805_10V4Z

1
2 2 2 2 2 2 2 2 2 2 C
2 Q9 0 1 0 1 1 166 100 33.3 133
B MMBT3904_SOT23

1
D C E @ D

3
2 Q10 0 1 0 1 0 200 100 33.3 133
B MMBT3904_SOT23
E @

3
+3VS

RP39
Use SB03904008L & SB000006A00 FootPrint
5 4 MODE
6 3 CLK_RESET#
7 2 STOP# CLKGEN_VDD
8 1 48M

10K_1206_8P4R_5% +3VS

14
19
23
24
56

39
29
L30

2
Remove R43 R66 R529 R527 and use PR39 U4
Michael 2008/5/30 1 2 KC FBM-L11-201209-221LMAT_0805

VDDREF

VDDZ
VDDPCI_0
VDDPCI_1

VDD48

VDDPCIEX_0
VDDPCIEX_1
VDDCPU
1 1 1
+3VS C420 C403 C404
@ VDDA 50 55 CPUT_L0 R95 1 2 33_0402_5% H_CLK_DP0
VDDA CPUT_L0 H_CLK_DP0 <4>
10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z
R80 @ 2.7K_0402_5% 2 2 2 CPUC_L0 R102 1
47 GNDA CPUC_L0 54 2 33_0402_5% H_CLK_DN0
H_CLK_DN0 <4>
FSL0
R55 @ 2.7K_0402_5% 52 CPUT_L1 R94 1 2 33_0402_5% H_CLK_DP1
CPUT_L1 H_CLK_DP1 <7>
R78 @ 2.7K_0402_5% XTAL_IN CPUC_L1 R101 1 2 33_0402_5% H_CLK_DN1
FSL1 Reference schematic use 1206
5 X1 ICS9LPR600 CPUC_L1 51 H_CLK_DN1 <7>
R54 @ 2.7K_0402_5% XTAL_OUT 6
C
X2 C
R76 @ 2.7K_0402_5% 44 PCIET_L0 R91 1 2 33_0402_5% PCIE_CLK_NB
PCIET_L0 PCIE_CLK_NB <7>
FSL2 CLK_14M_SIO R35 @ 22_0402_5% PCIEC_L0 R90 2 33_0402_5% PCIE_CLK_NB#
<33> CLK_14M_SIO 1 2 PCIEC_L0 43 1 PCIE_CLK_NB# <7> NB
R53 @ 2.7K_0402_5% REF_CLK0 R79 1 2 33_0402_5% FSL0 3
<9> REF_CLK0 *FSL0/REF0_2x
REF_CLK1 R77 1 2 22_0402_5% FSL1 4 41
<20> REF_CLK1 **FSL1/REF1_2x PCIET_L1
R52 2.7K_0402_5% VBRCLK R818 1 2 22_0402_5% 40
<18> VBRCLK PCIEC_L1
FSL3
R74 @ 2.7K_0402_5% SB CLK_PCI_SB R75 1 2 33_0402_5% FSL2 9 38 PCIET_L2 R89 1 2 33_0402_5% PCIE_CLK_SB
<19> CLK_PCI_SB **FSL2/PCICLK0_2x PCIET_L2 PCIE_CLK_SB <20>
PCIEC_L2 R88 2 33_0402_5% PCIE_CLK_SB#
PCIEC_L2 37 1 PCIE_CLK_SB# <20>SB
R73 @ 2.7K_0402_5% FSL3 10
FSL4 **FS3/PCICLK1_2x PCIET_L3 R106 1
PCIET_L3 36 2 33_0402_5% PCIE_CLK_307
PCIE_CLK_307 <18>
R56 2.7K_0402_5% EC CLK_PCI_EC R72 1 2 33_0402_5% FSL4 11 35 PCIEC_L3 R105 1 2 33_0402_5% PCIE_CLK_307# 307LV
<31> CLK_PCI_EC **FS4/PCICLK2 PCIEC_L3 PCIE_CLK_307# <18>

DB STOP# 12 34 PCIET_L4F R87 1 2 33_0402_5% PCIE_CLK_EXP


*(PCI_STOP#)/PCICLK3 PCIET_L4F PCIE_CLK_EXP <30>
PCIEC_L4F R86 2 33_0402_5% PCIE_CLK_EXP#
PCIEC_L4F 33 1 PCIE_CLK_EXP# <30> NewCard
MODE 15 **MODE/PCICLK4 PCIET_L5F R104 1
PCIET_L5F 31 2 33_0402_5% PCIE_CLK_WLAN
PCIE_CLK_WLAN <29>
EXP_CLKREQ# R50 1 2 33_0402_5% CLKREQ0# 16 30 PCIEC_L5F R103 1 2 33_0402_5% PCIE_CLK_WLAN# WLAN
<30> EXP_CLKREQ# (PECLKREQ0#)/PCICLK5 PCIEC_L5F PCIE_CLK_WLAN# <29>
WLAN_CLKREQ# R71 1 2 33_0402_5% CLKREQ1# 17 48 SATACLKC_L R92 1 2 33_0402_5% SATA_CLK_DN
<29> WLAN_CLKREQ# (PECLKREQ1#)/PCICLK6 SATACLKC_L SATA_CLK_DN <21>
R39 1 2 4.7K_0402_5% FSL0 49 SATACLKT_L R93 1 2 33_0402_5% SATA_CLK_DP
<5> CPU_BSEL0 SATACLKT_L SATA_CLK_DP <21>
R40 1 2 4.7K_0402_5% FSL1 CLK_PCI_DB R51 1 @ 2 33_0402_5% PCICLK7 18
<5> CPU_BSEL1 <33> CLK_PCI_DB PCICLK7
R38 1 2 4.7K_0402_5% FSL2 21 ZCLK0 R49 1 2 22_0402_5% Z_CLK0
<5> CPU_BSEL2 ZCLK0 Z_CLK0 <9>
<46> CLK_EN# CLK_EN# R62 1 @ 2 0_0402_5% 22 ZCLK1 R70 1 2 22_0402_5% Z_CLK1
ZCLK1 Z_CLK1 <19>
VTTPWRGD R81 1 @ 2 0_0402_5%
VGATE R82 1 2 0_0402_5% CK_PWRGD 1
<46> VGATE VTTPWRGD/PD#/(CLK_STOP#)
CPUSTP# R67 1 2 0_0402_5% CLK_RESET# 28
<25> CPUSTP# *(CPU_STOP#)/RESET#
26 48M R65 1 2 33_0402_5% CLK_48M_CR
B C82 18P_0402_50V8J **SEL24_48#/24_48MHz CLK_48M_CR <26> B
XTAL_IN
1

<12,13,15,20> SDATA SDATA R338 1 2 0_0402_5% SMDATA 45 25 12M R68 1 2 33_0402_5% USB_CLK_12M
SDATA 12MHz USB_CLK_12M <21>
Y1

GNDPCIEX_0
GNDPCIEX_1
14.31818MHZ_16PF_DSX840GA <12,13,15,20> SCLK SCLK R337 1 2 0_0402_5% SMCLK 46 SCLK

GNDPCI_0
GNDPCI_1

GNDCPU
GNDREF
2

XTAL_OUT Pin 26 need BIOS to set disable,

GND48
GNDZ
C86 18P_0402_50V8J
for saving power & good EMI
ICS9LPR600BGLF-T_TSSOP56

7
8
13
20
27
53

42
32
+3VALW +3VS

Z_CLK0 C62 1 2 @ 10P_0402_50V8J


Z_CLK1 C61 1 2 @ 10P_0402_50V8J
CLK_PCI_SB C63 1 2 @ 10P_0402_50V8J
R352 R355 R344 R343
CLK_PCI_EC C66 1 2 @ 10P_0402_50V8J
2.2K_0402_5% 2.2K_0402_5% 1K_0402_5% 1K_0402_5% CLK_PCI_DB C59 1 2 @ 10P_0402_50V8J
REF_CLK0 C65 1 2 @ 10P_0402_50V8J
2N7002DW-T/R7_SOT363-6 REF_CLK1 C64 1 2 @ 10P_0402_50V8J
Q3A
<29,30> DDATA DDATA 6 1 SDATA

A A
2

+3VS
5

DCLK 3 4 SCLK
<29,30> DCLK Security Classification Compal Secret Data
Q3B Title
2N7002DW-T/R7_SOT363-6
Issued Date 2005/03/01 Deciphered Date 2006/03/01
Clock Generator ICS9LPR600C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Replace Package from SOT23 to SOT363-6 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
Michael 2008/5/30 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 14 of 47
5 4 3 2 1
5 4 3 2 1

+1.8V
L25
1 2 KC FBM-L11-201209-221LMAT_0805 0.1U_0402_16V4Z 0.1U_0402_16V4Z CLKBUF_VDD

1 1 1 1 1 1 1
C274 C665 C301 C273 C302 C788 C275
D D
10U_0805_10V4Z 10U_0805_10V4Z
2 2 2 2 2 2 2

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

+1.8V
L26
1 2 KC FBM-L11-201209-221LMAT_0805 CLKBUF_AVDD

1 1 1
C789 C790 C276
@ Horizontal rotate
10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 2

C C
U12
Reference schematic use 1206
CLKBUF_VDD 3 7 CLKBUF_AVDD
VDD1.8_0 VDDA1.8
11 VDD1.8_1
25 VDD1.8_2
21 VDD1.8_3
1 DDR C0 R819 1 2 0_0402_5% DDR_CLK0#
DDRC0 DDR_CLK0# <12>
2 DDRT0 R820 1 2 0_0402_5% DDR_CLK0
DDRT0 DDR_CLK0 <12>
CLK_INC 10
<8> CLK_INC CLK_INC
CLK_INT 9 5 DDR C1 R821 1 2 0_0402_5% DDR_CLK2#
<8> CLK_INT CLK_INT DDRC1 DDRA_CLK2# <13>
4 DDRT1 R822 1 2 0_0402_5% DDR_CLK2
DDRT1 DDRA_CLK2 <13>
SDATA R245 2 1 0_0402_5% 20 13 DDR C2 R823 1 2 0_0402_5% DDR_CLK1#
<12,13,14,20> SDATA SDATA DDRC2 DDR_CLK1# <12>
SCLK R244 2 1 0_0402_5% 19 12 DDRT2 R824 1 2 0_0402_5% DDR_CLK1
<12,13,14,20> SCLK SCLK DDRT2 DDR_CLK1 <12>
FB_OUTA R243 2 1 0_0402_5% FB_INA 18 15 DDR C3 R825 1 2 0_0402_5% DDR_CLK3#
FB_IN DDRC3 DDRA_CLK3# <13>
R242 2 1 22_0402_5% 17 16 DDRT3 R826 1 2 0_0402_5% DDR_CLK3
FB_OUT DDRT3 DDRA_CLK3 <13>

DDRC4 23
8 GND_0 DDRT4 22
6 GND_1
28 GND_2 DDRC5 27
24 GND_3 DDRT5 26
14 GND_4

1 ICS9P935AFLF-T_SSOP28
C300
B B
10P_0402_50V8J
2
C300 close to R242

A A

Security Classification Compal Secret Data


Issued Date 2006/03/01 Title
2005/03/01 Deciphered Date
Clock Buffer ICS9P935
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 15 of 47
5 4 3 2 1
5 4 3 2 1

LCD POWER CIRCUIT

+LCDVDD +3VALW +3VS


W=60mils
D D

1
1

1
R16 2 C36
300_0603_5% R17 C35 @
100K_0402_5% 4.7U_0805_10V4Z
+3VALW +3VS 0.1U_0402_16V4Z 2

1 2
1

3
D S
G
Q8 2 2 1 2 Q5

1
SSM3K7002FU_SC70-3 G R15 10K_0402_5% SI2301BDS_SOT23
R827 R828 S

3
Level Shift Circuit 10K_0402_5% 15K_0402_5%
D

1
1
D +LCDVDD

2
GMCH_ENVDD_Q 2 Q7 W=60mils
G SSM3K7002FU_SC70-3

1
C S

3
2 Q38
B MMBT3904_SOT23 1 1
E C29 C32

3
1
R829 C @
<18> GMCH_ENVDD 1 2 2 Q37 4.7U_0805_10V4Z 0.1U_0402_16V4Z
B 2 2
MMBT3904_SOT23
47K_0402_5% E Change Q7 Q8 package from SOT23 to SC70-3

3
1

Michael 2008/5/30
R22

100K_0402_5%
2

C C

LCD/PANEL BD. Conn.


(IFTXX)
JLVDS1
<18> TZOUT0+
TZOUT0+
TZOUT0-
1 1 2 2 TXOUT0+
TXOUT0-
TXOUT0+ <18>
INVERTER Conn.
<18> TZOUT0- 3 3 4 4 TXOUT0- <18>
5 5 6 6
+3VS TZOUT1+ 7 8 TXOUT1+
<18> TZOUT1+ 7 8 TXOUT1+ <18>
<18> TZOUT1- TZOUT1- 9 10 TXOUT1-
9 10 TXOUT1- <18>
11 11 12 12
1 TZOUT2+ 13 14 TXOUT2+ JP37
<18> TZOUT2+ 13 14 TXOUT2+ <18>
C268 TZOUT2- 15 16 TXOUT2- DAC_BRIG 1 2
<18> TZOUT2- 15 16 TXOUT2- <18> 1
17 18 C44 470P_0402_50V7K
0.1U_0402_16V4Z TZCLK+ 17 18 TXCLK+ INV_PWN_R 2 INVT_PWM
<18> TZCLK+ 19 19 20 20 TXCLK+ <18> 3 1 2
2 TZCLK- TXCLK- DISPOFF# C48 470P_0402_50V7K
<18> TZCLK- 21 21 22 22 TXCLK- <18> 4
23 24 DISPOFF# 1 2
23 24 <31> DAC_BRIG 5
+LCDVDD L10 2 1 +LCDVDD_L 25 26 I2CC_SDA +INVPWR_B+ C45 470P_0402_50V7K
25 26 I2CC_SDA <18> 6
(60 MIL) 27 28 I2CC_SCL
27 28 I2CC_SCL <18> 7
FBMA-L11-201209-221LMA30T_0805 +3VS 29 30 +3VS
29 30 MOLEX_53780-0790
1 1
B C269 C270 ME@ B
31 GND1
32 +3VS
220P_0402_50V7K GND2 220P_0402_50V7K
2 ACES_88242-3001 2

1
+LCDVDD_L CONN@
<EMI> <EMI> R28
1
C271
1
C272
Follow HEL80's pin definition 4.7K_0402_5%
Except pin 29
0208 Add C796 , C797 for EMI

2
10U_0805_10V4Z 0.1U_0402_16V4Z BKOFF# D11 1 2 RB751V_SOD323 DISPOFF#
2 2 <31> BKOFF#

INVT_PWM R25 1 2 0_0402_5% INV_PWN_R


<31> INVT_PWM

copy jhtxx by ivan

+INVPWR_B+

L12 2 1 B+
KC FBM-L11-201209-221LMAT_0805

L11 2 1
KC FBM-L11-201209-221LMAT_0805
1
C49 C43

A 0.1U_0603_50V4Z 68P_0402_50V8K A
2 @

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS & DVI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 16 of 47
5 4 3 2 1
A B C D E

CRT Connector +5VS

Checklist recommend: 2-pole filter on R/G/B signals


D5 D6 D7
C-L-C-L-C

2
@ @ @
DAN217_SC59 DAN217_SC59 DAN217_SC59 L13
10p - 47 Ohm/100MHz - 22p - 47 Ohm/100MHz - 10p KC FBM-L11-201209-221LMAT_0805

1
+R_CRT_VCC +CRT_VCC
W=40mils

1
D8 F1 W=40mils
+L_CRT_VCC 2 1 1 2
1 1

3
RB491D_SC59-31.1A_6VDC_FUSE

Place closed to chipset


12/15 Modified. Note L26~L30 are 0 Ohm resisters +3VS 1
C278
(IFTXX) 0.1U_0402_16V4Z
2
VGA_CRT_R CRT_R_1 L15 1 2 CRT_R_2 JCRT1
<9> VGA_CRT_R
L14 0_0603_5% FBMA-L10-160808-800LMT_0603 6
11
VGA_CRT_G CRT_G_1 L17 1 2 CRT_G_2 1
<9> VGA_CRT_G
L16 0_0603_5% FBMA-L10-160808-800LMT_0603 7
12
VGA_CRT_B CRT_B_1 L19 1 2 CRT_B_2 2
<9> VGA_CRT_B
L18 0_0603_5% FBMA-L10-160808-800LMT_0603 8

1
13
R212 R213 R214 1 1 1 1 1 1 3
C279 C280 C281 C282 C283 C285 1 1 1 9
75_0402_5% 75_0402_5% 75_0402_5% 14
C284 C286 C287 4
2

2
2 2 2 2 2 2 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10 16
10P_0402_50V8J 10P_0402_50V8J 22P_0402_50V8J 2 2 2
15 17
22P_0402_50V8J 22P_0402_50V8J 1 5
10P_0402_50V8J
SUYIN_070546FR015S233CR
+CRT_VCC CRT_HSYNC_2 C288
1 2
L20 FCM1608C-121T_0603 <EMI> 2
1 2 2 1 <EMI> 100P_0402_50V8J DSUB_12
C289 0.1U_0402_16V4Z R215 10K_0402_5% 1 2 CRT_VSYNC_2
L21 FCM1608C-121T_0603 1

1
U5 <EMI> C290
1 1 <EMI>

OE#
2 VGA_CRT_HSYNC CRT_HSYNC_0 2
<9> VGA_CRT_HSYNC 2 A Y 4 1 2 CRT_HSYNC_1 C292 68P_0402_50V8K
R216 39_0402_1% C291 2

G
10P_0402_50V8J 10P_0402_50V8J DSUB_15
TC7SET125FUF_SC70 <EMI> 2 2 <EMI>

3
+CRT_VCC 1
C293
Place closed to chipset 68P_0402_50V8K
1 2
C294 0.1U_0402_16V4Z 2

1
U6
<EMI>

OE#
VGA_CRT_VSYNC 2 4 CRT_VSYNC_0 1 2 CRT_VSYNC_1 12/22 Change to SE071680J80
<9> VGA_CRT_VSYNC A Y R218 39_0402_1%

G
(IFTXX)

1
TC7SET125FUF_SC70

3
D9 D10 Add IFTXX
<EMI> <EMI>
DAN217_SC59 DAN217_SC59
Andy_1102
@ @

3
+5VS

+3VS
+CRT_VCC

1
3 R220 3

+3VS 2.2K_0402_5%

2
R221 R222

2.2K_0402_5% 2.2K_0402_5%

2
DSUB_12 6 1 GMCH_CRT_DATA <9>
Q44A

5
2N7002DW-T/R7_SOT363-6

DSUB_15 3 4 GMCH_CRT_CLK <9>


Q44B
2N7002DW-T/R7_SOT363-6

1
10/5 Change to SB00000AR00 R225

2.2K_0402_5%

2
+3VS

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TV-OUT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 17 of 47
A B C D E
5 4 3 2 1

+1.8VS +1.8VS

L2 1 2 MBK1608121YZF_0603 VB_PCIEVDD L37 1 2 MBK1608121YZF_0603 VB_PCIEAVDD 96mA +3VS


1 1 1 1 1 1 254mA 35mA MBK1608121YZF_0603
C436 C444 C425 C424 C423 C422 1 1 1 VB_LAVDD L35 1 2
C439 C443 C442 1 1 1 1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C430 C429 C431 C427 C428
2 2 2 2 2 2 10U_0805_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z
Modify 10U_1206 to VB_PCIEAVSS 2 2 2 2 2
1 2
10U_0805 Modify 10U_1206 to R365 0_0402_5%
10U_0805 Modify 10U_1206 to
D 10U_0805 D

VB_VDD3V +1.8VS VB_DACVDD


VB_PCIEAVDD VB_LAVDD +3VS
392mA VB_PCIEVDD VB_LVDSPLLVDD L32
VB_PLL1VDD VB_LVDSPLLVDD 1 2
30mA 1 1 MBK1608121YZF_0603 1
C421 C402 C399

0.1U_0402_16V4Z 0.01U_0402_16V7K 10U_0805_10V4Z


VB_LVDSPLLVSS 2 2 2
1 2

G10

H13
H12
H11
H10

D13
D12
D11
D10
M1
G4
H4

C2
R336 0_0402_5%

K3
K4

B3
K2

E9
E8
E7
E6
E5
L1
L2
L3

L6
J4

J5
J6
J7
J8
J9
U7 Modify 10U_1206 to
10U_0805

VDD3V

IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD

PCIEVDD
PCIEVDD
PCIEVDD
PCIEVDD
PCIEVDD
PCIEVDD
PCIEVDD
PCIEVDD
PCIEVDD
PCIEVDD
PCIEVDD

DACVDD
PCIEAVDD
LVDSPLLVDD
PLL1VDD

LAVDD
LAVDD
LAVDD
LAVDD
LAVDD
LAVDD
LAVDD
LAVDD
LAVDD
T17 PAD G2 GPIOA PERN5/SVB_Bn N12 HDVBN2_C <7>
T20 PAD H2 GPIOB PERP5/SVB_Bp N13 HDVBP2_C <7>
T21 PAD H1 GPIOC PERN4/SVB_Gn N10 HDVBN1_C <7>
T18 PAD G1 GPIOD PERP4/SVB_Gp N11 HDVBP1_C <7>
For 307LV/ELV only T7 PAD E12 LCDSENSE/GPIOE PERN3/SVB_Rn N8 HDVBN0_C <7>
T8 PAD E11 INTN/GPIOF PERP3/SVB_Rp N9 HDVBP0_C <7>
<16> GMCH_ENVDD G13 GPIOG
<31> ENBKL G12 GPIOH PERN2/SVA_Bn N6 HDVAN2_C <7>
T10 PAD F11 GPIOI PERP2/SVA_Bp N7 HDVAP2_C <7>
1

T12 PAD F3 GPIOJ PERN1/SVA_Gn N4 HDVAN1_C <7>


R130 PAD G3 N5
T16 GPIOK PERP1/SVA_Gp HDVAP1_C <7>
T13 PAD F2 V2HSYNC/GPIOL PERN0/SVA_Rn N2 HDVAN0_C <7>
C 100K_0402_5% PAD F1 N3 C
T14 V2VSYNC/GPIOM PERP0/SVA_Rp HDVAP0_C <7>
T19 PAD H3
2

TSCLKI/GPION
T22 PAD J3 TVCLKO/GPIOO REFCLKN L7 PCIE_CLK_307# <14>
VB_LAVDD R108 1 @ 2 1.65K_0402_1% L8
REFCLKP PCIE_CLK_307 <14>
R107 1 2 6.04K_0402_1% EXTSWING C13 L4 VB_PCIERSET0R370 1 2 499_0402_1%
EXTSWING PCIERSET0
1 2 R96 1 2 24K_0402_1% A12 LX3P PCIERSET1 L5 VB_PCIERSET1R369 124_0402_1%
C110 A13
1U_0603_10V4Z LX3N
<16> TZOUT2+ C11 LX2P VACLK K13 VACLK <9>
C12 J12 VBCLK_RR132 1 2 33_0402_5%
<16> TZOUT2- VBCLK <9>
307LV/ELV:
Un-stuff R108
<16>
Stuff R107, R96, C110 <16>
<16>
TZOUT1+
TZOUT1-
TZOUT0+
A10
A11
C9
LX2N
LX1P
LX1N
LX0P
SiS307ELV VBCLK
VBHSYNC
VBVSYNC
VBHCAD
K11
J11
L13
VBHSYNC <9>
VBVSYNC <9>Side-Band
VBCAD <9> Signals
307DV/CP: Stuff R108 <16> TZOUT0- C10 LX0N VBHCLK L12 VBHCLK <9>
Un-stuff R107, R96, C110 A8 R345 1 2 0_0402_5% VB_DACVDD
<16> TZCLK+ LXC1P
A9 B2 V2RSET R346 115_0402_1% AGND
<16> TZCLK- LXC1N V2RSET
C7 B1 V2COMP @ 307ELV:stuff R345, un-stuff R346
<16> TXCLK+ LXC2P V2COMP
<16> TXCLK- C8 LXC2N TVDACR D2 307LV/DV/CP:stuff R346, un-stuff R345
<16> TXOUT0+ A6 LX4P TVDACG D1
<16> TXOUT0- A7 LX4N 8/28 Change U6 from SIS307LV SA00000O920 to SIS307ELV SA00000O930 TVDACB E2 5/20 Change R345 from @ to stuff
<16> TXOUT1+ C5 LX5P TVCSYNC E1 PAD T6 307ELV:NC these 4 pins!
<16> TXOUT1- C6 LX5N
A4 L9 VB_PCIEAVSS
<16> TXOUT2+ LX6P PCIEAVSS
A5 A2 VB_LVDSPLLVSS
<16> TXOUT2- LX6N LVDSPLLVSS
C3 K1 VB_PLL1VSS C109 1 2 0.1U_0402_16V4Z
LX7P PLL1VSS
C4 LX7N
DACVSS C1 AGND
<16> I2CC_SDA E13 LDDCDATA DACVSS D3 307ELV:change C94 to 0 ohm
<16> I2CC_SCL F12 LDDCCLK DACVSS E3 307LV/DV/CP:C94=0.1uF
VBOSCO J1 E4
B VBRCLK R830 1 VBOSCO DACVSS B
<14> VBRCLK 2 0_0402_5% VBRCLK_R J2 VBRCLK DACVSS F4 V2COMP C94 1 2 0_0402_5%
T15 PAD G11 PFTEST2 VB_DACVDD
8/28 Change C94 from 0.1U to 0 Ohm+3VS
T11 PAD F10 PFTEST1
AGND
PAD E10 99mA L4
T9 PFTESTO
<9,19> NB_RST# F13 EXTRSTN
1 1 1 1 1
C92 C93 C91 C669 C670 1_0603_5%
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS
PCIEVSS

LAVSS
LAVSS
LAVSS
LAVSS
LAVSS
LAVSS
LAVSS
LAVSS
LAVSS
LAVSS
LAVSS
LAVSS
LAVSS
LAVSS
LAVSS
LAVSS
LAVSS
0.1U_0402_16V4Z 10U_0805_10V4Z 10U_0805_10V4Z
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2 2 2 4.7U_0805_10V4Z 2 2
0.01U_0402_16V7K 7/30 change L14 to 1_0603
SIS307LV-B0_BGA_167P AGND
F5
F6
F7
F8
F9
G5
G6
G7
G8
G9
H5
H6
H7
H8
H9
J10

K12
K10
K9
K8
K7
K6
K5
L10
L11
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1

A3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
D4
D5
D6
D7
D8
D9
+3VS
Add C669 and C670
General I/O Power
Y2 @
14.31818MHZ_16PF_DSX840GA
VBOSCO 2 1 R125 1 @ 2 10_0402_5% VBRCLK_R
1 2 VB_VDD3V 2 2
R358 0_0402_5% 1 C116 C113
C434 @ @
27P_0402_50V8J 27P_0402_50V8J
0.1U_0402_16V4Z 1 1
2 11mA +3VS
L7
NOTE: all stuffed(default) VB_PLL1VDD 1 2
R334 0_0603_5% MBK1608121YZF_0603 1
Modify before using! 1
C118
1
C119 C154
+1.8VS
0.1U_0402_16V4Z 0.01U_0402_16V7K 10U_0805_10V4Z
VB_PLL1VSS 2 2 2
A 1 2 A
1 1 1 1 AGND R139 0_0402_5%
C441 C437 C440 C433
DDC pull-up
0.1U_0402_16V4Z 0.1U_0402_16V4Z +5VS
2 2
0.1U_0402_16V4Z
2 2
0.1U_0402_16V4Z I2CC_SCL
R124 2.2K_0402_5% Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
1 2 Issued Date 2005/03/01 Deciphered Date 2006/03/01
I2CC_SDA 1
R118
2
2.2K_0402_5% LVDS Encoder SiS307LV
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Internal Core Power AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 18 of 47

5 4 3 2 1
5 4 3 2 1

+3VS

RP44
U11A PCI_REQ#4 1 8
D PCI_REQ#3 2 7 D
H5 H2 PCI_REQ#4 PCI_REQ#2 3 6
AD31 PREQ4# PCI_REQ#3 PCI_REQ#1
J4 AD30 PREQ3# H1 4 5
J3 G3 PCI_REQ#2
AD29 PREQ2# PCI_REQ#1 8.2K_1206_8P4R_5%
K1 AD28 PREQ1# G4
K2 G2 PCI_REQ#0
AD27 PREQ0# RP45
J5 AD26
K4 J2 PCI_GNT#4 PAD PCI_REQ#0 1 8
AD25 PGNT4# T28
K3 J1 PCI_GNT#3 PAD INT_N_A 2 7
AD24 PGNT3# T29
L2 H3 PCI_GNT#2 PAD PCI_PIRQB# 3 6
AD23 PGNT2# T27
K5 H4 PCI_GNT#1 PAD PCI_PIRQC# 4 5
AD22 PGNT1# T26
L4 AD21 PGNT0# G5
L3 8.2K_1206_8P4R_5%
AD20
M1 AD19 C/BE3# L1
M2 M3 RP46
AD18 C/BE2# PCI_PIRQD#
L5 N5 1 8
M4
P3
R1
AD17
AD16
AD15
AD14
PCI C/BE1#
C/BE0#

INTA#
R5

F5 INT_N_A
INT_N_A <7,9>
PCI_FRAME#
P CI_IRDY#
PCI_TRDY#
2
3
4
7
6
5
R2 F4 PCI_PIRQB#
AD13 INTB# PCI_PIRQC# 8.2K_1206_8P4R_5%
P5 AD12 INTC# F3
R4 G1 PCI_PIRQD#
AD11 INTD# RP47
R3 AD10
T1 N1 PCI_FRAME# PCI_STOP# 1 8
AD9 FRAME# P CI_IRDY# PCI_SERR#
T2 AD8 IRDY# N2 2 7
T4 M5 PCI_TRDY# PCI_DEVSEL# 3 6
AD7 TRDY# PCI_STOP# PCI_PLOCK#
T3 AD6 STOP# N3 4 5
U1 P2 PCI_SERR#
AD5 SERR# 8.2K_1206_8P4R_5%
U2 AD4 PAR P4
C T5 N4 PCI_DEVSEL# C
AD3 DEVSEL# PCI_PLOCK#
U4 AD2 PLOCK# P1
U3 AD1
V1 V2 CLK_PCI_SB
AD0 PCICLK CLK_PCI_SB <14>
D5 PCI_RST#_R R384 1 2 33_0402_5%
PCIRST# PCI_RST# <28,29,30,31,33>
R831 1 2 33_0402_5% NB_RST# <9,18>
ZAD[0..16] ZAD0 Y22 AE19
<9> ZAD[0..16] ZAD0 IDA0
ZAD1 Y25 AD18
ZAD2 ZAD1 IDA1
Y23 ZAD2 IDA2 AC17
ZAD3 W21 AF18
ZAD4 ZAD3 IDA3 +3VS
Y26 ZAD4 IDA4 AB16
ZAD5 W22 AE17
ZAD6 ZAD5 IDA5 IDE _DIORDY R450 1 @
W24 ZAD6 IDA6 AD16 2 4.7K_0402_5%
ZAD7 W25 AF16 IDE_DD7
+1.8VS ZAD8 ZAD7 IDA7 IDE_IRQ R434 1
U21 ZAD8 IDA8 AE16 2 8.2K_0402_5%
ZAD9 U24 AF17
ZAD10 ZAD9 IDA9
U22 ZAD10 IDA10 AC16
1

MuTIOL
ZAD11 T22 AD17 IDE_DDREQ R441 1 @ 2 4.7K_0402_5%
R198 ZAD12 ZAD11 IDA11
U25 ZAD12 IDA12 AE18
ZAD13 T23 AB17 IDE_IRQ R437 1 @ 2 4.7K_0402_5%
150_0402_1% ZAD14 ZAD13 IDA13
T25 ZAD14 IDA14 AF19
ZAD15 T26 AC18 IDE_DD7 R259 1 2 5.6K_0402_5%

IDE
2

ZAD16 ZAD15 IDA15


AA26 ZAD16
SZVREF AD21
ZSTB_DP0 IDSAA2
<9> ZSTB_DP0 V22 ZSTB0 IDSAA1 AD20
<9> ZSTB_DN0 ZSTB_DN0 V23 AB20 R450 => Intel :Pull-up 4.7K ohm (Mount) SiS : Pull-up ? ohm (Un-Mount)
ZSTB0# IDSAA0
1

1 <9> ZSTB_DP1 ZSTB_DP1 V25


R200 C194 ZSTB_DN1 ZSTB1
B <9> ZSTB_DN1 V26 ZSTB1# IDECSA1# AC21 R434 => Intel :Pull-up 8.2K ohm (Mount) SiS :Not Pull-up B
IDECSA0# AB21
49.9_0402_1% 0.1U_0402_16V4Z <9> ZUREQ ZUREQ AA23 R441 => Intel :Don't Pull-down SiS : Pull-down ? ohm (Un-Mount)
2 ZDREQ ZUREQ
<9> ZDREQ AA24 AF20
2

ZDREQ IIORA#
SZCMP_N IIOWA# AD19 R437 => Intel :Don't Pull-down SiS : Pull-down ? ohm (Un-Mount)
AB24 ZCMP_N IDACKA# AC19
SZCMP_P AB25 R218 => Intel :Don't Pull-down SiS : Pull-down 5.6K ohm (Mount)
ZCMP_P IDE _DIORDY
ICHRDYA AE20
AVDD_SZ4X AA22 AB18 IDE_DDREQ
AVSS_SZ4X AVDD_Z4X IDREQA IDE_IRQ +1.8VS
AB23 AVSS_Z4X IIRQA AB19
CBLIDA AC20 8mA
SZVREF AB26 ZVREF IDEAVDD IDEAVDD L66 1
<14> Z_CLK1 AC26 ZCLK AVDD_IDE V3 2
V4 IDEAVSS MBK1608121YZF_0603
+1.8VS AVSS_IDE
1 1 1
C536 C535 C521
1 2 SZCMP_N AE22
R206 56_0402_5% SPI_DI 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z
AD22

1
R204
2
56_0402_5%
SZCMP_P AF21
AE21
SPI_DO

SPI_CS1N
SPI_CS0N
SPI SPI_CLK

SPI_HARDWARE_TRAP
AF22

AF23 1 2
IDEAVSS
2 2
1
R428
2
0_0402_5%
2

R257 4.7K_0402_5%

SIS968-B0_TEBGA_570P
SPI_Hardware Trap
0:LPC (Default)
+1.8VS
1:SPI
16mA
L67 1 2 AVDD_SZ4X
A A
MBK1608121YZF_0603
1 1 1
C541 C549 C550

10U_0805_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K


2 2 2
1
R446
2
0_0402_5%
AVSS_SZ4X Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2008/05/15 Deciphered Date 2009/05/15
SIS968(1/5)-PCI_IDE_MuTIOL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 19 of 47
5 4 3 2 1
5 4 3 2 1

U11B

8mA +1.8VALW
C175 15P_0402_50V8J OSC32KHO E2 C8 AVSS_GMACCMP
OSC32KHI OSC32KHO AVSS_GMACCMP18 AVDD_GMACCMP AVDD_GMACCMP L38 1
E1 OSC32KHI AVDD_GMACCMP18 D9 2

RTC
10M_0402_5%
X1 MBK1608121YZF_0603

1
3 4 BAT_PWRGD F1 B8 MOSC25MHO 1 1
NC OUT BATOK OSC25MHO

R173
SB_PWRGD E4 A8 MOSC25MHI C459 C457
<9,31> SB_PWRGD PWROK OSC25MHI
2 NC IN 1 1
C473 +RTCVCC A12 GTXCLK PAD 0.1U_0402_16V4Z 0.01U_0402_16V7K
GTXCLK T4 2 2
32.768KHZ_12.5P_1TJS125BJ2A251 D1 F14 EXTCLK PAD T25

2
0.1U_0402_16V4Z RTCVDD EXTCLK AVSS_GMACCMP 1 2
C172 15P_0402_50V8J 2 TXCLK R832 0_0402_5%
D2 RTCVSS TXCLK B11 TXCLK <28>
D D
C12 TX_EN R389 1 2 33_0402_5%
TXEN TXEN <28>
8/07 modified from 12P to 15P C11 TXER PAD
TXER T24 Put closed to 968
<31,33> LPC_AD0 LPC_AD0 Y5
LPC_AD1 LAD0 TXD_0 R146 33_0402_5%
<31,33> LPC_AD1 AA4 LAD1 TXD0 D12 1 2 TXD0 <28>

GMAC
LPC
<31,33> LPC_AD2 LPC_AD2 AB2 A13 TXD_1 R159 1 2 33_0402_5%
LAD2 TXD1 TXD1 <28>
<31,33> LPC_AD3 LPC_AD3 AB3 B13 TXD_2 R158 1 2 33_0402_5% MOSC25MHO
LAD3 TXD2 TXD2 <28>
C13 TXD_3 R145 1 2 33_0402_5%
+3VS TXD3 TXD3 <28>
LPC_FRAME# AB1 R151 0_0402_5%
<31,33> LPC_FRAME# LFRAME#
LPC_DRQ0# AB4 A14 RGMCMP_N R161 1 2 56_0402_5% +3VALW MOSC25MHI 1 2
<33> LPC_DRQ0# LDRQ# RGMCMP_N
R430 1 2 4.7K_0402_5% LPC_DRQ0# SERIRQ AA5 B14 RGMCMP_P R160 1 2 56_0402_5%
<31,33> SERIRQ SIRQ RGMCMP_P

1
R429 1 2 10K_0402_5% SERIRQ C14 RGMVREF R147 1 2 150_0402_1% +3VALW @
RGMVREF R150
R430 => Intel :Not Pull-up SiS : Pull-up 4.7K ohm (Mount) A11 RXCLK
RXCLK RXCLK <28>

1
HD Audio
1 0_0402_5%
R429 => Intel :Pull-up 10K ohm (Mount) SiS :Not Pull-up C10 RXDV R142 C120 Y4
RXDV <28>

2
HDA_SDIN0 RXDV RXER
<35> HDA_SDIN0 E5 HDA_SDIN0 RXER E12 RXER <28> 1 2
HDA_SDIN1 C4 150_0402_1% 0.01U_0402_16V7K
<37> HDA_SDIN1 HDA_SDIN1 2
A10 RXD0 25MHZ_20PF_6X25000017
RXD0 <28>

2
HDA_SDOUT_SB RXD0 RXD1
Y3 HDA_SDOUT RXD1 C9 RXD1 <28>
HDA_SYNC_SB Y2 B9 RXD2 C152 C151
HDA_SYNC RXD2 RXD2 <28>
A9 RXD3
RXD3 RXD3 <28>
HDA_RST_SB# B3 33P_0402_50V8J 33P_0402_50V8J
HDA_BITCLK_SB HDA_RESET# COL
<35> HDA_BITCLK_AUDIO 1 2 Y1 HDA_BIT_CLK COL E10 COL <28>
R192 33_0402_5% E11 CRS
CRS CRS <28> the same with "180"
1 2 E14 H_MDC R260 1 2 33_0402_5% MDC
<37> HDA_BITCLK_MDC MDC MDC <28>
R194 33_0402_5% E13 MDIO MDIO <28> 7/30 modified from 27P to 33P
HDA_SDOUT_SB MDIO U9
<35> HDA_SDOUT_AUDIO 1 2
R201 33_0402_5% D8 GPIO21 GPIO23 4 5
C
GPIO21 GPIO22 GPIO22 DO GND C
<37> HDA_SDOUT_MDC 1 2 GPIO22 F8 3 DI NC 6
R203 33_0402_5% H_INIT# AC23 E8 GPIO23 GPIO21 2 7
<4> H_INIT# INIT# GPIO23 SK NC
1 2 HDA_SYNC_SB H_A20M# AE26 A7 GPIO24 GPIO24 1 8 +3VALW
<35> HDA_SYNC_AUDIO <4> H_A20M# A20M# GPIO24 CS VCC

CPU_S APIC ACPI


R197 33_0402_5% H_SMI# AD23
<4> H_SMI# SMI#
1 2 H_INTR AC22 AT93C46-10SI-2.7_SO8
<37> HDA_SYNC_MDC <4> H_INTR INTR
R199 33_0402_5% H_NMI AE25 @
<4> H_NMI NMI
1 2 HDA_RST_SB# H_IGNNE# AE24 M26 PCIE_PTX_C_IRX_P0
<35> HDA_RST_AUDIO# <4> H_IGNNE# IGNNE# PRX0+ PCIE_PTX_C_IRX_P0 <29>
R166 33_0402_5% H_FERR# AF24 M25 PCIE_PTX_C_IRX_N0 WLAN
<4> H_FERR# FERR# PRX0- PCIE_PTX_C_IRX_N0 <29>

PCI Express
1 2 H_STPCLK# AF25 N24 PCIE_ITX_PRX_P0 C515 1 2 0.1U_0402_10V7K PCIE_ITX_C_PRX_P0
<37> HDA_RST_MDC# <4> H_STPCLK# STPCLK# PTX0+ PCIE_ITX_C_PRX_P0 <29>
R167 33_0402_5% H_CPUSLP# AD24 N23 PCIE_ITX_PRX_N0 C511 1 2 0.1U_0402_10V7K PCIE_ITX_C_PRX_N0
<5> H_CPUSLP# CPUSLP# PTX0- PCIE_ITX_C_PRX_N0 <29>
8/29 change net from BAT_PWRGD to net +RTCVCC K26 PCIE_PTX_C_IRX_P1
PRX1+ PCIE_PTX_C_IRX_P1 <30>
K25 PCIE_PTX_C_IRX_N1
PRX1- PCIE_PTX_C_IRX_N1 <30>
L24 PCIE_ITX_PRX_P1 C512 1 2 0.1U_0402_10V7K PCIE_ITX_C_PRX_P1 NEW Card
+RTCVCC PTX1+ PCIE_ITX_C_PRX_P1 <30>
SMT1-05_4P L23 PCIE_ITX_PRX_N1 C506 1 2 0.1U_0402_10V7K PCIE_ITX_C_PRX_N1
PTX1- PCIE_ITX_C_PRX_N1 <30>
SW1
@ H_PROCHOT# AC24 F26
1 3 CPU IU <4,46> H_PROCHOT#
H_THERMTRIP# AD25 PROCHOT# NC11
F25
PCI-Express
<4> H_THERMTRIP# THERMTRIP# NC10
AGPBUSY# AE23 G24 30mA +1.8VS
<9> AGPBUSY# BMBUSY# NC9
2 4 NC8 G23
H26 AVDD_PEXTRX L9 1 2
NC7 MBK1608121YZF_0603
H25
6
5

NC6
7/30 add for debug R176 REF_CLK1 NC5 J24
C185
1 1
C186
<14> REF_CLK1 AA2 OSCI NC4 J23
1 2 F2 ENTEST
0_0402_5% SB_SPKR AA1 P26 PCIE_CLK_SB 0.1U_0402_16V4Z 0.01U_0402_16V7K
<35> SB_SPKR SPK PCLK100P PCIE_CLK_SB <14> 2 2
P25 PCIE_CLK_SB#
PCLK100N PCIE_CLK_SB# <14>
+3VALW PBTN_OUT# E6 R25 AVDD_PEXTRX AVSS_PEXTRX 1 2
<31> PBTN_OUT# PWRBTN# AVDD_PEXTRX
RP40 PCI_PME# A6 R26 AVSS_PEXTRX R190 0_0402_5%
<31> PCI_PME# PME# AVSS_PEXTRX
5 4 EC_SMI# PSON# E7 P22 R420 1 2 499_0402_1%
B <31> PSON# PSON# RSET0 B
6 3 EC_LID_OUT# P21 R426 1 2 124_0402_1%
EC_SCI# RSET1 +3VALW
7 2 <9,31> AUX_PWRGD C3 AUXOK
8 1 PM_SLP_S5# 2 1 A5 R21 PCIEPRSNT1
C168 0.1U_0402_16V4Z ACPILED PCIEPRSNT1 PCIEPRSNT0 R427 1
PCIEPRSNT0 R23 2 0_0402_5% GPIO23 R386 1 2 4.7K_0402_5%
10K_1206_8P4R_5% Remove R163 R162 R164 R388 R382 @ PBTN_OUT# R833 1 2 100K_0402_5%
RP41 PCI_PME# R385 1 2 4.7K_0402_5%
5 4 AGPSTOP#
R425 R387 R381; Add RP40 RP41 7/20 modified PSON# R834 1 2 100K_0402_5%
Michael 2008/5/30
6 3 CPUSTP_N_OLD <31> PM_SLP_S5#
PM_SLP_S5# C2 GPIO10/SLP_S5# GPIO0/STPCPU# U5 PROJECT_ID
7 2 GPIO14 PM_SLP_S3# C7 AB5 GPIO1
8 1 PM_SLP_S3#
<31> PM_SLP_S3# GPIO15/SLP_S3# GPIO1/LDRQ1#/PCIE_HOTPLUG
V5 GPIO2 10/26 modified 1 2 +3VS
EC_SMI# GPIO2/THERM# GPIO3 R611 1K_0402_5%
<31> EC_SMI# D6 GPIO7/GPWAK# GPIO3/EXTSMI# W4
10K_1206_8P4R_5% EC_LID_OUT# A4 W3 PM_CLKRUN# PM_CLKRUN# <31> GPIO1 R443 1@ 2 10K_0402_5%
<31> EC_LID_OUT# GPIO8/RING GPIO4/CLKRUN#
EC_SCI# C6 W2 GPIO5 PM_CLKRUN# R444 1 @ 2 10K_0402_5%
<31> EC_SCI# GPIO9/HDA_SDIN2 GPIO5/PREQ5#
R381 1 2 10K_0402_5% GPIO16 W1 IDE_HRESET#
R397 10K_0402_5% GATEA20 AGPSTOP# GPIO6/PGNT5# RP42
1 2 F6
R393
R390
1
1 @
2
2
10K_0402_5%
10K_0402_5%
KB_RST#
EC_THERM#
<9> AGPSTOP#
<25> CPUSTP_N_OLD
<25> SB_DPRSLPVR
CPUSTP_N_OLD
SB_DPRSLPVR
GPIO14
D4
D3
GPIO11/STP_PCI#/AGPSTOP#
GPIO12/CPUSTP#/DPSLP#
GPIO13/DPRSLPVR
GPIO GPIO19 Y4 SCLK
SDATA
SCLK <12,13,14,15>
GPIO3
GPIO5
IDE_HRESET#
5
6
4
3
B5 GPIO14/AGPSTOP#/S3AUXSW# GPIO20 W5 SDATA <12,13,14,15> 7 2
+3VS GPIO2 8 1
GPIO16 B7
R403 1 @ GPIO16/DPRSTP#
2 10K_0402_5% GATEA20 GATEA20 D7 Remove R433 R435 R438 R439 10K_1206_8P4R_5%
R398 1 @ 2 10K_0402_5% KB_RST#
<31> GATEA20
KB_RST# B4
GPIO17/GA20# 7/20 modified Add RP42 Michael 2008/5/30
<31> KB_RST# GPIO18/KBDRST#

R187 2 1 4.7K_0402_5% +1.8VS SB_DPRSLPVR R404 1 2 4.7K_0402_5%


D20 +RTCVCC
+RTC_BATT SIS968-B0_TEBGA_570P
- BATT1 + R291
2 +CHGRTC Change D19 footprint from RLS4148_LL34-2 to LL34
@
PCIEPRSNT1
D14
2 1 CP_PE#
RB751V_SOD323
CP_PE# <30>

A 2 1+RTCBATT1 2 1 J2 1 2 JOPEN PROJECT_ID R436 1 @ 2 10K_0402_5% +3VS A


D19 RLS4148_LL34-2
511_0603_1% 3 1 2 BAT_PWRGD GPIO2 R431 1 2 0_0402_5% EC_THERM# 1 2
EC_THERM# <31>
GPIO14 R394 1 @ 2 0_0402_5% R424 14W@ 1K_0402_5%
ML1220T13RE BAS40-04_SOT23 R279 10K_0402_5% 8/29 change J1,J4 from net BAT_PWRGD to net +RTCVCC
@ 1 1 1 1 1 2
C346 C326 C333 C332 1 Security Classification Compal Secret Data Compal Electronics, Inc.
1

J1 C328
1U_0603_10V4Z 0.01U_0402_16V7K @ Title
2 2 2 2 JOPEN
Issued Date 2008/05/15 Deciphered Date 2009/05/15
SIS968(2/5)-PCIE_LAN_RTC
2

10U_0805_10V4Z 2
Decoupling Capacitor THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1U_0402_16V4Z 10U_0805_10V4Z Custom 0.1
Please close to SB DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 20 of 47
5 4 3 2 1
5 4 3 2 1

+1.8VALW 7mA
L8 1 2 USBPVDD18
MBK1608121YZF_0603 1 1
C170 C171
U11C
D 0.1U_0402_16V4Z 0.01U_0402_16V7K D
2 2 USBPVSS18
1 2
R168 0_0402_5% USB20_P0 D26 A22 USB_CLK_12M
USB <30>
<30>
USB20_P0
USB20_N0 USB20_N0 D25
UV0+ OSC12MHI
B22
USB_CLK_12M <14>
USB20_P1 UV0- OSC12MHO USBREF R402 1
E24 F20 2 127_0402_1%
+3VALW 8mA BT <33>
<33>
USB20_P1
USB20_N1 USB20_N1 E23
UV1+ USBREF
USB20_P2 UV1- USBPVDD18
A20 B26
L43 1 2
New Card <30>
<30>
USB20_P2
USB20_N2 USB20_N2 B20
UV2+ AVDD_USBPLL18
B25 USBPVSS18
MBK1608121YZF_0603 USB20_P3 UV2- AVSS_USBPLL18
C489
1 1
C478
Place C478,C489 close to <37> USB20_P3
USB20_N3
C19 UV3+ USBCMPAVDD18
D19 E21
U11 Pin F17,F19,F22 WLAN <37>
<30>
USB20_N3
USB20_P4 USB20_P4 A18
UV3- AVDD_USBCMP18
E20 USBCMPAVSS18
0.1U_0402_16V4Z 0.01U_0402_16V7K USB20_N4 UV4+ AVSS_USBCMP18
B18
2 2 USB <30>
<30>
USB20_N4
USB20_P5 USB20_P5 C17
UV4-
D21 USBCMPAVDD33
USB20_N5 UV5+ AVDD_USBCMP33 USBCMPAVSS33
8mA USB <30> USB20_N5 D17 UV5- AVSS_USBCMP33 C21
<26> USB20_P6 USB20_P6 A16

C465
1 1
USBCMPAVDD33

C466
Place C465,C466
Card Reader <26>
<37>
USB20_N6
USB20_P7
USB20_N6
USB20_P7
USB20_N7
B16
C15
D15
UV6+
UV6-
UV7+
USB UVDD33
UVDD33
F17
F19
F22
USBCMPAVDD33

close to U11 Pin D21CAMERA <37> USB20_N7 UV7- UVDD33


0.1U_0402_16V4Z 0.01U_0402_16V7K USB_OC#06 A23 J15 UVDD18
2 2 <30> USB_OC#06 OC0# UVDD18
USB_OC#1 F21 H15
USBCMPAVSS33 USB_OC#2 OC1# UVDD18
1 2 A24 OC2# UVDD18 H16
R392 0_0402_5% USB_OC#3 B24 H17
USB_OC#45 OC3# UVDD18
<30> USB_OC#45 C23 OC4# UVDD18 H18
C24 OC5# UVDD18 J19
USB_OC#6 A25 F16
+1.8VALW USB_OC#7 OC6# UVDD18
9mA B23 OC7# UVDD18 F15
UVDD18 E18
L46 1 2 USBCMPAVDD18 E16
C MBK1608121YZF_0603 UVDD18 C
1 1
C476 C477
AC13 SATA_ITX_DRX_P0 C560 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P0
STX0+ SATA_ITX_C_DRX_P0 <24>
0.1U_0402_16V4Z 0.01U_0402_16V7K AVDD_SATARX AF14 AD13 SATA_ITX_DRX_N0 C559 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_N0
2 2 AVDD_SATARX STX0- SATA_ITX_C_DRX_N0 <24>
AVSS_SATARX AF15 AF12 SATA_DTX_C_IRX_P0
AVSS_SATARX SRX0+ SATA_DTX_C_IRX_P0 <24>
1 2 USBCMPAVSS18 AE12 SATA_DTX_C_IRX_N0
SRX0- SATA_DTX_C_IRX_N0 <24>
R407 0_0402_5% AVDD_SATAPLL33 AC9 AC6 SATA_ITX_DRX_P1 C791 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P1
AVDD_SATAPLL33 STX1+ SATA_ITX_C_DRX_P1 <24>
AD9 AD6 SATA_ITX_DRX_N1 C792 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_N1
AVDD_SATAPLL33 STX1- SATA_ITX_C_DRX_N1 <24>
AF5 SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_P1 <24>

+1.8VALW 284mA
AVSS_SATAPLL33 AC8
AD8
AVSS_SATAPLL33
AVSS_SATAPLL33
SATA SRX1+
SRX1-

XIN
AE5

AE8
SATA_DTX_C_IRX_N1

SOSC25MHI 1
SATA_DTX_C_IRX_N1 <24>
2
R211 1 2 12K_0402_1% SATA_REXT AF7 AF8 R219 0_0402_5%
L44 1 UVDD18 C216 22P_0402_50V8J REXT XOUT
2 1 2
MBK1608121YZF_0603 1 1 AA3 H_SATA_LED#
C475 C474 SATA_CLK_DP HDACT
<14> SATA_CLK_DP AE15 CLK100P
SATA_CLK_DN AD15 AC1 ISWITCHOPEN1 R207 1 2 1K_0402_5%
<14> SATA_CLK_DN CLK100N ISWITCHOPEN1
0.1U_0402_16V4Z 0.01U_0402_16V7K AD1 ISWITCHOPEN0 R209 1 2 1K_0402_5%
2 2 ISWITCHOPEN0

SB_PCIE_WAKE# E9 D22
<7,29,30> SB_PCIE_WAKE# PCIEWAKE IPB_OUT0
1 2 ATRAP D10 C22
R405 1 ATRAP IPB_OUT1
+3VALW 2 1K_0402_5% TRAP0 E22 TRAP0
R155 @ 1K_0402_5%
+3VS +5VS

+3VALW 133MHz:Internal pull-down SIS968-B0_TEBGA_570P C663 1 2 @ 0.1U_0402_16V4Z


B B
66MHz:External pull-up

1
R836 1 2 4.7K_0402_5% SB_PCIE_WAKE# R576 1 @ 2 10K_0402_5%
R205
@
10K_0402_5%

1
U39

OE#
H_SATA_LED# 2 4 SATA_LED#
+1.8VS A Y SATA_LED# <37>
6mA

G
L23 1 2 AVDD_SATARX @ TC7SET125FUF_SC70

3
MBK1608121YZF_0603 Remove R838 R839 R840 R552
1 1 Add RP43 Michael 2008/5/30
C222 C215
R837 1 2 0_0402_5%
0.1U_0402_16V4Z 0.01U_0402_16V7K +3VALW
2 2 RP43
1 2 AVSS_SATARX 5 4 USB_OC#2
R217 0_0402_5% 6 3 USB_OC#1
7 2 USB_OC#3
8 1 USB_OC#7

10K_1206_8P4R_5%

R841 1 2 10K_0402_5% USB_OC#6


+3VS 41mA
L51 1 2 AVDD_SATAPLL33
MBK1608121YZF_0603
A A
1 1
C545 C548

0.1U_0402_16V4Z 0.01U_0402_16V7K
2 2
1 2 AVSS_SATAPLL33
R440 0_0402_5% Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2008/05/15 Deciphered Date 2009/05/15
SIS968(3/5)-USB_SATA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-3961P Schematic
Date: Friday, August 01, 2008 Sheet 21 of 47
5 4 3 2 1
5 4 3 2 1

+3VS

0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0805_10V4Z

1 1 1 1 1 1 1 1
C502 C507 C522 C534 C542 C538 C543 C556

0.1U_0402_16V4Z
2 2 2 2 2 2 2 2
D D
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0805_10V4Z

U11D +1.8VS
+1.05VS
22mA +1.8VS
AA21 VTT IVDD T18
+3VS AB22 J14 413mA
VTT IVDD 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0805_10V4Z
IVDD U9
V16 PVDD IVDD T9
29mA V15 PVDD IVDD R9 1 1 1 1 1 1 1 1
V14 P9 C514 C525 C526 C527 C539 C540 C524 C523
PVDD IVDD
T8 PVDD IVDD N9
N8 M9 0.1U_0402_16V4Z
PVDD IVDD 2 2 2 2 2 2 2 2
L9 PVDD IVDD K9
IVDD V10
W17 V11 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0805_10V4Z
W16
W15
W14
OVDD
OVDD
OVDD
OVDD
Power IVDD
IVDD
IVDD
IVDD
V12
V13
V17
W13 OVDD IVDD R17
+1.8VS +1.8VS C557,C555,C217,C228,C551,C554 +1.8VALW +1.05VS
W12 R18
K8
OVDD IVDD close to U30 Pin AVDD_SATA
OVDD 1U_0603_10V4Z
L8 OVDD VDDZ N18
M8 OVDD VDDZ W19 413mA
P8 OVDD VDDZ V19 1 1 1 1 1 1 1 1
R8 V18 C533 C555 C217 C228 C497 C488 C547 C793
OVDD VDDZ
U8 OVDD VDDZ U18
+3VALW V8 W18 0.01U_0402_16V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z 1U_0603_10V4Z
C
OVDD VDDZ 2 2 2 2 2 2 2 2 C
VDDZ P18
H19 OVDD_AUX VDDZ Y24
4mA H9 V24 0.1U_0402_16V4Z 10U_0805_10V4Z
OVDD_AUX VDDZ
H8 OVDD_AUX VDDZ T24
F7 OVDD_AUX VDDZ R24

+3VALW
J11 OVDD_AUX VDDZ AA25
+1.8VS C504,C509,C494,C495,C513,C503 +3VALW
J12 W26
OVDD_AUX VDDZ
U26 +1.8VALW close to U30 Pin AVDDPEX
VDDZ 1U_0603_10V4Z 1U_0603_10V4Z
H10 GMIIVDD_AUX
8mA H11 GMIIVDD_AUX IVDD_AUX J9
H12 GMIIVDD_AUX IVDD_AUX J8 19mA 1 1 1 1 1 1 1 1
H13 J10 C504 C509 C494 C495 C501 C500 C148 C510
+1.8VS GMIIVDD_AUX IVDD_AUX
J13 GMIIVDD_AUX IVDD_AUX J16
J17 0.01U_0402_16V7K 0.1U_0402_16V4Z
IVDD_AUX +1.8VS 2 2 2 2 2 2 2 2
K18 AVDDPEX IVDD_AUX J18
153mA L18 AVDDPEX
L19 W11 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 1U_0603_10V4Z
AVDDPEX AVDD_SATA
M18 AVDDPEX AVDD_SATA W10 190mA
M19 AVDDPEX AVDD_SATA W9
N19 AVDDPEX AVDD_SATA W8
H21 AVDDPEX AVDD_SATA V9
J21 AVDDPEX AVDD_SATA AF10
K21 AVDDPEX AVDD_SATA AE10
L21 AVDDPEX AVDD_SATA AD11 Put under 968 solder side
M21 AVDDPEX AVDD_SATA AD10
N21 AVDDPEX AVDD_SATA AC11
M22 AVDDPEX AVDD_SATA AC10
H22 AB11 +1.8VS +3VS +1.05VS
AVDDPEX AVDD_SATA
AVDD_SATA AB10
B 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
AVDD_SATA AB9
AVDD_SATA AB8
1 1 1 1 1 1 1 1 1 1
C537 C530 C520 C517 C794 C531 C519 C516 C532 C546

SIS968-B0_TEBGA_570P 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


2 2 2 2 2 2 2 2 2 2

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

+3VALW +3VALW +1.8VALW +1.8VS +1.8VS

1 1 1 1 1 1 1 1 1 1
C493 C499 C482 C486 C492 C498 C513 C503 C551 C544

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.01U_0402_16V7K
2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2008/05/15 Deciphered Date 2009/05/15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SIS968(4/5)-POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 22 of 47
5 4 3 2 1
5 4 3 2 1

U11E

K10 VSS VSSZ U17


K11 VSS VSSZ U16
D K12 VSS VSSZ T16 D
L10 VSS VSSZ R16
L11 VSS VSSZ R15
L12 VSS VSSZ T17
L14 VSS VSSZ P15
L15 VSS VSSZ T15
L16 VSS VSSZ Y21
M10 VSS VSSZ V21
M11 VSS VSSZ T21
M12 R22
M13
M14
M15
VSS
VSS
VSS
VSS
Gound VSSZ
VSSZ
VSSZ
W23
U23

N10 VSS USBVSS D14


AD26 VSS USBVSS E15
AC25 VSS USBVSS A15
B10 VSS USBVSS B15
B12 VSS USBVSS C16
D11 VSS USBVSS D16
D13 VSS USBVSS A17
U15 VSS USBVSS B17
U14 VSS USBVSS E17
U13 VSS USBVSS C18
U12 VSS USBVSS D18
U11 VSS USBVSS A19
U10 VSS USBVSS B19
T14 VSS USBVSS E19
T13 VSS USBVSS C20
T12 VSS USBVSS D20
C T11 A21 C
VSS USBVSS
T10 VSS USBVSS B21
R14 VSS USBVSS D23
R13 VSS USBVSS D24
R12 VSS USBVSS C25
R11 VSS USBVSS C26
R10 VSS USBVSS K13
P14 VSS USBVSS K14
P13 VSS USBVSS K15
P12 VSS USBVSS K16
P11 VSS USBVSS K17
P10 VSS USBVSS L13
N14 VSS USBVSS L17
N13 VSS
N12 VSS AVSS_SATA AB6
N11 VSS AVSS_SATA AB7
AVSS_SATA AB12
P24 AVSSPEX AVSS_SATA AB13
P23 AVSSPEX AVSS_SATA AB14
N22 AVSSPEX AVSS_SATA AB15
N26 AVSSPEX AVSS_SATA AC2
N25 AVSSPEX AVSS_SATA AC3
M24 AVSSPEX AVSS_SATA AC4
M23 AVSSPEX AVSS_SATA AC5
L22 AVSSPEX AVSS_SATA AC7
K22 AVSSPEX AVSS_SATA AC12
J22 AVSSPEX AVSS_SATA AC14
G22 AVSSPEX AVSS_SATA AC15
L26 AVSSPEX AVSS_SATA AD2
B B
L25 AVSSPEX AVSS_SATA AD3
K24 AVSSPEX AVSS_SATA AD4
K23 AVSSPEX AVSS_SATA AD5
J26 AVSSPEX AVSS_SATA AD7
J25 AVSSPEX AVSS_SATA AD12
H24 AVSSPEX AVSS_SATA AD14
H23 AVSSPEX AVSS_SATA AE1
G26 AVSSPEX AVSS_SATA AE2
G25 AVSSPEX AVSS_SATA AE3
F24 AVSSPEX AVSS_SATA AE4
F23 AVSSPEX AVSS_SATA AE6
E26 AVSSPEX AVSS_SATA AE7
E25 AVSSPEX AVSS_SATA AE9
P16 AVSSPEX AVSS_SATA AE11
M17 AVSSPEX AVSS_SATA AE13
N17 AVSSPEX AVSS_SATA AE14
P17 AVSSPEX AVSS_SATA AF2
M16 AVSSPEX AVSS_SATA AF3
N16 AVSSPEX AVSS_SATA AF4
N15 AVSSPEX AVSS_SATA AF6
AVSS_SATA AF9
AVSS_SATA AF11
AVSS_SATA AF13

SIS968-B0_TEBGA_570P

A A

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2008/05/15 Deciphered Date 2009/05/15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SIS968(5/5)-GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 23 of 47
5 4 3 2 1
A B C D E F G H

14W SATA ODD Conn.


1 1

+5VS

0.1U_0402_16V4Z

1 1 1
C369 C370 C371
14W@ 14W@ 14W@
2 2 2

1000P_0402_50V7K 10U_0805_10V4Z
SATA ODD Conn.
Copy JIWA2 Symbol

JSATA1

1 GND
SATA_ITX_C_DRX_P1 2
<21> SATA_ITX_C_DRX_P1 A+
SATA_ITX_C_DRX_N1 3
<21> SATA_ITX_C_DRX_N1 A-
4 GND
SATA_DTX_IRX_N1 5
SATA_DTX_IRX_P1 B-
6 B+
7 GND
SATA HDD Conn.
R373 1 @ 2 1K_0402_1% 8 DP
+5VS 9 +5V
2 2
10 +5V
11 MD
12 GND
13 GND
OCTEK_SLS-13SB1G
SATA_DTX_C_IRX_N1 1 2 SATA_DTX_IRX_N1
<21> SATA_DTX_C_IRX_N1
C372 0.01U_0402_16V7K

SATA_DTX_C_IRX_P1 1 2 SATA_DTX_IRX_P1 Update FootPrint from


<21> SATA_DTX_C_IRX_P1
C373 0.01U_0402_16V7K
OCTEK_SLS-13SB1G_13P-T to +5VS +3VS
OCTEK_SLS-13SB1G_13P_RV-T 0.1U_0402_16V4Z 10U_0805_10V4Z

1 1 1 1 1 1
C366 C365 C367 C353 C354 C68

0.1U_0402_16V4Z
2 2 2 2 2 2 @

1000P_0402_50V7K 1U_0603_10V4Z 10U_0805_10V4Z

15W SATA ODD Conn.


+5VS_ODD
JSATA3
0.1U_0402_16V4Z 1
SATA_ITX_C_DRX_P0 GND
<21> SATA_ITX_C_DRX_P0 2 A+
3 SATA_ITX_C_DRX_N0 3
1 1 1 <21> SATA_ITX_C_DRX_N0 3 A-
C381 C382 C380 4
15W@ 15W@ 15W@ SATA_DTX_C_IRX_N0 SATA_DTX_IRX_N0 GND
<21> SATA_DTX_C_IRX_N0 1 2 5 B-
C400 0.01U_0402_16V7K 6
2 2 2 SATA_DTX_C_IRX_P0 SATA_DTX_IRX_P0 B+
1 2 7

1000P_0402_50V7K 10U_0805_10V4Z
SATA ODD Conn. <21> SATA_DTX_C_IRX_P0
C395 0.01U_0402_16V7K GND

Copy JIWA2 Symbol +3VS 8


9
V33
V33
10 V33
11 GND
JSATA2 12 GND
13 GND
1 GND +5VS 14 V5
SATA_ITX_C_DRX_P1 R374 2 1 0_0402_5% SATA_ITX_C_DRX_P1_R SATA_ITX_C_DRX_P1_R 2 15
15W@ SATA_ITX_C_DRX_N1_R A+ V5
3 A- 16 V5
SATA_ITX_C_DRX_N1 R375 2 1 0_0402_5% SATA_ITX_C_DRX_N1_R 4 17
15W@ SATA_DTX_IRX_N1_R GND GND
5 B- 18 Reserved
SATA_DTX_IRX_N1 R376 2 1 0_0402_5% SATA_DTX_IRX_N1_R SATA_DTX_IRX_P1_R 6 19
15W@ B+ GND
7 GND 20 V12
SATA_DTX_IRX_P1 R377 2 1 0_0402_5% SATA_DTX_IRX_P1_R 21 25
15W@ V12 GND
22 V12 GND 26
R378 1 @ 2 1K_0402_1% 8 DP FOX_LD2122H-S43_NR
+5VS_ODD 9 +5V
10 +5V
11 MD CONN@
12 GND 6/18 Change symbol from JHTXX by Ivan
13 GND (NEW)
OCTEK_SLS-13SB1G Change Library
4
Update Symbol 4

Update FootPrint from SP01000G800


+5VS +5VS_ODD
OCTEK_SLS-13SB1G_13P-T to FOX_LD2122H-S43_NR
1
R778
2
15W@ 0_1206_5%
OCTEK_SLS-13SB1G_13P_RV-T Manually update pin number
1 2
R779 15W@ 0_1206_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/05/15 Deciphered Date 2009/05/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 24 of 47
A B C D E F G H
5 4 3 2 1

+3VS

+3VS
C496 1 2 0.1U_0402_16V4Z
C448 1 2 0.1U_0402_16V4Z

Connecte to CPU

1
U32 U24

P
Vcc

NC
D R401 1 2 33_0402_5% 2 4 R414 1 2 33_0402_5% R391 1 2 33_0402_5% 2 4 R842 1 2 33_0402_5% DPRSTP_N_INV D
<20> SB_DPRSLPVR A Y PM_DPRSLPVR_D <46> <20> SB_DPRSLPVR A Y
NC 1

G
1 1 NL17SZ14DFT2G_SOT353-5
C464 NL17SZ17DFT2G_SOT353-5 C460

3
@ @
0.01U_0402_16V7K 0.01U_0402_16V7K
2 2
Use SA00001N400 FootPrint

R553 1 @ 2 0_0402_5%

+3VS 8/1 Rotate +1.05VS

R170 R171 R172

1
@ R157 R165

8/1 Rotate

1.05K_0402_1%

1.05K_0402_1%

200K_0402_5%

300_0402_5%

300_0402_5%
2

2
7/20 Reserved

8
C U10 C
U40

EN
DPRSTP_N_INV 1 6 H_DPRSTP# 7 2
A1 Y1 VREF2 VREF1
DPRSTP_N_INV 6 3
SCL2 SCL1 H_DPRSTP# <5,46>
2 GND VCC 5 +3VALW
H_DPSLP_N_LS 5 4
SDA2 SDA1 H_DPSLP# <5>

GND
H_DPSLP_N_LS 3 4 H_DPSLP#
A2 Y2
1
C173 PCA9306DCUR_VSSOP8

1
NC7WZ07P6X_NL_SC70-6 @ @
0.01U_0402_16V7K
2

+3VS +3VS

C450 1 2 0.1U_0402_16V4Z C458 1 2 0.1U_0402_16V4Z +3VS

1 2
B C446 0.1U_0402_16V4Z B
5

Use SA00001N400 FootPrint

5
U33
Vcc

2 4 1 2 2

P
<20> CPUSTP_N_OLD A Y B
R372 499_0402_1% 1 R371 33_0402_5% 4 H_DPSLP_N_LS
NC Y
G

U23 1 A

G
NL17SZ17DFT2G_SOT353-5
3

NC7SZ08P5X_NL_SC70-5

3
Vcc

1 2 2 A Y 4 1 2
R380 33_0402_5% 1 R379 33_0402_5%
NC
G

U31
1 1 NL17SZ17DFT2G_SOT353-5 +3VS
3

C447 C451
@ 1 2
100P_0402_50V8J 0.01U_0402_16V7K Use SA00001N400 FootPrint C452 0.1U_0402_16V4Z
2 2

5
U22
2

G Vcc
B CPUSTP#
Y 4 CPUSTP# <14>
1 A
NC7SZ32P5X_NL_SC70-5

3
A A

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2008/05/15 Deciphered Date 2009/05/15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Other
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 25 of 47
5 4 3 2 1
5 4 3 2 1

SD,MMC,MS muti-function pin define


MDIO SD Card MMC Card MS Card
PIN Name PIN Name PIN Name PIN Name
MS_CLK SD_CLK SP1
Change BOM control C796 R843 MODE_SEL

1
for 5158 and 5158E co-layout SP2 SDWP#

1
R857 R858
Michael 2008/6/18 @ @
1 SP3 SDCD#
C796 R843 10_0402_5% 10_0402_5%
SP4 SDCDAT1 MSWR

2
47P_0402_50V8J 10K_0402_5%

2
D 5158@ 2 5158@ 1 1 SP5 MSBS D
C812 C813
Add C823 C824 for 5158 and 5158E co-layout @ @ SP6 SDCDAT1 MSCDAT1
Michael 2008/6/18 10P_0402_50V8J 10P_0402_50V8J
2 2
+3VS
SP7 SDCDAT0 MSCDAT0
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 SP8 SDCDAT7 MSCDAT2
1 1 1 1 1 C797 C798 U41 SP9 MS_INS#
C799 1U_0603_10V4Z 0.1U_0402_16V4Z
C800 C801 C823 C824 AV_PLL 1 1
1 AV_PLL SP10 SDCDAT6 MSCDAT3
1U_0603_10V4Z 3 NC
2 2 2 2 2
7 NC SP11 SDCCLK MSCCLK
5158@ 5158@ +VCC_OUT 9 CARD_3V3
0.1U_0402_16V4Z 0.1U_0402_16V4Z 11 D3V3 SP12 SDCDAT5 MSCDAT6
33 D3V3 10 AV_PLL
VREG
MS_D4 22 SP13 SDCDAT4 MSCDAT7
NC 30
+3VS 1 R844 2 0_0603_5% +3V3_IN 8 3V3_IN SP14
CARD_RST# 44
@ MODE_SEL RST#
+3VALW 1 2 45 MODE_SEL SP15 SDCDAT3
R845 0_0603_5% 1 C803 CARD_XTLO 47 43
CARD_XTLI XTLO XD_CLE_SP19
48 XTLI XD_CE#_SP18 42 SP16 SDCDAT2
C802 0.1U_0402_16V4Z 41
+3VS USB20_N6 XD_ALE_SP17 SDDAT2_XDRE#
4.7U_0805_10V4Z
2 <21> USB20_N6 4 DM SD_DAT2/XD_RE#_SP16 40 SP17
<21> USB20_P6 USB20_P6 5 39 SDDAT3_XDWE#
DP SD_DAT3/XD_WE#_SP15
14 GPIO0 XD_RDY_SP14 38 SP18
1

SD_DAT4/XD_WP#/MS_D7_SP13 37
R846 35 R847 0_0402_5% SP19
SD_DAT5/XD_D0/MS_D6_SP12 SDCLK_MSCLK SD_CLK
C 100K_0402_5% Change C802 package from 0603 to 0805 SD_CLK/XD_D1/MS_CLK_SP11 34 1 2 C
Michael 2008/5/30 31 SDDAT6_MSD3 R848 0_0402_5%
R849 SD_DAT6/XD_D7/MS_D3_SP10
29 MS_INS# 1 2 MS_CLK
2

CARD_RST# MS_INS#_SP9 SDDAT7_MSD2


1 2 SD_DAT7/XD_D2/MS_D2_SP8 28
27 SDDAT0_MSD0
SD_DAT0/XD_D6/MS_D0_SP7
1

C804 0_0402_5% 26 SP6


SD_DAT1/XD_D3/MS_D1_SP6 MS_BS +3VS
XD_D5_SP5 25
@ R850 23 SP4
XD_D4/SD_DAT1_SP4 U42
1U_0603_10V4Z 499K_0402_1% 21 SD_CD#
SD_CD#_SP3 SD_WP CARD_EECS
20 8 1
2

SD_WP_SP2 VCC CS CARD_EESK


Change C804 package from 0402 to 0603 XD_CD#_SP1 19 1 7 NC SK 2
18 CARD_EEDI +3VS 6 3 CARD_EEDO
Change R850 part number EEDI NC DI
5158E@ C805 5 4 CARD_EEDI
Michael 2008/5/30 GND DO
2 RREF XTAL_CTR 13 1 2 0.1U_0402_16V4Z
R851 0_0402_5% 2
24

@
5158@ MS_D5 AT93C46-10SI-2.7_SO8
12 DGND
R852 32 15 CARD_EEDO @
Y5 DGND EEDO
1

0_0402_5% 16 CARD_EECS
CARD_XTLI 1 EECS
<14> CLK_48M_CR 1 2 2 CARD_XTLO R853 6 AGND EESK 17 CARD_EESK
6.19K_0402_1% 46 36 SD_CMD
5158E@ 12MHZ_16P_6X12000012 AGND SD_CMD
JREAD1
2

R854 +VCC_3IN1 6
5158@ R855 RTS5158E-GR_LQFP48_7X7 5158@ SDDAT0_MSD0 VDD_SD
Add R852 for 5158 and 9 DAT0_SD
5158E co-layout 0_0402_5% 5158E@ R873 0_0402_5% XDD4_SDDAT1 10
270K_0402_5% SP6 XDD4_SDDAT1 SDDAT2_XDRE# DAT1_SD
Michael 2008/6/18 1 1 1 2 2 DAT2_SD
SDDAT3_XDWE# 3
2

C806 C807 5158E@ SD_CLK CD/DAT3_SD


7 CLK_SD
6P_0402_50V8J 6P_0402_50V8J R874 0_0402_5% SD_WP 11
B 2 2 U41 SP4 XDD4_SDDAT1 SD_CMD WP_SD B
5158@ 5158@ 1 2 4 CMD_SD
SD_CD# 1 CD_SD
5 VSS_SD
8 VSS_SD
Add R873 R874 for 5158 and
+3VS 5158E co-layout
S IC RTS5158-GR LQFP 48P CARD READER SP6 19
Michael 2008/6/18 VCC_MS
13 VCC_MS
U43 +VCC_3IN1 5158@ MS_CLK 14
MS_INS# SCLK_MS
16 INS_MS
3 1 SDDAT0_MSD0 18
+VCC_OUT VIN VOUT +VCC_3IN1 MS_BS SDIO_MS
4 VIN/CE VOUT 5 20 BS_MS
SDDAT6_MSD3
1 R856 40mil 15 RESERVED_MS
1

1U_0603_10V4Z

C810 2 SDDAT7_MSD2 17
GND RESERVED_MS
1

R859 1 +VCC_OUT 1 2 21 VSS_MS


C811

10U_0805_10V4Z

0.1U_0402_16V4Z
100K_0402_5% 0.1U_0402_16V4Z RT9701-PB_SOT23-5 R860 12
@ 2 5158@ 5158E@ 0_0603_5% VSS_MS
5158@ 100K_0402_5% 1 1 22 GND
C808

@ 23
2

2 GND

C809
C822
2

4.7U_0805_10V4Z @ PROCO_MDR019-C0-1202
@ 2 2 CONN@

Add C822 4.7u and reserve C808 10u


A for cost down Michael 2008/5/30 A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/05/15 Deciphered Date 2009/05/15 Title
RTS5158E Cardreader
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 26 of 47
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/05/15 Deciphered Date 2009/05/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
None
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 27 of 47
5 4 3 2 1
5 4 3 2 1

+3VALW

T1

TPRX+ 1 16 RX+
TPRX- RD+ RX+ RX-
2 RD- RX- 15
R149 +3V_LAN +3V_LAN_AVDD PWFBOUT R33 0_0603_5% RCT 3 14 RXCT
+3V_LAN CT CT
Other CG use 1210 4 NC NC 13
0_0603_5% Other CG use 5 12
L6 TCT NC NC TXCT
1 6 CT CT 11
1 2 C56 TPTX+ 7 10 TX+
+3V_LAN FBM-L11-160808-601LMT_0603 TPTX- TD+ TX+ TX-
D 8 TD- TX- 9 D
1 1 1 1 0.1U_0402_16V4Z
C150 C149 C147 C102 2
350uH_NS0013LF
R350 1 2 1.5K_0402_1% MDIO 10U_0805_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2
R366 1 2 @ 4.7K_0402_5% ISOLATE

R152 1 2 @ 4.7K_0402_5% COL R30 0_0603_5% 7/20 Swap pin 1,2 to 7,8 and 16,15 to 10,9
R368 1 4.7K_0402_5% LED0
2 change T1 from SP050001210(BOTHHAND)to
Place L47, C460, C462, C463 as close to each power pin 1
R367 1 2 4.7K_0402_5% LED1
as possible.
C50 SP050001310(Lankcom)
R153 1 2 4.7K_0402_5% LED2 0.1U_0402_16V4Z
2
R154 1 2 4.7K_0402_5% LED3
+3V_LAN +3V_LAN
R364 1 2 4.7K_0402_5% LED4

R97 1 2 4.7K_0402_5% RXER

R354 1 2 4.7K_0402_5% CRS Other CG use 1206


1 1 L5
PWFBOUT 2 1 PWFBIN
C121 C122 FBM-L11-160808-601LMT_0603
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1
2 2 C95
C101 C153
C 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C
2 2 2
U8 +3V_LAN_AVDD
MDC 25 14
<20> MDC MDC DVDD33
<20> MDIO MDIO 26 48
TXD0 MDIO DVDD33
<20> TXD0 6 TXD0
TXD1 5 36 +3V_LAN Place C464, C465, L48 close to PWFBOUT and place C466 close to PWFBIN.
<20> TXD1 TXD1 AVDD33
TXD2 4
<20> TXD2 TXD2
TXD3 3 8/27 Change D7,D8 footprint from RLS4148_LL34-2 to LL34
<20> TXD3 TXD3
TXEN 2 32 PWFBOUT
PWR

<20> TXEN TXEN PWFBOUT


R156 1 2 33_0402_5% TXC 7 LED2 D3 2 1 RLS4148_LL34-2
MII I/F

<20> TXCLK TXC

1
R109 1 2 33_0402_5% RXD_V 22 8 PWFBIN
<20> RXDV RXDV PWFBIN
R117 1 2 33_0402_5% RXD_0 21 R362
<20> RXD0 RXD0
R122 1 2 33_0402_5% RXD_1 20 LED3 D4 2 1 RLS4148_LL34-2
<20> RXD1 RXD1
R129 1 2 33_0402_5% RXD_2 19 4.7K_0402_5%
<20> RXD2 RXD2
R135 1 2 33_0402_5% RXD_3 18 30 TPRX-
<20> RXD3

2
R138 1 33_0402_5% RXC RXD3 TPRX- TPRX+ D34
<20> RXCLK
R861 1
2
33_0402_5% COL_R
16 RXC TPRX+ 31 8/1 Change D7,D8 from SC1B751V010 to SC11N414880
<20> COL 2 1 COL 1 2
R862 1 2 33_0402_5% CRS_R 23 C435 1
Network I/F

<20> CRS CRS


R872 1 2 33_0402_5% RXER_R 24 3
<20> RXER RXER/FXEN
TPTX- 33
34
TPTX-
TPTX+ 2
0.1U_0402_16V4Z
PSOT24C_SOT23
Lan Conn.
R360 1 TPTX+
+3V_LAN 2 4.7K_0402_5% MII_SNIB 44 MII/SNIB
@
28 RTSET R351 1 2 2K_0402_1% 2 1 JP23
RTSET +3V_LAN C31 680P_0402_50V7K 12 Amber LED+ ACTIVITY LED
43 ISOLATE R361 1 2 4.7K_0402_5%
LAN_XTAL_IN ISOLATE RPTR R356 4.7K_0402_5% R12
46 X1 RPTR 40 1 2 1 2 150_0402_1% 11 Amber LED-
39 SPEED R353 1 2 4.7K_0402_5% 16
PHY/LED CLK

LAN_XTAL_OUT SPEED DUPLEX R123 4.7K_0402_5% R863 1 SHLD2


47 X2 DUPLEX 38 1 2 2 75_0402_5% 8 PR4-
B ANE R116 4.7K_0402_5% B
ANE 37 1 2 SHLD1 15
Y3 41 LDPS R357 1 2 4.7K_0402_5% R864 1 2 75_0402_5% 7
LDPS RESETB R363 PR4+
1 2 RESETB 42 1 2 0_0402_5%
R359 1 2 @ 0_0402_5% 8/1 Change R12 from 300ohm to 150ohm RX- 6
25MHZ_20PF_6X25000017 LED0 PCI_RST# <19,29,30,31,33> PR2-
9 PHYAD0/LED0 NC 27
LED1 10 R865 1 2 75_0402_5% 5
LED2 PHYAD1/LED1 PR3-
12 PHYAD2/LED2 DGND 11
LED3 13 17 R575 1 2 75_0402_5% 4
C115 C117 LED4 PHYAD3/LED3 DGND PR3+
15 45
GND

PHYAD4/LED4 DGND RX+


33P_0402_50V8J 33P_0402_50V8J AGND 29 For EMI => Change C31,C38 from SE071680J80 3 PR2+
35
AGND (68pF) to SE074681K80 (680pF) TX- 2 PR1-
RTL8201CL-VD-LF
8/30 Add L61 FBMA-L10-160808-800LMT_0603 for EMI TX+ SHLD2 14
1 PR1+
FBMA-L10-160808-800LMT_0603 13
LED0 R14 SHLD1
1 2 300_0402_5% L61 1 2 LINKLED# 10 Green LED-
7/30 modified from 27P to 33P D33
2 1 2 +3V_LAN 9 Green LED+ LINKLED
C38 680P_0402_50V7K 1
3 TYCO_3-440470-4
TPRX- R23 1 2 49.9_0402_1% <BOM Structure>
C41
PSOT24C_SOT23 C42
TPRX+ R26 1 2 49.9_0402_1% 1 2 0.1U_0402_16V4Z RXCT R34 1 2 75_0402_5% @ 1 2 LANGND
TXCT R29 1 2 75_0402_5%
1000P_1206_2KV7K 1 1
TPTX- R36 1 2 49.9_0402_1%
C60
C26 C27
TPTX+ R41 1 2 49.9_0402_1% 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/05/15 Deciphered Date 2009/05/15 Title
LED0 LED1 LED2 LED3 LED4 LAN RTL8201CL
Link Dupx 10Act 100Act COL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 28 of 47
5 4 3 2 1
A B C D E

1 1

Kill SWITCH
+3VALW

2
D21 +3VALW
DAN217_SC59

2
@
R461

1
100K_0402_5%

1
KILL_SW#
KILL_SW# <31>

3
1

3
01/22 change sw2 P/N DE100000300
SW2
1BS003-1211L_3P 11/23 Change SW2 to correct symbol (by Andy)
2 2

Mini-Express Card for WLAN


8/31Add R593 connect net WLAN_ACTIVE to JP22 pin3
+1.5VS +3VS
8/31Add R594 connect net BT_ACTIVE
*** to JP22 pin5 L68
JMIN2
<7,21,30> SB_PCIE_WAKE#
SB_PCIE_WAKE# 1 2 MINI_VCC 1 2
WLAN_ACTIVE R866 1 1 2
<33> WLAN_ACTIVE 2 0_0402_5% 3 3 4 4
BT_ACTIVE R867 1 2 0_0402_5% 5 6 KC FBM-L11-201209-221LMAT_0805
<33> BT_ACTIVE 5 6
W LAN_CLKREQ# 7 8
<14> WLAN_CLKREQ# 7 8
9 9 10 10
CLK_PCIE_WLAN# 11 12
3 <14> PCIE_CLK_WLAN# 11 12 3
CLK_PCIE_WLAN
<14> PCIE_CLK_WLAN 13
15
13 14 14
16
12/13 Add
15 16
17 17 18 18
19 20 MINI_RF_OFF#
19 20 PCI_RST#
21 21 22 22 PCI_RST# <19,28,30,31,33>
23 24 MINI_VCC
<20> PCIE_PTX_C_IRX_N0 23 24
<20> PCIE_PTX_C_IRX_P0 25 25 26 26
27 27 28 28
29 30 DCLK DCLK <14,30>
29 30 DDATA
<20> PCIE_ITX_C_PRX_N0 31 31 32 32 DDATA <14,30>
<20> PCIE_ITX_C_PRX_P0 33 33 34 34
35 35 36 36
37 37 38 38
MINI_VCC 39 40
39 40
41 41 42 42
43 44 WLAN_LED#
43 44 WLAN_LED# <37>
45 45 46 46
47 47 48 48
49 49 50 50
51 52 +3VS
51 52
53 54 R223
GND1 GND2
1 2 +3VS

1
FOX_AS0B226-S56N-7F 100K_0402_5% R462 Please place these caps between JMIN1 and JMIN2
ME@ @
10K_0402_5%
DCLK C757 1 2 @ 100P_0402_50V8J
2

MINI_RF_OFF# DDATA C758 1 2 @ 100P_0402_50V8J


1

D
4 +3VS +1.5VS Q45 2 RF_ON# 4
RF_ON# <31>
SSM3K7002FU_SC70-3 G
S
3

1 1 1 1 1 1
C206 C205 C199 C241 C207 C203

0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z


2 2 2 2 2 2 Security Classification
2008/05/15
Compal Secret Data
2009/05/15 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
Mini-Card/Kill SW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 29 of 47
A B C D E
A B C D E

New Card Socket (Left/TOP)


New Card Power Switch +3VS_CARD1

JAQ60
New Card
JEXP1

1 1 1 GND
C695 C696 <21> USB20_N2 USB20_N2 2
@ USB20_P2 USB_D-
<21> USB20_P2 3 USB_D+
+1.5VS 0.1U_0402_16V4Z 4.7U_0805_10V4Z CP_USB# 4
C694 U18 2 2 CPUSB#
40 mils 5 RSV
2 1 0.1U_0402_16V4Z 12 1.5Vin 1.5Vout 11 +1.5VS_CARD1 6 RSV
14 13 DCLK 7
1 +3VS 1.5Vin 1.5Vout <14,29> DCLK SMB_CLK 1
<14,29> DDATA DDATA 8
C689 +1.5VS_CARD1 SMB_DATA
60 mils +1.5VS_CARD1 9 +1.5V
2 1 0.1U_0402_16V4Z 2 3.3Vin 3.3Vout 3 +3VS_CARD1 10 +1.5V
4 5 SB_PCIE_WAKE# 11
3.3Vin 3.3Vout <7,21,29> SB_PCIE_WAKE# WAKE#
2 1 0.1U_0402_16V4Z 1 1 +3VALW_CARD1 12 +3.3VAUX
+3VALW C693 17 15 +3VALW_CARD1 40 mils C697 C698 PERST1# 13
AUX_IN AUX_OUT @ PERST#
+3VS_CARD1 14 +3.3V
PCI_RST# 6 19 0.1U_0402_16V4Z 4.7U_0805_10V4Z 15
<19,28,29,31,33> PCI_RST# SYSRST# OC# 2 2 +3.3V
EXP_CLKREQ# 16
<14> EXP_CLKREQ# CLKREQ#
SYSON 20 8 PERST1# CP_PE# 17
<31,39> SYSON SHDN# PERST# <20> CP_PE# CPPE#
PCIE_CLK_EXP# 18
<14> PCIE_CLK_EXP# REFCLK-
SUSP# 1 16 PCIE_CLK_EXP 19
<31,39,45> SUSP# STBY# NC <14> PCIE_CLK_EXP REFCLK+
20 GND
+3VALW 2 1 CP_PE# 10 7 PCIE_PTX_C_IRX_N1 21
CPPE# GND <20> PCIE_PTX_C_IRX_N1 PERn0
R635 100K_0402_5% PCIE_PTX_C_IRX_P1 22
+3VALW_CARD1 <20> PCIE_PTX_C_IRX_P1 PERp0
2 1 CP_USB# 9 23
R636 100K_0402_5% CPUSB# PCIE_ITX_C_PRX_N1 GND
<20> PCIE_ITX_C_PRX_N1 24 PETn0
18 PCIE_ITX_C_PRX_P1 25
RCLKEN <20> PCIE_ITX_C_PRX_P1 PETp0
26 GND
R5538D001-TR-F_QFN20_4X4~D 1 1
C699 C700 27 29
internal pull high to 3.3Vaux-in @ 28
GND1
GND2
GND3
GND4 30
0.1U_0402_16V4Z 4.7U_0805_10V4Z
EC need setting at Hi-Z & output Low 2 2 SANTA_130810-1
CONN@

Change to GMT PartNumber


Update FootPrint from
SANTA_13181060-5_26P-T to
2 2
SANTA_130810-1_26P

USB IO Conn.
+USB_VCCC

JP52
80 mils 1
2
USB20_N0 3
<21> USB20_N0 4
<21> USB20_P0 USB20_P0
5
6
7
USB20_N4 8
<21> USB20_N4 9
<21> USB20_P4 USB20_P4
10
11
12
13
150u 14
<21> USB20_N5 USB20_N5
ESR 0.9 ohm USB20_P5 15
<21> USB20_P5 16
Package(L*W*H)7.3*4.3*2.9
3 17 3
Rating 6.3V 18
19
20
ACES_85201-20051
+USB_VCCC
W=80mils
+USB_VCCC
1 1
1 C768
+ C564 C563
@ 10U_0805_10V4Z
150U_D_6.3VM 470P_0402_50V7K 2
2 2
11/29 change this symbol's footprint as
ADT7421ARMZ-REEL_MSOP8
+5VALW +USB_VCCC +3VALW
copy LM75CIMMX-3_MSOP8
footprint
2

R468
U26
1 8 10K_0402_5%
GND OUT R691 0_0402_5%
2 7
1

IN OUT
3 IN NC 6 2 1 USB_OC#45 <21>
1 4 EN# OC 5 USB_OC#06 <21>
C566
G545A2P8U MSOP 8P
4.7U_0805_10V4Z 1
2 C568
4 4
0.1U_0402_16V4Z
2 @
<31> USB2_ON#

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
NewCard & USB Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 30 of 47
A B C D E
5 4 3 2 1

+3VALW L28 20 mils +EC_DVCC


1 2 +EC_AVCC +3VALW
L29 1 2 FBM-11-160808-601-T_0603 FBM-11-160808-601-T_0603
+3VALW +EC_AVCC
2 1

1
C355 C363 1 1 1 1 1 1

0.1U_0402_16V4Z
C396

0.1U_0402_16V4Z
C417

0.1U_0402_16V4Z
C406

0.1U_0402_16V4Z
C386

1000P_0402_50V7K
C815

1000P_0402_50V7K
C359
20 mils R312
0.1U_0402_16V4Z 1000P_0402_50V7K RA@
1 2
1 ECAGND 2 Ra 100K_0402_5%
L27 FBM-11-160808-601-T_0603 2 2 2 2 2 2

2
MB_ID
20 mils

1
1

111
125
C356 R311

22
33
96

67
9
U21 14_A@
D
0.1U_0402_16V4Z
Rb 0_0402_5%
D

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
2
1 2

2
R342 0_0402_5%

D22 @ GATEA20 1 21 INVT_PWM


<20> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM <16>
KB_RST# 2 1 2 23 BEEP#
<20> KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# <35>
<20,33> SERIRQ SERIRQ 3 26
RB751V_SOD323 LPC_FRAME# SERIRQ# FANPWM1/GPIO12 ACOFF +5VS
<20,33> LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF <42>
C426 <20,33> LPC_AD3 LPC_AD3 5
@ LPC_AD2 LAD3 ECAGND TP_CLK R316 1
2 1 2 1 <20,33> LPC_AD2 7 LAD2 PWM Output 1 2 2 4.7K_0402_5%
R340 10_0402_5%<20,33> LPC_AD1 LPC_AD1 8 63 BATT_TEMP C816 0.01U_0402_16V7K
LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <41>
@ 22P_0402_50V8J LPC_AD0 BATT_OVP TP_DATA R315 1 2 4.7K_0402_5%
<20,33> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP <42>
ADP_I/AD2/GPIO3A 65 ADP_I <42>
CLK_PCI_EC 12 AD Input 66
<14> CLK_PCI_EC PCICLK AD3/GPIO3B
PCI_RST# 13 75 PCI_RST# R256 1 2 100K_0402_5%
<19,28,29,30,33> PCI_RST# PCIRST#/GPIO05 AD4/GPIO42
R331 1 2 EC_RST# 37 76 MB_ID
+3VALW ECRST# SELIO2#/AD5/GPIO43
47K_0402_5% EC_SCI# 20
<20> EC_SCI# SCI#/GPIO0E
1 <20> PM_CLKRUN# 1 @ 2 38 +3VALW
C391 R329 0_0402_5% CLKRUN#/GPIO1D DAC_BRIG
DAC_BRIG/DA0/GPIO3C 68 DAC_BRIG <16>
70 EN_FAN1
EN_DFAN1/DA1/GPIO3D EN_FAN1 <4>
0.1U_0402_16V4Z DA Output 71 IR EF
2 IREF/DA2/GPIO3E IREF <42>
KSI0 55 72 CHGVADJ P_USB# R64 2 1 10K_0402_5%
KSI0/GPIO30 DA3/GPIO3F CHGVADJ <42>
KSI1 56
KSI2 KSI1/GPIO31 TONTEK@ SM_KEY# R60
+3VALW 2 1 57 KSI2/GPIO32 2 1 10K_0402_5%
R347 10K_0402_5% KSI3 58 83 CLK_GUEST_R L53 1 <EMI> 2 0_0402_5% CLK_GUEST
KSI3/GPIO33 PSCLK1/GPIO4A CLK_GUEST <34>
1 2 EC_PME# KSI4 59 84 DATA_GUEST_R L54 1TONTEK@ 2 0_0402_5% DATA_GUEST +5VALW
<20> PCI_PME# KSI4/GPIO34 PSDAT1/GPIO4B DATA_GUEST <34>
R349 0_0402_5% KSI5 60 85 POWER_USB_LED# <EMI> TONTEK@
+5VALW KSI5/GPIO35 PSCLK2/GPIO4C POWER_USB_LED# <34>
KSI6 61 PS2 Interface 86 GPXOA02 R813 1 2 10K_0402_5%
C CYPRESS@ KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK C
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK <33>
1 2 EC_SMB_CK1 L57 1 <EMI> 2 0_0402_5% CLK_GUEST KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <33>
R317 4.7K_0402_5% CYPRESS@ KSO1 40 No stuff when use KB926C0 CLK_GUEST
EC_SMB_DA1 L58 1 <EMI> 2 0_0402_5% DATA_GUEST KSO2 KSO1/GPIO21
1 2 41 KSO2/GPIO22 KB926 SPI STRAP PIN
R3101 24.7K_0402_5% CLK_GUEST_R KSO3 42 97 R320 1 @ 2 10K_0402_5% DATA_GUEST
R711 10K_0402_5% KSO4 KSO3/GPIO23 SDICS#/GPXOA00
43 KSO4/GPIO24 SDICLK/GPXOA01 98 1 1
DATA_GUEST_R KSO5 GPXOA02 R812 1TONTEK@ 2 0_0402_5% ACK_GUEST C719 C720
R712
1 2
10K_0402_5% KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
SM_KEY# @ @
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 SM_KEY# <34>
1 2 ACK_GUEST_R KSO7 46 SPI Device Interface 22P_0402_50V8J 22P_0402_50V8J
R713 10K_0402_5% KSO[0..15] KSO8 KSO7/GPIO27 <EMI> 2 2 <EMI>
<32> KSO[0..15] 47 KSO8/GPIO28
KSO9 48 119 FRD#SPI_SO
KSI[0..7] KSO9/GPIO29 SPIDI/RD# FRD#SPI_SO <33>
KSO10 49 120 FWR#SPI_SI
<32> KSI[0..7] KSO10/GPIO2A SPIDO/WR#
ISP MODE SUPPORT KSO11 50 SPI Flash ROM SPICLK/GPIO58 126 SPI_CLK
KSO12 KSO11/GPIO2B FSEL#SPICS#
51 KSO12/GPIO2C SPICS# 128
2 @ 1 KSO3 KSO13 52
R327 4.7K_0402_5% KSO14 KSO13/GPIO2D AUX_PWRGD
53 KSO14/GPIO2E
KSO15 54 73 S3AUXSW# BEEP#
KSO15/GPIO2F CIR_RX/GPIO40 S3AUXSW# <8>
81 74 PSON# SYSON
KSO16/GPIO48 CIR_RLC_TX/GPIO41 PSON# <20>
+3VS 82 89 FSTCHG EC_SCI#
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <42>
90 CHARGE_LED0# EC_THERM#
BATT_CHGI_LED#/GPIO52 CHARGE_LED0# <37>
1 2 EC_SMB_CK2 91 CAPS_LED# SERIRQ
CAPS_LED#/GPIO53 CAPS_LED# <34>

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J
R309 4.7K_0402_5% <33,41> EC_SMB_CK1 EC_SMB_CK1 77 GPIO BATT_LOW_LED#/GPIO54 92 CHARGE_LED1#
SCL1/GPIO44 CHARGE_LED1# <37>
1 2 EC_SMB_DA2 <33,41> EC_SMB_DA1 EC_SMB_DA1 78 93 PWR_LED#
SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED# <34,37>
R308 4.7K_0402_5% 1 1 <4> EC_SMB_CK2 EC_SMB_CK2 79 SM Bus 95 SYSON
SCL2/GPIO46 SYSON/GPIO56 SYSON <30,39>
C357 C358 <4> EC_SMB_DA2 EC_SMB_DA2 80 121 VR_ON 1 1 1 1 1 1
SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <46>
@ @ 127 AC IN
AC_IN/GPIO59 ACIN <40,42>
100P_0402_50V8J 100P_0402_50V8J
2 2
+3VALW PM_SLP_S3# AUX_PWRGD 2 2 2 2 2 2
<20> PM_SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 AUX_PWRGD <9,20>
B PM_SLP_S5# EC_LID_OUT# B
<20> PM_SLP_S5# 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 EC_LID_OUT# <20>
1 @ 2 FRD#SPI_SO EC_SMI# 15 102 EC_ON C401 C416 C418
<20> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <34>
R325 100K_0402_1% ENE@ LID_SW# 16 103 C419 C360 C817
<34> LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06
CLK_GUEST L55 1 <EMI> 2 0_0402_5% ESB_CLK 17 104 SB_PWRGD
SUSP#/GPIO0B ICH_PWROK/GPXO06 SB_PWRGD <9,20>
1 @ 2 FSEL#SPICS# DATA_GUEST L56 1 <EMI> 2 0_0402_5% ESB_DAT 18 GPO 105 BKOFF#
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# <16>
R335 100K_0402_1% <34> P_USB# ENE@ P_USB# 19 GPIO 106 RF_ON# SB_PWRGD
EC_PME#/GPIO0D WL_OFF#/GPXO09 RF_ON# <29>
USB2_ON# 25 107 BT_ON# PBTN_OUT#
<30> USB2_ON# EC_THERM#/GPIO11 GPXO10 BT_ON# <33>
1 2 SUSP# FAN_SPEED1 28 108 EN_FAN1
<4> FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11
C413 @ 100P_0402_50V8J ACK_GUEST_R 29
EC_TX_P80_DATA FANFB2/GPIO15
<12,13> EC_TX_P80_DATA 30 EC_TX/GPIO16
EC_RX_P80_CLK 31 110 KILL_SW#
<12,13> EC_RX_P80_CLK EC_RX/GPIO17 PM_SLP_S4#/GPXID1 KILL_SW# <29>

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J
ON/OFF# 32 112 ENBKL_Q
<34> ON/OFF# ON_OFF/GPIO18 ENBKL/GPXID2
SM_KEY_LED# 34 114 EAPD
<34> SM_KEY_LED# PWR_LED#/GPIO19 GPXID3 EAPD <35,36>
NUM_LED# 36 GPI 115 EC_THERM#
<34> NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# <20>
CYPRESS@ 116 SUSP# 1 1 1
GPXID5 SUSP# <30,39,45>
ACK_GUEST 1 2 ACK_GUEST_R 117 PBTN_OUT#
<34> ACK_GUEST GPXID6 PBTN_OUT# <20>
R814 0_0402_5% 118 EC_PME#
XCLKI GPXID7
122 XCLK1
SPI_CS# FSEL#SPICS# XCLKO 2 2 2
<33> SPI_CS# 1 2 123 XCLK0 V18R 124
R341 0_0402_5% 2 +3VS R868 1 2 15K_0402_5% ENBKL_Q
AGND

SPI_CLK_R 1 2 SPI_CLK C415


GND
GND
GND
GND
GND

<33> SPI_CLK_R
R332 0_0402_5% C518 C361 C818

1
SPI_SI 1 2 FWR#SPI_SI XCLKI XCLKO 4.7U_0805_10V4Z C
<33> SPI_SI 1
R326 0_0402_5% KB926QFA1 LQFP 128P +3VALW R869 1 2 10K_0402_5% 2 Q40
11
24
35
94
113

69

B MMBT3904_SOT23 AC IN C389 1 2 100P_0402_50V8J


C820 C821 E
Use KB926C0

3
ECAGND
1

1
R546 C VR_ON C819 1 2 100P_0402_50V8J
12P_0402_50V8J 12P_0402_50V8J 1 2 2 Q39
OUT
IN

<18> ENBKL B ENBKL_Q C374 1 2 100P_0402_50V8J


A EC DEBUG PORT 47K_0402_5% E
MMBT3904_SOT23 A

3
JP61
NC

NC

+3VALW
EC_TX_P80_DATA
1
2
1 X2
Level Shift Circuit
2

EC_RX_P80_CLK 2 32.768KHZ_12.5P_1TJS125BJ2A251
3
4
3
4
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
ACES_85205-0400
Issued Date 2008/05/15 Deciphered Date 2009/05/15
ME@
EC_KB926
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Modify X2 part number from SJ132P7KW10 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
to SJ132P7K220 for cost down; Michael 2008/5/30 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 31 of 47
5 4 3 2 1
5 4 3 2 1

INT_KBD Conn.
KSI[0..7]
D For KSW91 For KSW01 KSO[0..15]
KSI[0..7] <31>
D
KSO[0..15] <31>
JP43 JP44
KSI1 1 KSI1 1
KSI7 2
1 KSI7 2
1 Delete C525~C548 SE071101J80 (100pF)
KSI6 2 KSI6 2
KSO9
3
4
3 KSO9
3
4
3 Add SI102101K80 (CP : 100pF)
4 4
KSI4
KSI5
5
6
5
KSI4
KSI5
5
6
5 (EMI Recommend)
KSO0 6 KSO0 6
7 7 7 7
KSI2 8 KSI2 8
KSI3 8 KSI3 8
9 9 9 9
KSO5 10 KSO5 10 CP1 <EMI> CP4 <EMI>
KSO1 10 KSO1 10 KSI4 KSO6
11 11 11 11 1 8 1 8
KSI0 12 KSI0 12 KSI5 2 7 KSO3 2 7
KSO2 12 KSO2 12 KSO0 KSO12
13 13 13 13 3 6 3 6
KSO4 14 KSO4 14 KSI2 4 5 KSO13 4 5
KSO7 14 KSO7 14
15 15 15 15
KSO8 16 KSO8 16 100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
KSO6 16 KSO6 16
17 17 17 17
KSO3 18 KSO3 18 CP2 <EMI> CP5 <EMI>
KSO12 18 KSO12 18 KSI1 KSI3
19 19 19 19 1 8 1 8
KSO13 20 KSO13 20 KSI7 2 7 KSO5 2 7
KSO14 20 KSO14 20 KSI6 KSO1
21 21 21 21 3 6 3 6
KSO11 22 KSO11 22 KSO9 4 5 KSI0 4 5
KSO10 22 KSO10 22
23 23 23 23
KSO15 24 KSO15 24 100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
24 24
25 25 25 25
C 27 27 CP3 <EMI> CP6 <EMI> C
GND GND KSO2 KSO14
GND 26 GND 26 1 8 1 8
KSO4 2 7 KSO11 2 7
ACES_88502-2501 ACES_88502-2501 KSO7 3 6 KSO10 3 6
CONN@ CONN@ KSO8 4 5 KSO15 4 5
100P_1206_8P4C_50V8 100P_1206_8P4C_50V8

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/05/15 Deciphered Date 2009/05/15 Title
KB /SW Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 32 of 47
5 4 3 2 1
+3VALW +5VALW

@ EEPROM_VCC
8M SPI ROM To TP/B Conn.
2 1
R301 0_0603_5%
JP12
2 @ 1 +3VALW 1
R302 0_0603_5% SWR# 1
2 2
SWL# 3
20mils TP_DATA 3
1 <31> TP_DATA 4 4
C108 U3 <31> TP_CLK TP_CLK 5 5
8 VCC VSS 4 +5VS 6 6
EEPROM_VCC 0.1U_0402_16V4Z 7
2 GND
3 W 8 GND
1 @ 2 EC_SMB_CK1 7 ACES_85201-06051
EC_SMB_CK1 <31,41> HOLD
R298 4.7K_0402_5%
1 @ 2 EC_SMB_DA1 EC_SMB_DA1 <31,41> SPI_CS# 1
<31> SPI_CS# S
R299 4.7K_0402_5% SWR#
SPI_CLK_R 6
<31> SPI_CLK_R C +5VS
SWL#
SPI_SI 5 2SPI_SO 2 1
<31> SPI_SI D Q FRD#SPI_SO <31>

3
R110 0_0402_5%
SST25LF080A_SO8-200mil C552
D25
@ 0.1U_0402_16V4Z
PSOT24C_SOT23

1
JP6
SPI_CS# 1 2 +3VALW
SPI_SO 1 2
3 3 4 4
SPI_CLK_R
Update Footprint
+3VALW 5 5 6 6
7 8 SPI_SI
7 8
E&T_2941-G08N-00E~D
ME@

14W Use 15W Use

Bluetooth Conn. SW4 SW5

6
5

6
5
Need to check BT pin definition again! SWL# SWL#
2 4 2 4
9/20 modified this block
Left Switch 1 3 Left Switch 1 3

SMT1-05_4P SMT1-05_4P
14W@ 15W@
+5VS
1

L39 <EMI>
R529 1 2 SW6 SW7
1 2

6
5

6
5
10K_0402_5% +BT_VCC SWR# 2 4 SWR# 2 4
4 3
2

4 3 JP42
BT_LED# WCM2012F2SF-121T04_0805
Right Switch 1 3 Right Switch 1 3
<37> BT_LED# 1 1
BT_ACTIVE @ 2 SMT1-05_4P SMT1-05_4P
<29> BT_ACTIVE 2
<21> USB20_P1 USB20_P1 1 <EMI> 2 USB20_R_P1 3 14W@ 15W@
3
1

D R638 1
<21> USB20_N1 USB20_N1 2 0_0402_5% USB20_R_N1 4 4
Q18 2 BTON_LED R639 <EMI> 0_0402_5% 5
G WLAN_ACTIVE 5
SSM3K7002FU_SC70-3 <29> WLAN_ACTIVE 6 6
S 7
3

7
1

8 8
9 GND1
R530 10
10K_0402_5% GND2
MOLEX_53780-0870
2

CONN@

FOR LPC DEBUG PORT


FOR LPC SIO DEBUG PORT
+3VS JP54
1 1 +5VS
2 2
3 3 +3VS
+3VALW 4
4
5 5
JP57 6
6 CLK_14M_SIO <14>
1 7 LPC_AD0
1 CLK_PCI_DB 7 LPC_AD1
1 2 2 CLK_PCI_DB <14> 8 8
C553 C554 3 9 LPC_AD2
3 LPC_AD0 9 LPC_AD3
4 4 LPC_AD0 <20,31> 10 10
0.1U_0402_16V4Z 1U_0603_10V4Z 5 LPC_AD1 LPC_AD1 <20,31> 11 LPC_FRAME#
5 11
3

2
S
6 LPC_AD2 LPC_AD2 <20,31> 12 LPC_DRQ0#
G 6 12 LPC_DRQ0# <20>
1 2 2 7 LPC_AD3 LPC_AD3 <20,31> 13 PCI_RST#
<31> BT_ON# 7 13
R531 100K_0402_5% Q19 8 LPC_FRAME# 14 2 @ 1
8 LPC_FRAME# <20,31> 14
SI2301BDS_SOT23 9 15 CLK_PCI_DB R467 10K_0402_5%
9 PCI_RST# 15 SERIRQ
D 10 10 PCI_RST# <19,28,29,30,31> 16 16 SERIRQ <20,31>
W=40mils 11 17
1

GND 17
+BT_VCC GND 12 1 18 18
19 19
1 ACES_85201-1005N C576 20
C557 C558 ME@ @ 20
@ 2 0.1U_0402_16V7K ACES_85201-2005
4.7U_0805_10V4Z 0.1U_0402_16V4Z ME@
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/05/15 Deciphered Date 2009/05/15 Title
BIOS, I/O Port & K/B Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 33 of 47
A B C D E

TOP Side
ON/OFF switch 2 1
12/4 Change D14 to correct symbols
J3 @ JOPEN
2 1
J4 @ JOPEN +3VALW
Bottom Side Power USB Board Conn.

2
R533

100K_0402_5%
+5VALW

1
1 D26 For EMC command 1
C7
2 ON/OFF# Michael Hsiao 2008/6/18
ON/OFF# <31>
ON/OFFBTN# 1 2 1
3 51_ON# 51_ON# <40>
0.1U_0402_16V4Z @
DAN202UT106_SC70-3 JP62
1
Power Button ON/OFFBTN#
D_P_USB#
2
1
2
3 3
PWR_LED# 4
<31,37> PWR_LED# 4

1
2 POWER_USB_LED# 5
<31> POWER_USB_LED# 5
C561 D27 6 6
7 GND
1000P_0402_50V7K RLZ20A_LL34 8
1 GND

2
ACES_85201-06051
SMT1-05_4P
SW3
A@
1 3ON/OFFBTN#

2 4

1
D
EC_ON 2 +3VALW
<31> EC_ON
6
5

G
2

1
R535 Q21
SSM3K7002FU_SC70-3 R659
10K_0402_5%
10/09 add for debug 10K_0402_5%
1

2
D67
2 P_USB# 2
2 P_USB# <31>
D_P_USB# 1
3 51_ON#
51_ON# <40>

Function Board Conn. DAN202UT106_SC70-3

+3VS R817 2 @ 1 0_0603_5%

+3VALW R816 2 @ 1 0_0603_5%

+5VS R805 2 @ 1 0_0603_5% +5V_SW

+5VALW R806 2 1 0_0603_5% For EMC command


C8 Michael Hsiao 2008/6/18
@
2 1

JP48
0.1U_0402_16V4Z 1 1
2 2
CLK_GUEST 3
<31> CLK_GUEST 3
DATA_GUEST 4
<31> DATA_GUEST 4
ACK_GUEST 5
<31> ACK_GUEST 5
SM_KEY# 6
<31> SM_KEY# 6
SM_KEY_LED# 7
<31> SM_KEY_LED# 7
8 8
CAPS_LED# 9
<31> CAPS_LED# 9
NUM_LED# 10
<31> NUM_LED# 10
D12 11 GND
12 GND
2 CLK_GUEST
3 ACES_85201-1005N 3
1
3 DATA_GUEST CONN@

PJSOT24C_SOT23-3
@ SINGLE INT MIC
ACK_GUEST C759 1 2 @ 100P_0402_50V8J
05/29 close to codec

R610
2 1
Lid Switch 0_0402_5%

D41 @
+MIC2_VREFO 2 1 1 2
R870 2.2K_0402_5%
RB751V_SOD323

JMIC2
1 MIC2 2 1 MIC2_R
1 MIC2_R <35>
+3VALW 1 2 +VCC_LID R537 1 2 100K_0402_5% 2 2 1 R871 0_0402_5%
R536 0_0402_5% 2 C675 220P_0402_50V7K 1
3 @ C677
GND
2

GND 4
D42 15P_0402_50V8J @
VDD

ACES_88231-02001 2 @ L64 1
4
MIC_GND PSOT05C-LF-T7 SOT-23-3 2
MBK1608121YZF_0603 4
1 @
C565 3 MIC@
OUTPUT LID_SW# <31>
1

0.1U_0402_16V4Z 2 R608 0_0603_5%


GND

2 C567 MIC_GND
U25 10P_0402_50V8J
GNDA
1

A3212ELHLT-T_SOT23W-3 1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/05/15 Deciphered Date 2009/05/15 Title
PWROK/LID/Front/IO Board
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 34 of 47
A B C D E
5 4 3 2 1

+3VS_DVDD

HD Audio Codec 10mil 1 1


L33 1 2
FBMA-L11-160808-800LMT_0603
+3VS
+VDDA

C570 C571

1
@
4.7U_0805_10V4Z R538
2 2 @
0.1U_0402_16V4Z 10K_0402_5%
+AVDD_AC97

2
L34
0.1U_0402_16V4Z 40mil R539 @ 0_0603_5% C572 1 2 0.1U_0402_16V4Z
+VDDA +3VS

1
D 0_0603_5% 1 1 1 1 D
C573 C574 C575 C577 R540
@ 10mil 1
C580
1
C581
10U_0805_10V4Z 100P_0402_50V8J @ 0_0402_5%
2 2 2 2 4.7U_0805_10V4Z EC Beep

2
2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 R541 2 1 R804 2 MONO_IN_1 1 2 MONO_IN
<31> BEEP#
10K_0402_5% 0_0402_5% C582 0.1U_0402_16V4Z

25

38

9
U27

1
C R542 1 @ 2

AVDD1

AVDD2

DVDD_IO
DVDD
<20> SB_SPKR 1 R543 2 2 Q22 2.4K_0402_5%
10K_0402_5% B @
E 2SC2411K_SOT23
PCI Beep

3
14 35 AMP_LEFT
NC LINE_OUT_L AMP_LEFT <36>
Need Update Footprint

1
15 36 AMP_RIGHT
NC LINE_OUT_R AMP_RIGHT <36>
R544 D28
C589 2.2U_0603_6.3V6K MIC2_C_L 16 39 AMP_LEFT_HP @
MIC2_L HP_OUT_L AMP_LEFT_HP <36>
10K_0402_5% CH751H-40PT_SOD323-2
1 2 MIC2_R_R C585 2.2U_0603_6.3V6K MIC2_C_R 17 41 AMP_RIGHT_HP 9/19 Realtek suggest
<34> MIC2_R AMP_RIGHT_HP <36>

2
R716 1K_0402_5% MIC2_R HP_OUT_R
Add bypass schematic.
23 LINE1_L NC 45

24 LINE1_R DMIC_CLK 46

18 CD_L NC 43
2/01 Let them floating
20 CD_R NC 44
C 19 C
CD_GND HDA_BITCLK_AUDIO
1 2 MIC1_R_L C591 2.2U_0603_6.3V6K MIC1_C_L 21
BIT_CLK 6 HDA_BITCLK_AUDIO <20> Sense Pin Impedance Codec Signals Funnction
<36> MIC1_L MIC1_L
R717 1K_0402_5%
MIC1_R_R C592 2.2U_0603_6.3V6K MIC1_C_R SDIN0 39.2K PORT-A (PIN 39, 41)
<36> MIC1_R 1
R718
2
1K_0402_5%
22 MIC1_R SDATA_IN 8 1
R545
2
33_0402_5%
HDA_SDIN0 <20> HP
C594 1 2 100P_0402_50V8J MONO_IN 12 37
@ PCBEEP MONO_OUT
20K PORT-B (PIN 21, 22) MIC
LINE1_VREFO 29 SENSE A / B
<20> HDA_RST_AUDIO# 11 RESET#
GPIO1 31 10K PORT-C (PIN 23, 24) LINE IN
<20> HDA_SYNC_AUDIO 10 SYNC
MIC1_VREFO_L 28 10mil +MIC1_VREFO_L
<20> HDA_SDOUT_AUDIO 5 SDATA_OUT 5.1K PORT-D (PIN 35, 36) LINE OUT
2
MIC1_VREFO_R 32 10mil +MIC1_VREFO_R
GPIO0
SENSE_A
3 GPIO3 MIC2_VREFO 30 10mil +MIC2_VREFO 39.2K PORT-E (PIN 14, 15) HP
SENSE_B
13
34
SENSE A
27 ACZ_VREF 10mil
SENSE B VREF
ACZ_JDREF
20K PORT-F (PIN 16, 17) MIC
<31,36> EAPD 47 EAPD JDREF 40 SENSE B

1
48 SPDIFO NC 33 1 1 10K PORT-G (PIN 43, 44) LINE IN
2

R548 C596 C597


R547 4 26
DVSS1 AVSS1 20K_0402_1% 10U_0805_10V4Z 100P_0402_50V8J
10_0402_5%
7 DVSS2 AVSS2 42
2 2 5.1K PORT-H (PIN 45, 46) LINE OUT

2
@ ALC268-GR_LQFP48
1

B
1 B
C598 DGND AGND
15P_0402_50V8J 5/29 Realtek suggest change P/N:SA00001GD10
2 @

SENSE FOR Ext. Mic. HDA_BITCLK_AUDIO

Regulator for CODEC


2

R549
1 2 SENSE_A
<36> MIC_SENSE
R550 20K_0402_1% 10_0402_5%
@
40mil
1

L36 U28 +VDDA


1 +5VS
60mil +5VS_VDDA 1 IN (Max output = 300 mA)
C599 5
0_0603_5% OUT
2
SENSE FOR Solo Int. Mic. 10P_0402_50V8J
2 @
C600
1 1
C601 GND
1 4.75V
3 4 C602
SHDN BYP
10U_0805_10V4Z 2 2 0.1U_0402_16V4Z G9191-475T1U_SOT23-5 1 4.7U_0805_10V4Z
@ C603 2 @

1 2 SENSE_B 0.01U_0402_16V7K
R551 20K_0402_1% 2
A A

Moat Bridge 10/2 change circuit


SENSE FOR HP U8 change footprint
2 1 SENSE_A 1 2
<36> HP_SENSE
R554 39.2K_0402_1% R555 0_0805_5% Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
1 2 Issued Date 2008/05/15 Deciphered Date 2009/05/15
R556 0_0805_5% <Title>
HD Audio Codec ALC268
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 35 of 47
5 4 3 2 1
A B C D E

+MIC1_VREFO_R

APA2057 SPK/HP Amplifier 10/2 U6 APA2057A P/N:SA00001QD00


+MIC1_VREFO_L

10mil 10mil MICROPHONE

1
+5VALW R557 R558
IN JACK
W=40mil 2.2K_0402_5% 2.2K_0402_5%
JP63

2
680P_0402_50V7K

0.1U_0402_16V4Z

10U_0805_10V4Z
1 1 2 MIC_SENSE 5
<35> MIC_SENSE
C604 C605 C606 C607
4 10
+3VALW 1U_0603_10V4Z 9
2 2 1 MIC1_R L47 1
<35> MIC1_R 2 <EMI> MIC1_R_1 3 8
1 KC FBM-L11-160808-121LMT 0603 1
6 7
MIC1_L L48 1 2 <EMI> MIC1_L_1 2
<35> MIC1_L
R560 @ 1.5K_0402_1% KC FBM-L11-160808-121LMT 0603

11

19

20
10
1 1 1

1
fo=1/(2*3.14*R*C)=106Hz 1 2 U29 C610 C611

3
R=1.5K / C= 1uF R562 @ 1.5K_0402_1% <EMI> <EMI> FOX_JA6333L-B3S0-7F~N

CVDD

HVDD

PVDD
PVDD

VDD
1 2 220P_0402_50V7K 220P_0402_50V7K CONN@
2 2
1 2 AMPR
<35> AMP_RIGHT
C609 1U_0603_10V4Z SPKR+
AMPL
3 INR_A ROUT+ 22
SPKR- @ RED
<35> AMP_LEFT 1 2 5 21
Trace width/spacing/other=8/6/50

1
C608 1U_0603_10V4Z INL_A ROUT- D29
R563 1 2 100K_0402_5% AMP_EN# 27 8 SPKL+ PSOT05C-LF-T7 SOT-23-3
/AMP EN LOUT+ SPKL- <EMI>
LOUT- 9
+5VS R564 1 @ 2 100K_0402_5% HP_EN 24 HP EN HP_R
HP_R 17
1 2 AMP_RHPIN 1 2 INR _H 4 18 HP_L
<35> AMP_RIGHT_HP INR_H HP_L
C612 4.7U_0805_10V4Z R565 39K_0402_5% 6
AMP_LHPIN INL_H INL_H
1 2 1 2
<35> AMP_LEFT_HP
C613 4.7U_0805_10V4Z R566 39K_0402_5% 26 /SD
10mil
AMP_SD# 15 CVSS
AMP_BEEP CVSS
1 2 1 2 1 2 28
R569 0_0402_5% C614 0.47U_0603_16V4Z R567 0_0402_5% BEEP
16
HEADPHONE
AMP_CP+ VSS
1 2 AMP_CP-
12
14
CP+
2
OUT JACK
CP- GND

1
C617 1U_0603_10V6K 23 C619
AMP_BIAS PGND 1U_0603_10V6K JP64
25 BIAS PGND 7
C618 2.2U_0603_6.3V6K 13 HP_SENSE 5
<35> HP_SENSE

2
CGND
2 1 GND 29
C620 0.1U_0402_16V4Z 4 10
APA2057A_TSSOP28 9
HP_R L49 1 2 <EMI> HPR 3 8
9/5 If implement AMP BEEP, Swap C641 and R524. KC FBM-L11-160808-121LMT 0603 6 7
2 IN_A Gain = 10dB (Internal Speaker) HP_L L50 1 2 <EMI> HPL 2 2
R524 change from 0 Ohm to 47K KC FBM-L11-160808-121LMT 0603 1
IN_H Gain = 0dB (Headphone)

1
1 1

3
R570 R568 C615 C616 FOX_JA6333L-B3S0-7F~N
@ @ <EMI> <EMI> CONN@
0_0402_5% 0_0402_5%
11/28 Modified to X5R 10P_0402_50V8J2 2 10P_0402_50V8J

2
11/28 Change to SE080105K80 @

1
D30
PSOT05C-LF-T7 SOT-23-3 GREEN
Trace width/spacing=15/9 <EMI>

Add below circuit for APA2057 gain tunning use


+5VALW

R571

10K_0402_1%
+3VALW
2

AMP_SD# R572 1 2 10K_0402_5% HP_EN


2

3 R573 3
1
1

1 C622
10K_0402_5% C621 R574
1

D 0.1U_0402_16V4Z
1

22K_0402_1% 2
2
G 0.01U_0402_16V7K 2
2

S
3
1

D
EAPD 2 1 2 Q23
<31,35> EAPD
R577 0_0402_5% G
Q24 S SSM3K7002FU_SC70-3 1/8 change JSPK1 following JAW91
3

SSM3K7002FU_SC70-3

JSPK1
Gain= 10dB SPKL- R580 1 2 <EMI> 0_0603_5% SPK_L1- 4 4 G2 6
SPKL+ R578 1 2 <EMI> 0_0603_5% SPK_L1+ 3 5
SPKR- R581 <EMI> 0_0603_5% SPK_R1- 3 G1
1 2 2 2
SPKR+ R579 1 2 <EMI> 0_0603_5% SPK_R1+ 1 1

20mil ACES_88266-04001
Gain (dB) Low (V) High (V) Recommended (V) Speaker Conn. CONN@

3
10 3.45 3.51 3.48 D31 D32
@ @
11 3.56 3.62 3.59 PSOT24C_SOT23 PSOT24C_SOT23
<EMI> <EMI>

1
4 4

12 3.68 3.73 3.70

13 3.80 3.85 3.82


+5VALW assume equal 5.1V
10 dB ---> 5.1 x 220 / 320 = 3.5 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title
AMP/VR/Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 36 of 47
A B C D E
MDC Conn.
Mount R710; Michael 2008/5/30

20mil
JMDC1 1 R710 2 0_0402_5% +3VS
Camera Conn +5VS R590 2 1 0_0603_5%

1 2 +VCC_MDC +5VALW R591 2 @ 1 0_0603_5%


HDA_SDOUT_MDC GND1 RES0
<20> HDA_SDOUT_MDC 3 IAC_SDATA_OUT RES1 4
5 6 +3V_MDC 1 R697 2 0_0402_5% +3VS
HDA_SYNC_MDC GND2 3.3V
<20> HDA_SYNC_MDC 7 IAC_SYNC GND3 8
SDIN1_MDC 9 10 1 1
HDA_RST_MDC# IAC_SDATA_IN GND4 HDA_BITCLK_MDC C627 C628
<20> HDA_RST_MDC# 11 IAC_RESET# IAC_BITCLK 12 HDA_BITCLK_MDC <20>
1
C629 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2

GND
GND
GND
GND
GND
GND
22P_0402_50V8J JP3
2 @ +5V_CAMERA 1
USB20_N7 R594 1 USB20_R_N7 1
<21> USB20_N7 2 0_0402_5% 2

13
14
15
16
17
18
USB20_P7 R595 1 2
<21> USB20_P7 2 0_0402_5% USB20_R_P7 3 3
4 4
Connector for MDC Rev1.5 5 5
@ 6 GND1
ACES_88018-124G 7
CONN@ WCM2012F2SF-121T04_0805 GND2
4 3 ACES_88266-05001
+VCC_MDC +3V_MDC 4 3 CAMCONN@

R593 1 2
HDA_SDIN1 SDIN1_MDC 1 2
<20> HDA_SDIN1 1 2
L42
1 1
33_0402_5% C746 C745

0.1U_0402_16V4Z 0.1U_0402_16V4Z
@ 2 2 @

Please add these caps close to JMDC1 as close as possible,

HDA_SDOUT_MDC C752 1 2 @ 100P_0402_50V8J

HDA_SYNC_MDC C753 1 2 @ 100P_0402_50V8J Finger Print board 1/05 Modified D3 to SCA00000A00 For EMI 2/1 change JP4 pin 6 to +5VS for LTT FP use
HDA_RST_MDC# C754 1 2 @ 100P_0402_50V8J

SDIN1_MDC C756
0208 Remove D3 , Add D55 (SC300000G00)
1 2 @ 100P_0402_50V8J
+5VS

@ C9
05/26 Change D36 from SC300000X00 to SC300000K00; D36 FP@
3 2 WCM2012F2SF-121T04_0805 1 2
Michael 2008/5/30 I/O I/O
4 4 3 3
0.1U_0402_16V4Z
4 VCC GND 1
1 2 @
PJLCR05 SOT143 1 2
05/30 Change R660,R596,R597,R598,R599,R600 to 820ohm for 15W@ L60 JP4
FP@
05/30 Add R660,R596,R597,R598,R599,R600 to 2kohm for 14W@; follow JHXXX <21> USB20_P3 USB20_P3 R640 10_0402_5%2USB20_R_P3
1
2
1
USB20_N3 2
<21> USB20_N3 1 2USB20_R_N3 3 3
R641 0_0402_5% FP@ 4
R660 R596 R597 R598 R599 R600 4
5 5
6
LED +3VS
7
8
6
GND
GND
1 1 ACES_85201-06051
2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% C630 C631 FPCONN@
14W@ 14W@ 14W@ 14W@ 14W@ 14W@
4.7U_0805_10V4Z 0.1U_0402_16V4Z
@ 2 2 FP@

R660 15W@
820_0402_5%
+5VS 1 2 2 1 LED4 SATA_LED# <21>
HT-191NB_BLUE_0603
R596 15W@
820_0402_5%
+5VALW 1 2 2 1 LED1 PWR_LED# <31,34>
HT-191NB_BLUE_0603

R597 15W@ HT-191UD_AMBER_0603


820_0402_5% Amber
+5VALW 1 2 2 1 LED6 CHARGE_LED0# <31>
R598 15W@ Blue
+5VALW 1 2 2 1 LED7 CHARGE_LED1# <31>
820_0402_5%

HT-191NB_BLUE_0603

R599 15W@ HT-191UD_AMBER_0603


820_0402_5% Amber
+3VS 1 2 2 1 LED5 WLAN_LED# <29>
R600 15W@ Blue
+5VS 1 2 2 1 LED3 BT_LED# <33>
820_0402_5%

HT-191NB_BLUE_0603 Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/05/15 Deciphered Date 2009/05/15 Title
LED/MDC/CAMERA
12/7 Modified LED footprint to LED_HT-297UD-CB_4P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
12/15 Modified to correct LED symbol! B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 37 of 47
11/27 Add screw for layout request

H1 H2 H3 H4 H5 H6 H7 H8 H10 H11 H12 H13 H14


HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

H_3P0
1

1
H22 H23 H26
HOLEA HOLEA HOLEA
H_3P7
1

H28 H29 H30 H31


HOLEA HOLEA HOLEA HOLEA
H_4P2
1

2/22 change these from H_3P7 to H_3P8


H9 H21 H27 H32
HOLEA HOLEA HOLEA HOLEA
1

2/22 change these from H_3P2 to H_3P3 FD1 FD2 FD3 FD4 FD5 FD6

H15 H16 H19 H20


HOLEA HOLEA HOLEA HOLEA @ @ @ @ @ @

1
1

M1 M2
HOLEA HOLEA
1

H_5P0X3P2N H_5P0X3P2N

M3 M4 M5
HOLEA HOLEA HOLEA

11/27 Add screw for layout request


1

H_5P2X3P2N H_3P1N-* H_5P0X3P2N

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/05/15 Deciphered Date 2009/05/15 Title
FAN & Screw Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JFWXX M/B LA-3961P Schematic
Date: Friday, August 01, 2008 Sheet 38 of 47
A B C D E

1 +5VALW TO +5VS +1.8VALW TO +1.8V +1.8VALW to +1.8VS 1

+5VALW +5VS +1.8VALW +1.8V +1.8VALW +1.8VS

U13 U17 U15


8 D S 1 8 D S 1 8 D S 1
7 D S 2 7 D S 2 7 D S 2 1 1

2
6 3 1 1 6 3 1 1 6 3 C330 C342
D S C344 C334 R295 D S C340 C329 R294 D S @ R293
1 1 5 D G 4 1 1 5 D G 4 1 1 5 D G 4
C335 C345 @ @ C324 C341 @ @ C322 C337 10U_0805_10V4Z @
@ @ AO4468_SO8 10U_0805_10V4Z 470_0603_5% @ @ AO4468_SO8 10U_0805_10V4Z 470_0603_5% @ @ AO4468_SO8 2 2
1U_0603_10V4Z 470_0603_5%
10U_0805_10V4Z 2 2
1U_0603_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 2 2
1U_0603_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z

1 1

1
2 2
10U_0805_10V4Z 2 2 2 2
D

6
Q52A 2 SYSON# Q53A
@ G @
S Q46

3
+VSB 5VS_GATE 2 SUSP +VSB 1 2 1.8V_GATE SSM3K7002FU_SC70-3 +VSB 2 1 1.8VS_GATE 2N7002DW-T/R7_SOT363-6 2 SUSP
R288 R286 R284
33K_0402_5% 1 2N7002DW-T/R7_SOT363-6 47K_0402_5% 1 47K_0402_5% 1

1
1

1
D C323 D C318 C319

1
SUSP SYSON# D
2 2 Change Q46 package from SOT23
G 0.1U_0603_25V7K G 0.1U_0603_25V7K to SC70-3; Michael 2008/5/30 SUSP 2 0.1U_0603_25V7K
Q48 S 2 Q49 S 2 G 2
3

3
SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 Q15 S

3
SSM3K7002FU_SC70-3

Change Q48 package from SOT23 Change Q49 package from SOT23
to SC70-3; Michael 2008/5/30 to SC70-3; Michael 2008/5/30 Change Q15 package from SOT23
to SC70-3; Michael 2008/5/30
2 2
Change Q25 Q50 package from SOT23
+3VALW TO +3VS to Q52A Q52B SOT363-6; Michael 2008/5/30 +1.2VALW TO +1.2VS
+3VALW +3VS +1.2VALW +1.2VS

U16 U14
8 D S 1 8 D S 1
7 D S 2 7 D S 2 Change Q47 Q51 package from SOT23
2

2
6 D S 3 1 1 6 D S 3 1 1 to Q53A Q53B SOT363-6; Michael 2008/5/30
1 1 5 4 C331 C343 R292 1 1 5 4 C327 C338 R290
C339 C325 D G @ @ C336 C321 D G @ @
@ @ AO4468_SO8 10U_0805_10V4Z 470_0603_5% @ @ AO4468_SO8 10U_0805_10V4Z 470_0603_5% +5VALW
10U_0805_10V4Z 10U_0805_10V4Z 2 2
1U_0603_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 2 2
1U_0603_10V4Z
3 1

3 1
2 2 2 2

2
Q52B Q53B
@ @ R285

5 SUSP 5 SUSP 100K_0402_5%


+VSB 1 2 3VS_GATE +VSB 1 2 1.2VS_GATE

1
R287 2N7002DW-T/R7_SOT363-6 R283 2N7002DW-T/R7_SOT363-6
4

4
47K_0402_5% 1 47K_0402_5% 1 SYSON#
1

1
D C320 D C317

1
SUSP SUSP D SSM3K7002FU_SC70-3
2 2
G 0.1U_0603_25V7K G 0.1U_0603_25V7K SYSON 2
2 2 <30,31> SYSON
Q17 S Q16 S G Q14
3

3
SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 S

3
1
R281

Change Q17 package from SOT23 Change Q16 package from SOT23 10K_0402_5%
3 3
to SC70-3; Michael 2008/5/30 to SC70-3; Michael 2008/5/30

2
Change Q13 Q14 package from
SOT23 to SC70-3; Michael 2008/5/30

+5VALW
7/24 Change R281 from 100K to 10K
+1.5VS +1.05VS +0.9VS

2
R278
2

R289 R280 R296 100K_0402_5%


470_0603_5% 470_0603_5% 470_0603_5%

1
@ @ @ SUSP
SUSP <45>
1

Q20 Q12 Q26

1
D SSM3K7002FU_SC70-3
1

D SSM3K7002FU_SC70-3 D SSM3K7002FU_SC70-3 D SSM3K7002FU_SC70-3


<30,31,45> SUSP# 2
2 SUSP 2 SUSP 2 SUSP G Q13 1
G G G S C316

3
1
S @ S @ S @
3

R282 100P_0402_50V8J
2
10K_0402_5%

2
Change Q20 Q12 Q26 package from SOT23 to SC70-3; Michael 2008/5/30

4 4

3/14 Change R16 from 100K to 10K

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/05/15 Deciphered Date 2009/05/15 Title
DC Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSWXX M/B LA-4611P Schematic
Date: Friday, August 01, 2008 Sheet 39 of 47
A B C D E
A B C D

DC301001Y00
PL1 VIN
@ SINGA_2DW-0268-B16 ADPIN HCB4532KF-800T90_1812
1 1 1 2
2 2
3 3

0.022U_0603_50V7K
4 4

0.01U_0402_50V7K

0.01U_0402_50V7K

0.022U_0603_50V7K
2200P_0402_50V7K
PJP1

1
PC142
PC1

PC2

PC3

PC4
1 1

2
PR2 PC5
@ 10K_0402_1% @ 0.01U_0402_25V7K
1 2 1 2
VS
PR3
VIN 1M_0402_1%
1 2

10K_0402_1%
1
84.5K_0402_1%
1

VS

PR5
PR4

PR6

8
10K_0402_1%
1 2 5

P
ACIN <31,42>

2
PR7 +
7
2

22K_0402_1%
8 O
- 6

G
1 2 3 PU2B
P

+ LM393DG_SO8
1

4
O
1000P_0603_50V7K

20K_0402_1%

2 -
1

G
0.1U_0402_16V7K

RLZ4.3B_LL34

10K_0402_1%
PU2A
1

1
PR8

LM393DG_SO8
4
PC6

PC7

PR9
2
Vin Detector 2

PD2
2

2
2

PR10

2
10K_0402_1%
2 1
High 18.764 17.901 17.063
RTCVREF
3.3V Low 17.745 16.9 16.03

VIN

2
PD3

RLS4148_LL34-2

1
PD4
2 1
3.3V BATT+

1
68_1206_5%

68_1206_5%
RTCVREF

PR11

PR12
RLS4148_LL34-2
G920AT24U_SOT89-3 VS
PR13
560_0603_5% PR14 PU3 PR15

2
560_0603_5% 200_0805_5%
1 2 1 2 3 2 2 1 CHGRTCP 3 1
OUT IN
0.22U_1206_25V7K
1

PC9

0.1U_0603_25V7K
4.7U_0805_10V4Z

1U_0805_25V4Z

3 +CHGRTC 3
1

GND
PC8

100K_0402_1%

1
PR16

PC10

PC11
2

1
2

PR17
2

22K_0402_1%
<34> 51_ON# 1 2
PQ1
TP0610K-T1-E3_SOT23-3

PJ2 PJ1 PAD-OPEN 3x3m PJ17 PAD-OPEN 3x3m


PAD-OPEN 3x3m 1 2 +1.8VALW 1 2 +1.5VS
+1.8VALWP +1.5VSP
1 2 +5VALW PJ14 PAD-OPEN 3x3m
+5VALWP
+1.05VSP_LDO 1 2
(8.5A,340mils ,Via NO.= 17) (2A,80mils ,Via NO.= 4)
(7A,280mils ,Via NO.= 14) PJ3
PAD-OPEN 3x3m PJ4 PAD-OPEN 3x3m
PJ5 1 2 +0.9VS 1 2 +1.05VS
+0.9VSP +1.05VSP
PAD-OPEN 3x3m
+3VALWP 1 2 +3VALW
(3A,120mils ,Via NO.= 6)
(2A,80mils ,Via NO.= 4)
(5A,200mils ,Via NO.=10)
4 PJ7 4

PJ6
PAD-OPEN 3x3m PAD-OPEN 3x3m
+1.2VALWP 1 2 +1.2VALW +VSBP 1 2 +VSB

(4A,160mils ,Via NO.=8) (0.3A,40mils ,Via NO.= 2) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/DECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 01, 2008 Sheet 40 of 47
A B C D
A B C D

BATT++ PJ8
DC040003600 PAD-OPEN 3x3m
1 2 BATT+

PJP2
PH1 under CPU botten side :
BATT++
1 1
2
1 2 +3VALWP CPU thermal protection at 89 degree C
2

1000P_0402_50V7K

1000P_0402_50V7K
CNT1 PR19 @ PR18
3 3 Recovery at 70 degree C

0.01U_0402_50V7K
4 CNT2 1 2 100K_0402_5%
4 +3VALWP

1
1 5 EC_SMCA VS 1
5

1
PC12

PC13

PC14
6 EC_SMDA @ 100K_0402_5%
6 TS_A
7

2
7

2
VL

0.1U_0603_25V7K
1K_0402_1%
8 GND

2
8

2
VL

PR21
9 9

PC15
G1 10

150K_0402_1%
G2 11 PR20

2
10K_0402_1%
1K_0402_1%

2
1

PR23
SUYIN_200275MR009G180ZR

PR22
<BOM Structure> PR24
1 442K_0603_1%
2

1
2
100_0402_1%
PR27
1

8
100_0402_1%
78.7K_0603_1% PU4A
PD5
PR25

PR26
1 2 3 +

P
0 1 1 2 MAINPWON <43>
TM_REF1 2 -

G
100K_0603_1%_TH11-4H104FT
2

1SS355TE-17_SOD323-2

1
LM358ADR_SO8

4
<BOM Structure> <BOM Structure>

PH1
1000P_0402_50V7K
EC_SMB_CK1 <31,33>

1U_0603_6.3V6M
2
1

PC16
EC_SMB_DA1 <31,33>

PC17
PR28
2 150K_0402_1%
1 VL

2
1 2 +3VALWP
2 2

150K_0402_1%
PR29

1
1K_0402_1%

6.49K_0402_1%
1

PR31
PR30

2
2

BATT_TEMP <31>

PQ2
TP0610K-T1-E3_SOT23-3

B+ 3 1 +VSBP
0.22U_1206_25V7K

0.1U_0603_25V7K
1

100K_0402_1%

1
PR32

PC18

PC19
2

PR33
2

22K_0402_1%
VL 1 2
3 3
10K_0402_1%
2
PR34

PR35
1

0_0402_5% D
1 2 2 PQ3
<43,44> SPOK
G SSM3K7002F_SC59-3
0.1U_0402_16V7K

S
3
1

PC20
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN. / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 01, 2008 Sheet 41 of 47
A B C D
A B C D

65W, Iadapter=0~3.42A, Current sense=0.015ohm, PR45=110K, CP=3.175A


90W, Iadapter=0~4.74A, Current Sense=0.015ohm, PR45=54.9K, CP=4.303A B+

AO4407_SO8
PQ5
PQ4
AO4407_SO8
VIN 8 1 1 8 PR36 PC23 PL11
7 2 2 7 0.015_2512_1% 10U_1206_25V6M FBMA-L11-453215-121LMA90T_2
6 3 3 6 1 4 1 2

1
1 1

5 5

2
10U_1206_25V6M
2 3 PR38
1

2
PC145 PC21 100K_0402_1%

4
0.01U_0402_25V7K

PC24
PR37 2200P_0402_50V7K 0.01U_0402_25V7K

CHGEN#

1
2

100K_0402_1%
3.3_1210_5%

2
1
PC22 PC27

5
6
7
8

3
2
1
PC26

PR39
0.01U_0603_50V7K 0.1U_0402_16V7K PU5 PC28
2

1
1 2 1 28 CHG_PVCC 1 2 PQ7
CHGEN PVCC AO4407_SO8

1
1

1
PR40 0.1U_0805_25V7K BATDRV# 4

2
PR43 PC29 PC30 2.2_0603_5% PQ6
3.3_1210_5% 0.1U_0603_25V7K @0.1U_0603_25V7K 27 1 2 4 AO4466_SO8

2
BTST

2
PR41
2

340K_0402_1% A CN 2 26 1 PR181 2
ACP ACN HIDRV
3

3
2
1

5
6
7
8
ACP 0_0603_5% PR44

1
1

ACDRV 4 25 PL2 0.02_2512_1%


ACDRV PH
1

@ PD6 ACDET 5 PD7 10UH_SIL1045RA-100PF_4.5A_30% BATT+


PC31 ACDET
2 1 1 2 1 2 1 4

10U_1206_25V6M
<BOM Structure>
RLZ24B_LL34 2.2U_0805_25V6K
2

10U_1206_25V6M
REGN
RLS4148_LL34-2 PC32 2 3
2

2 PR45 0.1U_0603_25V7K PR46

5
6
7
8

PC34
PR42 110K_0402_1% 4.7_1206_5%

PC33
54.9K_0402_1% 1 2 ACSET 6
VREF ACSET <BOM Structure>
24 PQ8

2
REGN

1
1

1
PR47 PC36 AO4466_SO8
PC35 100K_0402_1% 1U_0603_10V6K 4

1
@ 0.01U_0402_25V7K

2
2

PC37

2
2
1 2 7 ACOP 680P_0603_50V7K 2

2
PR48 PC38 23

3
2
1
340K_0402_1% 0.47U_0603_16V7K LODRV
Icharge=(Vsrset/Vvdac)*(0.1/PR44)
CP setting
1

PGND 22
Iadapter=(Vacset/Vvdac)*(0.1/PR36) OVPSET 8 PC39
OVPSET 0.1U_0402_16V7K
Input OVP : 22.3V 1 2
9 AGND LEARN 21 ACOFF <31>
2

Input UVP : 17.26V

1
PR49
Fsw : 300KHz 54.9K_0402_1% VREF=3.3V PR50
PC40 PC41
VREF 20 1 2 0.1U_0603_25V7K @0.1U_0603_25V7K

2
CELLS
1

10 VREF 0_0402_5%
VREF VREF PR51
3

1
100K_0402_1% PC42
PR178 1U_0603_10V6K
1

200K_0402_1% 19 SE_CHG+
1

2
SRP
1

PR179 2 11 18 SE_CHG-
100K_0402_1% PQ9 VDAC SRN
17
2

BAT
1

D SI2301BDS-T1-E3_SOT23-3
2

1
2 PC43 VADJ 12
G 0.1U_0603_25V7K VADJ PC44
2

1
1

PC141 D ACSET 0.1U_0603_25V7K


S
3

2
ACOFF 1 2 2 PQ31 29
G RHU002N06_SOT323-3 ACGOOD# TP
S PQ30
13 ACGOOD ICHG setting
3
1

0.1U_0402_16V7K PR53
PR180 RHU002N06_SOT323-3 16 2 1
3
SRSET IREF <31> 3
340K_0402_1% BATDRV# 14 49.9K_0402_1%
BATDRV

1
PR55
2

15 1 2 100K_0402_1% PC45
IADAPT @0.01U_0402_25V7K

2
BQ24751ARHDR_QFN28_5X5 PR54

2
REGN 10_0603_5%

1
1

PC46
PR56 100P_0402_50V8J

2
0_0402_5% <31> ADP_I
IREF Current
PR57
2

OVP voltage : 1 2 VADJ 2.968V 3A VREF


BATT+ <31> CHGVADJ
LI-3S :13.50V--BATT-OVP=1.5V VS
@ 4.3K_0402_5%

2
VREF
BATT-OVP=0.111*BATT+
1

RTCVREF PR58
1

PC140 100K_0402_1%

2
PR59 CHGVADJ Per Cell @1000P_0402_50V7K
2
0.01U_0402_25V7K

340K_0402_1% PR61

1
2

3.3V 4.35V @ 100K_0402_1% CHGEN#


2
1

PC47

PR52

1
D
1

100K_0402_1% 2 PQ10
ACIN <31,40> <31> FSTCHG
2

PR62 0V 4V PR60 G RHU002N06_SOT323-3


2

1
499K_0402_1% @ 10K_0402_5% D
S

3
ACGOOD# 2 PQ11
8

4
PR63 PU4B G @ SSM3K7002F_SC59-3 4
2

10K_0402_1% 5 S
P

+
<31> BATT_OVP 1 2 7 0
0.01U_0402_25V7K

- 6
G

LM358ADR_SO8
4
1

1
PC48

<BOM Structure> PR64 PC49


105K_0402_1% 0.01U_0402_25V7K
@ Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2006/05/18 Deciphered Date 2007/05/18 Title


2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
CHARGER
Date: Friday, August 01, 2008 Sheet 42 of 47
A B C D
A B C D

ISL6237_B+
ISL6237_B+
B+
PR65
PJ10 PAD-OPEN 3x3m
1 2 1 2

4.7U_1206_25V6K

2200P_0402_50V7K

2200P_0402_50V7K
0_0603_5%

2200P_0402_50V7K

5
6
7
8

4.7U_1206_25V6K

4.7U_1206_25V6K
PQ12

1
PC50

PC51
PQ13

8
7
6
5

1
AO4466_SO8

PC150

PC54
1
VL AO4466_SO8 1

PC52

PC53
2

1U_0603_10V6K

2
2
PC55 4

4.7U_0805_6.3V6K
0.1U_0603_25V7K

1
PC56
4

PC57
1
+5VALWP

3
2
1
1
2
3
PL4

7
PL3 PU6 PC58 2 1
1 2 1U_0603_10V6K 4.7UH_SIL104R-4R7PF_5.7A_30%

LDO
VIN

VCC
+3VALWP 4.7UH_SIL104R-4R7PF_5.7A_30% 33 19 1 2
TP PVCC

2.2_1206_5%
1

8
7
6
5

5
6
7
8
2.2_1206_5%
DH3 26 15 DH5
UGATE2 UGATE1

@ PR67

@ PR69
PR66 PR68
220U_6.3V_M

0_0402_5%
2 1 BST3A 24 BOOT2 BOOT1 17 BST5A 2 1
2

1 0_0603_5%

1 2
2

2
PR70

61.9K_0402_1%
PC60 0_0603_5% PC61

220U_6.3V_M
+ 4 0.1U_0603_25V7K 4

2
680P_0603_50V8J
PC59

0.1U_0603_25V7K

1
1
680P_0603_50V8J

PC63

@ PR71
LX3 25 16 LX5 1
1

2
2 PHASE2 PHASE1

PC62

PC64
+
Rds=18mOHM

1
2
3

3
2
1
DL3 23 18 DL5 @

1
@ LGATE2 LGATE1
PQ15 2
AO4712_SO8 22 PQ14
PGND

2
FB3 AO4712_SO8
2 30 OUT2 Rds=18mOHM 2

PR72
0_0402_5%
10K_0402_1%

OUT1 10
2

VL 32 REFIN2
PR74

1
11 FB5
2VREF_ISL6237 FB1
1

@ 1 2 1 REF VFB=0.7V
PC65 0.22U_0603_10V7K
BYP 9
8 LDOREFIN @ PR75 0_0402_5%
SKIP 29 2 1 VL
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical) PR76 0_0402_5%
1 2
PZD1 20 28
RLZ5.1B_LL34 PR77 NC POK2
100K_0402_1%
3.3VALWP VS
1 2 1 2 4 13
SPOK <41,44>
EN_LDO POK1 PR79
Imax=5.59A
2
200K_0402_5%

301K_0402_1%
2

Ipeak=7.85A
PR78

PC66 14 12 ILM1 2 1
0.22U_0603_25V7K EN1 ILIM1
Iocp=10.133A PR80
1

27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2

NC
2
3 301K_0402_1% 3

0_0402_5%
PR81 ISL6237IRZ-T_QFN32_5X5

21
@ 0_0402_5%

PR82
1

2VREF_ISL6237
1
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)

1
PR84
<41> MAINPWON

2
PR85 0_0402_5%
0_0402_5%
5VALWP

2
2 1 1 2 Imax=4.9A
2

PC139

2VREF_ISL6237
@ PR86 1U_0603_10V6K Ipeak=7A
47K_0402_1%
Iocp=10.146A
0.047U_0603_16V7K

0.047U_0402_16V7K
1

1
PC67

PC68

1 3
2

@
PQ29
TP0610K-T1-E3_SOT23-3

PD8
1 2

1SS355TE-17_SOD323-2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 01, 2008 Sheet 43 of 47
A B C D
5 4 3 2 1

PR83 PR87 PR99 PR97


44.2K_0402_1% 75K_0402_1% 75K_0402_1% 107K_0402_1%

+1.2VALWP 1 2 1 2 2 1 2 1 +1.8VALWP

D D

51124_B+

2
PR89 51124_B+

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
0_0402_5%
PJ11
1 1 2 2 B+

1
PC83

PC75

1
1
@ JUMP_43X118

PC77
2

4.7U_1206_25V6K

4.7U_1206_25V6K

2200P_0402_50V7K
8
7
6
5

5
6
7
8

1
PC85

PC70
PU7 PQ17

1
GND
VO2

VFB2

TONSEL

VFB1

VO1

PC71
PQ16 25 AO4466_SO8

2
AO4466_SO8 P PAD

2
4 7 PGOOD2 PGOOD1 24 4
PC81
PC69 PR88 8 23 PR95
EN2 EN1 0.1U_0402_16V7K
0.1U_0402_16V7K 2.2_0603_5% 2.2_0603_5%
1 2 1 2 1 BST_1.2V 9 22 BST_1.8V 2 1 1 2
2
3

3
2
1
VBST2 VBST1
PL5 UG_1.2V-1 2 PR101 1 UG_1.2V 10 21 UG_1.8V 2 PR100 1 UG_1.8V-1 PL6
1.8U_D104C-919AS-1R8N_9.5A_30% 0_0603_5% DR VH2 DR VH1 0_0603_5% 1.8U_D104C-919AS-1R8N_9.5A_30%
1 2 LX_1.2V 11 20 LX_1.8V 1 2
+1.2VALWP LL2 LL1 +1.8VALWP
LG_1.2V 12 19 LG_1.8V
DR VL2 DR VL1
1

8
7
6
5
4.7_1206_5%

C C

5
6
7
8

4.7_1206_5%
PR90

PGND2

PGND1
1

V5FILT
TRIP2

TRIP1
4.7U_0805_6.3V6K

4.7U_0805_6.3V6K
PR91
220U_6.3V_M

PQ18 1

V5IN
1
PC84

+ AO4712_SO8 PQ19

2
PC79

AO4712_SO8 + PC86
2

PC74
4 TPS51124RGER_QFN24_4x4 220U_6.3V_M
2

13

14

15

16

17

18

2
2
4

1
1

2
680P_0603_50V7K
PC87

680P_0603_50V7K
2

1
2
3

PC76
PR93

3
2
1
6.49K_0402_1% PR92

2
1 2 14.7K_0402_1%

2
PR94 PR96
0_0402_5% 0_0402_5%
<41,43> SPOK 2 1 1 2 +5VALWP 1 2 SPOK <41,43>
PR98
3.3_0402_5%
1

PC82

1
@ 0.1U_0402_16V7K PC78 PC88 PC80
1U_0603_10V6K 4.7U_0805_10V6K @ 0.1U_0402_16V7K
2

2
B B

VFB=0.764V

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title
1.5VP/1.8VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 01, 2008 Sheet 44 of 47
5 4 3 2 1
5 4 3 2 1

PJ12
2 1 6268_B+
B+ 2 1
@ JUMP_43X118
PHASE_1.05V
PR111

1
0_0603_5%
PC149 DH_1.05-1 1 2 DH_1.05-2

1
3300P_0402_50V7K PC92 6268_1.05V
PC93

2
PC91 4.7U_1206_25V6K

1
PR112 1 PR113 2 1 2

2
4.7U_1206_25V6K 2.2_0603_5%

1
10K_0402_1% 0.1U_0402_16V7K
PR114 +5VS
D 0_0603_5% BOOT_1.05V D

5
6
7
8
PR115

1
0_0603_5% PQ20

2
AO4466_SO8

16

15
8

1
PU500 PR116
4.7_0603_5% 4

PHASE
GND

PGOOD

UG

BOOT

2
PC94 1 2 6268_1.05V

1 2 3 VIN PVCC 14 1 2

3
2
1
@ 0.1U_0603_25V7K PC95 2.2U_0603_6.3V6K

6268_1.05V LG_1.05V PL7


4 VCC LG 13
1.8UH_SIL104R-1R8PF_9.5A_30%
+1.05VSP

1
1 2 +1.05VSP
PC96

1
2.2U_0603_6.3V6K 12 1

2
PGND PR117

5
6
7
8
4.7_1206_5% + PC97
PR118 220U_D2_4VY_R15M
1 2 5 11 ISEN_1.05V
1 2 PQ21
<30,31,39> SUSP#

2
EN ISEN AO4712_SO8 2

COMP
0_0402_5% PR119

FSET
1

1
3.65K_0402_1%

VO
FB
4

1
PC99 PR120
0.1U_0402_16V7K PC98 2.37K_0402_1%
2

10
@ @ISL6268CAZ-T_SSOP16 680P_0603_50V7K

2
3
2
1

2
ZZZ

C C
Rds=18mOHM

FB_1.05V
1
PR121
1 49.9K_0402_1%

1
ISL6268CAZ PC100

1
+1.8VS 22P_0402_50V8J PR122
2

2
57.6K_0402_1% @PC500
VFB=0.6V

1
0.01U_0402_25V7K

2
1

1
PR123

2
PJ15 3.01K_0402_1%
1

JUMP_43X118 +5VS

2
2
2

PC102
1

PC167 6800P_0402_25V7K
1

1U_0603_6.3V6M
2

PC168
4.7U_0805_6.3V6K
2

PU8
6 VCNTL
PR268 5 3
0_0402_5% VIN VOUT
9 VIN VOUT 4 +1.5VSP
1

1
<30,31,39> SUSP# 1 2 8 EN
1

+5VS +1.2VS

22U_0805_6.3V6M
7 2 PR269
GND

POK FB
PC169
PC170 2
1

3K_0402_1% PJ16
2

B PC171 APL5913-KAC-TRL_SO8 B
1

2
@ 0.1U_0402_16V7K @ JUMP_43X118
2

1U_0603_6.3V6M

2
1

0.01U_0402_25V7K

PC263

1
PR270
3.4K_0402_1%

4.7U_0805_6.3V6K
2

VFB=0.8V

1
+1.8V

PC264
2
1

6
PU11
PJ13 5
1

VCNTL
JUMP_43X118 VIN
7 POK
VOUT 4 +1.05VSP_LDO
2

1.1K_0402_1%

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
3 1
2

PR315 VOUT

1
PC266

PC267

PC268
PU9 1 2 8 2 + PC270
<30,31,39> SUSP# EN FB

PR316
1 6 PC265 @220U_6.3V_M

GND
VIN VCNTL +3VALWP
0_0402_5% 9

2
VIN @ 2
2 GND NC 5
1

2
1

PC103 3 7 PC104 APL5912-KAC-TRL_SO8 0.01U_0402_25V7K


4.7U_0805_6.3V6K VREF NC 1U_0603_6.3V6M
2

1
PR124 4 8
1K_0402_1% VOUT NC PC269

3.4K_0402_1%
9 0.1U_0402_16V7K
2

TP
@

PR319
A PR125 APL5331KAC-TRL_SO8 A

+0.9VSP

2
1

0_0402_5% D
1

<39> SUSP 1 2 2
1

G
S PC106
3

2
1

10U_0805_6.3V6M
2

PC107
@ 0.1U_0402_16V7K Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

PC105
1.05VSP/0.9VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PQ22 PR126 0.1U_0402_16V7K AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
SSM3K7002F_SC59-3 1K_0402_1% DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 01, 2008 Sheet 45 of 47
5 4 3 2 1
5 4 3 2 1

+5VS

2
CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
<5>

<5>

<5>

<5>

<5>

<5>

<5>
PR127

<31>
VR_ON
1_0603_5% +CPU_B+ PL8
D
HCB4532KF-800T90_1812 D
1 2 B+

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
1

220U_25V_M
1

1
PC110

PC111

PC112
0.022U_0402_16V7K
PR128 0_0402_5% +

1
PC109

PC113
2.2U_0603_6.3V6K
1 2 PC143
<25> PM_DPRSLPVR_D

PC108
2200P_0402_50V7K

2
PR129 0_0402_5% 2

2
PR133

PR134

PR135

PR136

PR137

PR138

PR139
PR132
<5,25> H_DPRSTP# 1 2

5
PR130 @ 0_0402_5% PQ23
1 2 SI7686DP-T1-E3_SO8
<14> CLK_EN#

1
1

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
PR131 0_0402_5%
+3VS 1 2 4
+3VS

1U_0603_6.3V6M

2
2
1.91K_0402_1%
2.2_0603_5% 0.22U_0603_10V7K

1
PC114
PR141 PC115 UGATE_CPU1-2 .36UH +-20% ETQP4LR36WFC 24A

3
2
1
1 BOOT_CPU1 1 2 1 2 2 1 +CPU_CORE
2

PR140

PR142

1
3.65K_0805_1%

10K_0402_1%
PL9

AO4456-T1-E3_SO8

PR145

PR146
499_0402_1% PR147

49

48

47

46

45

44

43

42

41

40

39

38

37
1 2

5
6
7
8

5
6
7
8
0_0603_5% 1_0402_5%
2

PR143 PR144

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
GND

DPRSLPVR

VR_ON

D
D
D
D

D
D
D
D
1

PQ25
4.7_1206_5%

1 2

2
1 36 PR148 @ 0_0603_5%
<14> VGATE PGOOD BOOT1
1 2

G
S
S
S

S
S
S
2 35 UGATE_CPU1-1 VSUM PC117
<5> H_PSI# PSI# UGATE1 PC116 1 2

4
3
2
1

4
3
2
1

2
1 2 3 34 PHASE_CPU1 PQ24 680P_0603_50V8J VCC_PRM
PMON PMON PHASE1
PR149 @ 0_0402_5% AO4456-T1-E3_SO8 ISEN1
C 0.22U_0603_10V7K C
1 2 4 RBIAS PGND1 33
@ PR151 0_0402_5% PR150 147K_0402_1%
1 2 VR_TT# 5 32 LGATE_CPU1 +CPU_B+
<4,20> H_PROCHOT# VR_TT# LGATE1

10U_1206_25V6M

10U_1206_25V6M
PR152 @ 4.22K_0402_1% PH2

1
1 2 1 2 6 NTC PVCC 31

PC119

PC120
PQ26
@ 100K_0603_1%_TH11-4H104FT 7 30 LGATE_CPU2 SI7686DP-T1-E3_SO8

2
SOFT LGATE2
1 2
@ PC118 8 29
0.015U_0402_16V7K 0.022U_0603_50V7K PC121 OCSET ISL6262ACRZ-T_QFN48_7X7 PGND2
4
1 2 9 28 PHASE_CPU2
VW PHASE2 PR154
PR153 13K_0402_1% 10 27 UGATE_CPU2-1 1 2 UGATE_CPU2-2
COMP UGATE2 0_0603_5% .36UH +-20% ETQP4LR36WFC 24A
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 2 1
FB BOOT2 PR155 PL10
1 2

1
1000P_0402_50V7K PC122 2.2_0603_5% PC123
DROOP

12 FB2 NC 25

5
6
7
8

5
6
7
8

1
VDIFF

ISEN2

ISEN1
VSUM

10K_0402_1%
VSEN

PR156 6.81K_0402_1% 0.22U_0603_10V7K PR157


GND

VDD
RTN

DFB

1
VIN

3.65K_0805_1%

PR159
4.7_1206_5% PR160
VO

1 2

D
D
D
D

D
D
D
D

PR158
1 2 PU10 PQ27
13

14

15

16

17

18

19

20

21

22

23

24

1 2
<BOM Structure> AO4456-T1-E3_SO8 1_0402_5%

2
G

G
S
S
S

S
S
S
PC124 1000P_0402_50V7K

2
ISEN1 PC125 PR164 @ 0_0603_5%

4
3
2
1

4
3
2
1
ISEN2 680P_0603_50V8J 1 2

2
2

PR161 97.6K_0402_1% PC126 470P_0402_50V7K 1 2 +5VS


1

1 2 2 1 PR162 VSUM PC128


1

@ 0_0402_5% PR163 1_0603_5% 1 2


PR165 PC127
1 2 1U_0402_6.3V6K
1

1K_0402_1% PQ28 0.22U_0603_10V7K


2

B PC129 220P_0402_50V7K AO4456-T1-E3_SO8 VCC_PRM B


PR167 ISEN2
255_0402_1% PC130 1000P_0402_50V7K 10_0603_5%
1 2 1 2 1 2 +CPU_B+
1

PR1661 2 PC131
0.1U_0603_25V7K
PR168 1K_0402_1%
2

PC132 0.018U_0603_50V7J
<5> VCCSENSE 1 2 1 2
VSUM
1

PR169 0_0402_5%
1

2.61K_0402_1%

PC134 PC133
PR171

+CPU_CORE 1 2 0.018U_0603_50V7J 0.018U_0603_50V7J


2

PR170 20_0402_5% 1 2
PR172 0_0402_5%
<5> VSSSENSE
2
1

11K_0402_1%

PC135 180P_0402_50V8J
PR174

PR173 1 2
2

10KB_0603_5%_ERTJ1VR103J
20_0402_5% 1 2 1 2 PH3
2

PR175 1K_0402_1% PR176 3.92K_0402_1%


PC136 0.1U_0402_16V7K
1

VCC_PRM 1 2

PC138 0.22U_0402_6.3V6K
PC137 2 1 2 1
0.22U_0603_10V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 01, 2008 Sheet 46 of 47
5 4 3 2 1
5 4 3 2 1

page Reason for change Modify list

PVT Add PR46 & PC37 for EMI request

Add bead at charger B+ for EMI request


D D

Add PR141,PR144,PC116,PR155,PR157,PC125 for EMI power board band noise.

Add PC87,PR90,PR88,PR95,PR91,PC76 for EMI power board band noise.

Add PR113,PR117,PC98 for EMI power board band niose.

Change 1.8V from 1.836 to 1.853. SO PR97 to 107K for HW request

Change PR176 to 3.92K for adjust Loadline

Change PC97 to 220UF form EVT SMT MEMO

C C

B B

A A

Title
<Title>

Size Document Number R ev


Custom<Doc> <RevCode>

Date: Friday, August 01, 2008 Sheet 47 of 47


5 4 3 2 1

You might also like