‫تنظ_حس كما يجب أن تكون‬

C.O. as it must be
Final 2019
Q1) a)
module counter(input clk, input up_down, input clear, input load, input
[0:7] load_value, output reg [0:7] count);
always @(posedge clk)
begin
if(~clear)count<=8'b0; //clear is active low.
else if(load)count<=load_value; //load is not required in the question.
else if(up_down)count<=count+1;
else if(~up_down)count<=count-1;
end
endmodule
Q1) b)

Typical Scenario:
1- Disk will require DMAC to have a data transfer transaction via
DREQ signal.
2- DMAC will ask CPU to leave the bus via HREQ (hold request) signal.
3- CPU will finish the current instruction & leave the bus.
 4- After leaving the bus, CPU will activate HACK (hold acknowledge)
signal.
5- DMAC now has the bus & can start the data transfer transaction.
Q2) a)
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 0 0 1 0
I/O mode Mode Mode Port A is Upper Port B is Port B is Lower
selection selection input port C is in mode input port C is
output 0 output

Q2) b)

North bridge:
1- Slows down the speed of FSB to be connected to PCI bus.
 2- Multiplexes some of FSB signals to be connected to PCI bus.
South bridge:
1- Slows down the speed of PCI bus to be connected to ISA bus.
2- Multiplexes some of PCI bus signals to be connected to ISA bus.
Q2) c) ‫مش علينا عىل ما أعتقد‬

Q3) a)

Data path.
Control signals. (Not required. For clarification only.)

Signals required in each pipeline stage by LW instruction.

Q3) c) ‫مش علينا عىل ما أعتقد‬
Q4) a)

Frame: Indicates the beginning & the end of the write transaction.
AD: Multiplexed address & data lines.
C/BE:
• Command: indicates the type of transaction (write).
• Byte enable: gives the bytes will be transmitted (indicated with
0) & bytes will be ignored (indicated with 1).
IRDY: Indicates whether the initiator is ready or not.
TRDY: Indicates whether the target is ready or not.
DEVSEL: indicates that the target has decoded the address sent by the
initiator & found that it was the selected target.
.‫ ده بق؟ معرفش‬PCI controller ‫ايه ال‬
Q4) b)
𝑉𝑖𝑟𝑡𝑢𝑎𝑙 𝑚𝑒𝑚𝑜𝑟𝑦 𝑠𝑖𝑧𝑒 256 𝑇𝐵
Page table entries = = = 0.0625 𝑇𝐵 = 286
𝑃𝑎𝑔𝑒 𝑠𝑖𝑧𝑒 4 𝐾𝐵
Assume that every entry needs 4 bytes
Page table total size = 286 * 22 = 288 = 0.25 TB !‫عظمة‬
Q4) c)
𝐶𝑎𝑐ℎ𝑒 𝑠𝑖𝑧𝑒 16 𝐾𝐵
2cache index = = = 4 𝐾𝐵 (index field size)
𝐵𝑙𝑜𝑐𝑘 𝑠𝑖𝑧𝑒 4𝐵
Cache index = 12
2cache address = 16 KB Cache address = 14
Tag = Physical address – Cache address = 32 - 14 = 18
Tag field size = 218