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MULTIPLIER
N. Sureka1, Ms.R.Porselvi2, Ms.K.Kumuthapriya3
PG Student1, Assistant Professor2, Sr.Assistant Professor
Tagore Engineering College, Chennai.
sureka.ns05@gmail.com
Abstract—Power dissipation of integrated circuits is a a carry save adder for adding the partial products so obtained
major concern for VLSI circuit designers. A Wallace tree and a carry propagate adder in the final stage of addition.
multiplier is an improved version of tree based multiplier In the proposed architecture, partial product reduction is
architecture. It uses carry save addition algorithm to accomplished by the use of 4:2, 5:2 compressor structures and
reduce the latency. This paper aims at further reduction of the final stage of addition is performed by a proposed carry
the latency and power consumption of the Wallace tree select adder.
multiplier. This is accomplished by the use of 4:2, 5:2
compressors and a proposed carry select adder. The result II. COMPRESSOR FOR PARTIAL PRODUCT REDUCTION
shows that the proposed Wallace tree multiplier is 44.4%
faster than the conventional Wallace tree multiplier, along The multiplier architecture comprises of a partial product
with realization of 11% of reduced power consumption. generation stage, partial product reduction stage and the final
The simulations have been carried out using the Modelsim addition stage. The latency in the Wallace tree multiplier can
and Xilinx tools be reduced by decreasing the number of adders in the partial
products reduction stage. In the proposed architecture, multi bit
Keywords- Wallace tree, Carry select adder, compressors, compressors are used for realizing the reduction in the number
of partial product addition stages. The combined factors of low
adder, multiplier
power, low transistor count and minimum delay makes the 5:2
and 4:2 compressors, the appropriate choice. In these
I. INTRODUCTION compressors, the outputs generated at each stage are efficiently
A multiplier is one of the key hardware blocks in most used by replacing the XOR blocks with multiplexer blocks [3].
digital and high performance systems such as FIR filters, The select bits to the multiplexers are available much ahead of
digital signal processor, microprocessors etc. With advances in the inputs so that the critical path delay is minimized. The
technology, many researchers have tried and strive to design various adder structures in the conventional architecture are
multipliers which offer either of the following- high speed, low replaced by compressors.
power consumption, less area combination of them in
multipliers, thus making them compatible for various high
speed, low power, and compact VLSI implementations.
However, area and speed are two conflicting constraints.
Therefore, improving speed always results in larger area. The
most efficient multiplier structure will vary depending on the
throughput requirement of the application. The first step of the
design process is the selection of the optimum circuit structure.
There are various structures to perform the multiplication
operation starting from the simple serial multipliers to the
complex parallel multipliers. Any speed improvement in the
multiplier will improve the operating frequency of the digital
signal processors or can be traded for energy by optimizing
circuit sizes and the voltage supply. The new architecture
enhances the speed performance of the widely acknowledged Figure 1. A 4:2 Compressor
Wallace tree multiplier. The structural optimization is
The use of two full adders would introduce a delay of 4
performed on the conventional Wallace multiplier, in such a
whereas the use of 4:2 compressors reduces the latency to 3.
way that the latency of the total circuit reduces considerably.
Two full adders are replaced by a single 4:2 compressor. The
The Wallace tree basically multiplies two unsigned integers.
equations governing the outputs of the 4:2 compressor
The conventional Wallace tree multiplier architecture [1] [2]
architecture is shown below.
comprises of an AND array for computing the partial products,
SUM = ( X 1⊕ X 2) • X 3 ⊕ X 4 + ( X 1⊕ X 2) • ( X 3 ⊕ X 4) • CIN + and carries are calculated, the final sums are computed using
multiplexers having minimal delay. The multiplexer block
( X1 ⊕ X 2) • X 3 ⊕ X 4 + ( X1 ⊕ X 2) • ( X 3 ⊕ X 4) • CIN receives the two sets of 5-bit input (four sum bits and one
COUT = ( X 1⊕ X 2) • X 3 + ( X 1⊕ X 2) • X 1CARRY = ( X1 ⊕ X 2 ⊕ X 3 ⊕ X 4) carry bit each) and selects the final sum based on the select
• CIN + ( X 1⊕ X 2 ⊕ X 3 ⊕ X 4) • X 4
Proposed 2748 15
VI. CONCLUSIONS
In this paper, the implementation and analysis of a
novel Wallace tree architecture is proposed. The latency of
existing Wallace tree multiplier which is found to be 27 has
been reduced to 15.The comparison result also shows that a
significant reduction of latency and area is achieved. The
results obtained prove that the proposed architecture is more
efficient than the conventional one in terms of area
consumption and latency.
REFERENCES