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Formal Verification
Formal Verification
Formal Verification
Dilawar Singh
1
I’m done simulating; Now what?, Kantrowiz M and Noack Lisa, DEC
Dilawar Singh Formal Verification in VLSI
Exhaustiveness
2
Bounded Model Checking, Armien Biere et al. Advances in computers,
2003
Dilawar Singh Formal Verification in VLSI
Symbolic Trajectory Evaluation
I f : T holds.
I EGf is true. In fact for every path f is
true i.e. AGf holds.
Dilawar Singh Formal Verification in VLSI
Model Checking
I In model checking, one builds a finite model of a system and
check that a desired property holds in that system. This is
done by search exhaustively (and some times wisely), if it does
not hold and a counterexample is produced. That is its
greatest strength to able to produce and error and thus
suitable for debugging. Since model is finite, it will terminate.
It is mostly used in hardware and protocol verification.
I Two approaches are genrally used in model checking,
TEMPORAL MODEL CHECKING (we have seeb them ) and
‘find and automation and compare to the specification to
determine whether or not its behaviour conforms to that
specification . For example, Language Inclusion (Har’El and
Krushan, 19941], refinement ordering [Cleaveland et all. 93],
observal equivalence [Cleaveland et all 93, Fernandez, 96, Roy
and de Simone 90].
I Vardi and Wolper [1986] have shown how the temporal model
checking problem could be recast in terms of automata, thus
Dilawar Singh Formal Verification in VLSI
Theorem Proving V/s Model Checking