Diode Lab Manual

Department of Electrical & Electronic Engineering ORT Braude College
Advanced Laboratory for Characterization of Semiconductor Devices - 31820
Semiconductor
diode
January 5, 2020
Dr. Radu Florescu Dr. Vladislav Shteeman

Department of Electrical and Electronic Engineering ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
The goal.
The goal of this experiment is to measure the Current-Voltage (I-V) and Capacitance-Voltage (C-V)
characteristics of semiconductor diode (at room temperature and under heating conditions) and
extract from the measurements basic physical parameters / characteristics of the device. You will
use Keithley SCS 4200 measurement system and Agilent 4284A C-R-L analyzer.
The following parameters will be acquired from the I-V measurements:
 Saturation current I sat
 Parasitic series resistance Rseries
 Parasitic shunt resistance Rshunt
The following parameters will be acquired from the C-V measurements:
 Built-in voltage of pn-junction, V0
 Doping densities N A and N D
 Depletion layer width W and depletion layer widths x p , x n on the p- and n-sides of the junction
unit unit
 Electric charges (per unit area) on the p- and n-sides of the junction, Q area and Q area .
Dr. Radu Florescu Dr. Vladislav Shteeman 2

Short theoretical background.

Diode[0] is a two-terminal electronic component that conducts electric current in one direction
(from positive (p) to negative (n) terminal) and blocks it the opposite direction.
Semiconductor diodes (represented physically by a p-n junction) are most common type of
contemporary diodes. They are widely used as a rectifiers, stabilitrons, voltage-dependent
capacitors etc. Special modifications of semiconductor diodes are used as solar cells, photodiodes,
light emitting diodes (LEDs) and laser diodes.
p-n junction consists of two regions (in a single semiconductor crystal) with opposite doping type
(Figure 1). The region on the left is p-type with an acceptor density N A , while the region on the
right is n-type with a donor density N D . The electrons (holes) density in the n-type (p-type) region
is approximately equal to the donor (acceptor) density (i.e. p0  N A , n0  N D ).
Figure 1. Sketch of p-n junction (after [12]).
I. Electrostatics of pn – junction.
1. pn – junction at zero-bias (applied voltage VD = 0) (after [5])
To reach the thermal equilibrium, electrons/holes close to the pn-junction diffuse across the
junction into the p-type/n-type region where hardly any electrons/holes are present. This process
leaves the ionized donors (acceptors) behind, creating a region around the junction, which is
depleted of mobile carriers. This region is called depletion region, extending from x   x p 0 to
x  xn 0 . The charge due to the ionized donors and acceptors creates built–in difference in
potentials between the two sides of the pn-junction, qV0 (where V0 is a built-in voltage). This built-
in potential qV0 is also expressed by the existence of the built-in electric field, which in turn causes
a drift of carriers in the opposite directions. The diffusion of carriers continues until the drift

current balances the diffusion current, thereby reaching thermal equilibrium (zero total current) as
indicated by a constant Fermi energy. This situation is shown on Figure 2 and Figure 3:
Figure 2. Concentration of carriers, electric charge density, electric field and electric potential
distribution in pn-junction at zero bias (after [0]).

Figure 3. Energy band diagram of a p-n junction at zero bias (after [0]).
The built-in voltage V0 can be expressed in terms of concentrations of donors N D , acceptors N A

and intrinsic concentration ni :
V0 
kT N A N D
ln  0.0256  ln
N AND
V 
q ni2 at room temperature ni2 (1)
T 300K
(where k  8.61733  10 5 eV K  is Boltzmann constant, T K  is a temperature and

q  1.6 10 19 C  is an electron charge)
   
Typical value of V0 for a standard Si diode (for N D  1015 cm 3 and N A  1018 cm 3 ): V0  0.7 V  .
Capacitance of a pn–junction at zero bias, C j 0 , originates mainly from the stationary ions
in the depletion region (i.e. from so-called junction capacitance C j at VD  0 ). It is expressed via
the total width of the depletion layer, W0 , and the relative dielectric constant of the
semiconductor,  r , as follows:
 0 r
C j0  A (2)
W0

(where A is a cross-section area of the pn-junction and  0 is the vacuum permittivity)
2. Biased pn-junction (applied voltage VD ≠ 0).
Depending on the applied external voltage, VD , there are two modes of diode biasing: forward
biased conducting mode and reverse biased non-conducting mode. Band diagrams of reverse- and
forward- biased pn-junction are shown on Figure 4 and Figure 5.
Figure 4. Band diagram of a p-n junction under reverse bias (after [4]).

Figure 5. Band diagram of a p-n junction under reverse bias (after [4]).
Depletion layer width W. The total width of the depletion layer W  x p  x n for biased pn-
junction is voltage-dependent.
Figure 6. Depletion layer in biased pn-junction.

 2  V  V   1 1 
 r 0 0 D
   VD  0
 q  DN N A 

W 
 2  V  V   1 1 
(3)
 r 0 0 D
   VD  0

 q  D
N N A 
The width of the depletion layers on the p- and n- sides of the junction, x p and x n :
W W
xn  , xp 
ND N (4)
1 1 A
NA ND
Capacitance of ideal biased pn – junction. A total capacitance of biased pn-junction is a

sum of 2 different capacitances, connected in parallel, namely:
1. C j (junction capacitance) - capacitance of

stationary ions in the depletion layer
(negatively charged acceptor ions at the p-side
vs positively charged donor ions at the n-side).
This capacitance is dominant at the reverse
bias VD  0 .
2. CS (stored or diffusion capacitance) -

capacitance of mobile carriers (electrons at
the p-side vs holes at the n-side), stored (as
the result of diffusion) outside the depletion
layer. This capacitance is dominant at the
forward bias VD  0 and not exists at the
reverse bias VD  0 (since for VD  0 , there
is no excess carriers outside the depletion
layer).
Thus a total capacitance of diode is

 C j for reverse bias VD  0

 C j  C S for forward bias VD  0
For reverse bias, C j (and therefore a total capacitance of a diode) depends on VD as follows:
A  2q r  0 N A N D  A
Cj      r  0
 V0  VD  N A  N D 
(5)
2 W
(where A is a junction’ cross-section area)
At the forward bias, a total capacitance of diode is C j  C S , not C j , and therefore (with
1
increasing VD ) it rises faster than
V0  VD  , as expected from Eq. (5). For this reason,
measured 1 characteristics of a real diode experience drastic decrease for VD  0 (see ).

C 2 VD 
Figure 7. Measured total capacitance C VD  and C 2 VD  of 1N4007 diode.

Calculation of built-in voltage, V0 from C-V measurements. From Eq. (5), 1 C 2j is a linear
function of VD :
N A  ND
1

2
V0  VD  (6)
C j q 0 semiconductor A N A N D
2 2
Figure 8. Sketch of a total capacitance C VD  and C 2 VD  for an ideal pn – junction (after [4]).
1
From the latter equation, for VD  V0   0 (i.e. C j   ). This allows one to find the built-
C 2j
in voltage V0 from the C-V measurements, as shown on Figure 8. V0 is obtained at the
intersection of the 1 C 2j curve and VD axis.
Calculation of dopant concentrations N A and N D from C-V measurements. N A and

N D can be obtained from the slope of the graph 1 C 2j vs VD  (see e.g. Figure 8) and Eq. (1). The
d C j 2 VD 
slope is given by:
dVD
d C j 2 VD  2 NA  ND
 (7)
dVD q 0 r A2 N A N D

Therefore,
q 0 r A2  d C 2
j VD  
   NA  ND
2  dVD  N AN D (8)
 
From Eq. (1), at the room temperature (i.e. kT q  0.0256 V  ), for the V0 and intrinsic
concentration ni known, we get another expression for N A and N D :
 V0 
ni2  exp    N A  N D
 0.0256 
V  
(9)
From Eq. (8) and Eq. (9) one can find the 2 unknowns, N A and N D .
Electric charge over the junction for reverse bias. The total electric charge over the
junction (for reverse biase) is given by:
Figure 9. Sketch of a biased pn-junction and a static charge distribution over it.
Q  qAxn N D  Q   qAx p N A
  (10)
n  side p  side
charge charge
where A is a junction’ cross-section area.
Electric charges per unit area on both sides of the junction are:

unit unit
Q  qxn N D  Q
area
  qx p N A
area

(11)
 
n  side p  side
charge charge
II. I-V characteristics of diode.
1. I-V characteristics of an ideal pn – junction.
Current via an ideal pn-junction obeys Shockley equation:
 kTVD 
 q 
I D  I sat  e  1 (12)
 
 
where I sat is a saturation current, q  1.6 10 19 C  is an electron charge, k is Boltzmann constant
and T is temperature. Figure 10 shows a sketch of I-V characteristics of an ideal diode.
Figure 10: I-V characteristics of an ideal diode (after [6]).

Asymptotic behavior of Shockley equation.
Note that e 1  e for   5 and e  0 for   5 . In our case, the condition   5

corresponds (at the room temperature, for kT  0.026 V  ) to the external voltage VD  0.13 V ,
q
while   5 corresponds to the VD  0.13 V . Therefore, for the forward biased junction with
VD  0.13 V ,
VD
I D  I sate kT q
VD  0.13 V  (13)
while for the reverse biased junction with VD  0.13 V 
I D   I sat VD  0.13 V  (14)
In other words, for reverse biased ideal pn-junction, current I D quickly reaches its saturation value
 I sat and remains constant for all the range of voltages VD  0.13 V  . As opposite to the
former, the forward bias, current increases exponentially all along; there is no current saturation.
Typical values of the saturation current are:
 I sat  109 A for silicon diodes

 I sat  106 A for germanium diodes.
2. Deviations of real diodes from Shockley model.
Deviations under forward bias. Parasitic series resistance Rseries .

When (at forward bias) VD reaches V0 (i.e. VD  V0 ), the potential barrier between p- and n- sides
of diode disappears: qV0  VD   0 . Thus, I D cannot continue rise exponentially, as before (as in
Eq. (13)). In order to describe a slower rising of I D for VD  V0 , a model of parasitic series
resistance Rseries is introduced. (This is so-called “second-order” I-V analysis of diode, extending
ideal Shockley model to the case, where it is actually inapplicable (i.e. to VD  V0 ).) According to
the model, for VD  V0 a diode should suffer from a parasitic series resistance Rseries (see Figure

11). This resistance reduces the voltage drop over the junction from VD to VD  I D Rseries . Thus, Eq.
(13) should be re-written as:
VD  I D Rseries
I D  I sate kT q
(15)
Figure 11. Sketch of I-V characteristics of "ideal" and "real" pn – junction (after [7]).
Transformation of this equation gives:

ID V I R
ln  D  D series
I sat kT q kT q (16)
This allows us to express Rseries as follows:
1  kT I D 
Rseries    ln  VD  (17)
ID  q I sat 
Thus, Rseries (according to the model) should be a linear function of VD .
Typical values of Rseries for Si diode are: Rseries  5  50  .
Deviations under reverse bias. Parasitic shunt resistance Rshunt .

Experimentally, at reverse bias, for VD  0.13 V , I D does not saturate to  I sat but rather
continues to increase (in abs value, see Figure 12).

Figure 12. I-V characteristics of reverse-biased 1N4148 diode.
qAWni  qV D

This increase is due to the generation current (drift current) I gen   e 2kT  1 ,
2 g  
 
originating from thermal generation of electron-hole pairs in the volume of depletion layer (where
A and W are cross-section of width of depletion layer of pn-junction, ni is intrinsic concentration
and  g is a lifetime of electron-hole pair from thermal generation to recombination). In a good
approximation, I D increases linearly with VD (see e.g. I D VD  graph on Figure 12 for
 1  VD  0.3 ).
One can modify Shockley model to account for I gen by introducing a parasitic shunt resistance
Rshunt , connected in parallel to the ideal diode and assuming I gen  VD Rshunt (see Figure 13).
For VD  10kT / q  0.26 V , Shockley equation should be replaced with:
qAWni V
I D   I sat  I gen   I sat    I sat  D
2 g Rshunt (18)

Figure 13. Explanation to the model of parasitic shunt resistance Rshunt and saturation current
I sat for reverse biased diode.
Note that Rshunt is a single value, independent on VD .
Typical values of Rshunt for a Si diode are: Rshunt  10  10 M .

2 3
One can compute both the Rshunt and I sat of a diode using trendline of the I D VD  curve in the
1
“deep” reverse bias region (say, in the range  1  VD  0.3 ). Rshunt  of this trendline,
slope
while I sat  free term (see Figure 13).
3. Diode response vs. temperature.

Diode performance is strongly affected by the temperature factor. Consider again the Shockley
model, I sat in Eq. (12) has a form:
 De( p ) (n)
Dhole  2
I sat  qA ( p )  (n) ni (19)
 Le N A Lhole N D 
where: q is an electron charge, De( p ) and Dhole

(n )
are the diffusion coefficients of the electrons on
the p-side and the holes on the n-side, L(ep ) and L(nhole) are the diffusion lengths of the electrons on

the p-side and the holes on the n-side, A is the pn-junction cross-section area, N A , N D are the
donors and acceptors concentrations and ni is the intrinsic concentration of Si.
(n )
For simplicity, assume, that De( p ) , Dhole , L(ep ) and L(nhole) are temperature independent. Nevertheless,
the current I sat in Eq. (19) does depend on the temperature, since n i is strongly dependent on the
temperature. It is possible to show, that I sat increases approximately for 7% for each temperature
degree. Thus, for two different temperatures T1 and T2 holds:
I sat T2   I sat T1   1.07T2 T1 (20)
Since 1.07  2 , there is a mnemonic rule, which says, that I sat doubles itself each 10 degrees:
10
T2 T1
I sat T2   I sat T1   2 10

(21)
The higher the temperature, the faster grows the forward branch of the I-V characteristics and the
larger the absolute value of the breakdown voltage at the reverse bias. Figure 14 illustrates the
aforesaid.
Figure 14. Diode response vs. temperature.

Assignments and analysis.

Part I. Room temperature measurements.
1. Acquire I-V measurements of diode using Keithley measurement

system. (See Appendix 2 for details about pin connections and
Keithley program parameters.)
2. Acquire C-V measurements of diode using Agilent R-C-L meter and

Keithley measurement system. (See Appendix 3 for details about
pin connections and Keithley program parameters.)
Note: after executing the measurements and before processing the acquired data, save this
Diode measurements
Excel template on your computer (double click on the Excel icon  File  Save as … ). Thenempty.xlsx
close
the Excel template and open the Excel file, saved recently. Copy the results of the measurements
(located in the measurements folder of Keithley in the subdirectory “tests/data”) to the Excel
template, saved on your computer.
Evaluation of physical parameters of diode from I-V measurements.
1. Shunt resistance Rshunt : I-V characteristics of diode in the “deep”

reverse bias (e.g. 0.5 V   VD  2 V ) in a good approximation is a
1 1
straight line. of the trendline of section is Rshunt : Rshunt 
slope slope
VD
2. Saturation current I sat : I D   I sat  I gen   I sat 
Rshunt
Free term of the trendline of the section above is I sat :
I sat  free term

3. Series resistance Rseries : for forward bias region VD  0.2 V , from the
graph ln  I D  vs V and Eq. (17), it is possible to find the range of


 I sat 
D
VD , corresponding to the ideal diode (red line) and another range,

corresponding to the diode with series resistance (blue line). It is also
possible to find the Rseries itself. To do this:
 in Excel, fill in the column ln  I D 


 I sat 
 make a graph ln  I D  vs V ; on the graph, find (visually) the sections, corresponding to the

 I sat 
D
red and to the blue lines.
 add to the graph plot ln  I D  vs V for the “blue” range only.


 I sat 
D
 add to the graph trend line for the “blue” range points (with “show equation” and “show R
square” boxes marked) to get the linear equation coefficients. (Note that in our case
ln  I D 
 is the “y” axis and VD is the “x” axis).
 I sat 
 fill in a column, “ Rseries ”, in the datasheet using Eq. (17)
 make 2 additional plots: Rseries vs VD and Rseries vs I D .
Evaluation of physical parameters of the diode from C-V measurements.

Note: the items below refer to the model of uniformly doped pn-junction. Nevertheless, usually, this is
not the case for real diodes. For one-sided hyperabrupt junction (e.g. p+n junction), see reference 8,
p.196 (double click to open ).
Neamen total.pdf
4. Built-in junction potential, V0 . This potential should be obtained

at the intersection of the C j 2 curve and the horizontal axis (VD
voltage).
In order to get V0 :
 in Excel, build the graph C j 2 vs VD .
 add to the graph trend line with the option “show equation” marked.
 from the trend line equation, find V0 (note that in our case 1 C 2j is the “y” axis and VD is the “x”
axis).

d C j 2 
5. Dopants’ concentration N A and N D . If the slope , the built-in voltage V0 , the intrinsic
dVD
carriers’ concentration ni and the cross section area of the pn- junction A are known ( see List
of symbols in Appendix 1 and Appendix 3 for details)) – one can find N A and N D by solving Eq.
(8) and Eq. (9):
 q  A2  d C j 2   N  N
 0 r   A D
 2  
 dVD  N AN D

 2  V0 
ni  exp  0.0256 V    N A  N D
  
d C j 2 
 the built-in voltage V0 and the slope were found on the previous step.
dVD
  r and ni for the specific diode could be found elsewhere (see e.g. Appendix 1).
 pn-junction’ cross-section area, A : for the 1N4148 Si diode, assume A  1mm  0.01cm .
2 2
6. Depletion layer width W vs VD for the reverse bias VD  0 .

 in Excel, compute (fill in the corresponding columns) depletion layer width W and depletion
layers width at the p- and n- sides ( x p and x n ) for the reverse bias VD  0 (see Eq. (3) and Eq.
(4) ).
 in Excel, make on a single graph 3 plots: W vs VD , x p vs VD and xn vs VD .
7. Electric charge (per unit area) over the junction for the reverse bias VD  0 .
 in Excel, compute (fill in the corresponding columns), using Eq. (11), electric charges per unit
unit unit
area on both sides of the junction Q area and Q area for reverse bias VD  0 .
unit unit
 in Excel, make on a single graph 2 plots: Qarea vs VD and Qarea vs VD .

Part II. Diode measurements under heating conditions.

For a room temperature and 4-5 other temperatures in a range of 40 C  70 C , acquire the I-V
 
measurements of the diode using the Keithley measurement system. (See Appendix 2 for details
about the pin connections and the Keithley program parameters.)
Important: execute the 1st measurement (under room temperature) using the green button ,
and all the rest of the measurements (under heating conditions, for 4-6 different temperatures)
using the yellow-greed button (“append”). DO NOT use the green button for the
measurements under heating conditions: it will override all your previous measurements.) After
each measurement save the data in the Keithley program.
After finishing the measurements, you can automatically process the data using Matlab program.
To do this:
1. Double-click on the zip-file “Diode heating processing.zip”. In the newly opened

window, folder “Diode heating processing” will appear.
2. Drag this folder to the Desktop of your computer.
3. In the Keithley measurements folder (subfolder tests/data) find the files

( C VD  & C VD  data), IU_forward#1@1.xls ( I D VD 
2
connect_pin_agilent#1@1.xls
measurements – forward bias data) & IU_backward#1@1.xls ( I D VD  measurements –
reverse bias data)

4. Copy the files connect_pin_agilent#1@1.xls, IU_forward#1@1.xls & IU_backward#1@1.xls

to the folder “Diode heating processing.zip”:
5. Double-click on the file processed_data_DIODE_sf2.m in the directory

“Diode heating processing”. This will start Matlab. Wait for 1-2 minutes
to allow Matlab start.

6. Go to the Matlab Editor window and run the file processed_data_DIODE_sf2.m (press F5 or
Debug Run on the Editor menu bar)
7. The program will ask you to input the temperatures, at which you measured the diode.
Input the temperatures in the square parentheses with the spaces between the different
values, e.g. [25 35 45 55 65]. Press Enter to continue.
8. Wait for approximately 1 minute, until the program will finish the processing of the
measured data.
9. The results of the computations (Excel file processed_data.xls, Matlab files and figures) are
located in the subfolder Results.


Final Report content.

Final Report must include the following diode parameters and graphs
with explanations:
Part I – room temperature measurements:
[1] I  V characteristics of diode (2 graphs: I D VD  for forward and for reverse bias)
[2] C  V characteristics of diode (a single graph, including C VD  & C 2 VD  curves)
[3] ln I D I sat  vs VD graph
[4] Shunt resistance Rshunt (a single value)
[5] Saturation current I sat (a single value)
[6] Series resistance Rseries (2 graphs: Rseries vs VD and Rseries vs I D )
[7] Built-in voltage V0 (a single value)
[8] Dopant concentrations N A and N D (two single values)
[9] Depletion layer width W vs VD and depletion layers widths at the n- and p-sides x p vs VD , x n vs VD
(a single graph)
unit
[10] Electric charge per unit area Q area vs VD (a single value)
Part II – measurements under heating conditions:
[1] I  V characteristics of the diode (forward bias) for all the

temperatures (on a single plot).
[2] I  V characteristics of the diode (reverse bias) for all the temperatures
(on a single plot).

[3] The graph of the saturation current I sat as a function of temperature T,

I sat T  .
[4] The graph of the parasitic shunt resistance Rshunt T  as a function of

temperature, Rshunt T  .
[5] The graph of the relative variation of the anode current versus anode voltage
I T   I Troom 
(forward bias) I  100%  for all the temperatures.
I Troom 
[6] The graph of the relative variation of the anode current versus anode voltage
I T   I Troom 
(reverse bias) I  100%  for all the temperatures.
I Troom 
[7] The graph of the total width of the depletion layer W0 at zero bias as a function of temperature. (The
total width of the depletion layer W0 can be evaluated from Eq. (2).)

Experimental set-up and samples to be studied

The experimental setup includes Keithley matrix and Agilent L-C-R analyzer (Figure 17).
(a) For the room temperature measurements, you will use Test fixture probe station (Figure 15) (with dual
in-line package (18 pins) for diodes on Teaching chip No 3, or two-pins connection table for standard
stand-alone diodes), connected by the triax cables No 9,10,11,12 to the Keithley switching matrix.
(b) For the measurements under the heating conditions, you will use the temperature controlling oven
(Figure 16) connected by the triax cables No 5,6,7,8 to the Keithley switching matrix.
Monitor
Keithley 708A
Switching Matrix Figure 15. Test fixture probe station.
Agilent 4284A
LCR meter
Keithley SCS 4200 I-V

AND Parameter analyzer
Figure 16. Temperature controlling oven.
Figure 17. Keithley and Agilent L-C-R
measurement setup.
Table 1. Diode samples for available for study.
Test chip No 3 1N4148 diode 1N4001 diode
Appendix 3
1N4148_1N4448 1n4001.pdf
datasheet datasheet.pdf

Acknowledgement
Electrical Engineering Department of Braude College would thank to Alexander Goldenberg, Vadim
Goyhman, Adi Atias and Moran Efrony for their extensive help in preparation of this laboratory
work.
Several parts of this guide were adapted from the pn-junction manual of the Advanced
Semiconductor Devices Lab (83-435) of School of Engineering of Bar-Ilan University. We would like
to thank Dr. Abraham Chelly for the granted manual.

Appendix 1 : List of symbols and definitions.

List of symbols.
  
A - pn-junction’ cross-section area cm2 (See Appendix 3 for the details about the cross-
section area of different diodes on the Teaching chip No 3). For the 1N4148 Si diode assume
A  1mm2  0.01cm 2 .
 V0 - built-in voltage V .
  
ni - intrinsic carriers concentration cm 3 . The following table presents ni for the basic
semiconductors at the room temperature (T = 300 K):
Si Ge GaAs

ni cm 3
 1.5  10 10
2.4  1013
1.79  106
 p0 , n0 - holes (electrons) concentration in the quasi-neutral regions of p- and n- sides of pn-


junction cm 3 . 
 
N A , N D - acceptors (donors) concentration at the p- and n- sides of pn-junction cm 3 . 
 Rseries - parasitic serial resistance [  ]; a voltage VD - controlled variable; usually ~ 5  50  .
 Rshunt - parasitic serial resistance [  ]; a voltage VD -independent constant; usually ~ 1 M .
  r - relative dielectric constant of a semiconductor [dimensionless]. The following table
presents relative dielectric constants of the basic semiconductors:
Si Ge GaAs
 semiconductor 11.9 16 13.1
    
 0 - permittivity of vacuum.  0  8.85  10-14 F cm  8.85  10-12 F m
 C j - pn-junction capacitance, originating from the stationary ion charges in the depletion region
F 
 C j 0 - C j at zero bias VD  0 F 
 (n )
De( p ) and Dhole - diffusion coefficients of the electrons on the p-side and the holes on the n-side
of the pn-junction.
 I D - diode current A.
 I gen - generation current A. Originates from thermal generation of electron-hole pairs in the
qAWni
volume of depletion layer: I gen 
g
 I sat - saturation current A.
 L(ep ) and L(nhole) - diffusion lengths of the electrons on the p-side and the holes on the n-side of
the pn-junction cm .
 VD - voltage applied to pn-junction V .
 W - total depletion layer width cm .

 W0 - total depletion layer width at zero bias VD  0 cm .

 x p , x n - depletion layers width in the p- and n- regions cm . W  x p  x n .
 k  1.38 10 23  Joule   8.617 10 5 eV  - Boltzmann constant

 deg .K   deg .K 
 T - temperature [deg. K]
 q  1.6  1019 C - electron charge.
 E F , Ei - Fermi and intrinsic Fermi level in semiconductor .
 E F , p , E F ,n - Fermi level on the p- (n-) side of the pn-junction.
 EC , EV - energy of the bottom of the conduction band and at the top of the valence band .
 Q , Q - electric charge (originating from the stationary ions in the depletion region) on the p-
and n- sides of the pn-junction C  ; voltage VD -dependent.
unit unit
 Qarea , Qarea - total electric charge per unit area and electric charges per unit area on the p- and

n- sides of the pn- junction C cm 2 
  g - generation time. An average time between thermal generation and recombination of an
electron-hole pair in the depletion layer.
List of definitions
n  - high doping density of n-type ( N D  1019 cm 3 ).

p  - high doping density of p-type ( N A  1019 cm 3 ).
Inversion - change of carrier type in a semiconductor obtained by applying an external voltage.
Inversion layer - the layer of free carriers of opposite type at the semiconductor interface (layer of
electrons in p-type semiconductor and layer of holes in n-type semiconductor).

Appendix 2 : Kite settings for I-V and C-V measurements.

1. pin connection scheme:
I-V
SMU 1 (cable 9) SMU 2 (cable 10)
measurement
s
C-V
LoPin (cable 12) HiPin (cable 11) measurement
s
2. I-V Keithley settings
Connect pins

Forward bias settings
Expected results – forward bias

Reverse bias settings
Expected results – reverse bias

3. C-V Keithley settings
frequency 1kHz
Expected results – C-V measurements (10 kHz)

Appendix 3 : Teaching chip No 3 diodes specifications

Diodes’ details and pins Chip appearance

Bibliography.
1 Diode at wikipedia: http://en.wikipedia.org/wiki/Diode.
2 B. Streetman, S. Banerjee, “Solid state electronic devices” (6th edition), Prentice Hall, 2005.
3 К.В. Шалимова, «Физика полупроводников» (3е издание), Энергоатомиздат, 1985.
4 B. Van Zeghbroeck, “Principles of semiconductor devices”, Lectures – Colorado University, 2004.
5 A. Chelly, “pn-junction”, Lab manual - Advanced Semiconductor Devices Lab (83-435), School of
Engineering of Bar-Ilan University.
6 J. Singh, “Semiconductor devices: basic principles”, Whiley, 2001.
7 A. del Alamo. “pn diode characterization” – project in the framework of course “Microelectronic
Devices and Circuits” (6.012), MIT, 2003.
8 D. Neamen, “Semiconductor Physics and Devices: Basic Principles” (3rd edition), McGraw Hill, 2003.
9 S. Kasap, “pn-junction: the Shockley model”. An e-booklet (2001).

10 pn-junction Simulation using Java Applet: http://jas.eng.buffalo.edu/education/pn/iv/index.html
11 pn-junction properties calculator: http://www.ee.byu.edu/cleanroom/pn_junction.phtml
12 http://en.wikipedia.org/wiki/P%E2%80%93n_junction
Silicon chip with PN

junction
2 mm

Preparatory Questions
1. Explain (in short) the principle of diode operation
2. Plot the qualitative graph of diode I-V characteristics
3. Plot the qualitative graph of diode C-V characteristics
4. How can you find from the I-V characteristics:
a. saturation current I sat
b. series resistance Rseries
5. How can you find from the C-V characteristics:
a. built-in voltage of the pn-junction V0
b. doping densities N A and N D
c. total depletion layer width W and depletion layer width x p , x n on each side of the junction

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Department of Electrical & Electronic Engineering ORT Braude College

Advanced Laboratory for Characterization of Semiconductor Devices - 31820

Dr. Radu Florescu Dr. Vladislav Shteeman

Advanced Laboratory for Characterization of Devices – 31820

The following parameters will be acquired from the I-V measurements:

 Saturation current I sat

 Parasitic series resistance Rseries

 Parasitic shunt resistance Rshunt

The following parameters will be acquired from the C-V measurements:

 Built-in voltage of pn-junction, V0

 Doping densities N A and N D

Dr. Radu Florescu Dr. Vladislav Shteeman 2

Advanced Laboratory for Characterization of Devices – 31820

Short theoretical background.

Figure 1. Sketch of p-n junction (after [12]).

1. pn – junction at zero-bias (applied voltage VD = 0) (after [5])

Dr. Radu Florescu Dr. Vladislav Shteeman 3

Advanced Laboratory for Characterization of Devices – 31820

Dr. Radu Florescu Dr. Vladislav Shteeman 4

Advanced Laboratory for Characterization of Devices – 31820

The built-in voltage V0 can be expressed in terms of concentrations of donors N D , acceptors N A

(where k  8.61733  10 5 eV K  is Boltzmann constant, T K  is a temperature and

Dr. Radu Florescu Dr. Vladislav Shteeman 5

Advanced Laboratory for Characterization of Devices – 31820

(where A is a cross-section area of the pn-junction and  0 is the vacuum permittivity)

2. Biased pn-junction (applied voltage VD ≠ 0).

Dr. Radu Florescu Dr. Vladislav Shteeman 6

Advanced Laboratory for Characterization of Devices – 31820

Figure 6. Depletion layer in biased pn-junction.

Dr. Radu Florescu Dr. Vladislav Shteeman 7

Advanced Laboratory for Characterization of Devices – 31820

Capacitance of ideal biased pn – junction. A total capacitance of biased pn-junction is a

1. C j (junction capacitance) - capacitance of

2. CS (stored or diffusion capacitance) -

Thus a total capacitance of diode is

Advanced Laboratory for Characterization of Devices – 31820

 C j for reverse bias VD  0

(where A is a junction’ cross-section area)

measured 1 characteristics of a real diode experience drastic decrease for VD  0 (see ).

Figure 7. Measured total capacitance C VD  and C 2 VD  of 1N4007 diode.

Dr. Radu Florescu Dr. Vladislav Shteeman 9

Advanced Laboratory for Characterization of Devices – 31820

Calculation of dopant concentrations N A and N D from C-V measurements. N A and

Dr. Radu Florescu Dr. Vladislav Shteeman 10

Advanced Laboratory for Characterization of Devices – 31820

where A is a junction’ cross-section area.

Dr. Radu Florescu Dr. Vladislav Shteeman 11

Advanced Laboratory for Characterization of Devices – 31820

II. I-V characteristics of diode.

1. I-V characteristics of an ideal pn – junction.

Current via an ideal pn-junction obeys Shockley equation:

Figure 10: I-V characteristics of an ideal diode (after [6]).

Dr. Radu Florescu Dr. Vladislav Shteeman 12

Advanced Laboratory for Characterization of Devices – 31820

Asymptotic behavior of Shockley equation.

Note that e 1  e for   5 and e  0 for   5 . In our case, the condition   5

while for the reverse biased junction with VD  0.13 V 

I D   I sat VD  0.13 V  (14)

Typical values of the saturation current are:

 I sat  109 A for silicon diodes

2. Deviations of real diodes from Shockley model.

Deviations under forward bias. Parasitic series resistance Rseries .