USHA RAMA COLLEGE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

LESSON PLAN

Course: VLSI Lab Course code :

Academic year: 2019-20 Semester : II

Class/ section : III ECE B (Batch 2) Date of Commencement of class work:
18.11.2019
Faculty Name: Mr A.Sarath Raja Date of End of class work:23.03.2020

Cycle 1
S. No Name of Experiment No. of Periods Mode of Execution Date
Demonstration on Lab Lecture interspersed 1 week
1 Experiments & Software 3 with discussion 22.11.2019

Lecture 2 week
Demonstration on Lab
interspersed with 29.11.2019
2 Experiments & Software 3
discussion

Design and Implementation of 3 week

3 Experiment
3 CMOS Inverter 06.12.2019
Design and Implementation of conducted by using 4 week
4 3
CMOS Nand Gate Mentor Graphics 13.12.2019
Design and Implementation of Version 17.0 5 week
3
5 CMOS Nor gate Software 20.12.2019
Design and Implementation of D- 6 week
6 3
Latch 27.12.2019
Design and Implementation of RS- 7 week
7 3
Latch Experiment 03.01.2019
Design and Implementation of conducted by using 8 week
8 3 Mentor Graphics
Decoder 10.01.2020
Version 17.0 9 week
Design and Implementation of
9 3 Software 31.01.2020
Asynchronous Counter
Cycle 2
10 Design and Implementation static 10 week
3 07.02.2020
RAM cell
Design and Implementation of Full 11 week
11 3 Experiment
Adder 14.02.2020
conducted by using
Design and Implementation of Full Mentor Graphics 12 week
12 3
Subtractor Version 17.0 28.02.2020
Design and Implementation of 8 bit Software 13 week
13 3
DAC using R2R ladder Network 06.03.2020
Design and Implementation of ring 14 week
14 3
oscillator 13.03.2020
15 week
15 Internal Lab Examination 3
20.03.2020

Signature of Faculty Signature of HOD