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A Fully Synthesized All-Digital VCO-Based Analog-to-Digital Converter
A Fully Synthesized All-Digital VCO-Based Analog-to-Digital Converter
A Fully Synthesized All-Digital VCO-Based Analog-to-Digital Converter
Analog-to-Digital Converter
Abstract—Synthesis of all-digital ADCs leads to significant according to post layout parasitic extracted simulations using
reduction in design cost and design time, besides improving the Spectre simulator. Performance from the post synthesis
cross-technology portability. In this work, an ADC which is fully simulation as well as from the post place-and-route parasitic
described in digital HDL is synthesized, placed and routed using extracted simulation are provided to aid estimation of the
standard digital design tools. A VCO-based architecture is chosen drop in resolution due to automatic place-and-route. Section II
for its synthesizability. The design flow employed is discussed.
provides an overview of the ADC circuit. Section III discusses
The circuit is synthesized using the standard cell library in a
65 nm CMOS process, delivering a resolution of 9 ENOB over the design flow employed. Section IV presents the simulation
10 MHz bandwidth according to post layout parasitic extracted results and Section V concludes the discussion.
simulations using the Spectre simulator. Post synthesis and post
place-and-route performances are provided. II. ADC CIRCUIT
I. I NTRODUCTION VCO-based ADC architecture is an attractive candidate
for high performance synthesizable all-digital ADCs due to
The ongoing trend of CMOS technology scaling and inherent noise shaping and anti-aliasing properties. A converter
System-on-Chip integration demands high performance inte- circuit similar to the one used in [7] is used in this work to
grated data converters portable to fine-feature processes. How- investigate the feasibility of synthesis of ADCs. The circuit
ever, the analog intensive nature of conventional data converter is shown in Fig. 1 and can be modeled as shown in Fig. 2.
architectures makes their design and cross-technology porting ψ(v(t)) is the instantaneous frequency of the oscillator, and,
difficult, expensive and time consuming. It is possible to φ(t), its instantaneous phase. φq (t) is the quantized phase
implement data converters entirely using digital circuits by which is sampled using frequency Fs (= 1/Ts ). A backward
representing signals using time instead of using voltage or difference operation on the resulting sequence generate the
current, which is a technique referred to as time-mode or converter output y(k), where k is the sample index. It can
time-domain signal processing. This enables automated design be shown that the quantization noise transfer function (NTF)
and porting of the circuit using commercial digital design of the converter is
tools. Furthermore, an all-digital implementation is expected to
improve its performance as well as area and energy efficiency Nφ
NTF = − (1 − z −1 ) (1)
as the feature size scales down. 2π
Several analog-to-digital converter (ADC) architectures where Nφ is the number of inverter stages in the ring oscillator,
employing time-mode techniques have been demonstrated re- indicating first order shaping of the quantization error. Further,
cently, achieving high performance and low power consump- the model has an inherent sinc anti-aliasing filtering due to
tion [1]–[6]. However, they use custom circuits or analog continuous-time sampling.
circuits limiting the possibility of synthesis and automatic A supply controlled multi-phase ring oscillator with Nφ
place-and-route using a standard digital design flow. A time- static CMOS inverters is used as the VCO where Nφ is an
mode ADC built exclusively using standard cells is presented odd number. The phase taps of the oscillator are connected
in [7] and a stochastic flash ADC that is fully synthesized to an array of counters which performs accumulation of the
is reported in [8]. In this work, an all-digital ADC circuit phase progression. Output of the counter array is sampled by
is fully described and synthesized from a digital hardware a register. The counters are encoded in Gray-code in order to
description language (HDL) using the standard cell library in eliminate spurious error samples arising from partial sampling
a 65 nm CMOS process. A VCO-based ADC architecture [2], of the counter output [7]. The sampled counter output from
[4] is chosen to demonstrate the synthesis of ADCs. The idea each phase tap is binary converted and first order differentiated.
can, however, be easily extended to a variety of possible all- The results are added together to generate the converter output.
digital architectures. The design flow employed to synthesize
and place-and-route the circuit is discussed. The circuit de- The use of supply controlled oscillator implies non-linear
livers an ENOB of around 9 bits over a 10 MHz bandwidth voltage frequency conversion necessitating digital post pro-
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Fig. 3. Design flow for automatic synthesis and place-and-route of the ADC.
−20
−40
PSD (dBFS/NBW)
−60
−80
−100
−120 5 6 7
10 10 10
Frequency (Hz)
After correction
0 NBW = 73.1 kHz
−20
Fig. 4. Layout of the ADC generated after automatic place-and-route.
−40
PSD (dBFS/NBW)
cells. Besides placing the standard cells and routing the nets, −60
place-and-route involves multitude of other tasks including
floor planning, power planning, placement of well straps, −80
clock tree synthesis (CTS) etc. Place-and-route constraints are
utilized to exercise control over these tasks in order to limit −100
Frequency (Hz)
process time-continuous information and any delay mismatch
between the parallel signal paths in this block contributes to
Fig. 5. Spectrum from the single tone test of the post synthesis circuit before
the error in the phase signal. In order to limit the wire load and after digital correction.
imbalance in this block, the cell placement of the block is
restricted to a small area. Further, the ring oscillator needs TABLE I. S IMULATED DYNAMIC PERFORMANCE AFTER SYNTHESIS
to be connected to the signal input pin of the converter. This
is achieved by assigning the oscillator to a separate power Performance Metric Correction OFF Correction ON
domain. The placement area for this power domain should be Sample rate (MHz) 150
restricted as well, in order to limit the wire load imbalance due OSR 7.5 7.5
to automatic place-and-route. The place-and-route tasks and
Bandwidth (MHz) 10 10
the constraints are managed using scripts, enabling automated
repetitions and script based tuning of circuit parameters and ENOB 4.0 9.4
SNDR (dB) 26.0 58.4
constraints. Important outputs from place-and-route include SNR (dB) 70.1 67.4
the GDSII file describing the geometry of the layout and the SFDR (dB) 28.9 65.8
modified netlist, in addition to the reports summarizing timing, THD (dB) −26.0 −59.7
V. C ONCLUSION
−60
Automated circuit and layout generation of all-digital
−80
mixed signal circuits is of interest due to reduction in design
cost and design time as well as due to better cross-technology
−100 portability. A time-mode all-digital analog-to-digital converter
is fully described in a digital HDL, and, is synthesized, placed
−120
10
5 6
10 10
7 and routed using a standard digital design flow in this work.
Frequency (Hz) A VCO-based ADC architecture is chosen for its inherent
After correction
noise shaping and anti-aliasing properties. A digital correction
0 NBW = 73.1 kHz block employing polynomial-fit estimation corrects for the
static VCO non-linearity, which is verified using a MATLAB
−20
model. The design flow employed to synthesize the ADC
−40
circuit is discussed. The circuit, when implemented using the
PSD (dBFS/NBW)