UNIT-1

Introduction to VLSI

Advantages of VLSI:

 Integration improves the design

 Lower parasitic = higher speed

 Lower power consumption

 Physically smaller

 Integration reduces manufacturing cost - (almost) no manual

assembly.

Review of microelectronics & Introduction to MOS Technologies:

 Evolution of IC’s and

 comparison of currently available technologies (Including

BICOMOS& GaAs as well as nmos & CMOS).

 MOS Transistor action.

 Fabrication process.

Introduction to IC Technology:

Electronics devices can be characterized by

 Reliability

 Low power dissipation

 Low weight and volume

 Low cost

 Ability to cope up with high degree of sophistication and complexity.

The History of VLSI:

 IC(Integrated Circuits) History Evolution

 vacuum tube,

 single transistor,

 IC (Integrated Circuits)

SSI, MSI, LSI, VLSI, SoC .

  80’s—IC composed mainly by nMOS and BJT

 90’s—IC composed mainly by CMOS and BiCMOS

 1995— AT&T, Phillips proposed SOC .

ICs:

 Integration improves

 size

 speed

 power

 Integration reduce manufacturing costs

 (almost) no manual assembly

 Using Ic memories, we can implement a wide range of logic

and analog circuitry and has many Applications.

 Integration improves

 size

 speed

 power

 Integration reduce manufacturing costs

 (almost) no manual assembly

 Using Ic memories, we can implement a wide range of logic

and analog circuitry and has many Applications.

IC Evolution:

 SSI – Small Scale Integration (early 1970’s)

 contained 10 – 100 logic gates

 MSI – Medium Scale Integration

 contained 100 – 1000 logic gates

  logic functions, counters

 LSI – Large Scale Integration

 contained 1000 – 20,000 logic gates

 first microprocessors on the chip

 VLSI – Very Large Scale Integration

 contained >20,000 logic gates(i.e millions ).

 now offers 64-bit microprocessors,

complete with cache memory, floating-point arithmetic
unit(s), etc.

5th Generation:

 ULSI (Ultra large scale integration)

contains 3 million devices on single chip.

The progress in Ics can be seen in

• The no. of devices/chip.

• Size of chip.

• Process technology used varies.

 The later stages progress is to produce

• Smaller chip.

• Faster.

• More reliable.

• Less expensive which consumes less power.

• Bipolar technology

• TTL (transistor-transistor logic)

• ECL (emitter-coupled logic).

MOS (Metal-oxide-silicon)

• Although invented before bipolar transistor,

was initially difficult to manufacture

• nMOS (n-channel MOS) technology developed in 1970s

required fewer masking steps, was denser, and consumed less
power than equivalent bipolar ICs => an MOS IC was cheaper
 than a bipolar IC and led to investment and growth of the
MOS IC market.

 Aluminum gates replaced by polysilicon by early 1980

 CMOS (Complementary MOS): n-channel and p-channel MOS

transistors =>
lower power consumption, simplified fabrication process

 Bi-CMOS - hybrid Bipolar, CMOS (for high speed)

 GaAs - Gallium Arsenide (for high speed)

Moore’s Law:

 Gordon Moore: co-founder of Intel

 Predicted that the number of transistors per chip would grow

exponentially (i.e Double every 18 months)

 Exponential improvement in technology is a natural trend:

 In 1965, Gordon Moore predicted that the number of transistors

that can be integrated on a die would double every 18 to 14 months

 i.e., grow exponentially with time

 visionary – million transistor/chip barrier was crossed in the

1980’s.

 2300 transistors, 1 MHz clock (Intel 4004) - 1971

 42 Million, 2 GHz clock (Intel P4) - 2001

 140 Million transistor (HP PA-8500)

Moore’s Plot:
Variation of Gate length & supply voltg w.r.t Year:

Comparison b/n technologies:

 Silicon CMOS tech became dominant fabrication process

• For high performance and

• cost effective

 Development of Ics by the use of silicon is indicated by the increase

in number of transistors/Chip.

 The progress can be seen in RISC chips – 35 million instruction/sec.

 In order to improve this throughput rate it is necessary to improve

technology, both in terms of scaling and processing.

 Silicon tech-100 million inst./sec.

 GaAs –High speed.

Speed vs Power performance:

Technological Background of the Moore’s Law:

 To accommodate this change, the size of the silicon wafers on which

the integrated circuits are fabricated have also increased by a very
significant factor – from the 2 and 3 in diameter wafers to the 8 in
(200 mm) and 12 in (300 mm) diameter wafers

 The latest catch phrase in semiconductor technology (as well as in

other material science) is nanotechnology – usually referring to
GaAs devices based on quantum mechanical phenomena

 These devices have feature size (such as film thickness, line width
etc) measured in nanometres or 10-9 metres

Recurring Costs:

VLSI Applications:

 VLSI is an implementation technology for electronic circuitry -

analogue or digital

 It is concerned with forming a pattern of interconnected switches

and gates on the surface of a crystal of semiconductor

 Microprocessors

 personal computers

 microcontrollers

 Memory - DRAM / SRAM

 Special Purpose Processors - ASICS (CD players, DSP applications)

  Optical Switches

 Has made highly sophisticated control systems mass-producable

and therefore cheap .

MOS and related VLSI Technologies:

 Leading Ic technology:

• nMOS

• CMOS

• BICMOS & GaAs technology.

 nMos is generally preferred because of following Reasons:

 1. Design methodologies and design process are simple and easy to

learn.

 2. It provides an excellent background for other Technologies.

 3. Easy transition.

Creating Wafers - Czochralski Method:

 Start with crucible of molten silicon (≈1425oC)

 Insert crystal seed in melt

 Slowly rotate / raise seed to form single crystal boule

 After cooling, slice boule into wafers & polish.

 Make sure that the inside of the machine is very clean too and that
the gas flow - the gas you introduce but also the SiO coming from
the molten Si because parts of the crucible dissolve - does not
interfere with the growing crystal.

 Dissolve the Si in the crucible and keep its temperature close to the
melting point. Since you cannot avoid temperature gradients in the
crucible, there will be some convection in the liquid Si. You may
want to suppress this by big magnetic fields.

 Insert your seed crystal, adjust the temperature to "just right", and
start withdrawing the seed crystal. For homogeneity, rotate the
 seed crystal and the crucible. Rotation directions and speeds and
their development during growth, are closely guarded secrets!

 First pull rather fast - the diameter of the growing crystal will
decrease to a few mm. This is the "Dash process" ensuring that
the crystal will be dislocation free even though the seed crystal may
contain dislocations.

 Now decrease the growth rate - the crystal diameter will increase -
until you have the desired diameter and commence to grow the
commercial part of your crystal at a few mm/second.
Fabrication Cycle:

Processing Wafers:

 All dice on wafer processed simultaneously

 Each mask has one image for each die

 The basic approach:

  Add & selectively remove materials

Metal - wires

Polysilicon - gates

Oxide

 Selectively diffuse impurities

 Photolithography is the key.

1.Fabrication steps that go towards forming the devices and

2.Inter-connections between these devices to produce the functioning
IC's.
3.The end result are wafers each containing a regular array of the same
IC chip or die.
4.The wafer then has to be tested and the chips diced up and the good
chips mounted and wire-bonded in different types of IC package and
tested again before being shipped out.

Mos transistor:

• Enhancement mode transistors

• Depletion mode transistors

Mos circuit symbols:

N-Channel MOSFET:

N-Transistor Operation – Cutoff:

 Vgs << Vt : Transistor OFF

 Majority carrier in channel (holes)

  No current from source to drain

N Transistor Operation – Subthreshold:

 0 < Vgs < Vt : Depletion region

 Electric field repels majority carriers (holes)

 Depletion region forms - no carriers in channel

 No current flows (except for leakage current)

N Transistor Operation – ON:

 Vgs > Vt , VDS=0: Transistor ON

 Electric field attracts minority carriers (electrons)

 Inversion region forms in channel

 Depletion region insulates channel from substrate

 Current can now flow from drain to source!

N Transistor Operation – Linear:

 Vgs > Vt , VDS <VGS -VT : Linear (Active) mode

 Combined electric fields shift channel and depletion region

 Current flow dependent on VGS, VDS

N Transistor Operation – Saturation:

 Vgs > Vt , VDS >VGS -VT : Saturated mode

 Channel “pinched off”

 Current still flows due to electron drift

 Current flow dependent on VGS

P Transistor Operation:

 Opposite of N-Transistor

 Vgs >> Vt : Transistor OFF

Majority carrier in channel (electrons)

No current from source to drain

 0 > Vgs > Vt : Depletion region

Electric field repels majority carriers (electrons)

Depletion region forms - no carriers in channel

No current flows (except for leakage current)

 Vgs < Vt , VDS=0: Transistor ON

Electric field attracts minority carriers (holes)

Inversion region forms in channel

Depletion layer insulates channel from substrate

 Current can now flow from source to drain!

P Transistor Modes of Operation:

 Vgs <Vt , VDS >VGS -VT : Linear (Active) mode

 Combined electric fields shift channel and depletion region

 Current flow dependent on VGS, VDS

 Vgs < Vt , VDS <VGS -VT : Saturation mode

 Channel “pinched off”

 Current still flows due to hole drift

 Current flow dependent on VGS

I-V Characteristics of MOS Transistors:

Architecture of MOS Field-Effect Transistors (FETs):

 The metal-oxide semiconductor field-effect transistor

(MOSFET) : the gate is insulated from the channel by a silicon
dioxide (SiO2) layer.
nMOS Fabrication:

 The fabrication processes used for nMOS are relevant to CMOS and
Bi-CMOS which may be viewed as involving additional fabrication
steps.

1. Processing is carried out on a thin wafer cut from a single crystal of

silicon of high purity into which the required p-impurities are introduced
as the crystal is grown.

Such wafers are typically 4" to 8" in diameter and 0.4 mm thick and
are doped with, say, boron to impurity concentrations of 10 15/cm3 to
1016/cm3, giving resistivity in the approximate range 25 Ohm/cm to 2
Ohm/cm.

2 . A layer of silicon dioxide (SiO2), typically 1 mm thick, is grown all

over the surface of the wafer to protect the surface, act as a barrier to
dopants during processing, and provide a generally insulating substrate
onto which other layers may be deposited and patterned.

3. The surface is now covered with a photoresist which is deposited onto

the wafer and spun to achieve an even distribution of the required
thickness.
4. The photoresist layer is then exposed to ultraviolet light through a
mask which defined those regions into which diffusion is to take place
together with transistor channels,

Assume, for example, that those areas exposed to ultraviolet

radiation are polymerized (hardened), but that the areas required for
diffusion are shielded by the mask and remain unaffected.

5 . These areas are subsequently readily etched away together with the
underlying silicon dioxide so that the wafer surface is exposed in the
window defined by the mask.

6. The remaining photoresist is removed and a thin layer of SiO2

(0.1mm typical)

is grown over the entire chip surface and then polysilicon is deposited on
top of this to form the gate structure.

* The polysilicon layer consists of heavily doped polysilicon

deposited by chemical vapour deposition (CVD).

* In the fabrication of fine pattern devices, precise control of

thickness, impurity concentration, and resistivity is necessary.
7. Further photoresist coating and masking allows the poly-silicon to be
patterned

(as shown in Step 6), and then the thin oxide is removed to expose areas
into which n-type impurities are to be diffused to form the source and
drain as shown.

Diffusion is achieved by heating the wafer to a high temperature

and passing a gas containing the desired n-type impurity (for example,
phosphorus) over the surface as indicated in Figure . Note that the poly-
silicon with underlying thin oxide and the thick oxide act as masks during
diffusion - the process is self-aligning.

8. Thick oxide (SiO2) is grown over all again and is then masked with
photoresist and etched to expose selected areas of the polysilicon gate
and the drain and source areas where connections (i.e. contact cuts) are
to be made.

9. The whole chip then has metal (aluminium) deposited over its
surface to a thickness typically of 1 mm. This metal layer is then masked
and etched to form the required interconnection pattern.
The process revolves around the formation or deposition and patterning of
three layers, separated by silicon dioxide insulation.

The layers are:

1. Diffusion within the substrate,

2. Poly-silicon on oxide on the substrate, and

3. Metal insulated again by oxide.

Formation of Depletion mode devices:

The Depletion mode device is formed by introducing a masked ion –

implantation for the step b/n step 5 step 6 for channel establishment .

Some extra process steps are necessary such as

 Over-glassing of whole wafer, except where the contacts are

required.

Summary of an nMOS process:

• Processing takes place on a p-doped silicon crystal wafer on which is

grown a ‘thick’

layer of SiO2.

• Mask 1 - Pattern SiO2 to expose the silicon surface in areas where paths
in the diffusion layer or source, drain or gate areas of transistors are
required. Deposit thin oxide over all. For this reason, this mask is often
known as the ‘thinox’ mask but some texts refer to it as the diffusion
mask.
• Mask 2 - Pattern the ion implantation within the thinox region where
depletion mode

devices are to be produced - self-aligning.

• Mask 3 - Deposit polysilicon over all (1.5mm thick typically), then

pattern using Mask

Using the same mask, remove thin oxide layer where it is not covered by
polysilicon.

• Diffuse n+ regions into areas where thin oxide has been removed.
Transistor drains and sources are thus self-aligning with respect to the
gate structure.

• Mask 4 - Grow thick oxide over all and then etch for contact cuts.

• Mask 5 - Deposit metal and pattern with this mask.

• Mask 6 - This mask is required for the overglassing process step, and is
called the

passivation mask.

Introduction to cmos Fabrication:

There are a number of approaches to CMOS fabrication, including

the p-well, the n-well, the twin-tub, and the silicon-on-insulator
processes.

The p-well and n-well processes are widely used in practice (the n-
well process was an easy retrofit to existing nMOS lines).

Complementary MOS fabrication :

• CMOS Technology depends on using both N-Type and P-Type

devices on the same chip.

• The two main technologies to do this task are:

– P-Well (Will discuss the process steps involved with this

technology)

• The substrate is N-Type. The P-Channel device is built

directly on the substrate, while the N-channel device is
built into a P-Type well within the parent N-Type
substrate.

– N-Well

• The substrate is P-Type. The N-channel device is built

directly on the substrate, while the P-channel device is
 built into a N-type well within the parent P-Type
substrate.

• Two more advanced technologies to do this task are:

Becoming more popular for sub-micron geometries where device

performance and density must be pushed beyond the limits of the
conventional p & n-well CMOS processes.

– Twin Tub

• Both an N-Well and a P-Well are manufactured on a

lightly doped N-type substrate.

– Silicon-on-Insulator (SOI) CMOS Process

• SOI allows the creation of independent, completely

isolated nMOS and pMOS transistors virtually side-by-
side on an insulating substrate.

• p-well process:

The basic processing steps are of the same nature as those used for
nMOS.

In primitive terms, the structure consists of an n-type substrate in

which p-devices may be formed by suitable masking and diffusion and, in
order to accommodate n-type devices, a deep p-well is diffused into the
n-type substrate as shown.

This diffusion must be carried out with special care since the p-well
doping concentration and depth will affect the threshold voltages as well
as the breakdown voltages of the ntransistors.

To achieve low threshold voltages (0.6 to 1.0V), we need either

deep well diffusion or high well resistivity. However, deep wells require
larger spacing between the n- and p-type transistors and wires, because
of lateral diffusion, and therefore require a larger chip area.

P-well on N-substrate :

Steps :

• N-type substrate

• Oxidation, and mask (MASK 1) to create P-well (4-5mm deep)

• P-well doping

P-well acts as substrate for nMOS devices.

The two areas are electrically isolated using thick field oxide (and often
isolation implants [not shown here])

Poly-silicon Gate Formation :

Steps :

• Remove p-well definition oxide

• Grow thick field oxide

• Pattern (MASK 2) to expose nMOS and pMOS active regions

• Grow thin layer of SiO2 (~0.1mm) gate oxide, over the entire chip
surface

• Deposit polysilicon on top of gate oxide to form gate structure

• Pattern poly on gate oxide (MASK 3)

nMOS P+ Source/Drain difusion – self-aligned to Poly gate :

 Implant P+ nMOS S/D regions (MASK 4)

pMOS N+ Source/Drain difusion – self-aligned to Poly gate :

Implant N+ pMOS S/D regions (MASK 5 – often the inverse of MASK 4)

pMOS N+ Source/Drain difusion, contact holes & metallisation :

Oxide and pattern for contact holes (MASK 6)

Deposit metal and pattern (MASK 7)

Passivation oxide and pattern bonding pads (MASK 8)

P-well acts as substrate for nMOS devices.

Two separate substrates : requires two separate substrate connections

Definition of substrate connection areas can be included in MASK

4/MASK5

CMOS N-well process :

An N-well process is also widely used.

N-well CMOS circuits are also superior to p-well because of the

lower substrate bias effects on transistor threshold voltage and inherently
lower parasitic capacitances associated with source and drain regions.

Composite layout and cross-section view of n-well CMOS device:

(excludes passivation and patterning of wire-bonding pads)

Main steps in a typical n-well Process:

Advantages:

The n-channel devices are used to form logic elements that provides :

1. High Speed &

2. High Density.

Latch-up problem can be reduced by using a low resistance epitaxial

P-type substrate as a starting material, which acts as a very low
resistance ground-plane to collect substrate currents.

Disadvantages:

In conventional p & n-well CMOS process, the doping density of the well
region is typically higher than the substrate , which results in un-balanced
drain Parasitics.

The Twin-tub process avoids this Problem.

Twin-Tub (Twin-Well) CMOS Process

This technology provides the basis for separate optimization of the

nMOS and pMOS transistors, thus making it possible for threshold
voltage, body effect and the channel transconductance of both types of
transistors to be tuned independently.
 Generally, the starting material is a n+ or p+ substrate, with a
lightly doped epitaxial layer on top. This epitaxial layer provides the
actual substrate on which the n-well and the p-well are formed.

Since two independent doping steps are performed for the creation
of the well regions, the dopant concentrations can be carefully optimized
to produce the desired device characteristics. The Twin-Tub process is
shown below.

In the conventional p & n-well CMOS process, the doping density of

the well region is typically about one order of magnitude higher than the
substrate, which, among other effects, results in unbalanced drain
parasitics.

*The twin-tub process avoids this problem.

Silicon-on-Insulator (SOI) CMOS Process :

Rather than using silicon as the substrate material, technologists

have used an insulating substrate to improve process characteristics such
as :

1. speed and

2. latch-up susceptibility.

The SOI CMOS technology allows the creation of independent,

completely isolated nMOS and pMOS transistors virtually side-by-side on
an insulating substrate.

A cross-section of nMOS and pMOS devices using SOI process is

shown below:
 1. The SOI CMOS process is considerably more costly than the
standard p & n-well CMOS process.

2. Yet the improvements of device performance and the absence of

latch-up problems can justify its use, especially for deep-sub-micron
devices.

Advantages:

The main advantages of this technology are:

1. The higher integration density (because of the absence of

well regions),

2. complete avoidance of the latch-up problem,

3. lower parasitic capacitances compared to the conventional

p & n-well or twin-tub CMOS processes.

Bi-CMOS Technology:

Combines Bipolar and CMOS transistors in a single integrated circuit

By retaining benefits of bipolar and CMOS, BiCMOS is able to

achieve VLSI circuits with speed-power-density performance previously
unattainable with either technology individually.

Characteristics of CMOS Technology:

 Lower static power dissipation

 Higher noise margins

 Higher packing density – lower manufacturing cost per device

 High yield with large integrated complex functions

 High input impedance (low drive current)

 Scalable threshold voltage

 High delay sensitivity to load (fan-out limitations)

 Low output drive current (issue when driving large capacitive loads)

 Low transconductance , where transconductance , gm a Vin

 Bi-directional capability (drain & source are interchangeable)

 A near ideal switching device

Characteristics of Bipolar Technology:

 Higher switching speed

  Higher current drive per unit area, higher gain

 Generally better noise performance and better high frequency

characteristics

 Improved I/O speed (particularly significant with the growing

importance of package limitations in high speed systems).

 high power dissipation

 lower input impedance (high drive current)

 low voltage swing logic

 low packing density

 low delay sensitivity to load

 high gm (gm a Vin)

 high unity gain band width (ft) at low currents

 essentially unidirectional

Performance Gap b/n CMOS and Bi-polar :

Combined advantages in BiCMOS Technology:

• BiCMOS technology some way combines the virtues of both CMOS

and Bipolar technologies

• Design uses CMOS gates along with bipolar stage where driving of
high capacitance loads is required

• Resulting benefits of BiCMOS technology over solely CMOS or solely

bipolar :

• Improved speed over purely-CMOS technology

• Lower power dissipation than purely-bipolar technology

(simplifying packaging and board requirements)

• Latchup immunity (Discussed later in course)

Advantages of Bi-CMOS :
  A known deficiency of MOS technology is its limited load
driving capabilities (due to limited current sourcing and sinking
abilities of pMOS and nMOS transistors.

 Bipolar transistors have

 higher gain

 better noise characteristics

 better high frequency characteristics

 BiCMOS gates can be an efficient way of speeding up VLSI circuits.

 CMOS fabrication process can be extended for BiCMOS

 Example Applications

 CMOS - Logic

 BiCMOS - I/O and driver circuits

 ECL - critical high speed parts of the system

The production of npn Bipolar transistor with good performance

char’s can be achieved, by extending the standard n-well processing to
include futher masks to add two additional layers.
 1. the p+ base layer and

2. The n+ sub-collector .

Further advantages of BiCMOS Technology:

 High impedance CMOS transistors may be used for the input

circuitry while the remaining stages and output drivers are realised
using bipolar transistors.

 In general, BiCMOS devices offer many advantages where high load

current sinking and sourcing is required. The high current gain of
the NPN transistor greatly improves the output drive capability of a
conventional CMOS device.

 MOS speed depends on device parameters such as saturation

current and capacitance. These in turn depend on oxide thickness,
substrate doping and channel length.

 Compared to CMOS, BiCMOS’s reduced dependence on capacitive

load and the multiple circuit and I/Os configurations possible greatly
enhance design flexibility and can lead to reduced cycle time (i.e.,
faster circuits).

 Bi-CMOS is inherently robust with respect to temperature and

process variations, resulting in less variability in final electrical
parameters, resulting in higher yield.

 Large circuits can impose severe performance penalties due to

simultaneously switching noise, internal clock skews and high nodal
capacitances in critical paths – Bi-CMOS has demonstrated
superiority over CMOS in all of these factors.

 BiCMOS can take advantage of any advances in CMOS and/or

bipolar technology, greatly accelerating the learning curve normally
associated with new technologies.

Disadvantages with BiCMOS technology:

 Main disadvantage : greater process complexity compared to CMOS

 Results in a 1.25 -> 1.4 times increase in die costs over

conventional CMOS.

 Taking into account packaging costs, the total manufacturing costs

of supplying a BiCMOS chip ranges from 1.1-> 1.3 times that of
CMOS.

BASIC ELECTRICAL PROPERTIES

Drain to Source Current Ids Vs Voltage Vds:

The whole concept of the MOS transistor evolves from the use of a
voltage on the gate to induce a charge in the channel between source and
drain, which may then be caused to move from source to drain cender the
influence of Vds applied between source and drain. Since the charge
induced in dependent on Vgs, then Ids in dependent on both Vgs and Vds.
Change induced in channel (Qc )
 I ds   I sd 
Electron Transittim e (T )

Length of channel ( L)
Tsd 
Velocity (V )

but Velocity

V = µEds

Where

µ=Electron or hole mobility (Surface)

Eds= Electric field (Drain to Source)

vds
Eds 
L

mVds
V 
L
L2
Tsd  2
mVds

Non – Saturation Region:

When device is operated in Non – Saturated region, the IR drop in the

channel is same throughout the channel and can be taken as average
 VDS
value as 2 where VDS is difference between gate and channel assuming
substrate connected to the channel.

 In non-saturated region effective gate voltage Vv is given by

Vg = VGS - Vt

Vt = Threshold Voltage

The charge gets enduced into the channel due to gate voltage and if E g is
average electric field. From gate to channel.

The charge per unit area = EvEinsEo

Eins=Relative permittivity of insulator between gate and channel.

Eo=Obsolute permittivity (8.85 × 10-14 F/cm)

The total educed charge for the area of WL is

Qc=EgtinstoWL
[(Vgs  Vt )  Vds ]
Eg 
Eg= D

Where,

D is oxide thickness.

Putting the expression for Eg

Eins EoWL  V 
Qc   (Vgs  Vt )  ds  3
D  2 

Now, combining equations

2 ,3 &1 we have

E ins Eo m W  V 
I ds =  (Vgs  Vt )  ds Vds
D L  2 

W Vds 
2
I ds = K (V
 gs  Vt )Vds   4 or resistive region where
In the non-saturated
L  2 
Vds <Vvs – Vt and

Let Eins Eo m
K
D
W
 K
L

So that

 V 
2
I ds =  (Vgs  Vt )Vds  ds 
 2 
 5

5 Alternative forms equation

Gate / Channel Capacitance

E ins EoWL
Cg =
D
C gm
K
WL

C gm  Vds 
2
6
I ds = (V
 gs  Vt )Vds  
L2  2 

Sometimes it is convenient to use gate capacitance per unit area co,

which is often denoted as cox,

Cg=CoWL

W Vds 
2
 I ds = Co m (Vgs  Vt )Vds   7
L  2 

The Saturated Region:

Saturation begins when Vds=Vvs-V, at this point the IR drop in the channel
equals the effective gate to channel voltage. The current through the
channel remainsI fairlyW (V  V ) 2
constant for any further increase in V ds.
gs t
ds = K
L 2

W
(Vgs  Vt ) 2   K
I ds =  N
2

Eins toWL
I ds =
C gm
2L2
V gs  Vt
2
 C g 
D

Where Cg=gate Capacitance

I ds  Com
W
Vgs  Vt  2
2L
Co=gate capacitance unit area

Threshold Voltage of MOSFET and Significance:

The gate structure of MOS transistor consists, electrically, of

charges stored in the dielectric layers and in the surface to surface
interfaces as well as in the substrate itself.
 Switching an enhancement mode MOS transistor from off to on
state necessitates applying sufficient gate voltage to neutralize these
changes and enable the under lying silicon to undergo an inversion due to
electric field from the gate.

For switching an depletion mode nMOS transistor from ON to OFF

State consists in applying enough voltage to the gate to add to the soared
charge and invert the ‘n’ implant region to p region.

The threshold voltage Vt in given by

QB  QSS
Vt  ms  2 fN
CO

QB=The Charge per unit area in the depletion layer beneath the oxide.

QSS=The charge density at Si; Sio2 interface.

CO=Capacitance / Unit gate area.

ms  Work function difference between gate and Si

 fN 
Fermi level potential between invested surface and bulk si

The expression for V+ can be evaluated through the following data.

QB  2 EO E Si QN (2 fN  VSB )
Coulomb/m2

KT  n 
 fN  n 
Q  ni  voth

Qss  (1.5 to 8)×10-8 coulomb / m2 depending on crystal orientation.

Where VSB = substrate bias voltage (-Ve wrt source for nµos and +Ve wrt
PMOS)

Q=1.6×10-19 coulomb

N=impurity concentration in substrate (NA or ND)

ESi=Relative permittivity of Si (11.7)

Ni=Intrinsic Electron concern (1.6 × 1010 / cm3 at 3000k)

K=Boltzmann’s constant = 1.4 × 10-23 joule / 0K

The Variation with Vt with VSB (Substrate bias) is called body effect.
Body effect Co-efficient = 0.223 (Volts)1/2

Vt interms of VSB is
D
2 EO ESi qN VSB 
1/ 2
Vt = Vt(O) ±
E O Eins
Empirical formula for V(t)

Where, Vt(0) Corresponds to threshold voltage of device when V SB is

supposed to be zero volts.

D=Oxide thickness

EO=Absolute permittivity

Eins=Relative permittivity of Sio2 =4

Esi=Relative permittivity of silicon = 11.7

Q=Electron charge

VSB=Substrate bias.

‘D’ is standard = 50A0

 Vt  Vt  o    VSB 
1/ 2

Where
 0.233 (Volts)1/2 is body effect Co-efficient

MOS Transistor Trans conductance (gm) and output conductance (gds):

 Tran conductance shows the relationship between output current I ds
and input voltage Vgs.
S Ids
gm  Vds  Cons tan t
SVgs
i.e.

To find an expression for gm in terms of circuit and transistor parameters,

consider that the charge in channel Qc is such that.
Qc

I ds

Where ζ is transit time? Thus change in current.

SQc
SI ds 
 ds

L2
 ds 
mVds
 SQcVds m
SI ds 
L2
But change in change
SQc  C g SV gs

So that

C g SVgs mVds
SI ds 
L2

Now
SI ds C g mVds
gm  
SVgs L2

In saturation
Vds  V gs  Vt

Cg m
gm  V gs  Vt 
L2

Eins EoWL
Cg 
And substituting for D

mEins Eo W
gm  Vgs  V 
D L

g m   Vgs  V 

 Output conductance is the ration of output current to the output

voltage.
I ds
g ds  Vgs 
i.e. Vds constant
1
g ds 
Rds

Vds
Rds  Vgs  1
I ds Constant

We have
 W
 Vgs  Vt Vds  Vds 
2
I ds  K 2
L 2 

Assuming Vds to be small, and neglecting Vds2term in equation

2

 I ds  K
W
L

Vgs  Vt Vds  3

By Substituting in we get
3 1
Vds
Rds 
K
W
L

Vgs  Vt  Vds 
1
Rds 
K
W
L
Vgs  Vt 
1
 W
 K Vgs  Vt  
 L 

g ds  K
W
Vgs  Vt 
L

Figure of Merit (Wo):

It is the quantity used to characterize the performance of a device relative

to other device of the same type. In engineering figure of merit (FOM) are
often defined for particular materials are devices in order to determine
their relative utility for an application.

MOS transistor FOM Wo indicates the frequency response of MOS

transistor. It is defined as

m  1 
 2 Vgs  Vt   
gm
Wo   1
cg L   sd 

This shows that switching speed depends on gate goltage above threshold
and on carries mobility and inversely as the square of channel length. A
fast circuit require that gm be as high as possible.

Body Effect:

 CMOS devices are consisting of common substrate. The substrate bias

level is normally equal.

Effect of substrate Bias:

Consider two nMOS transistors connected vertically in series as shown in

figure.
 The source to substrate voltage V sb as observed vertically upward i.e.
Vsb1=0 and Vsb2≠0. It means that Vsb2 and Vsb1 one not same. This
variation of Vsb causes variation in threshold voltages i.e. V t2 and Vt1.
Since Vsb2>Vsb1 therefore.

 This variation of threshold voltage due to source to substrate voltage is

referred as body effect.

 In complex circuits body effect is significantly important.

 The body effect is because of variation in depletion region under oxide

as a result of source substrate voltage.

 Change in threshold voltage ∆Vt is given by

Vt 
2qN A E si
Co
 2 s  Vsb  2 s 
Vt   n  2 s  Vsb  2 s 
Where
 n in body effect factor depends on gate oxide thickness and substrate
doping.

Pass Transistor:

 MOS transistors can be used as switches by virtue of the isolated

nature of the gate.

 When the transistor is operating in the linear region, the device act as
a linear resistance under gate voltage control.

 In this mode the transistor can be used as an on off switch as shown in

figure.
 The switch is turned off when V gs=0. By setting Vgs=VDD, the switch is
turned ON.

 In case of P-channel transistor, switch is turned ON When V gs=-VDD.

 If the transistor is connected in series with a high impedance circuit

the total current flowing through the transistor will be very small and
so will be the voltage drop across the channel.

 An NMOS transistor is a perfect switch when passing a ‘O’ we say it

passes ‘a’ stron ‘O’. However, the nMOS transistor is imperfect at
passing ‘I’. The high voltage level is somewhat less than V DD. So it is
passing weak ‘I’.

 PMOS has opposite behavior passing strong ‘I’ s and degraded ‘O’.

When an NMOS or PMOS is used alone as an imperfect switch, we call it

as pass transistors.

NMOS Inverter:

The basic inverter circuit requires a transistor with source connected to

ground and a load resistor of some sort connected from drain to the
positive supply rail VDD. The output is taken from the drain and the input
applied between gate and ground.

 With no current drawn from the output, the currents I ds for both
transistor4s must be equal.

 For the depletion made transistor, the gate is connected to the source
so it is always on and only the characteristic curve Vgs=O is relevant.
 In this configuration the depletion made device is called the pull-up
(P.u.) and the enhancement made device the pull-down, (P.d)
transistor.

 To obtain the inverter transfer characteristic we superimpose the

Vgs=O depletion mode characteristic curve on the family of curves for
the enhancement mode device, maximum voltage across the
enhancement mode device corresponds to minimum voltage across the
depletion mode transistor.

 Note that as Vin(=Vgs P.d Transistor) exceeds the P.d threshold voltage
current begins to flow. The output voltage V out will cause the P.d
transistor to come out of saturation and become resistive. Note that
the P.u transistor is initially resistive as the p.d turns on.

 The point at which Vout=Vin is denoted as Vinv and it will be noted that
the transfer characteristics and Vinv can be shifted by variation of the
ration of pull-up to pull – down resistances.

Determination of Pull-up and pull-down Ration:

NMOS Inverter driven by another inverter:

Consider the arrangement shown in figure in which an inverter in driven

from the output of another similar inverter.

Vin Vout
Consider the depletion mode transistor for which V gs=O under all
conditions, and further assume that in order to cascade inverters without
degradation of levels we are aiming to meet the requirements.

Vin=Vout=Vinv

We set Vinv=0.5 VDD, at this point both transistor is saturation and.

2
w  v gs  vt 
I ds k  
l  2 
 1

In the depletion mode

w p.u   rtd  2
I ds  k   2
l p .u  2 
Since Vgs=O

And in the enhancement mode

w p.d  vinv  vt  2
I ds  k   3
l p.d  2  Since V =V
gs inv

By equating 2
& 3
w p.d  vinv  vt  2 w p.d
     vtd  2
l p .d  2  l p.u

Where Wp.d, Lp.d, Wp.u and Lp.u are the widths and length of pull-down and
pull-up transistor respectively.

Now write
L p.d L p.u
Z p.d  ; z p.u 
W p.d W p.u

We have
1
 vinv  vt  2  1   vtd  2
Z p.d Z p .d

Hence
Vtd
Vinv  Vt 
Z p .u Z p.d 4

4 in
By substituting the typical values of the following

Vt=0.2 VDD; Vtd=-0.6VDD

Vinv=0.5VDD
 0.6
0.5  0.2 
Z p.u Z p .d

Z p .u Z p . d
Hence =2
Z p .u 4

Z p .d 1

NMOS Inverter driven through two or more pass transistors:

Now Consider the arrangement as shown in figure in which the input to

inverter2 come from the output of inverter1 but passes through one or
more NMOS transistors used as switches in series (Called pass
transistors).

 The Connection of pass transistors in series will degrade the logic 1

level / into inverter2 so that the output will not be a proper logic O
level.

 The critical condition is when point A is OV and B is thus at V DD. But

the voltage into inverter2 at point C is now reduced from V DD by the
threshold voltage of the pass transistor.

 With all pass transistors gates connected to V DD, these is a loss of V tp,
however many are connected in series, since no static current flows
through them and there can be no voltage drop in the channels.

 The input voltage to inverter2 is

Vin2=VDD-Vtp

Where Vtp=Threshold voltage for pass transistor.

Consider inverter1with input=VDD. If the input is at VDD then the P.d

transistor T2 is conducting but with a low voltage across it; therefore, it is
in its resistive region represented by and P.u transistor T 1 is in saturation
and is represented as a current source a shown in figure.

For the P.d transistor

 w p .d 1  2

I ds  k  vDD  vt Vds1  Vds1 
l p.d  2 

 
Vdsl l L p .dl  1 
R1   
I ds k Wp.dl  V 
VDD  V  dsl t
 2 

vds1
Note that Vdsi is small and 2 is ignored

1   1 
R1   Z P.d 1  
K  VDD Vt 

Now, for depletion mode P.u in saturation with Vgs=0

2
W   Vtd 
I 1 I ds  K P.u1  
LP .u1  2 

2
Z p .d 1  1  1  V td 
I1 R1  Vout 1     
Z p.u1 VDD  Vt  VDD  Vt  2 

For inverter2 consider input=VDD-Vtp.

1 1
R2  S p .d 2
K VDD  Vtp   Vt
2
1   Vtd 
I2  K  
Z P.u 2  2 

Z p.d 2  1  V td  2
Vout 2  I 2 R2    
Z p.u 2 VDD  Vtp  Vt  2 

If the inverter2 is to have the same output voltage under these conditions
then.

Vout1=Vout2

Z P.u 2 Z P.u1 VDD  Vt 

 
Z p.d 2 Z p.d 1 VDD  Vtp  Vt 

By taking the typical values of the following

Vt  0.2VDD

Vtp  0.3VDD
 Z P.u 2 Z 0 .8
  P.u1 
Z p.d 2 Z p . d 1 0 .5

Z P .u 2 Z 8
  2 P .u1 
Z p .d 2 Z p .d 1 5

Alternative forms of pull-up:

1. Load Resistance (RL):

This arrangement is not often used because of the large space

requirements of resistors produced in a silicon substrate.

 Dissipation is high since rail to rail current flows when V in =logical 1.

 Switching of output from 1 to 0 begins when V in exceeds Vt of p.d

device.

 When switching the output from 1 to 0, the p.u device is non-saturated

initially and this presents lower resistance through which to charge
capacitive loads.

nMOS Enhancement Mode Pull-Up:

 Dissipation is high since current flows when Vin =logical 1.

 Vout can never reach VDD.

 VGG may be derived from a switching source.

 If VGG is higher than VDD then an extra supply rail is required.

Complementary Transistor Pull-Up:

 No current flow either for logic 0 or for logic 1 inputs.

 Full logic 1 and 0 levels are presented at the output.

 For devices of similar dimensions the p-channel is slower than the n-

channel device.

CMOS Inverter:

The current / voltage relationship for the MOS transistor may be written.
2
Vds
w

I ds  k v gs  vt Vds 
L 2

In the resistive region
2
w  v gs  vt 

I ds  k
L  2 


‘K’ is a technology dependent parameter such that

 Eins Eo m
K
D
W
The factor L is, of course, geometry and it is common practice to write.
W
 K
L

Such that, for example


I ds  Vgs  Vt  2
2

In saturation, where  may be applied to both nMOS & pMOS transistors

as follows.
Eins Eo m n Wn
n 
D Ln

Eins Eo m p W p
P 
D Lp

Wn, Ln, Klp, Lp on the nmos & pMOS dimensions respectively.

Region1:

For which Vin=logic 0, we have p-transistor fully turned. ON while the n-

transistor is fully tuned off. Thus no current flows through the inverter
and the output is directly connected to V DD through the p-transistor. A
good logic 1 output voltage is thy present at the output.

Region2:
The input voltage increased to a level which just exceeds threshold
voltage of the n-transistor. The n-transistor conducts and has a large
voltage between source and drain; so it is in saturation. The p-transistor
is also conducting but with only a small voltage across it, it operates
unsaturated resistive region.

A small voltage now flows from VDD to Vss.

Region3:

Is the region in which the inverter en habits gain and in which both
transistors one in saturation.

The current in each device must be the same since the transistors are in
series, so we may write.
I dsp   I dsn

Where

 p Vin  VDD   Vtp 

2

I dsp 
2
And
n
I dsn  Vin  Vtn  2
2

Hence we can express Vin in terms of the β ratio and the other circuit
voltages and currents.
1
 2
VDD  Vtp  Vtn  n 
 
Vin   p 
1
 2
1  n 
 
 p 

Since both transistors are in saturation, they act as current sources so

that the equivalent circuit in this a region is two current sources in scribes
between VDD and Vss with output voltage coming from their common point.
The region is inherently unstable in consequence and the change over
from on level to the other is rapid.

Region4:

I Similar to region2 but with roles of the p-and n-transistors reversed

however the regions 2 and 4 are small and most of the nergy consured in
switching from on state ot the other is due to the larger current which
flows in region3.

Region5:
Vin=logic1, the n-transistor is fully on while the p-transistor is fully off.
Again, no current flows and a good logic 0 appear at the output.

BiCMOS Inverter:

The figure shows the circuit diagram of BiCMOS inverter. It consists of

two bipolar transistors Q1 and Q2 and a enhancement mode nMOS Q n and
p-MOS Qp.

Operation:

When the input voltage Vin of the BiCMOS inverter in figure is low, the
transistor QN and Q2 are cut – off. The transistor Q p is turned on and
provides base current ot Q11 so that Q1 turned on and supplies current to
the load capacitance CL. The load capacitance charges and the output
voltage goes high.

The output voltage charge to a maximum value of approximately

Vout(max)=VDD-VBE(on).

When the input voltage Vin goes high, Qp turns OFF eliminating any bias
current to Q1, so Q1 is also OFF. The two transistors Q N and Q2 turn ON
and provide voltage goes low. The output voltage will discharge to a
minimum value of Vo (min) =VBE (on).

Q1 and Q2 will present low impedances when turned ON into saturation the
load CL will charge and discharged rapidly.

The inverter has high input impedance and low output impedance.

Improved Performance of BiCMOS Inverter:

One serious disadvantage with BiCMOS inverter as shown in figure is that

there is no path through which base charge from n pn transistors can be
removed when they are turning OFF. Thus turn-off time for two n pn
transistor is relatively long. The solution to this problem is to include pull-
wosn transistors, as shown in figure.
 When npn transistors are turned OFF, the stored base charge can be
removed to ground through R1, and R2.

 An added advantage of this circuit is, when V in goes high and output
goes low, the very small output current through Q N and R2 means the
output voltage is pulled to ground potential.

 Also, as Vin goes low and output goes high, the very small load current
means that the output is pulled up to essentially v DD through the
resistor R1.

 The below figure shows the way in which R 1 are implemented nMOS
devices QR1 and QR2 are used to realize R1 and R2.

 And these two transistors are made to conduct only when needed. The
QR1 conducts only, when Vin rises. At which time its drain current
constitutes a reverse base current for Q11 speeding up its turn off.

 Similarly RQ2 will conduct only when Vin falls and Qp conducts, pulling
the gate of QR2 high.