Interview questions

Intel
General
* Non blocking vs blocking. How are they interpreted in hardware? Why shouldn’t the non
blocking be used everywhere?
* Leakage in sub micron technologies. What can be done to prevent leakage?
* High performance - what circuit design methodologies can be used?
* How to resolve set up and hold time violations?
* Which of the above violations do we get when supply voltage is increased or decreased?
* High K dielectrics?
* Inverter using NAND? 3 different ways ?
http://www.ccse.kfupm.edu.sa/~elrabaa/coe202/Lessons/Lesson2_6.pdf
* Synthesis flow? What files are needed for synthesis and what information do they contain?
* 4x+1 -> Design a logic
* Difference between signal and a variable in VHDL
* Advantages of pipelining
* Voltage scaling in sub-micron technologies?
* Why does shrinking of transistors cause an increase in temperature/power dissipation, even
though voltage does not scale after a certain level
* At what stage in the design do we need to rectify the hold time violation?
* What does the Environment file contain?
* What are wire load models? what do they contain or represent?
* Difference between single,multi and many cores?
* Out of order execution
* Can branch prediction be used for any processor or just for of order execution processors?
* Difference between Write back and write through
* Why L1 caches are smaller than L2 and L3 caches?
* Which cache (1,2 or 3) has got highest associativity and why?
* What is the ideal output resistance of an op amp?
*****************************************************************************
* cell library design - what topology was used for laying out the d flip flop. Was it Nand or
transmission gate based?
* For sub-micron technologies how will the cell library design vary?
* How to obtain minimum area for any design?
* Does a library file having large number of cells necessarily give better speed and area?
* Pipelining Advantages and Disadvantages?
* Difference between Static and Dynamic Timing Analysis. Which one is fastest?
* What happens to MIS from 500nm to 32nm process?

Altera
Projects in the resume
ASIC/FPGA design flow
Different types of FSM coding styles. Explain the advantages and disadvantages for each of
them http://www.xilinx.com/itp/3_1i/data/fise/xst/chap02/xst02014.htm
Mux - equation, in terms of NAND gate
Digital Circuit given - Minimize the circuit (K Map)
Equation given - Minimize the circuit (K Map)
Sequence detector(1011)- FSM, Circuit and Verilog
Why do we use different types of state encoding. Advantage and disadvantage for each of them
How to implement a multiple bit (1011) sequence detector without FSM- Design a ckt (Ans: Shift
reg and a AND gate)
Verilog code for 8 bit Shift Register - Serial In and Serial Out with parallel synchronous load and
a valid signal which goes high for every 8 bits
Verliog code for a DFF with negedge clock and async reset
Given a D flip flop and an external enable signal. Design a logic to make it a Enable based D flip
flop
Set up and Hold Time questions
Latch Inference in verilog code
All gates in terms of NAND gate
Blocking vs Non blocking assignements
http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf
Metastability, Clock domain Crossing issues, FIFO design, Gray Counter?
Volume control question -2 sensors. design a ckt to control volume(direction(flip flop), counter)
What are the different types of variables in perl?

Marvell
ASIC design flow - Overview
Synthesis and PR flow - In detail. Including files required, generated, commands and design
constraints
Blocking vs Non Blocking
Difference between flops and latches?
Design an Edge detector circuit
Design a 2 input (each input 2 bits) multiplier circuit
What are different ways by which setup and hold violations occur and what are the different
ways by which by which you can get rid of them(Think in terms of skew, operating conditions,
frequency, combinational logic delay, jitter and clock tree)
If a designer is given a choice to choose only one violation to correct, either setup or hold.
Which one to consider and why?
After a chip comes back and when checked if it fails, it is either due to one of the following:
setup, hold or logical functionality violation. How do you determine which caused the chip not to
work?
If a chip has setup time violation, how do we still run it at the desired frequency?
Given a best case and a worst case library, which will you use for timing analyses of setup and
hold?
Clock Domain Crossing - Metastability and synchronizers
Equations for minimum clock period based on skew and neg edge triggered capturing flop
How do you constrain paths across multiple clock domains?
Explain the concept of static timing analyses? What are the different timing paths in a design
and how do you constraint them?
Dynamic Logic - Basic idea
Cross talk - Why and when does it occur. What are the ways by which it can be minimized?
Describe how Shielding minimizes cross talk
Antenna Effect - Same questions as for crosstalk
Perl question - How to replace a word from a file using regular expressions
C question - Swapping of 2 variables without a temporary variable
Logical Effort and Transistor Sizing - Basic Idea
Considering a series of transistors, where do we place the signal arriving late and why?
What is meant by Latch up. How to prevent it?
What is meant by Fanout of 4
What happens when a signals slew rate is slow ? What cases can cause a signal transition to
be slow? How can you increase the slew rate?
Design a circuit to compare 2 four bit inputs (eg.1100 and 1010)
Is there a problem in this code:
always@(posedge clk)
a=b
always@(posedge clk)
b=a
Why is pmos width a certain ratio of nmos? What is the ratio?
Given 2 flops. In between there are 2 combinational paths. One path contains 2 NAND and 1
Inverter. Other path contains 2 NAND. Which path will the tool select for analyzing setup and
hold?
What are the various timing constraints and exceptions given to Synopsys DC? Explain each of
them?
How to calculate Power ring widths?
How did you do timing closure?
What is meant by DRC and LVS? Why do we need to do it? What files were needed to do it?
What will you do if there is a timing violation after Place and Route?
What is meant by global and detailed route?
What are the different types of adders? Explain the basic principle for each of them?