红米Note元件分布图-TOP D903

XJ601 (ALS&PS)
(PH_JACK) (VIETMOBILE.VN)
D601
(S_MIC)
X701
(26MHz) U805
TCXO
26MHz
U705
(Transceivers)
MTK6166 D901
TD-SCDMA (3-Axis
GGE GYROSCOPE)

U201(AP+BP) D1001
MTK6592V 39V BL Driver
A7八核1.7G

U401 D402
PMIC (Switch
MT6333 Charger)

U701
U501
(SW+PA)
DDR2_2G
SKY77594

U301 U302
XJ1105 PMIC U502
PMIC+AUDIO
(BAT_CONN DC-DC EMMC 8G
MT6322GA
 红米Note元件分布图-BOT

(VIETMOBILE.VN)

XJ1201
XJ1202
F_CAMERA
(M_CAMERA_
CONNECT)

U801 D902
MT6625N (COMPASS)
(WIFI/BT/FM/
GPS)

XJ1002
XJ1001 TP_CONNECT
(MAIN
LCD/BL)

D602
AUDIO PA)

D1102
Haptic Driver
XJ1106
SIDE KEY

XJ1101 XJ1104 XJ1102

(SIM1_ (TF_ (SIM2_
CONNECT) CONNECT) CONNECT)
 红米Note TD&W 主板逻辑框图 2G(TD)_LB/HB
U702

(VIETMOBILE.VN) X701
3GB1_RXP/N XJ701

26MHz
D701 W_PA_OUT_B8 U704
U705
W_PA_LB_IN W900_TRX
B8_PA B8
U701
MT6166
GGE_PA_LB_IN

MIPI CAM_DATA*8/CLK*2
EMI
MIPI_RD*8/RC*2 SKY77593/4

XJ1202
GGE_PA_HB_IN
1204/5
RF IC
RST/PDN/I2C RST/PDN/I2C
/6/7/8
W_PA_B1_IN D702 W_PA_OUT_B1 U703 W2100_TRX
PA&SWITCH
B1_PA B1

MIPI SUB_CAM_MD*4/MC*2 3GB8_RXP/N

MIPI_RD_A*4/RC*2

XJ1201
I2C1 SCL1/SDA1/CMMCLK1 EMI1201

BSI-A_D_0/1/2
RX_BBIQ*4

DCOC_FLAG
BSI-A_EN/CK

TX_BBIQ*4
CLK1_BB
F /2/3

32.768KHz
X301
U201 MT6592V/W
REC601
POWER_KEY
1.4/1.7G Hz
D1102 AU_HSP/N XJ1106 ECKE/ECS0/1EDCLK
VIBIR_PMU
Modem Analog
RX TX U501
AU_VIN2_P/N SYSRST_B/WATCHDOG_B ADC APC AFC External
D601
ADC
Memory ED(32bit) LPDDR2
Interface EA(10bit)
D603 SW_EN AUD_CLK/DAT_MOSI/MISO
Modem 1/2G
HP_L/R/MIC HP_L/R SW GSM/GPRS/
XJ601 HSPA+ EDGE
DSP
AU_VIN1_P/N
U301
PMIC_SPI_CS/SCK/MISO/MOSI
eMMC RST/ CMD/CLK
U502
HPL
AU_

SPK_P/N
SPK_P/N PMIC Modem MCU
PowerVR™ eMMC_DAT*8
eMMC
M_MIC D602 Analog
AMP SPK_EN AUDIO EINT_PMIC/RTC32K_CK GP Timer Cache TCM JTAG
SGX544 8G
KPLED
USB_V/D+D- XJ1103 KPLED CODEC Graphics PLL
accelerator
AU_VIN0P/N/MICBIAS0 MT6322 CHG_DP/M SIM1/2_CLK/IO/RST Internal ARM® MC1CK/CM

Cortex-R4 DMA
USB_DP/M Memory XJ1104
DAC MC1DA*4
SIM1/2_CLK/IO/RST

LED1101 (RGB)

XJ1101 XJ1102
Power
Management ADC
Multimedia SCL0/DA0 LCM
VBUS ISENSE
XJ1105
BATT
D402 SCL1/SDA1 EXT_PMIC_EN
JPEG Image EINT_CTP_RST
Capacitive Touch Screen
1080P
Codec Post-process
Video
LCD

EMI1001
ARM®

2/3/4/5
Codec
MIPI_TC/D*8
Camera LCD Control Trust Zone® XJ1001
ISP
GPIO19_CHG_EN GPIO93_DRVVBUS LPTE/LRSTB LCD_ID1

U401 PWM
TP XJ1002
FV1201 VLED(FLASH) SCL1/SDA1/EINT0_MT6333 LED_S1/2
PMIC GPIO120_EN D1001 VLED_P
MT6333 ARM® ARM® ARM® ARM®
Cortex- Cortex- Cortex- Cortex-
U805 XOIN EINT_6628_WIFI/BGF A7 MP A7 MP A7 MP A7 MP EINT1_A
BT/WL_ANT

AP MCU
26M Core TM Core TM Core TM Core TM
NEON

L2 Cache

D903
GPS_RX_IQ ALS&PS
WBG_ANT
GPS_ANT SA1001 U801 WB_TX_IQ ARM® ARM® ARM® ARM® SDA2/SCL2 D902
MT6627 Cortex- Cortex- Cortex- Cortex- M SENSOR
BT/WIFI/FM/G WB_RX_IQ A7 MP A7 MP A7 MP A7 MP
GPS_RF EINT3/5
D802 D801 PS Core TM Core TM Core TM Core TM
EINT20_GY/EINT11_G
D901
A&GYROSENSOR
WB_SCLK/DATA/EN FM_DATA/CLK
(VIETMOBILE.VN)
(VIETMOBILE.VN)
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

R119 0R
0201 BUCK1_FB [4]

DVDD12_EMI

M11
U11
U12
1.2V IO for DDR2

T13
T16
T17
T18
T21

V11
V12
V13
U201-B R101 0R
0603 VM12_SW_PMU
T11 H18

DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS DVDD12_EMI
R11 DVSS DVDD12_EMI H16
R2 DVSS DVDD12_EMI H15
G6 DVSS DVDD12_EMI G9
G7 G11 100nF 100nF 100nF 100nF 10uF 10uF
DVSS DVDD12_EMI 0201 0201 0201 0201 0603 0603
G14 DVSS DVDD12_EMI G13
G17 DVSS DVDD12_EMI G15
G20 DVSS DVDD12_EMI G16 C142 C143 C144 C151 C130 C135
H10 DVSS DVDD12_EMI G18 GND GND GND GND GND GND
M20 DVSS DVDD12_EMI H8
N11 DVSS DVDD12_EMI E7 Bottom cap/1st cap group
A19 DVSS DVDD12_EMI F7
A26 DVSS DVDD12_EMI F8
B4 DVSS DVDD12_EMI G8 check MSDC1/2 check MSDC1/2
B10 DVSS DVDD12_EMI H11 IO power C115 close to pin E1 (150mil) IO power
E21 DVSS DVDD12_EMI H13 C125 close to pin G26 (150mil)
F6 0R
DVSS R108
B12 DVSS DVDD28_MSDC1 E1 DVDD28_MSDC1 0402 0R VMC_PMU
B14 V1 DVDD18_MSDC2 R105
DVSS DVDD28_MSDC2 R106 0402 VIO28_PMU
B17 DVSS DVDD28_BPI AD26 0402 0R VIO18_PMU
B22 DVSS DVDD18_IO1 U25 DVDD18_MSDC0
B24 DVSS DVDD18_MSDC0 G26
R109 0R
C4 DVSS DVDD18_IO0 L26 0402 VIO18_PMU
C8 DVSS DVDD18_IO1 Y26
C11 DVSS DVDD18_IO2 D1
C12 DVSS DVDD18_IO3 W1 For low-power testing proposal.
C16 AG13 100nF 1uF 100nF 100nF 100nF 100nF 100nF 100nF
C17
DVSS DVDD18_IO4 0201 0402 0201 0201 0201 0201 0201 0201 It can be cancel for cost-down proposal
DVSS
C18 DVSS VCCK R10
C20 DVSS VCCK P9 C125 C115 C116 C117 C123 C122 C127 C128
C C21
C22
DVSS
DVSS
VCCK
VCCK
L11
L12 C
C23 DVSS VCCK L13 GND
C25 DVSS VCCK L14 VCORE_SW_BB
D4 DVSS VCCK L15
D5 DVSS VCCK L16 VCORE_SW_BB
D7 L17 VCCK R112 0R
DVSS VCCK 100nF 100nF 100nF 1uF 1uF 1uF 10uF 10uF 0603 VCORE_SW_PMU
D9 DVSS VCCK M10 22uF
D11 M18 0201 0201 0201 0402 0402 0402 0603 0603 0603
DVSS VCCK
D13 DVSS VCCK N10
D15 DVSS VCCK N18 C104 C124 C131 C140 C152 C153 C129 C136 C137
D17 DVSS VCCK P18
D21 DVSS VCCK R9 GND Bottom cap 1st cap group
D24 DVSS VCCK R18
E5 DVSS VCCK T10
E8 DVSS VCCK U10
E10 DVSS VCCK V10
E18 DVSS VPROC_BB
F18 N12 VCCK_VPROC R104 0R
DVSS VCCK_VPROC 100nF 100nF 100nF 1uF 1uF 1uF 0603 VPROC_PMU
P21 N13 22uF 22uF 22uF
DVSS VCCK_VPROC 0201 0201 0201 0402 0402 0402 0603 0603 0603
L10 DVSS VCCK_VPROC N14
VCCK_VPROC N15
AE5 AVSS18_WBG VCCK_VPROC N16 C156 C157 C158 C148 C155 C154 C132 C133 C134
V7 AVSS18_WBG VCCK_VPROC N17
U7 AVSS18_WBG VCCK_VPROC P14 GND
W7 AVSS18_WBG VCCK_VPROC R15 Bottom cap 1st cap group
Y7 AVSS18_WBG VCCK_VPROC P15
AB6 AVSS18_WBG VCCK_VPROC R14
AB8 AVSS18_WBG VCCK_VPROC R13
AC3 AVSS18_WBG VCCK_VPROC R12
AC5 AVSS18_WBG VCCK_VPROC R16
AC7 AVSS18_WBG VCCK_VPROC R17 To MT6323 GND_VPROC_FB pin
AD4 AVSS18_WBG VCCK_VPROC T14
AE3 AVSS18_WBG VCCK_VPROC T15 VPROC_BB
[3]
To MT6323 VPROC_FB pin
VCCK_VPROC U15
VCCK_VPROC U16
VCCK_VPROC V15
W20 AVSS18_MD VCCK_VPROC V16
U20 AVSS18_MD
(1)VPROC_BB, GND pin of 1st cap group should be laid differential
V20 AVSS18_MD pair with ground shielding remote sense to PMIC
V21 AVSS18_MD DVSS M15
U21 AVSS18_MD DVSS N21
W21 AVSS18_MD DVSS P10 (2)R107 & R103 must be close to 1st cap group.
Y20 AVSS18_MD DVSS P11 GND If you want to remove them,
Y21 AVSS18_MD DVSS P12
AA21 AVSS18_MD DVSS P13 please make sure the VPROC_FB/GND_VPROC_FB must connect from 1st cap. group of VPROC
AB21 AVSS18_MD DVSS P16
U17 AVSS18_AP DVSS P17
U18 AVSS18_AP DVSS L18
For low-power testing proposal. DVSS M14
It can be cancel for cost-down proposal GND A2 AVSS18_MEMPLL DVSS M13
R24 AVSS33_USB DVSS M12
DVDD18_MIPI
0R R111 AVDD18_MD_AP AE21 L2 0R R116
VIO18_PMU 0402 AVDD18_MD DVDD18_MIPITX 0402 VIO18_PMU
AE19 AVDD18_AP
G1 C111 C113
DVDD18_MIPIIO
VTCXO_PMU
0R
0402
R113 AVDD28_DAC AE22 AVDD28_DAC
For low-power testing proposal.
DVDD18_PLL AE18 T24 AVDD33_USB 0R R117 VUSB_PMU 0201 0201
0R R114 AVDD18_MEMPLL A3
DVDD18_PLLGP AVDD33_USB
P26 AVDD18_USB 0R 0402 R118 100nF GND
100nF GND
It can be cancel for cost-down proposal
VIO18_PMU 0402 AVDD18_MEMPLL AVDD18_USB 0402 VIO18_PMU
AC21 AVSS18_MD
0R R115 C112 AD22 H4
VIO18_PMU 0402 AVSS18_MD DVSS18_MIPIIO
AG26 AVSS18_MD DVSS18_MIPIIO H5 For low-power testing proposal.
C108 C109 0201 V17 J5
100nF V18
AVSS18_AP DVSS18_MIPIIO
J7 C120 C119 It can be cancel for cost-down proposal
AVSS18_AP DVSS18_MIPIIO
0201 0201 AA18 AVSS18_AP DVSS18_MIPITX L4
100nF 100nF C110
GND AB19 AVSS18_AP DVSS18_MIPITX M7 0201 0402
DVSS18_MIPITX M8 100nF 1uF
0201 100nF AF3 N3
AVSS18_WBG DVSS18_MIPITX
AG1 AVSS18_WBG GND GND

DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
GND GND
GND

MT6592/VFBGA475/P0.4/B0.25/10.6X11(S1+S2+S3+S4+S5+S6+S7+S8+S9)TRUED:¤º³¡-p¹ºMT6582M82M_WTG_REF_SCHV0.153MT6588_MT6166_MT6625_MT6323_MT6333_EMMC_LPDDR2_WTG_V016TEMP.DSN
T12
M16
K21
M17
H12
J21
H20
H17
H14
V14
AVDD18_MEMPLL pin and AVSS18_MEMPLL pin should
be connected with PCB CAP first, and then connected
with PMU and PCB ground. CAP should be near MT6592
GND
as possible as we can.

B B

A A

COMPANY:
<Loncheer>
TITLE:

DRAWN: DATED:
<T8850&W8850>
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <1.0>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 1OF 12
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

SH201

1
GND
U201-A

SH-T8850-BB TX_BBIP
[7] AF22 UL_I_P BPI_BUS0 AB24 BPI_BS0
[7]
TX_BBIN
[7] AF21 UL_I_N BPI_BUS1 AB23 BPI_BS1
[7]
TX_BBQP
[7] AG20 UL_Q_P DVDD28_BPI
BPI_BUS2 AD25 BPI_BS2
[7]
TX_BBQN[7] AF20 UL_Q_N BPI_BUS3 AC24 WG_GGE_PA_ENABLE [7]
BPI_BUS4 AC23
AE25 U201-D
BPI_BUS5
BPI_BUS6 AD24
ED[0:31]
BPI_BUS7 AF16 W_PA_B1_EN [7]
AA17 [5] LPDDR2 ballmap
BPI_BUS8
BPI_BUS9 AD16 ED31 C26 RDQ31 RCS0_B B7 ECS0_B [5]
RX_BBIP
[7] AG25 DL_I_P BPI_BUS10 AC16 W_PA_B8_EN [7] ED30 C24 RDQ30 RCS1_B B6 ECS1_B [5]
RX_BBIN
[7] AG24 DL_I_N BPI_BUS11 AF15 ED29 A25 RDQ29
RX_BBQP
[7] AG22 DL_Q_P BPI_BUS12 AC17 ED28 B25 RDQ28 RCKE B5 ECKE [5]
RX_BBQN
[7] AG23 DL_Q_N BPI_BUS13 AB17 ED27 B26 RDQ27
BPI_BUS14 AC15 ED26 B23 RDQ26
BPI_BUS15 Y15 ED25 A23 RDQ25 RDQM0 D16 EDQM0 [5]
ED24 D25 RDQ24 RDQM1 D18 EDQM1 [5]
DVDD18_IO4 ED23 A11 RDQ23 RDQM2 D10 EDQM2 [5]
VM0 AG14 VM0 [7] ED22 A14 RDQ22 RDQM3 D23 EDQM3 [5]
VM1 AF14 VM1 [7] ED21 A13 RDQ21
ED20 D12 RDQ20 RDQS0 F15 EDQS0 [5]
BSI_EN AD14 BSI-A_EN
[7] ED19 A10 RDQ19 RDQS1 F17 EDQS1 [5]
AF25 VBIAS BSI_CLK Y14 DVDD12_EMI ED18 B13 RDQ18 RDQS2 F12 [5]
BSI-A_CK
[7] EDQS2
WG_GGE_PA_VRAMP [7] AE24 APC BSI_DATA0 AB14 BSI-A_DAT0
[7] ED17 C10 RDQ17 RDQS3 E20 EDQS3 [5]
BSI_DATA1 AA14 BSI-A_DAT1[7] ED16 B11 RDQ16
AE14 AC14 100nF ED15 D22 E15
DCOC_FLAG
[7] TXBPI BSI_DATA2 BSI-A_DAT2
[7] R209 0201 RDQ15 RDQS0_B EDQS0_B [5]
ED14 B20 RDQ14 RDQS1_B E17 EDQS1_B [5]

0201
ED13 D20 RDQ13 RDQS2_B E12 EDQS2_B [5]
C205 ED12 A22 RDQ12 RDQS3_B F20 EDQS3_B [5]
ED11 C19 RDQ11
8.06K EVREF ED10 B19
[2,5] EVREF RDQ10
R211 ED9 A20 RDQ9 RCLK0_B F9 EDCLK_B [5]

MT6592/VFBGA475/P0.4/B0.25/10.6X11(S1+S2+S3+S4+S5+S6+S7+S8+S9)TRUED:¤º³¡-p¹ºMT6582M82M_WTG_REF_SCHV0.153MT6588_MT6166_MT6625_MT6323_MT6333_EMMC_LPDDR2_WTG_V016TEMP.DSN
100nF 1uF ED8 B21 E9
SCL0 [2,10] 0402 RDQ8 RCLK0 EDCLK [5]

0201
0201 ED7 B16
SDA0 [2,10] RDQ7
SCL1 [2,3,4,12] ED6 A17 RDQ6
SDA1 [2,3,4,12] C206 C207 ED5 B18 RDQ5
8.06K
SCL2 [2,9] GND GND GND ED4 A16 RDQ4 RA0 B8 EA0
ED3 B15 B9 EA1
C SDA2 [2,9]
ED2
ED1
C15
D14
RDQ3
RDQ2
RA1
RA2 D8
A8
EA2
EA3
C
RDQ1 RA3
ED0 C14 RDQ0 RA4 A7 EA4
Pin DVDD18_EFUSE FSOURCE_P Description RA5 C7 EA5
RA6 A5 EA6
VGPx (2V0) w/i EFUSE program [2,5] EVREF F16 VREF RA7 D6 EA7
Voltage RA8 C6 EA8
GND w/o EFUSE program RA9 A4 EA9
MT6333 switching charger function de-feature

REXTDN
EINT11_G
[9] (Need to add external SWCHR)
EINT14_CTP_RST
[10] Change notice: A1 TP_MEMPLL REXTDN B3
TP206 URXD2
EFUSE Notice Page 2 R221
UTXD2 EINT16_SUB_CMRST
[12]
TP205 EINT17_IDDIG
[11] 1. Add GPIO_CHG_EN/GPIO93_DRVVBUS trace

0402
EINT18_SUB_CMPDN
[12]
GPIO19_CHG_EN
[4]

MT6592/VFBGA475/P0.4/B0.25/10.6X11(S1+S2+S3+S4+S5+S6+S7+S8+S9)TRUED:¤º³¡-p¹ºMT6582M82M_WTG_REF_SCHV0.153MT6588_MT6166_MT6625_MT6323_MT6333_EMMC_LPDDR2_WTG_V016TEMP.DSN
TP204 URXD1 EINT20_GY
[9]
Please reserve UART0/1 test point 54.9R 1%
KCOL0
[11] GND
UTXD1
UART0 for AP log TP203 KROW0 [11]
KCOL1 [11]
UART1 for MD log TP202 URXD0

TP201 UTXD0 GPIO93_DRVVBUS

[4]

AD10

AD13

AA13
AC11

AC10

AC13
AE10

AB13

AE13
AF10
AA3

AD8

AA1
AA2

AD7

AG8
AC8
AC9
AB3

AE7

AB9

AE9
T23
R23

AF8

Y13
P23
P22
W2

U2
Y2

V2
U201-C
MT6605 OSC_EN (SRCLKENAI) need to default low

UTXD0
URXD0

UTXD1
URXD1

UTXD2
URXD2

UTXD3
URXD3

SCL0
SDA0
SCL1
SDA1
SCL2
SDA2

SPI_CS
SPI_MO
SPI_MI
SPI_CK

EINT11

EINT14
EINT15
EINT16
EINT17
EINT18
EINT19
EINT20

KPCOL0
KPROW0

KPCOL1
KPROW1

KPCOL2
KPROW2
for MT6605 TESTMODE boot-strap
[7] CLK1_BB AF26 CLK26M
DVDD18_IO3 DVDD18_IO1 M25
SYSRSTB NC SYSRST_B
[2,3]
[3] RTC32K_CK RTC32K_CK L25 RTC32K_CK 0402
AF11 TESTMODE SRCLKENAI M24 C208 are for ESD ehnhace proposal.
GND R5 N25 C208
R4
FSOURCE_P SRCLKENA SRCLKENA
[3,4,7] It can be cancel for cost-down proposal
DVDD18_EFUSE
[3] WATCHDOG_B N26 WATCHDOG PWRAP_SPI0_CSN J23 GND
PMIC_SPI_CS
[3]
PWRAP_SPI0_CK H23
TP213 TP209 PMIC_SPI_SCK
[3]
SYSRST_B
[2,3] AF12 JTCK PWRAP_SPI0_MI J24
PMIC_SPI_MISO[3]
TP210 AE12 JTDO PWRAP_SPI0_MO H22
PMIC_SPI_MOSI[3]
PWRAP_INT H24
TP211 EINT_PMIC
[3]
AG11 JTDI
K26 U201-E
AUD_CLK_MOSI AUD_CLK
[3]
TP212 AF13 JTMS AUD_DAT_MISO K25
AUD_DAT_MISO
[3]
AUD_DAT_MOSI J25 [10] M3 TCP LCM_RST U3
USB_VRT AUD_DAT_MOSI
[3] MIPI_TCP LRSTB
[10]
GND 0201 P25 USB_VRT [10] M4 TCN DSI_TE Y3
R201 5.1K MIPI_TCN LPTE
[10]
GPIO12 AG10 GPIO12_HAPTIC_PWM [11] [10] M1 TDP0 DISP_PWM AD9
MIPI_TDP0 PWM[10]
[11] USB_DP R26 USB_DP GPIO13 AF9 M2 TDN0
Close to MT6592 [10] MIPI_TDN0
[11] USB_DM R25 USB_DM [10] P2 TDP1
90 Ohm MIPI_TDP1
SIM1_SCLK L21 SIM1_SCLK [3] [10] N2 TDN1 GND
MIPI_TDN1
differential SIM1_SIO K23 SIM1_SIO [3] [10] P1 TDP2
MIPI_TDP2
SIM1_SRST L23 SIM1_SRST [3] [10] MIPI_TDN2
R1 TDN2 0201
SIM2_SCLK L20 SIM2_SCLK [3] For earpohne & MSDC hotplug EINT, [10] MIPI_TDP3
N5 TDP3
SIM2_SIO L24 SIM2_SIO [3] M5 TDN3
plase choose EINT0~15 MIPI_TDN3

C222
[10]

NC
N23 CHD_DP SIM2_SRST K24
[3] CHD_DP SIM2_SRST [3] 0R R222
[3] CHD_DM N24 CHD_DM with HW de-bounce function. K6 RCP CMMCLK B2 0402
[12] MIPI_RCP CMMCLK1
[12]
EINT0 W22 EINT0_MT6333[4] K5 RCN CMPCLK B1
[12] MIPI_RCN
EINT1 V22 L3 RDP0
EINT1_A
[9] [12] MIPI_RDP0
EINT2 AA24 K3 RDN0 CMDAT0 E2 GPIO120_EN [10]
EINT2_CTP
[10] [12] MIPI_RDN0
EINT3 V24 K1 RDP1 CMDAT1 F2
EINT3 [9] [12] MIPI_RDP1
EINT4 W25 K2 RDN1
EINT4_HP
[6] [12] MIPI_RDN1
EINT5 Y25 EINT5 [9] J1 RDP2_
[12] MIPI_RDP2
EINT6 AA23 GPIO6_SPK_EN [6] J2 RDN2_
DVDD18_IO1 [12] MIPI_RDN2
EINT7 AA26 GPIO_HAPTICS_EN [11] G2 RDP3_
Please reserve bypass cap DVDD18_IO3 [12] MIPI_RDP3
V5 I2S_BCK EINT8 AA25 LCD_ID1 [10] H2 RDN3_
[12] MIPI_RDN3
for AUX_ADC decoupling (from Antenna) proposal. U5 I2S_LRCK EINT9 Y23 EINT9_MAINCAM_RST
[12]
[6] GPIO105_SWITCH_EN W5 I2S_DATA_IN EINT10 Y22 EINT10_AF_EN
[12] [12] F5 RCP_A_
MIPI_RCP_A
It can be cancel for cost-down proposal [12] MIPI_RCN_A
G5 RCN_A_
VIO18_PMU PCM_CLK V23 G4 RDP0_A
[12] MIPI_RDP0_A
PCM_RX V26 G3 RDN0_A
[12] MIPI_RDN0_A
PCM_SYNC V25 [12] MIPI_RDP1_A J3 RDP1_A
[3] AUX_IN0_NTC AC19 AUX_IN0 PCM_TX U24 [12] MIPI_RDN1_A H3 RDN1_A
[3] AUX_IN1_NTC AD19 AUX_IN1
100pF 100pF
R217 R218 0201 0201 MIPI_VRT
AF18 AUX_XP N1 VRT
AG17 AUX_XM
0201

0201

C209 C210 AF17 DVDD28_MSDC2 DVDD28_MSDC1 DVDD18_MSDC0 R203

AUX_YP

MT6592/VFBGA475/P0.4/B0.25/10.6X11(S1+S2+S3+S4+S5+S6+S7+S8+S9)TRUED:¤º³¡-p¹ºMT6582M82M_WTG_REF_SCHV0.153MT6588_MT6166_MT6625_MT6323_MT6333_EMMC_LPDDR2_WTG_V016TEMP.DSN
GND GND AG16 AUX_YM

0201
4.7K 4.7K

MSDC2_DAT3
MSDC2_DAT2
MSDC2_DAT1
MSDC2_DAT0

MSDC1_DAT3
MSDC1_DAT2
MSDC1_DAT1
MSDC1_DAT0

MSDC0_DAT7
MSDC0_DAT6
MSDC0_DAT5
MSDC0_DAT4
MSDC0_DAT3
MSDC0_DAT2
MSDC0_DAT1
MSDC0_DAT0

MSDC0_RSTB
REFP AG19
B B

MSDC2_CMD

MSDC1_CMD

MSDC0_CMD
[2,9] SCL2 REFP

MSDC2_CLK

MSDC1_CLK

MSDC0_CLK
[2,9] SDA2 AF19 AVSS_REFN
1uF 1.5K 1%
0402 GND
VIO18_PMU
C213
MT6592/VFBGA475/P0.4/B0.25/10.6X11(S1+S2+S3+S4+S5+S6+S7+S8+S9)TRUED:¤º³¡-p¹ºMT6582M82M_WTG_REF_SCHV0.153MT6588_MT6166_MT6625_MT6323_MT6333_EMMC_LPDDR2_WTG_V016TEMP.DSN
Close to MT6592
T2
T1
T5
T6
R7
T3

D3
C2
D2
E4
C3
E3

F22
E23
F24
G24
E26
E25
G23
G22
D26
E24
G25
GND EMMC_RST
[5]
[11] BAT_INF EMMC_CMD
[5]
R210 R212 C213 Close to MT6582 EMMC_CLK
[5]
AF19 should connect to C213.2 first, EMMC_DAT0
[5]
0201

0201

EMMC_DAT1
[5]
than connect to GND by via EMMC_DAT2[5]
1K EMMC_DAT3
[5]
[2,3,4,12] SCL1 1K
EMMC_DAT4[5]
[2,3,4,12] SDA1 EMMC_DAT5[5]
EMMC_DAT6[5]
EMMC_DAT7[5]

VIO18_PMU
MC1CM [11]
MC1CK [11]
MC1DA0 [11]
MC1DA1 [11]
R219 R220 MC1DA2 [11]
MC1DA3 [11]
0201

0201

4.7K 4.7K
[2,10] SCL0
[2,10] SDA0

A A

COMPANY:
<Loncheer>
TITLE:

DRAWN: DATED:
<T8850&W8850>
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> A0
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 2OF 12
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

I2C Address U302 placement, please be close to MT6322

FAN53555 : 0xC0 L307 placement, please be close to L301
NCP6335D: 0x1C
VBAT

U302
GND B4 AGND AVIN D1 2
0402
A2 D2 4.7uF
D [8] ANT_SEL1

[8] ANT_SEL2 A1
EN

VSEL
PVIN
PVIN
PVIN
E1
E2 L307 1
C337
C337 must to be close
to U302
D
GND
B3 POWER_FAIL SW D3
U301 D4 N122857314
MT6322 B2 INTERRUPT
SW
SW E3 As short asVPROC_PMU
possible and L307 as close as possible to L301,
E4 0.47uH
SW then connect to VPROC_PMU
GND
VBAT C1
PGND
SPK_P K1 PGND C2
SPK_N L1 PGND C3 GND
P1 PGND C4
2.2uF 10mil VBAT_SPK
[2,4,12] SDA1 B1
0402 SDA
L2 GND_SPK AU_HSP H1 AU_HSP [6] [2,4,12] SCL1 A3 SCL FB A4 VPROC_BB [1,3]
GND AU_HSN G1 AU_HSN [6]

D:¤º³¡-p¹ºMT6582M82M_WTG_REF_SCHV0.20_ADDEXTBUCKMT6592_MT6166_MT6625_MT6322_MT6333_EMMC_LPDDR2_WTG_V020.DSN
NCP6335
C336 NCP6335 / FAN53555 VPROC_FB should be ground shielding.
GND AU_HPL H4 AU_HPL [6]
MICBIAS0 F2 AU_MICBIAS0 AU_HPR J4 AU_HPR [6]
MICBIAS1 G2 AU_MICBIAS1
if you use digital MIC, 100nF
0201 E4 E9
please change cap (C241) [6] AU_VIN0_P AU_VIN0_P AUDIO DRIVER ISINK0 ISINK0[11]
[6] AU_VIN0_N F4 AU_VIN0_N ISINK1 C9 ISINK1[11]
to 1.0uF C312 ISINK2 E10 ISINK2[11]
GND G3 C10
[6] AU_VIN1_P AU_VIN1_P ISINK3 KPLED [11]
[6] AU_VIN1_N G4 AU_VIN1_N
Symbol LPDDR2/1.2V PCDDR3L/1.35V PCDDR3/1.5V LPDDR1/1.8V Default
[6] AU_VIN2_P D2 AU_VIN2_P
Reserved for desense tuning proposal.
SPI_CSN H L (20K) H L (20K) PU [6] AU_VIN2_N D1 AU_VIN2_N It can be cancel for cost-down proposal
VA_PMU GND
AUD_MOSI L H (20K) H (20K) L PD 1uF J2 AVDD28_ABB
0402 D3
1uF AVDD28_AUXADC C354
H2 GND_ABB
C313 0402 C333 are for VPROC_FB decoupling proposal.
GND 0402 It can be cancel for cost-down proposal
C314 NC
E2 L301
[6] ACCDET ACCDET BUCK OUTPUT
GND C14 VPROC_PMU
E1
VPROC
D14
70mil 4.7uF
[7] CLK4_AUDIO CLK26M VPROC 0.68uH 0402
VPROC E14
Connect to MT6166 XO4 pin directly
MT6333 switching charger function de-feature (Need to add external SWCHR) C333
Change notice: VPROC_FB B12 GND VPROC_BB [1,3]
CHARGER C12
[3]
BATSNS GND_VPROC_FB
Page 3 P13 BATSNS
ISENSE
[3,4] P12 ISENSE VPA A14 From 1st cap. group of VPROC on MT6582 side
1. Add R335, MT6322 pin N13 (CHRLDO) connect to R335, then connect to VBUS_1 BAT_ON
[3] BAT_ON K3 B14 GND
BATON VPA
2. R330.1 connect to VUBS_1 VCDT
[3] VCDT A12 VCDT
VPROC_FB, GND_VPROC_FB should be laid differential
M13 VDRV VPA_FB D12 pair with ground shielding remote sense to PMIC
L301 / L302 / L303
VBUS
R335 3.3K CHR_LDO N13
Please use inductor recommand by MTK
VBUS 0402 CHRLDO
0402 0402
L303 Refer to MT6323 design notice
TP1 VSYS H14 VSYS_PMU
R330 VCDT rating: 1.268V 25milNC
C317 CONTROL SIGNAL 0402 0.68uH
C316
0402

NC M2 PWRKEY
1uF A1 C356
[2] WATCHDOG_B SYSRSTB
GND [2] SYSRST_B K4 RESETB GND
330K/1% ALDO OUTPUT
A9 M3 VA_PMU
VCDT
[3]
Close to PMIC GND GND
A7
FSOURCE VA 6mil
[2] EINT_PMIC INT
N12 EXT_PMIC_EN VCN28 N3 8mil VCN28_PMU
C317 is for noise decoupling proposal. [4] EXT_PMIC_EN VCAMA_PMU VA_PMU
R325 VTCXO L4 VTCXO_PMU
N2 6mil
It can be cancel for cost-down proposal PMU_TESTMODE
0402

P3 12mil 1uF 1uF

VCAMA VCAMA_PMU 0402 0402
[11] PWRKEY GND [2] AUD_DAT_MOSI E7 M6 VCN33_PMU
E8
AUD_MOSI VCN33
C3
350mA 12mil
[2] AUD_CLK AUD_CLK AVDD33_RTC VRTC

470nF
MT6166 side MT6322 side 4mil
Backup Batt.

0201

C335
39K/1% [2] AUD_DAT_MISO B6 AUD_MISO C352 C353
GND TP2
C159 C321 A2 GND GND GND
[2,4,7] SRCLKENA SRCLKEN DLDO OUTPUT
Plasse reservr R331/NTC301 & R339/NTC302 FCHR_ENB
M1 FCHR_ENB VRTC
No GPS NC 0.1uF VM J13 35mil
for thermal protection option TP301 D9 SPI_CLK VRF18 H11 15mil VRF18_PMU
Vbat should connect to C341 first, GPS co-clock 1uF 0.1uF [2] PMIC_SPI_SCK PMU side
[2] PMIC_SPI_CS
B7 SPI_CSN VIO18 L12 12mil VIO18_PMU
VBAT
then star-connetion to MT6323 w/ GPS [2] D8 SPI_MOSI VIO28 M4 8mil VIO28_PMU
VIO18_PMU GPS non co-clock 1uF 0.1uF PMIC_SPI_MOSI
B8 SPI_MISO VCN18 J12 12mil VCN18_PMU
VIO18_PMU [2] PMIC_SPI_MISO R310
K14 VCAMD_PMU
Star-connection Reserved C321 for no GPS application. VCAMD
L13
15mil

0201
VBAT INPUT VCAM_IO 6mil VCAMD_IO_PMU
R331 R339 F13 VBAT_VPROC
50mil 50mil 30mil 0R R360 F14
C 0402 30mil VBAT_VPROC
C
0402

0402

G13 P7 15mil 100nF 1K

30mil VBAT_VPROC VEMC_3V3 VEMC_3V3_PMU 0201
A13 VBAT_VPA VMC L6 8mil VMC_PMU
VMCH P4 12mil VMCH_PMU
39K/1% 39K/1% 20mil 0R R362 H13 N6 C318
20mil VBAT_VSYS VUSB 8mil VUSB_PMU

1
0402
12mil P8 VBAT_LDOS3 VSIM1 P9 VSIM1_PMU
[2] AUX_IN0_NTC [2] AUX_IN1_NTC 20mil 0R R363 P6 N9 6mil
22uF 0402 10mil VBAT_LDOS3 VSIM2 6mil VSIM2_PMU
NTC301 NTC302 0R R365 P5 L8
0402 10mil VBAT_LDOS2 VGP1 VGP1_PMU
Close to battery connector 0603 30mil 0R
0402
R364 P2 VBAT_LDOS1
6mil
12mil
0402

0402

VIBR M7 6mil VIBR_PMU

C341 0R R366 J14 N8 6mil
VSYS_PMU 0402 25mil AVDD22_BUCK VGP2 VGP2_PMU
M14 AVDD22_BUCK VGP3 L14 GB301

2
68K_NTC 68K_NTC SOD123 VCAM_AF N7
6mil VCAM_AF
GND GND GND PAS311HR
500mW DVDD18_DIG A8
VF : 4.85V~5.36V DVDD18_DIG
GND
VIO18_PMU
0R
0402
R367 A5 DVDD18_IO
For 32k-less, please change GB301(backup battery) to 22uF cap.
Recommend implementing 1~100uF for VRTC,

0402
Refer to MT6323 design For low-power testing proposal. [3,7] AUXADC_REF AUXADC_REF C2 AUXADC
AUXADC_VREF18 C320 DONOT implement the backup battery. (Because of the Time precision: +-1.5 sec every 30 sec)
notice for Zener selection It can be cancel for cost-down proposal [7] B1 AUXADC_AUXIN_GPS VREF P14
THERM_ADC
B2 AVSS28_AUXADC 100nF
C322 must to be close
For longer RTC time sustain after battery remove,
to MT6323 pin B1 C322 C321
BC 1.1 please refer to RTC design notice.
0402 0201 [2] CHD_DM A10 CHG_DM GND_VREF N14
1uF 100nF [2] CHD_DP A11 CHG_DP GND
Close to MT6322
GND_AUXADC GND
ISENSE
[3,4] GND
RTC_32K1V8 D5 RTC32K_CK [2]
SIM LVS RTC C4 RTC 32K :
RTC_32K2V8 X301
BATTERY CONNECTOR R328
0805
[2] SIM1_SCLK
[2] SIM1_SIO
B5
M11
SIM1_AP_SCLK
SIMLS1_AP_SIO
XIN
XOUT
A3
A4
32K_IN
32K_OUT (1) X301 / C324 / C319 = mount
56mR Connect X600 pin2 GND [2] SIM1_SRST E6 SIM1_AP_SRST
1 2
(2) R333 / R350 = NC
4.7uF 4.7uF 4.7uF 1uF
GND to MT6323 pin

0201

0201
4.7uF 0402 0402 0402 0402 0402 0603 0603 0402 0402 C5 B10
0201 BATSNS
[3] [2] SIM2_SCLK SIM2_AP_SCLK GND_ISINK C324 CRY_FC135 C319
B2 first then [2] SIM2_SIO K11 SIMLS2_AP_SIO GND_VSYS G11
R329 0R
AUXADC_REF [3,7] C309 C301 C302 C303 C304
C306 C311 C307 C308 [2] SIM2_SRST D6 SIM2_AP_SRST GND_VPA E13 RTC 32K-less (NOT MP yet)
1uF 1uF
connect E11
10uF 10uF
M9
GND_VPROC
F11
18pF 18pF (1) X301 / C324 / C319 = NC
to main GND (near pin B2) [11] SIM1_CARD_SCLK SIMLS1_SCLK GND_VPROC
VBAT R334
[11] SIM1_CARD_SIO N11 SIMLS1_SIO GND_VPROC F10 (2) R333 / R350 = 0R
[11] SIM1_CARD_SRST M10 SIMLS1_SRST
GND GND_LDO K6 GND
Close to MT6322 AUXADC_VREF18 PIN,
0402

[11] SIM2_CARD_SCLK K9 SIMLS2_SCLK GND_LDO K8

[11] SIM2_CARD_SIO L11 SIMLS2_SIO
and the path need shielding with GND K10 F5
16.9K/1% [11] SIM2_CARD_SRST SIMLS2_SRST GND_LDO
GND_LDO F6
40mil VBAT GND_LDO F7
F8

GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
[11] BAT_NTC 1K R332 F9
0402 BAT_ON [3] GND_LDO
GND GND_LDO G5
GND_LDO G6
0R/NC

MT6323/VFBGA145/P0.4/B0.25/5.8X5.8
R336 R333 PMU_32K [7]

J10
J9
J8
J7
J6
H10
H9
H8
H7
H6
H5
G9
G8
G7
0201
0402

GND R350 0R/NC

0201
Please refer to MT6322 design notice for
30K/1%
Buck GND layout rule

(1)MT6322 Buck GND(GND_VPROC/GND_VPA/GND_VSYS) is connected together first,

GND and then single trace connect to GND layer

(2)Use single trace >40mil or GND plan to connect buck input bypass cap Regulator Output Voltage(V) Output Current(mA) Input Decoupling Output Decoupling Notes
and MT6322 GND pins of buck in the same layer,
and then isolate this GND plan
VPROC 0.7~1.4 2800 >10uF L=0.68uH,C=10uF*4 Total outptu cap>40uF

VSYS 2.2 1200 >10uF L=0.68uH,C=10uF*2 Total outptu cap>20uF

VPA 0.5~3.4 600 >4.7uF L=2.2uH,C=2.2uF+2.2uF Output cap range 4.4uF +/-20%

LDO Output Voltage(V) Output Current(mA) Input Decoupling Output Decoupling Notes
B B
VM 1.24 /1.39/1.54/1.84 700 10uF -20%~+20% Far-end bypass cap

VRF18 1.825 200 1uF -20%~+200% Far-end bypass cap

VIO18 1.8 300 4.7uF -20%~+200% Far-end bypass cap

VCN_1V8 1.8 120 1uF -20%~+20% Far-end bypass cap

VCAMD 1.2 /1.3/1.5/1.8 150 1uF -20%~+20% Far-end bypass cap

VCAM_IO 1.8 100 1uF -20%~+20% Far-end bypass cap

VGP3 1.2 /1.3/1.5/1.8 200 1uF -20%~+20% Far-end bypass cap

VA 2.8 150 1uF -20%~+20% Far-end bypass cap

VTCXO 2.8 40 1uF -20%~+20% Far-end bypass cap

VCN28 2.8 30 1uF -20%~+20% Far-end bypass cap

VCAMA 2.8 150 3.2uF -20%~+20% 1uF near-end ,2.2uF Far-end bypass cap

VCN33 3.3/3.4/3.5/3.6 350 4.7uF -20%~+20% Far-end bypass cap

VIO28 2.8 200 2.2uF -20%~+200% Far-end bypass cap

VUSB 3.3 20 1uF -20%~+20% Far-end bypass cap

VMC 1.8 /3.3 100 1uF -20%~+20% Far-end bypass cap

VMCH 3.0 /3.3 400 2.2uF -20%~+20% Far-end bypass cap

VEMC_3V3 3.0 /3.3 400 4.7uF -20%~+20% Far-end bypass cap

1.2/1.3/1.5/1.8 /2.0
VCAM_AF 100 1uF -20%~+20% Far-end bypass cap
2.8/3.0/3.3

VSIM1 1.8 /3.0 50 1uF -20%~+20% Far-end bypass cap

VSIM2 1.8 /3.0 50 1uF -20%~+20% Far-end bypass cap

1.2/1.3/1.5/1.8/2.0
VGP1 100 1uF -20%~+20% Far-end bypass cap
2.8 /3.0/3.3
VGP2 1.2/1.3/1.5/1.8/2.0
100 1uF -20%~+20% Far-end bypass cap
2.5 /3.0/3.3
VIBR 1.2 /1.3/1.5/1.8/2.0
100 1uF -20%~+20% Far-end bypass cap Title
2.8/3.0/3.3 03 MT6592 - Power & MT6322
VDIG18 1.8 20 1uF -20%~+20% Far-end bypass cap Size Document Number Rev
A VRTC 2.8 2 0.1uF to 1000uF -20%~+20% Far-end bypass cap
Custom MT6592 PHONE V1.0 A
Date: Tuesday, July 30, 2013 Sheet 3 of 22
2 1

COMPANY:
<Loncheer>
TITLE:

DRAWN: DATED:
<T8850&W8850>
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number> <1.0>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 3OF 12
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

MT6333 switching charger function de-feature (Need to add external SWCHR)

Change notice:
Page 4
1. Delete R813/C839/U3/R817/R1812/C1815/R335
2. Change C1809 to 1uf
3. Add R341/C1810 for ESD protection
4. Delete ISENSE/BATSNS net GND
L1801 / L304 / L305 / L306
5. Change C1806 location (close to MT6333) GND GND GND
25V rating Please use inductor recommand by MTK
6. Add U402 and related circuits Refer to MT6333 design notice
C401 Height 1.1mm

D3
C5

C4

C3
U401 L406
0603
4.7uF

PGND_CHR

CHR_GATE

GND

AGND

N169012311

N169012321
B4 25mil 40mil 40mil
40mil LX
A5 CHRIN
B5 25mil 1uH
LX

C405

100nF
B3

0201
VBUS
BOOT A3

C402
0402
1uF
GND A2 DRVCDT CS D4
CS D5
40mil
GND R401 1K 1% C1
0201 ISET 40mil L403 40mil
BATSNS C2 VBAT

VIO18_PMU E4 40mil
25mil VBAT 10uF
A4 E5 10uF 10uF 0402
[12] VLED VLED VBAT 0402 0402
R406 Switching Charger C410
C409 C403
CloseGND
to L406

0201
GND GND
Buck Converter
4.7K
BUCK1_SW L401
E2 E3 VM12_SW_PMU
[2] EINT0_MT6333 INT VMEM_LX 38MIL 4.7uF
0.68uH
B2 BUCK1_FB 0402
VMEM_FB BUCK1_FB [1]
A1 SCL
[2,3,4,12]SCL1 B1 C411
[2,3,4,12]SDA1 SDA
Need pull-up resistor to VIO18
GND
L402
E1 SLEEP_B BUCK2_SW VCORE_SW_PMU
[2,3,7] SRCLKENA 4.7uF
0.68uH
F1 F5 0402
[3] EXT_PMIC_EN 0201 BUCK_EN VCORE_LX 50MIL
1K R407
VCORE_FB D1 VCORE_SW_BB C412

PGND_BUCK
PGND_BUCK
0201
GND

VRF_LX

VRF_FB
C413 47nF C411 / C412 are for VMEM_FB / VCORE_FB decoupling proposal.
GND It can be cancel for cost-down proposal

SETTINGSMTK03697DESKTOP20130110-2MT6582_MT6166_MT6627_MT6323_EMMC_LPDDR2_WTG_20130110-2.DSN
AND
MT6333/WLCSP30/P0.4/B0.25/2.1259X2.638C:DOCUMENTS
F3
F4

F2

D2
GND 15MIL

C C

CHARGE

B B

FAN5405 SUPPORT DOWNLOAD N/O BATTERY

C1308 NC FOR FAN5405 20130416

1uF C441

C440 0201
22pF

D402 1.0uH,¡À20%,1.9A[SPH252012H1R0MT] LQM2HPN1R0MG0 (1.0uH) [3]

VBUS A1 C1 ISENSE
[3,11] A2 VBUS SW C2
VBUS SW C3 L407
B1 SW C445 C446
B2 PMID A3
B3 PMID BOOT D1
0201 0201
C443

PMID PGND D2
NC
0201

4.7uF 0402 C442 100nF 22pF

PGND D3
[2,3,4,12] 6AH PGND
SCL1 A4
[2,3,4,12] B4 SCL E1
SDA1 C4 SDA CSIN E4 [3,4,6,7,9,10,11]
C450

STAT CSOUT VBAT

1uF
0402

GPIO93_DRVVBUS
[2] 0R R302 D4
0201 E2 OTG E3
[2] GPIO19_CHG_EN CD VREF

C447

R405 10K 0603

0201 22uF
0201

470K R1316 FOR FAN5405 SUPPORT DOWNLOAD N/O BATTERY

R301

FAN5405 I2C ADDR D4

A A

COMPANY:
<Loncheer>
TITLE:

DRAWN: DATED:
<T8850&W8850>
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number> <1.0>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 4OF 12
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

VDDI VCC VCCQ

SDIN8DE1-8G >=100nF <=100nF <=100nF
>=4.7uF >=4.7uF
Discrete LPDDR2

134 ball, 0.5mm pitch

VDD1=1.8V
VDD2=1.20V
VDDCA=1.2V
VDDQ= 1.20V
VDD1 : Core 1

DVDD18_EMI VIO18_PMU
0R
0402
R418
DVDD18_EMI VDD1=1.8V
EA[0:9]
[2] VDD2=1.20V
U501
EA0 P3 CA0 VDD1 B6
VDDCA=1.2V
EA1 N3 C1 VDD2 : Core 2
EA2 M3
CA1
CA2
VDD1
VDD1 R1 VDDQ= 1.20V
EA3 M2 CA3 VDD1 T6 DVDD12_EMI
EA4 M1 C542 C531
CA4
EA5 G2 CA5 VDD2 B5
EA6 F2 CA6 VDD2 D2 0402
2.2uF 0201
EA7 F3 G1 100nF Discrete eMMC (153 balls)
CA7 VDD2
EA8 E3 CA8 VDD2 J7
GND GND
EA9 E2 CA9 VDD2 P2
ED[0:31] T5
[2] VDD2
ED0
ED1
N8
M8
DQ0
C7
153 ball, 0.5mm pitch
DQ1 VDDQ
ED2 M7 DQ2 VDDQ C10
ED3 M9 DQ3 VDDQ D5
ED4 M6 Power E9
DQ4 VDDQ
ED5 L7 DQ5 VDDQ F10
ED6 L8 DQ6 VDDQ H6
ED7 L9 J6 C539 C540 C527 C528 C529 C530
DQ7 VDDQ
ED8 G9 DQ8 VDDQ M10
ED9 G8 DQ9 VDDQ N9 0402
2.2uF 0402 0201 0201 0201 0201
ED10 G7 P5 GND GND2.2uF 100nF
GND 100nF
GND 100nF
GND 100nF
GND
DQ10 VDDQ
ED11 F6 DQ11 VDDQ R7
ED12 F9 DQ12 VDDQ R10
C ED13
ED14
F7
F8
DQ13
DQ14
VDDQ K6 C
ED15 E8 DQ15 VDDCA F1
ED16 T7 DQ16 VDDCA H1 1. VCC : Core Voltage 2.7v ~ 3.6v
ED17 P6 DQ17 VDDCA N2 2. VCCQ : IO Voltage 1.7v~1.95v (low voltage range)
ED18 T8 DQ18
ED19 N5 DQ19 U502 2.7v~3.6v(high voltage range)
ED20 P7 DQ20
ED21 T9 DQ21 EMMC_DAT0 EMMC_DAT0 A3 E6 EMMC_VCC 0R R512
ED22 R8 [2] DAT0 VDDF 0402 VEMC_3V3_PMU
DQ22 EMMC_DAT1 EMMC_DAT1 A4 DAT1 VDDF F5
ED23 N6 DQ23 [2] EMMC_DAT2 A5 J10
ED24 E6 EMMC_DAT2 DAT2 VDDF
DQ24 [2] EMMC_DAT3 B2 DAT3 VDDF K9
ED25 C8 EMMC_DAT3
DQ25 [2] EMMC_DAT4 EMMC_DAT4 B3 DAT4
ED26 B9 DQ26 [2] EMMC_DAT5 B4 C6 EMMC_VCCQ 0R R513
ED27 D7 EMMC_DAT5 DAT5 VDD 0402 VIO18_PMU
DQ27 [2] EMMC_DAT6 EMMC_DAT6 B5 DAT6 VDD M4
ED28 E5 DQ28 [2] EMMC_DAT7 B6 N4
ED29 B8 EMMC_DAT7 DAT7 VDD C536 C524 C537 C543
DQ29 [2] VDD P3
ED30 D6 DQ30 C2 P5
ED31 B7 VDDI VDD
DQ31 0402 220nF 0402 0201
R509 C4 M5 4.7uF 2.2uF 100nF
240R D3 VSS CMD EMMC_CMD
[2]
ZQ0 E7 M6 0R R514
C3 VSS CLK 0201 EMMC_CLK
[2]
240R ZQ1 C523 G5 VSS
R510 H10 VSS RSTN K5 EMMC_RST
[2] GND GND GND GND
GND K8
C6 L1 0402 VSS
VSSQ CS0# ECS0_B 1uF N2
C9 L2 VSS
VSSQ CS1# ECS1_B [2] N5 VSS
D10 VSSQ [2] P4
E10 K1 ECKE ECKE GND VSS eMMC_CLK
VSSQ CKE0 P6 VSS
F5 K2 ECKE ECKE [2,5] should star
VSSQ CKE1
G10 VSSQ [2,5]
J5 J3 EDCLK Close to Memory connect from
VSSQ CLK EDCLK A1
L10 H3 EDCLK_B [2] Check MCP part's requirement NC MC0CLK
VSSQ CLK# EDCLK_B A2 NC NC H1
M5 VSSQ [2] A6
N10 L6 EDQS0
GND NC NC H12
VSSQ DQS0 GND A7 NC NC H13
P10 VSSQ DQS0# L5 EDQS0_B [2]
A8 NC NC H14
R6 VSSQ DQS1 G6 EDQS1 [2] A9
R9 G5 [2] NC NC H2
VSSQ DQS1# EDQS1_B A10 NC NC H3
DQS2 P8 EDQS2 [2] A11
E1 P9 [2] NC NC H5
VSSCA DQS2# EDQS2_B A12
J1 D8 [2] NC NC J1
VSSCA DQS3 EDQS3 A13 NC NC J12
N1 VSSCA DQS3# D9 EDQS3_B [2] A14
[2] NC NC J13
B1 NC NC J14
DM0 K5 EDQM0 B7
H5 [2] NC NC J2
DM1 EDQM1 B8
LP-DDR2 NC NC J3
C2 VSS DM2 N7 EDQM2 [2] B9 GND
C5 E7 NC NC J5
VSS DM3 EDQM3 [2] B10 NC NC K1
D1 VSS [2] B11
H2 G3 NC NC K10
VSS VREFCA EVREF B12 NC NC K12
J8 VSS VREFDQ J9 [2] B13
P1 NC NC K13
VSS B14 NC NC K14
R2 VSS NC B2 C1
R5 B3 NC NC K2
VSS NC C538 C541 C3 NC NC K3
NC J2 C5
K3 NC NC K6
NC C7 NC NC K7
A1 DNU NC L3 0402 0201 C8
A2 R3 4.7uF 100nF NC NC L1
DNU NC C9 NC NC L12
A9 DNU NC T2 C10
A10 T3
GND GND NC NC L13
DNU NC C11 NC NC L14
B1 DNU C12
B10 NC NC L2
DNU C13 NC NC L3
T1 DNU C14
T10 NC NC M1
DNU D1 NC NC M10
U1 DNU D2
U2 NC NC M11
DNU D3 NC NC M12
U9 DNU D4
U10 NC NC M13
DNU D12 NC NC M14
D13 NC NC M2
D14 NC M3
LPDDR2_FBGA134_16G_EDBA232B1MA_-2
GND NC
EDBA232B1MA E1 NC NC M7
E2 NC NC M8
E3 NC NC M9
E5 NC NC N1
E8 NC NC N10
E9 NC NC N11
E10 NC NC N12
E12 NC NC N13
E13 NC NC N14
E14 NC NC N3
F1 NC NC N6
F2 NC NC N7
F3 NC NC N8
F10 NC N9
B F12
F13
NC
NC NC P1 B
NC NC P10
F14 NC NC P11
G1 NC NC P12
G2 NC NC P13
G3 NC NC P14
G10 NC NC P2
G12 NC NC P7
G13 NC NC P8
G14 NC NC P9
THGBM5G8A4JBAIR_32GB_E-MMC
THGBM5G8A4JBAIR

A A

COMPANY:
<Loncheer>
TITLE:

DRAWN: DATED:
<T8850&W8850>
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number> <1.0>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 5OF 12
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D
PLACEMENT NERA BB HEAD MIC

33pF
0201

C603
100nF
[3] AU_VIN0_P ÓëµØ¼Ù²î·Ö
0201 C601 MAINMICP [11]
33pF
0201

C604
100nF MICBIAS1
[3] AU_VIN0_N MAINMICN [11]
0201 C602
33pF
0201

C635

GND of C435(10uF) and headset

R608
should tie together and single

FV613 via to GND plane

0201
Close to BB

2
1K

1
100nF

C617
0201
[3] AU_VIN1_N

1.5K
100pF
0201

C611

R609
C613

100nF

C616
0201
[6] 0402
[3] AU_VIN1_P HEADMIC_IN 4.7uF
Close to ear CON j600
33pF 33pF
0201 0201

R600
C615 C612

0201
1K
[3]
ACCDET

tie together and single via to GND plane

AUDIO PA [3,4,7,9,10,11] VBAT

4.7uF 100nF
0402 0201
C C628 C629
C
C609 HEAD EAR
100nF
0402
C610 1uF C630
R621
0R

0402 SPU0410HR5H
MICBIAS0
1 2 0402
0402 POWER GND 2.2uF
33pF

T601
0201 D601

D2
A3
B3

C1
R601

0201
4 3
C607 OUTPUT GND 100K

VDD

C1P
VDD

C1N
100nF
ÓëµØ¼Ù²î·Ö D1
[3] AU_VIN2_P 0201 C2P
C606 33pF

0402

C631
2.2uF
0201 [2] A4
GPIO6_SPK_EN SHDN B1
C2N
C608 B2
C2N
100nF
300R

[3] AU_VIN2_N D602 [11]

0201 C605 AW8736FCR B4 L605 0R
VOP SPK_P

220pF
33pF A2 0603
0402

C627
[3,6] AU_HPL R602 INN
3.3K

0402
0201

10nF

C625
0201

[11]
C614 D4 L606 0R SPK_N
VON 0603
R631

A1 1nF 1nF
0402 INP 0402 0402
R603 3.3K

10nF

C626
D3
PVDD
1

C633 C634

GND
GND
GND
4.7uF
0402
Close to BB

C2
C4
C3
C632
2

FV609 FV602 Z622

NC
NC Z623
together then single via to main GND
Close to MIC GND

SGM3717

6
22uF 22uF
C637

0603 0603

GND
[3] Z611 9 10 [6]
AU_HPR COM2 NO2 R610 100R
8 7 0402 HP_R

C638
IN2 NC2
4 5
[3,6] Z612 IN1 NC1

POWER
AU_HPL 3 2 [6]
COM1 NO1 R611 100R
0402 HP_L

D603 33pF 33pF

1
[2] GPIO105_SWITCH_EN 0201 0201

GND C618 C619

C648
100nF
0201
R633

0201
100K
Ìرð˵Ã÷£º
0402 VIO28_PMU [1,3,9,10,11]
R634 100R
1¡¢Á½¸öµçÔ´Òý½ÅA3/B3¶¼±ØÐë½Óµ½VBAT
2¡¢AW8736FCRͨ¹ýSHDNÒý½ÅÊ©¼ÓÂö³å½øÐÐģʽѡÔñ,Âö³å¸ßµÍµçƽ±£³Öʱ¼ä0.75us~10us,ÔöÒæ´óСÊǵ±ÊäÈëµç×èΪ3Kʱºò¼ÆËãËùµÃ
SHDNÓɵÍ-¸ß£¬²¢³ÖÐø±£³Ö¸ßʱ£¬¹¦·Å¹¤×÷ÔÚKÀà+NCN 1.2WģʽÏ£¬ÔöÒæ16.3±¶
GND
SHDNÓɵÍ-¸ß-µÍ-¸ß£¬²¢³ÖÐø±£³Ö¸ßʱ£¬¹¦·Å¹¤×÷ÔÚKÀà+NCN 1WģʽÏ£¬ÔöÒæ16.3±¶
3.5mm Headphone Jack
SHDNÓɵÍ-¸ß-µÍ-¸ß-µÍ-¸ß£¬²¢³ÖÐø±£³Ö¸ßʱ£¬¹¦·Å¹¤×÷ÔÚKÀà+NCN 0.8WģʽÏ£¬ÔöÒæ16.3±¶

SHDNÓɵÍ-¸ß-µÍ-¸ß-µÍ-¸ß-µÍ-¸ß£¬²¢³ÖÐø±£³Ö¸ßʱ£¬¹¦·Å¹¤×÷ÔÚKÀà+NCN OFFģʽÏ£¬ÔöÒæ16.3±¶

3¡¢µçÔ´Ïß¾¡Á¿´Ö(Ïß¿í²»µÍÓÚ0.75mm),4.7uFµçÈÝÐèÒª¿¿½üA3/B3¹Ü½Å·ÅÖÃ,È¥ñîµçÈݾ¡Á¿¿¿½ü¹¦·Å¡£µçÔ´Ïߣ¬µØÏß×îºÃ²ÉÓÃÐÇÐͽӷ¨

B 4¡¢ÒôƵÊäÈëÐźŲÉÈ¡ÉÏÏÂ×óÓÒ°üµØ´¦Àí
5¡¢Êä³öÏß¾¡¿ÉÄ̶ܶø´Ö(Ïß¿í²»µÍÓÚ0.5mm)£¬Ô¶ÀëFM¡¢ATV¡¢CMMBµÄÌìÏߺÍÊäÈëÐźÅÏß
B
6¡¢²»Í¬°æ±¾PADSÔÚÖ±½ÓʹÓñ¾ÔªÆ÷¼þ¿â»òÕß½¨¿âʱÇëÎñ±ØÈ·ÈÏPCBʵ¼Ê¹Ü½Å˳Ðò£¬±ÜÃâ°æ±¾×ª»»²»Í¬´øÀ´µÄ²îÒì

FV612

2
NC
0402

VIO18_PMU [1,2,3,4,5,7,9,10] C624

1
0201

[6] 470K Z603 1

HEADMIC_IN R617
[6] Z602 4
HP_L
47K 0201 R616 Z604 6
[2] EINT4_HP
5
[3] B612 BLM15BD102SN1D
RECEIVER CIRCUIT AU_HSP [6] Z601
0402 3
HP_R
100pF 2
0402 REC601
1 P
C620 2 N XJ601
AJ01356326-R
REC1506 470R
B613 BLM15BD102SN1D R622 R623
C636
0201
0201

AU_HSN
0402

[3] 470R
NC

0402
1

1
1

33pF 33pF 0402

0402 0402 L601 C <5pF
100nH
2

C621 C622 FV605

2

R614 0R [8]
FV606 FV607 FV608 0201 FM_ANT
2

FV603 FV604 0201 FM_RX_N_6627 [8]

0R R615

FV601
BLM18BD252SN1-1000R/100M
2

A A

COMPANY:
<Loncheer>
TITLE:

DRAWN: DATED:
<T8850&W8850>
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number> <1.0>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 6OF 12
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

SH701

1
GND

SH-T8850-TRANSIVE

SH702
×îÐÂÐ޸ĵÄ
1 [3,4,6,7,9,10,11]
GND VBAT

C724 C725
SH-T8850-RF-PA 2.2uF C726
100nF 82pF
0402 0201 0201

GND GND GND

BPI0~4 and 10~11 are 2G+3G mode both
BPI5~9 and 12~14 are 3G mode only [2,7] VM1
(suggest BPI5~9 = 1.8V) VM0
[2,7]
D 10K R705
D

10
4
3

1
0201 WG_GGE_PA_VRAMP [2]
L723

VMODE_0
VMODE_1

VCC1
VCC2
NOTE: Vramp 3.9nH
C704 0201 C727 0201 0402

0201
R704 [7] W_PA_B1_IN 0201 2 RF_IN RF_OUT 9 W_PA_OUT_B1 [7]
220pF R709 0R
24K 18pF
BPI0~6 are 2G+3G mode both R735 0402
D702
0402 C729
GND 0201 8 CPL_IN CPL_OUT 6 C728
BPI7~13 are 3G mode only GND GND R708 SKY77761 NC

0201
51R NC
NC
SKY77590 control logic table 5 VEN GND GND

GND
GND
VctA VctB VctC TxEn
R701 1K WG_GGE_PA_ENABLE [2] GND
BS2 BS1 mode ebable 0201

7
11
0201
(TRX1)G_DCS L L H L
[7] C703 C711 CPL_B8-IN-B1-OUT[7]
(TRX2)W_Band8 L H H L 2G_HB(TD)
22pF 22pF 0201

0201
(TRX3)W_Band1 H L H L 0201 GND
C708 [2] W_PA_B1_EN R738 1K
(TRX4)W_Band5 H H H L [7] 2G_LB(TD) R702 1K
22pF 0201 BPI_BS2
(TRX5)W_Band2 L H L L [2]

0201
(TRX6) NA H L L L C709 C712 R737
[7] W2100_TRX 0201
EDGETX_L H L H H 22pF 22pF 0201

0201
EDGETX_H H H H H NC
C710
[7] W900_TRX
GMSKTX_L H L L H 22pF
> 80 mil [3,4,6,7,9,10,11]
VBAT
GMSKTX_H H H L H

C705 C706 C707

GND 22pF 100nF 22uF
0201 0201 0603
GND GND GND

22
21
20
19
18
17
16
15
TRX_4/GND
TRX_3
TRX_2
TRX_1
VRAMP
TXEN
MODE
GND
U701 [3,4,6,7,9,10,11] VBAT
R703 1K BPI_BS0[2]
SKY77593/SKY77594 0201
Car Kit :out of shielding case C758 C748
2.2uF C749
C719 100nF 82pF
XJ701 22pF 0402 0201 0201
SA701 23 TRX_5/TRX_4 VCC 14
0201
ECT..163 NET1 is IN L701 24 TRX_6/GND VBATT 13

SKY77590
2 GND
3 GND C702 25 GND BS1 12 GND GND GND
1 0402 0402 R706 1K
4 GND RF 26 ANT BS2 11 0201 BPI_BS1[2]
2 1
GND 3 4 0R 39pF 27 GND TX_LB_IN 10
28 GND TX_HB_IN 9 VM1
GND 818000157 5 6 C720 [2,7]
GND

GND
GND
GND
GND
GND
GND
GND
GND
C701 29 22pF 0201 [2,7] VM0
ECT818000163
GND

10
4
3

1
GND GND

1
2
3
4
5
6
7
8
0402 L702 L736
NC L724

VMODE_0
VMODE_1

VCC1
VCC2
39nH NC

0402
0402
56pF
C750 0201 0402
GND NC NC [7] W_PA_B8_IN 0201 2 RF_IN RF_OUT 9 W_PA_OUT_B8 [7]
NC R733 0R
GND 0201 0201 0201 18pF
0402 0402
8 CPL_IN D701
CPL_OUT 6 C751 C752
C721 C722 C723 C739 SKY77768
R732 NC

0201
0201 GGE_PA_LB_IN(TD) [7] NC
56pF 0R R707 NC

0201
5 VEN GND GND

GND
GND
NC
0201 GND

7
11
C737 R718
C738
0201 GGE_PA_HB_IN(TD) [7] R711 R713

0201
22pF 0R [7] CPL_B8-IN-B1-OUT GND 0201 0201 PDET[7]
27R/1% 27R/1%

0201
R719

0201
NC R720
NC

0201
R736
C [2] W_PA_B8_EN R739
0201
1K 0201
33R
R712 C
NC

GND

Note : Use RX Co-banding

GSM900 = 3G B8
SAYRF1G95HQ0F0A W+G ==>SAYRF1G95HN0F0A TD+W+G (BLOCKING B34)
L717 NC

0201
L713 0201 0201

0201

0201
15pF N159840168
1.8nH

2
4
5
7
9
0201 L722
[7] W2100_TRX 10nH C746

G
G
G
G
G
L719
NC
L720

0201
8 RX
C741 U703 22nH 1 RX C745
SAYRF1G95HQ0F0A 3 6 0201 [7]
TX ANT W900_TRX

6
0201 L714 L718 5.6nH
0201 U704
NC

ANT
2.2nH

BAND5,836.5MHz/881.5MHz,BALANCED,2016
DUPLEXER,WCDMA
G 9 W_PA_OUT_B8
1.8nH SAYFH897MHC0F0A [7]
G 7
G 5
G 4
G 2

TX
RX
RX
3
1
8
[7] W_PA_OUT_B1

L715 0201 GGE_PA_HB_IN(TD)

4.3nH [7]
W_PA_B1_IN
[7]

C742 C743
4.3pF W_PA_B8_IN [7]
4.3pF 0201 N159839248
0201 GGE_PA_LB_IN(TD) [7]

L716 0201
4.3nH GND

0201
C730
470nF

VRF18_RF
L705
12 mil VRF18_RF
[7]
GND 0201

2.2nH
L721
12nH
[7]
PDET

0201
U702 L710

L709
GND
0201

10

NC
RFBLN2012090BM5T25 39nH
L703 GND
[7] 2G_LB(TD)
GND

0201

0201
2.2nH 1 9 L706
LBIN LBOUT
C715 C716 12nH

A10

A11

D11
GND

C10
B11

B10
2 8 0201

D3

A2

A3

A5

A6

A8

A9
C3

C2

C7

C8

C9
E3

B3

B4

B5

B6

B8
J2

J7

J8
GND LBOUT
GND

0201 0201 3 7 0201

GND
GND
GND
GND
GND

3GB1_RXP

3GB1_RXN

3GB5_RXP

3GB5_RXN

3GB2_RXP

3GB2_RXN

3GB8_RXP

3GB8_RXN

2GHB_TX

3GH1_TX

3GH2_TX

3GL5_TX

2GLB_TX

VTXHF

DET

GND
GND

GND
GND
GND
GND
GND
NC NC GND HBOUT
L704 GND
GND 0201 L707
2G_HB(TD) 4 HBIN HBOUT 6 6.2nH F3 GND GND D9
GND

[7]
2.0nH G3 GND GND E9

L711
L712 H3 F9

NC
C717 GND GND
C718 9.1nH J3 G9
5

GND FDD RX TXO GND

1.5pF C4 GND GND H9

0201

0201
0201 0201 D4 GND GND J9
NC GND
GND GND L708 0201 A1 D10 GND Remove external thermistor; use MT6166 built-in thermistor
B40_RXP DETGND
6.2nH delete R127
B L725
0402
B1 B40_RXN TMEAS C11 GND
connect to R712 firstly,then to main GND
B
[3] VRF18_PMU VRF18_RF [7] C1 LB_RXP V28 E10 VTCXO_PMU 4 mil VTCXO_PMU
[1,3,7]
0R TDD RX
C755 D1 G10
0402 LB_RXN 3GTX_IP TX_BBIP[2]
C731
1uF [7] VRF18_RF 12 mil E1 G11 470nF
HB_RXP 3GTX_IN TX_BBIN[2]
C736 TX(I/Q) 0201
GND NEED PROTECTION
F1 F10 GND

0201
470nF HB_RXN U705 3GTX_QP TX_BBQP[2]
Close to each other and nearby X700 connect to main GND VRF18_RF F2 MT6166 F11
R724 0R VRXHF 3GTX_QN TX_BBQN[2]
R722 NC
[3] AUXADC_REF 0201 0201 GND
connect to main GND G2 L11

0201
RFVCO_MON TXVCO_MON 10 mil VRF18_RF [7]
J1 J11 VRF18_RF C732 GND
XTAL1 VTXLF
470nF
R721 NC 4 3 H2 H10 DCOC_FLAG DCOC_FLAG [2]
[3] THERM_ADC 0201 GND/THERM HOT XTAL2 XO TXBPI
1 2 VTCXO_PMU K1 J10 RCAL
HOT GND VTCXO28 RCAL
Test pin
X701
CRY3225 G1 32K_EN TST2 K11

0201
L1 EN_BB TST1 L10
BSI R715
C740 [1,3,7] VTCXO_PMU 6 mil SRCLKENA
BSI-A_DAT2 2K¦¸,¡À1%
K2 CLK_SEL BSI_DATA2 G8 BSI-A_DAT2 [2]
26M output
0402 C735 BSI-A_DAT1
1uF 470nF L2 XO3 BSI_DATA1 H8 BSI-A_DAT1 [2]
R723 NC 0201 GND
0201 E4 GND GND B7

AVDD_VIO18
F4 GND GND J6
GND_AUXADC

BSI_DATA0
G4 RX(I/Q) D8
R725 GND GND GND

OUT32K

BSI_CLK
H4

VXODIG
E8
0201

XMODE

BSI_EN
GND GND

RX_QN
RX_QP
VRXLF

RX_IN
GND_AUXADC connect to mt6322 B2 0R

RX_IP
Connect X700 pin2

GND
GND
GND
GND
GND
GND

GND
GND

GND
GND
GND
GND
XO4

XO2

XO1
GND to MT6323 pin R726 NC BSI-A_XXX NEED PROTECTION
B2 first then [1,3,7] VTCXO_PMU 0201

J4
C5
D5
E5
F5
D7

K4

K3

L4

K5

L5

K6

K7

L7

L8

K8

K10

K9

G6

H6

F8

E7
J5

C6
D6
E6
F6
connect to main GND
connect connect to main GND
GND

RX_BBQN
RX_BBQP
to main GND GND 0201

RX_BBIN
RX_BBIP
BSI-A_DAT0
near pin B2 R727 0R BSI-A_DAT0 [2]

VIO18_LC
GND BSI-A_CK
[2,3,4]

VRF18_RF
SRCLKENA BSI-A_CK [2]
BSI-A_EN
1.Route AUXADC_REF_RF/THERM_SENSE with 4mil trace width BSI-A_EN [2]
2.Route AUXADC_REF_RF/THERM_SENSE as differential trace with well GND shielding [3] CLK4_AUDIO
[8] CLK2_WCN
3.Route AUXADC_GND with 24mil trace width under [2] CLK1_BB
RX_BBQN
THERM_SENSE/AUXADC_REF trace to provide RX_BBQP[2]
[3]
return current path.
PMU_32K
R728 RX_BBIN [2]
[2]
[7] VIO18_LC 0201 XMODE RX_BBIP
NEED PROTECTION [2]
DCXO_ 0R
Component R724 R721 Logic XMODE R729
MODE VXODIG
MODE X700 R722 C740 32K_EN [1,3,7] VTCXO_PMU 0201 10 mil VRF18_RF[7]
R725 R723
EX: EPSON, X1E000021043400 NC
Xtal Mode Xtal 0ohm NC NC 1uF C733
470nF
Xtal [7] VIO18_LC 0201
DCXO + 32K XO 0(GND) 1(VIO18) 1(VIO18)
GPS co-clock + Thermistor NC 100K+/-1% 0ohm 1uF R716 0402 GND
[1,2,3,4,5,6,9,10] VIO18_PMU
0R
4 mil
EX: Kyocera, CT2520DB26000C0FZZA1 DCXO + 32K-Less 1(VTXCO28) 1(VTXCO28) 1(VTXCO28)
C734
2.2uF
Reserved LC filter 0402
GND

R730
[7] VIO18_LC 0201 4 mil
0R
VXODIG power pin
R731
A [1,3,7] VTCXO_PMU 0201 A
NC

COMPANY:
<Loncheer>
TITLE:

DRAWN: DATED:
<T8850&W8850>
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number> <1.0>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 7OF 12
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

SH801

1
GND

SH-T8850-WIFI

SH802

1
GND

D SH-T8850-CRYSTAL
D

U201-F

[8] WB_RSTB AF6 WB_RSTB AVDD18_WBG AE4 10 mil VCN18_PMU [3,8]

XIN_WBG AD6 XO_IN [8]

GPS_RXQN AF5 [8] GPS_RX_QN C820

GPS_RXQP AG5 100nF
GPS_RX_QP [8] 0201
[8] FM_DATA Y10 F2W_DATA GPS_RXIN AG4 GPS_RX_IN [8]
[8] FM_CLK AA10 F2W_CLK GPS_RXIP AF4 GPS_RX_IP [8]
GND
[8] WB_SCLK AG7 WB_SCLK WB_TXQN AF2 WB_TX_QN [8]
[8] WB_SDATA AF7 WB_SDATA WB_TXQP AG2 WB_TX_QP [8]
[8] WB_SEN AE6 WB_SEN WB_TXIN AF1 WB_TX_IN [8]
WB_TXIP AE1 WB_TX_IP [8]

[8] WB_CTRL0 Y6 WB_CRTL0 WB_RXQN AE2 WB_RX_QN [8]

[8] WB_CTRL1 AA6 WB_CRTL1 WB_RXQP AD2 WB_RX_QP [8]
[8] WB_CTRL2 AA5 WB_CRTL2 WB_RXIN AC2 WB_RX_IN [8]
[8] WB_CTRL3 AA4 WB_CRTL3 WB_RXIP AC1 WB_RX_IP [8]
[8] WB_CTRL4 AB5 WB_CRTL4
[8] WB_CTRL5 AB4 WB_CRTL5 ANT_SEL0 [8]
ANT_SEL0 AB25 T310

TMM75D:WORKMT6583PHONEMT6583_MT6167_AST3001_MT6628_MT6320_EMMC_LPDDR2_WG+TG_V1.1_WS1819_20120625_3_TEMP.DSN
ANT_SEL1 AC26 T1

TMM75D:WORKMT6583PHONEMT6583_MT6167_AST3001_MT6628_MT6320_EMMC_LPDDR2_WG+TG_V1.1_WS1819_20120625_3_TEMP.DSN
ANT_SEL2 AC25 T2

TMM75D:WORKMT6583PHONEMT6583_MT6167_AST3001_MT6628_MT6320_EMMC_LPDDR2_WG+TG_V1.1_WS1819_20120625_3_TEMP.DSN
ANT_SEL1 [3]

MT6592/VFBGA475/P0.4/B0.25/10.6X11(S1+S2+S3+S4+S5+S6+S7+S8+S9)TRUED:¤º³¡-p¹ºMT6582M82M_WTG_REF_SCHV0.153MT6588_MT6166_MT6625_MT6323_MT6333_EMMC_LPDDR2_WTG_V016TEMP.DSN
Debug usage
ANT_SEL2 [3]

C C

Car Kit :out of shielding case

WB_CTRL5 [8]
ECT..163 NET1 is IN
SA1001 WB_CTRL4 [8]
2 1 WB_CTRL3 [8]
3 4
5 6 can be protected 6 lines in 1group

1
W801

1
WB_CTRL2 [8]
W802 ECT818000163
ANT_AND770
ANT_AND770 WB_CTRL1 [8]
GND

WB_CTRL0 [8]
C804 VCN18_PMU 10 mil
R805 R1010 NC NC

0201 0201
0201 C810 WB_RX_IP [8]
0402 0402 100nF
GND

0402

0201
0R WB_RX_IN [8]
C809
L808

0402
L811 100pF
39nH C811
L1008
NC NC Close to MT6572

30

29

28

27

26

25

24

23

22

21
NC 0201 U801
need protected 4 lines in 2 group

W_LNA_EXT

AVDD18_WBT

WB_CTRL5

WB_CTRL4

WB_CTRL3

WB_CTRL2

WB_CTRL1

WB_CTRL0

WB_RX_IP

WB_RX_IN
0R R804 WBG_ANT 50 Ohm 31 20
0201 WB_GPS_RF_IN WB_RX_QP WB_RX_QP [8] VCN18_PMU VCN18_PMU
Based on your system level design , if
better WiFi TX performance is needed on
50 Ohm
your system, please refer to WiFi 32 GPS_DPX_RFOUT WB_RX_QN 19 0402
WB_RX_QN [8] C828
performance enhance proposal 1uF

20 mil and more than 2vias 33 AVDD33_WBT WB_TX_IP 18 WB_TX_IP

[3] VCN33_PMU [8]
C822 100pF
0402 C823 GND
0201
4.7uF 34 NC WB_TX_IN 17
WB_TX_IN [8]
50 Ohm
GND need protected 4 lines in 2 group
FM FM_RX_N_6627
[6] FM_RX_N_6627
GND
35 NC WB_TX_QP 16
WB_TX_QP [8]
[8] AVDD28_FM
B801
[3,8]
VCN28_PMU
L802 600¦¸@100MHZ
0201
FM_ANT
[6] FM_LANT_P MTK

82nH
8 mil 36 15
[8] AVDD28_FM AVDD28_FM IC,MT6627N,WIFI/BT/FM/GPS 4 in 1 WB_TX_QN WB_TX_QN [8] Bead1001 are for FM desense-free proposal.
L804 L803 C818 10nF They can be cancel for cost-down proposal

GND
NC 100nH

0201
37 FM_LANT_N GPS_RX_IP 14 GPS_RX_IP [8]

0201

0201
MT6627

Close to MT6627
MT6628_GPS / FM GND GND
38 FM_LANT_P GPS_RX_IN 13 GPS_RX_IN [8]

need protected 4 lines in 2 group

50 Ohm
1

[8] ANT_SEL0 39 GPS_RFIN GPS_RX_QP 12 GPS_RX_QP [8]

W803 W804
ANT_AND770
ANT_AND770
VCN18_PMU 10 mil 40 AVDD18_GPS GPS_RX_QN 11
GPS_RX_QN [8]
4.7nF

AVDD28_FSOURCE
0201
B C808
41 DVSS B

F2W_DATA

F2W_CLK
FM_DBG
HRST_B

SDATA
GND

XO_IN
GND

CEXT
SCLK

SEN
GND
0201
0402 C806 MT6611_SMD_WLCSP-61_1
C807 MT6627 SMD QFN40
D801

10
D802 39pF 1uF 0201
GNSS SAW Filter RDALN16 C813
0201

R811 2.2pF GND

SAFEB1G57KE0F00R14 L801
GND
0R 3 4 L1 keepout then to main GND
C801 C803 RFIN VDD 0402 VCN28_PMU
1 4 0201 7.5nH 0R [3,8]
0402 IN OUT 2 5

XO_IN
0201

GND EN
2 5 18pF C805 L807
3 GND GND 0201 1
GND RFOUT
6 0201 [8] WB_RSTB
GND 33pF 6.2nH
C802
L805 L806
39nH NC Infineon LNA
NC
0402
0402

0402

[8] FM_DATA 0201

C815
C816
need protected seperately 100pF
1uF
Based on your system level design , if [8] FM_CLK
XO_IN [8]
better GPS performance is needed on GND

your system, please refer to GPS

[8] WB_SCLK
performance enhance proposal R806
[8] WB_SDATA 0201 CLK2_WCN[7]
NC

[8] WB_SEN
R807 0R
0201
0R
GND

0402 C814
1uF

5
R823 6 4
[3,8]

TSENS
VCN28_PMU 0402 VCC OUT
0R

1 VREF GND 3
change from AVDD28_FM to VCN_2V8_PMU refer to V0.4 by sunning 0411

EN
U805

2
RAKON/IT2205BE/26MHz
GND

A A

COMPANY:
<Loncheer>
TITLE:

DRAWN: DATED:
<T8850&W8850>
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number> <1.0>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 8OF 12
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D BMI058 G-SENSOR 0x18 D

GY 0x68

LSM330 G-SENSOR 0x1E [1,3,6,9,10,11]

GY VIO28_PMU
0x6A

ALS&PS

22R
0402
R913

FV905
1 2
FV904 FV903 C905

2
2
0402
1uF

[1,2,3,4,5,6,7,9,10] VIO18_PMU
[9] GYO_SCL

1
D903

1
[9] GYO_SDA

VDD 8
[3,4,6,7,10,11]

0402
R910 0R 7 5
[2,9] SCL2 0201 SCL LEDA R912
0402 5R
VBAT

100nF
C921
R911 0R 1 4
[2,9] SDA2 0201 SDA LEDK
[2]
EINT1_A 2 3 C906
INT LDR

1
GND
5
4
3
2
1
100nF 10uF 0402
0603 4.7uF

SDO2
SDA/SDI
VDDIO
SCL/SCK
VDDIO
0201

1
6

6
SDO1
R924 NC 7 C911 C912
0201 NC 8
DNC
24
R925 DNC VDD
0201

2
9 23
[2] EINT20_GY INT4 D901 VDD FV902
10 22 10nF
[2] EINT3 INT3 BMI058 VDD
11 21 25V GND

2
[2] EINT5 INT1 GND
12 20 0402 FV901 STK3311
[2] EINT11_G INT2 GND
13 19 C928
PS GND
18
GND

GND
GND
GND
GND
GND

14
15
16
17
VIO28_PMU
R924 R925 C928
BMI058 NC NC NC
LSM330 0R 0R 10nF

C C

MAG Sensor

0R
[9] GYO_SCL 0201 R915
0R
[9] GYO_SDA 0201 R916
0R
[9] M_SCL 0201 R917 SCL2 [2,9]
0R
[9] M_SDA 0201 R918 SDA2 [2,9]

VIO28_PMU VIO18_PMU
0201 100nF

B1 C3
VDD TRG
0201 100nF

C4 D4
VID RSTN

C2 A3 [9]
C903

TST1 SCLK/SK M_SCL

[9]
B3 A4
C904

RSV D902 SDA/SI M_SDA

GND
SENSOR-MAG-AK8963C-12 B4
SO
D1
CAD0
D2 A2
CAD1 CSB
A1
C907

4.7uF

DRDY
0402

C1 D3
VSS NC

GND

B B

CSB=1: IIC

IIC ADDRRSS is 0x0CH, CAD0=CAD1=0

power down(communicating), I < 10uA

G-Sensor

A A

COMPANY:
<Loncheer>
TITLE:

DRAWN: DATED:
<T8850&W8850>
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number> <1.0>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 9OF 12
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

4.3" COF CTP

MIPI CMEF
D D

T1001

T1002

T1003

T1006
T1000

T1005
T1004
[2] [10]
MIPI_TDN3 2 3 LCM_DATAN3
[2] ACFT4A2G900E [10]
MIPI_TDP3 1 4 LCM_DATAP3
EMI1001

0201
0201
10K NC
R1005 R1016
1 12
GND
2
[3] VGP1_PMU VDD 2.8V
3
FT[WAKE]
SDA0 4
[2] SDA
FCONH1MMPDMM3PIN39F_AW996 5
XJ1001 [2] SCL0 SCL
6
[2] EINT2_CTP 7
INT
[2] EINT14_CTP_RST RESET
2 line 6LEDs In Series 8
[2] ID
2 3 [10] [3] VGP2_PMU 1.8V 9
MIPI_TDN2 LCM_DATAN2 ATMEL[IOVCC]
10 11
[2] ACFT4A2G900E [10] 39 GND
MIPI_TDP2 1 4 CTP_LED-
EMI1002 LCM_DATAP2
38 XJ1002
CTP_LED+
LEDPWM
[10] 37
BLU_PWM

0402
0402
GND

2.2uF
36

C1009
C1008

1uF
GND
GND 35
[10] LED_S2 LED2-
FV1002
FV1001 34

2
[10] LED_S1 LED1- FV1003 FV1010

2
2 3 [10] FV1004 FV1005 FV1006 FV1007
[2] MIPI_TDN0 LCM_DATAN0 33
[10] VLED_P LED2+

C1003
ACFT4A2G900E [10]

1uF
1 4

1uF
[2] MIPI_TDP0 LCM_DATAP0 32
EMI1003 LED1+

0402

1
31

0402
C1001
GND

1
30
VIO18_PMU IOVCC GND
29
VCI
28
NC
27
GND
[2] 2 3 [10]
MIPI_TCN LCM_CLKN VIO28_PMU 26
ACFT4A2G900E [10] LCM_DATAN0 D0-
[2] 1 4 [10]
MIPI_TCP EMI1004 LCM_CLKP 25
NC
24
[10] LCM_DATAP0 D0+
23
GND
22
[10] LCM_DATAN1 D1-
21
NC
20
LCM_DATAP1 D1+
[2] [10] [10]
2 3 19
MIPI_TDN1 LCM_DATAN1 GND
[2] ACFT4A2G900E [10]
1 4 LCM_DATAP1 LCM_CLKN 18
MIPI_TDP1 EMI1005 CLK-
[10]
17
NC
16
LCM_CLKP CLK+
[10] 15
C 14
GND
C
LCM_DATAN2 D2-
[10]
13
NC

LCM_DATAP2 12
D2+
[10]
11
GND
10
LCM_DATAN3 D3-

T1007
TP_1
[10]
9
NC

LCM_DATAP3 8
D3+

1
[10]
7
GND
6
NC
5
[2] LPTE TE

[2] LRSTB 4
/RST
3
LANSEL

[2] LCD_ID1 1K R1006 2

0402 LCM_ID
1
GND

1
2

2
FV1008 FV1009

B B

Back Light Driver for 12LEDs In 2Series 6 P

[10] L1002 L1003 L1001

VLED_P [3,4,6,7,9,11]
VBAT
VD1010

22uH

33pF GND C1004

C1007 0402 C1006
10uF 0402
1uF/50V 0603 C10191uF/50V 0603
16

15

14

13

GND
GND
PGND

PGND

VIN

NC

LX NC
1 12
LX VOUT VLED_P [10]
2 11 LED_S1 [10] 18pF
R1001 0R 0201
[2] PWM 0201 PWM S1
R1002 NC 3 10 18pF C1014
[10] LEDPWM CABC 0201 0201
NC S2 LED_S2 [10] C1013
4 9 18pF
0201
KTD3102_04P

0201 C1011
CTRL

18pF
D1001
GND

A GND
A
NC

S3

C1012 GND
GND
5

GND

GND

[2] GPIO120_EN

COMPANY:
<Loncheer>
TITLE:

DRAWN: DATED:
<T8850&W8850>
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number> <1.0>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 10
OF 12
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

T_Flash

VMCH_PMU

D XJ1104
[2]
D
1 MC1DA2 [2]
DAT2
2 MC1DA3 [2]
CD/DAT3

10
10 3 MC1CM

9
AT820-SIM GND CMD
4 3 11 4
[3] CLK I/O SIM1_CARD_SIO [3] GND VDD
SIM1_CARD_SCLK 5 2 12 5
[3] SIM1_CARD_SRST RST VPP GND DETECT [2]
6 1 13 6
VCC GND GND CLK MC1CK
[3] VSIM1_PMU 7 [2]
VSS
8 MC1DA0 [2]
DAT0

0402

1
8

7
9 MC1DA1
XJ1101 DAT1
C1114

0402

0402
1

C1124
1

NC
C1122

C1123
TF006-1511XA91

NC
0402

NC
1uF 2.2uF
0402

2
FV1126

2
C1102 FV1135 FV1129
FV1115

2
FV1130
GND

10
9
AT820-SIM
4 3
[3] SIM2_CARD_SCLK CLK I/O SIM2_CARD_SIO [3]
5 2
[3] SIM2_CARD_SRST RST VPP
6 1
[3] VSIM2_PMU VCC GND

0402
1
8

7
XJ1102

C1128

NC
0402
1
1
0402

0402

1
1uF

C1127
C1125

C1126

NC
NC

0402 NC

2
FV1123
C1109

2
2

FV1121 FV1131 FV1122

GND

VIBR_PMU

[3,11] VIBR_PMU
3.3V 100mA

C1115

TP1101

TP1102
0402

TP_1

TP_1
1uF

R1133
1

1
R1125

0402
0402

0R
[11] DRV_DD

NC

6
[11]
OUT+

VDD
VIH=1.0V VIL=0.4V 1
XJ1103 [2] GPIO_HAPTICS_EN EN
+ 8
VDP OUT+ [11]
C [3,4,6,7,9,10,11] VBAT
1 24
MOTOR-XM
M1100 [2] GPIO12_HAPTIC_PWM
PWM 2
PWM D1102 VDN
5 C
[3,4,11]
2 23 VBUS - ISA1000
[11] Rf

R1126
OUT- NC R1131 3 4 NC R1114
[11] DRV_DD 0201 MODE GAIN 0402 OUT- [11]
[6] MAINMICN 3 22 GND GND R1132
0201

GND
GND
GND

GND

0402
10nF
0402
4 21 ERM=GND
[6] MAINMICP C1120
LRA=VDD

9
10
11

7
[3,6] MICBIAS0 0R R1123 5 20
0402

NC
6 19
GND GND
[3] KPLED 7 18 USB_DM
[2,11]
R1103 R1131 R1132 C1120 C1115
[2] EINT17_IDDIG
0R 0402
8 17 USB_DP R1114
[2,11]
9 16
ERM OPTIONAL NC 0R 10nF OPTIONAL
SPK_P
[6] 10 15
SPK_N [6]
1

11 14 3.9nF OPTIONAL
LRA OPTIONAL 0R NC
T1101 12 13
2

DF37NC-24DS FV1132 FV1133

The resistor of BATON pin pull to TREF pin (24kohm) --> 1% precision

NTC 10kohm-->24kohm

NTC 47kohm-->18kohm

4.7K
[1,3,6,9,10]VIO28_PMU

0201
VBAT

R1115
VBAT
4
RGB LED
[3,11] BAT_NTC 3 6
ASM
R1145 2
[2] BAT_INF 0201 XJ1105 5
22uF FV1101 1

1
FV1112
1

0603 C1106

1
FV1113 VD1101
+ 4

LED1101 C1103 0201 GND

2
33pF
MM3Z5V1-5

2
2

HDZMV4Z01_5.1B FV1102
2 GREEN

T425
3 BLUE
1 RED

B 19-237-R6GHBHW-C01-2T
GND B
GND

[3] ISINK0

[3] ISINK1

[3] ISINK2

FV1116 FV1117
1

FV1118
2

< MP Test Points > MARK POINT

[3,4,11]
VBUS T412
VBAT T401
Volume +power key
MARK1101 MARK1102 MARK1103 MARK1104
T403 1 1 1 1

MARKD2MM-2 MARKD2MM-2 MARKD2MM-2 MARKD2MM-2

[2,11]
[2,11] USB_DP T421
USB_DM T422
[3,11]
BAT_NTC T423

KROW0_T
KCOL0_T
FH34SRJ-6S-0.5SH(50)
6 XJ1106 GND
[2] KROW0 1K R1104 5
1K 0402 R1105 4 8
[2] KCOL0 0402 R1106 GND
[2] KCOL1 1K 0402
3
1K 0402 R1107
2
GND
7
[3] PWRKEY 1
A GND
A

FV1108 FV1109 FV1110 FV1111

COMPANY:
<Loncheer>
TITLE:

DRAWN: DATED:
<T8850&W8850>
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number> <1.0>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 11
OF 12
 6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

300W

DRIVR IC SEN_DVDD SEN_DOVDD SEN_AVDD

1.2V 2.8V/1.8V 2.8V

1.2/1.3/1.5/1.8 1.8/2.5/2.8/3.0
D 500W 1.2/1.3/1.5/1.8
D
DRIVR IC SEN_DVDD SEN_DOVDD SEN_AVDD

AR0543 NC 1.8V 2.8V

200mA 200mA 100mA

0.3M Sensor
MIPI CMEF

[2] 1 4 [12]
MIPI_RCN_A EMI1201 SUB_CAM_CLKN
[2] [12]

T1201
2 ACFT4A2G900E 3

TP_1
MIPI_RCP_A SUB_CAM_CLKP

1
Length matching in PCB < 100mil, in FPC < 20mil.
And, overall differential pair-to-pair mismatch to be controlled within 120 mils
[2] 2 3
MIPI_RDN0_A SUB_CAM_MDN0 [12]
ACFT4A2G900E
[2] 1 4
MIPI_RDP0_A EMI1202 SUB_CAM_MDP0 [12]
1
DGND
[2,3,4,12] SDA1
2
3
4
5
AF_GND
SIO_D
AF_POWER
DVDD=1.2V
[3,12] VCAMD_IO_PMU DOVDD
C [2,3,4,12] SCL1

EINT18_SUB_CMPDN
[2]
6
7
8
9
SIO_C
AGND
NC
DOVDD=1.8V C
[3,12] VCAMA_PMU AVDD2.8

[2]
[3,12] VCAMD_PMU
EINT16_SUB_CMRST
10
11
12
13
DVDD1.2
RESET
STROBE
AVDD=2.8V
DGND
[2,12]

[12]
CMMCLK1
SUB_CAM_MDP1
14
15
16
MCLK
DGND
MDP1
AF_POWER NC VLED
[12] SUB_CAM_MDN1 17 [4]
MDN1
18
DGND
[12] SUB_CAM_CLKP 19
[2] MCP
[12] SUB_CAM_CLKN 20
MIPI_RDN1_A 2 3 MCN
SUB_CAM_MDN1 [12] 21

1
DGND

2
ACFT4A2G900E [12] 22
[2] 1 4 SUB_CAM_MDP1 [12] SUB_CAM_MDP0 MDP0
MIPI_RDP1_A [12] SUB_CAM_MDN0 23
EMI1203 MDN0 FV1201

1
24
DGND HL701

GND

GND
25
DGND
XJ1201

2
26

27
FCONH1MM1PMM6PIN25F-R-XM1

GND

GND

only 150mA from VCAMD

please check your CAM module DVDD current.
external LDO is required for DVDD current > 150mA

B B
VCAM_AF VCAMD_IO_PMU VCAMA_PMU VCAMD_PMU
MIPI CMEF
8M Sensor

[2] 1 4
MIPI_RCN EMI1204 CAM_CLKN [12]
0402

[2] 2 ACFT4A2G900E 3 C1203 C1206

IMX135 S5K3L2
C1205

C1207
NC

MIPI_RCP CAM_CLKP [12] C1202

0402 0402 0402
0402 1uF 4.7uF
1uF
1uF
AF POWER 2.7V AF POWER 2.8V
GND GND GND

AVDD 2.7V AVDD 2.8V [2] MIPI_RDN2

2
ACFT4A2G900E
3
CAM_DATAN2 [12]
1 4
[2] MIPI_RDP2 CAM_DATAP2 [12]
[2] MIPI_RDN0

[2] MIPI_RDP0
2

1
ACFT4A2G900E
3

4
CAM_DATAN0

CAM_DATAP0
[12]

[12]
DVDD 1.2V DVDD 1.2V
EMI1207

EMI1205

DOVDD 1.8V DOVDD=1.8V

VRF18_2 1.05~1.25 (50mV/step)

1 EMI1206 4
[2] MIPI_RDN1 CAM_DATAN1 [12]
2 ACFT4A2G900E 3 [12]
[2] MIPI_RDP1 CAM_DATAP1 [12] [2] MIPI_RDN3 1 EMI1208 4 CAM_DATAN3
[12]
[2] MIPI_RDP3 2 ACFT4A2G900E 3 CAM_DATAP3

Length matching in PCB < 100mil, in FPC < 20mil.

And, overall differential pair-to-pair mismatch to be controlled within 120 mils DF37NC-30DS-0.4V(51)

1 30
[2,12] CMMCLK1
2 29
CAM_DATAP2 [12]
[12] CAM_DATAP0 3 28
4 27 CAM_DATAN2 [12]
[12] CAM_DATAN0
5 XJ1202 26
6 25 CAM_DATAN3 [12]
[12] CAM_DATAN1 CAM_DATAP3 [12]
7 24
[12] CAM_DATAP1
8 23
9 22 EINT10_AF_EN [2]
[12] CAM_CLKN
10 21
[12] CAM_CLKP 11 20 EINT9_MAINCAM_RST [2]
12 19 SDA1 [2,3,4,12]
[3,12] VCAM_AF SCL1 [2,3,4,12]
13 18 GND
[3,12] VCAMA_PMU 14 17
VCAMD_IO_PMU [3,12]
15 16
VCAMD_PMU [3,12]

A A

COMPANY:
<Longcheer>
TITLE:

DRAWN: DATED:
<T8850&W8850>
<Drawn By> <Drawn Date>
CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> A0 <Drawing Number> <1.0>
RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 12
OF 12