EXPERIMENT NO.

5
Aim: Design and simulation of 4:1 multiplexer
Tools Used: Xilinx ISE 14.7
Theory:
4:1 Multiplexer:
A 4-to-1 multiplexer consists four data input lines as I0 to I3, two select lines
as S1 and S0 and a single output line Y. The select lines S1 and S0 select one of the four input
lines to connect the output line. The particular input combination on select lines selects one of
input (through I0 to I3) to the output.
Table 5.1: Truth Table of 4:1 multiplexer

S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Design Equation:
Y=S1S0I0+S1S0I1+S1S0I2+S1S0I3

Synthesis:

Figure 5.1: Block Diagram of 4:1 multiplexer

 Figure 5.2: Diagram of 4:1 multiplexer

VERILOG CODE:
A.Gate module coding of 4:1 Multiplexer:
module mux4_1(input I0,input I1,input I2,input I3,input S0,input S1,
output Y
);
wire W0,W1,W2,W3;
and a0(W0,I0,(~S1),(~S0));
and a1(W1,I1,(~S1),S0);
and a2(W2,I2,S1,(~S0));
and a3(W3,I3,S1,S0);
or a4(Y,W3,W2,W1,W0);
endmodule

B.Data module coding of 4:1 Multiplexer:

module mux4_1assign(input S1,input S0,input I3,input I2,input I1,input I0,
output Y
);
assign Y=S1?(S0?I3:I2):(S0?I1:I0);
endmodule
C.Behavioural module coding of 4:1 Multiplexer:
module mux4_1behav(input S1,input S0,input I0,input I1,input I2,input I3,
output reg Y
);
initial begin Y=0; end
always @(*)
begin
if (S1==0 && S0==0)
Y=I0;
else if(S1==0 && S0==1)
Y=I1;
else if(S1==1 && S0==0)
Y=I2;
else if(S1==1 && S0==1)
Y=I3;
end
endmodule

RTL Schematic:

Figure 5.3: RTL schematic of 4:1 gate level module

 Figure 5.4: RTL schematic of 4:1 multiplexer data flow module

Figure 5.5: RTL schematic of 4:1 multiplexer using behavioural modelling technique
Test Bench:
module mux4_test;
// Inputs
reg S1;
reg S0;
reg I0;
reg I1;
reg I2;
reg I3;
// Outputs
wire Y;
// Instantiate the Unit Under Test (UUT)
mux4_1behav uut (
.S1(S1),
.S0(S0),
.I0(I0),
.I1(I1),
.I2(I2),
.I3(I3),
.Y(Y)
);
initial begin
I0=0;
I1=1;
I2=1;
I3=0;
//diffrent combination of S1S0
S1=0;S0=0; #100;
S1=0;S0=1; #100;
S1=1;S0=0; #100;
S1=1;S0=1; #100;
end
endmodule
Ouput:

Fig5.6: Output waveform of 4:1 multiplexer

Result:
4:1 multiplexer is designed with different modelling technique and test code is written for
that.RTL schematic for different modelling techniques is observed differently. By changing S1
and S0 we can observe the output .In above output diagram for fix I 0I1I2I3 to 0110 we can
observe the output.