UNIT -II

Digital Design

Sravankumar pagadala, Department of

1
ECE, JNTU Hyderabad
Digital Design using ROMs, PALs, PLAs
 Objectives
1. To learn Digital design approaches using ROM’s, PAL’s and PLA’s.
2. To illustrate the design of small Digital Systems.
3. To understand and design of various arithmetic and non-arithmetic designs.
4. arithmetic designs include BCD Adder,32 – bit adder, shift and add multiplier,
Array multiplier, and Binary divider.
5. Non-arithmetic designs include scoreboard and Controller, Keypad Scanner.
6. We will learn how designs have to be coded.

Sravankumar pagadala, Department of

2
ECE, JNTU Hyderabad
Design Example- Code Converter (Sequential)
• This circuit adds three to a binary-coded-decimal digit in the range 0 to 9.
• The input and output will be serial with the least significant bit first.
• list of allowed input and output sequences is shown below.

Sravankumar pagadala, Department of

3
ECE, JNTU Hyderabad
 Design Example- Code Converter (Sequential)
 Code Converter (Sequential)

Sravankumar pagadala, Department of

4
ECE, JNTU Hyderabad
Design Example- Code Converter (Sequential)

State Table for Code Converter

Sravankumar pagadala, Department of
5
ECE, JNTU Hyderabad
 Design Example- Code Converter (Sequential)
 Elimination of Redundant States using row matching.
 When matching rows which contain dashes (don’t-cares), a dash will match with
any state or with any output value.
 By matching rows, we have H ≡ I ≡ J ≡ K ≡ L and M ≡ N ≡ P. After eliminating I, J,
K, L, N,and P. we find E ≡ F ≡ G and the table reduces to seven rows.

Sravankumar pagadala, Department of

6
ECE, JNTU Hyderabad
Design Example- Code Converter (Sequential)

Reduced State Table for Code Converter

Sravankumar pagadala, Department of

7
ECE, JNTU Hyderabad
Design Example- Code Converter (Sequential)

State Graph for Code Converter

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8
ECE, JNTU Hyderabad
 Design Example- Code Converter (Sequential)
 Three flip-flops are required to realize the reduced table.
 states B and C,D and E, and H and M should be given adjacent assignments in
order to simplify the next-state functions.
 To simplify the output function, states (A, B, E,and M) and (C, D,and H) should be
given adjacent assignments (shown below).

Assignment Map and Transition Table for Flip-Flops

Sravankumar pagadala, Department of

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ECE, JNTU Hyderabad
 Design Example- Code Converter (Sequential)
 The transition table is filled in according to the assignment, and the next-state maps
are plotted as shown below.
 The D input equations are then read off the Q+ maps as indicated.

Karnaugh Maps for Code Converter

Design

Sravankumar pagadala, Department of

10
ECE, JNTU Hyderabad
 Design Example- Code Converter (Sequential)

Code Converter Circuit (Sequential)

Sravankumar pagadala, Department of

11
ECE, JNTU Hyderabad
 Digital Design using ROMs, PALs, PLAs
 A sequential circuit can be easily be designed using a ROM and flip-flops.
 The combinational part of the sequential circuit can be realized using a ROM.
 The ROM can be used to realize the output functions (Z1, Z2,...,Zn) and the next-
state functions (Q1+,Q2+...,Qk+).
 The state of the circuit can then be stored in a register of D flip-flops and fed back
to the input of the ROM.
 A Mealy sequential circuit with m inputs, n outputs, and k state variables can be
realized using k D flip-flops and a ROM with m+k inputs (2m+k words) and n+k
outputs.
 The next-state and output combinational subcircuits of the Moore circuit can be
realized using two ROMs.
 A single ROM can be used to realize both the next-state and output functions.
 D flip-flop input equations would generally require more gates than the J-K
equations is of no consequence because the size of the ROM depends only on the
number of inputs and outputs and not on the complexity of the equations being
realized.

Sravankumar pagadala, Department of

12
ECE, JNTU Hyderabad
 Digital Design using ROMs, PALs, PLAs
 We will now realize this converter using a ROM and D flip-flops.
 A ROM with four inputs (24 words) and four outputs is required.

Sravankumar pagadala, Department of

13
ECE, JNTU Hyderabad
 Digital Design using ROMs, PALs, PLAs
 This table gives the ROM outputs (Z,D1,D2,and D3) as functions of the ROM
inputs (X, Q1,Q2,and Q3).

Realization of State Table Using a ROM

Sravankumar pagadala, Department of

14
ECE, JNTU Hyderabad
 Digital Design using ROMs, PALs, PLAs
 The output equations and D flip-flop input equations, derived from the maps are
shown below.

 Digital designs can also be realized using PLAs (programmable logic arrays) and
flip-flops in a manner similar to using ROMs and flip-flops.
 State assignment is important, because good state assignment can reduce no. of
product terms required.

Sravankumar pagadala, Department of

15
ECE, JNTU Hyderabad
 Digital Design using ROMs, PALs, PLAs
 PALs are available which contain D flip-flops that have their inputs driven from
programmable array logic.

Segment of a Sequential PAL

 The AND gate inputs can be connected to A, A’, B, B’, Q, or Q’.

 The X’s on the diagram show the connections required to realize the next-state equation.
 Q+= D =A’BQ’+AB’Q.
 The flip-flop output is connected to an inverting tri-state buffer, which is enabled when
En =1.
Sravankumar pagadala, Department of
16
ECE, JNTU Hyderabad
 A BCD Adder
 Let 6 is added with 8, the sum is 14 in decimal.
 To obtain the correct BCD digit,6 should be added to the sum whenever it is greater
than 9.

Addition of Two BCD Numbers

Sravankumar pagadala, Department of
17
ECE, JNTU Hyderabad
 A BCD Adder
library IEEE;
use IEEE.numeric_bit.all;
entity BCD_Adder is
port(X, Y: in unsigned(7 downto 0);
Z: out unsigned(11 downto 0));
end BCD_Adder;
architecture BCDadd of BCD_Adder is
alias Xdig1: unsigned(3 downto 0) is X(7 downto 4);
alias Xdig0: unsigned(3 downto 0) is X(3 downto 0);
alias Ydig1: unsigned(3 downto 0) is Y(7 downto 4);
alias Ydig0: unsigned(3 downto 0) is Y(3 downto 0);
alias Zdig2: unsigned(3 downto 0) is Z(11 downto 8);
alias Zdig1: unsigned(3 downto 0) is Z(7 downto 4);
alias Zdig0: unsigned(3 downto 0) is Z(3 downto 0);
signal S0, S1: unsigned(4 downto 0);
signal C: bit;
Begin
S0 <= '0' & Xdig0 + Ydig0; /* overloaded */
Zdig0 <= S0(3 downto 0) + 6 when S0 > 9
else S0(3 downto 0); // add 6 if needed
C <= '1' when S0 > 9 else '0‘;
S1 <= '0' & Xdig1 + Ydig1 + unsigned'(0=>C);
// type conversion done on C before adding
Zdig1 <= S1(3 downto 0) + 6 when S1 > 9
else S1(3 downto 0);
Zdig2 <= "0001" when S1 > 9 else "0000";
end BCDadd;

Sravankumar pagadala, Department of

18
ECE, JNTU Hyderabad
 32-Bit Adders
Ripple-Carry Adder (RCA)
 A simple adder that can add 32-bit is a ripple-carry adder.
 The carry “ripples” from the least significant bit to the most significant bit.

A 32-Bit RippleCarry Adder

 delays are Tg ,a 1-bit adder delay is 2Tg. a 32-bit ripple-carry adder will take
approximately 64 gate delays. If Tg = 1ns maximum operating frequency for 32-bit
ripple-carry adder is 16 MHz (approximately).

Sravankumar pagadala, Department of

19
ECE, JNTU Hyderabad
 32-Bit Adders
Carry Look-Ahead Adders (CLA)
 A popular fast-addition technique is carry look-ahead (CLA) addition.
 The carry signals are calculated in advance.
 a carry will be generated if input bits Ai, Bi are ‘1’ or if there was a carry-in to that
bit and at least one of the input bits are ‘1’.
 In other words, bit i has carry-out if Ai and Bi are ‘1’ (irrespective of carry-in to bit
i) bit i also has a carry-out if Ci=‘1’ and either Ai or Bi is ‘1’.
 for any stage i,the carry-out is Ci+1=Ai Bi +(Ai Bi)Ci.
 there is a carry out if it generated a carry by itself (Ai Bi=1) or it simply propagated
the carry from the lower bit ((Ai Bi)Ci).
 General Generate (Gi) function Gi= Ai Bi and General Propagate(Pi) function Pi
=Ai Bi.
 propagate and generate functions only depend on the input bits and can be realized
with one or two gate delays.
 there will be a carry whether one of Ai or Bi is ‘1’ or both are ‘1’. New Pi =Ai+Bi.
 sum signal is expressed as Si= Ai Bi Ci =Pi Ci.
 The carry-out equation can be rewritten as Ci+1= Gi +PiCi.
Sravankumar pagadala, Department of
20
ECE, JNTU Hyderabad
 32-Bit Adders
Carry Look-Ahead Adders (CLA)
 In a 4-bit adder, the Ci’s can be generated by
C1=G0+P0C0
C2= G1+P1 C1=G1+P1G0+P1P0C0
C3= G2+P2C2= G2+P2G1+P2P1G0+P2P1P0C0
C4= G3+P3C3 = G3+P3G2+P3P2G1+P3P2P1G0 +P3P2P1P0C0

Block Diagram of a 4-Bit CLA

Sravankumar pagadala, Department of
21
ECE, JNTU Hyderabad
 32-Bit Adders
Carry Look-Ahead Adders (CLA)
 The disadvantage is quite complicated for more than 4 bits.
 CLAs are usually implemented as 4-bit modules and used in a hierarchical
structure to realize adders that have multiples of 4 bits.

Block Diagram of a 16-Bit CLA

Sravankumar pagadala, Department of

22
ECE, JNTU Hyderabad
 4-Bit Carry Look-Ahead Adder
VHDL Description of a 4-Bit Carry Look-Ahead Adder
entity CLA4 is
port(A, B: in bit_vector(3 downto 0); Ci: in bit; // Inputs
S: out bit_vector(3 downto 0);
Co, PG, GG: out bit); // Outputs end CLA4;
architecture Structure of CLA4 is
component GPFullAdder
port(X, Y, Cin: in bit; // Inputs
G, P, Sum: out bit); // Outputs
end component;

component CLALogic is
port(G, P: in bit_vector(3 downto 0);
Ci: in bit; // Inputs
C: out bit_vector(3 downto 1);
Co, PG, GG: out bit); // Outputs end component;
signal G, P: bit_vector(3 downto 0); // carry internal signals
signal C: bit_vector(3 downto 1);
begin // instantiate four copies of the GPFullAdder
CarryLogic: CLALogic port map (G, P, Ci, C, Co, PG, GG);
FA0: GPFullAdder port map (A(0), B(0), Ci, G(0), P(0), S(0));
FA1: GPFullAdder port map (A(1), B(1), C(1), G(1), P(1), S(1));
FA2: GPFullAdder port map (A(2), B(2), C(2), G(2), P(2), S(2));
FA3: GPFullAdder port map (A(3), B(3), C(3), G(3), P(3), S(3));
end Structure;
entity CLALogic is
port(G, P: in bit_vector(3 downto 0);
Ci: in bit; // Inputs
C: out bit_vector(3 downto 1);
Co, PG, GG: out bit); // Outputs
end CLALogic;
architecture Equations of CLALogic is
signal GG_int, PG_int: bit;
Begin // concurrent assignment statements
C(1) <= G(0) or (P(0) and Ci);
C(2) <= G(1) or (P(1) and G(0)) or (P(1) and P(0) and Ci);
C(3) <= G(2) or (P(2) and G(1)) or (P(2) and P(1) and G(0)) or (P(2) and P(1) and P(0) and Ci);
PG_int <= P(3) and P(2) and P(1) and P(0);
GG_int <= G(3) or (P(3) and G(2)) or (P(3) and P(2) and G(1)) or (P(3) and P(2) and P(1) and G(0));
Co <= GG_int or (PG_int and Ci);
PG <= PG_int;
GG <= GG_int;
end Equations;
entity GPFullAdder is
port(X, Y, Cin: in bit; // Inputs
G, P, Sum: out bit); // Outputs
end GPFullAdder;
architecture Equations of GPFullAdder is
signal P_int: bit;
begin // concurrent assignment statements
G <= X and Y;
P <= P_int;
P_int <= X xor Y;
Sum <= P_int xor Cin;
end Equations;

Sravankumar pagadala, Department of

23
ECE, JNTU Hyderabad
 A BCD Adder
Behavioral Model for a 32-Bit Adder
library IEEE;
use IEEE.numeric_bit.all;
entity Adder32 is
port(A, B: in unsigned(31 downto 0); Ci: in bit; //Inputs
S: out unsigned(31 downto 0); Co: out bit); //Outputs
end Adder32;
architecture overload of Adder32 is
signal Sum33: unsigned(32 downto 0);
Begin
Sum33 <= '0' & A + B + unsigned'(0=>Ci); //adder
S <= Sum33(31 downto 0);
Co <= Sum33(32);
end overload;

Sravankumar pagadala, Department of

24
ECE, JNTU Hyderabad
 State Graphs for Control Circuits
 Control state graphs using variable names instead of 0’s and 1’s.
 Mealy state graph will be labeled as inputs/outputs. Ex: X1 /Z2 Z3=1000/0110.
 Must place the following constraints on the input labels for every state Sk.
 If Ii and Ij are any pair of input labels on arcs exiting state Sk, then IiIj=0 if I ≠ j.
 If n arcs exit state Sk and the n arcs have input labels I1,I2,. . .,In, respectively, then
I1+I2+ ...In =1.

 The preceding partial state graph represents the following state table

Sravankumar pagadala, Department of

25
ECE, JNTU Hyderabad
 Scoreboard and Controller
 Data Path:
 The design will be a two-digit BCD counter to perform the counting.
 We will also require BCD to seven-segment decoders.
 Reset should happen only after pressing reset for 5 clock cycles, used 3-bit reset counter
called rstcnt.

Overview of Simple Scoreboard

 Controller:
 There are two states in this FSM. S0 is an initialization state where all the counters are
cleared.
 counting gets done for every clock cycle, incrementing or decrementing is done according to
the input signals.
 If reset signal rst arrives, the rstcnt is incremented.
 If the inc=1 and dec=0, the BCD, counter is incremented.
 If the inc=0 and dec=1, the BCD, counter is decremented.
 The sub1 indicate that the BCD counter is decremented.
 If both the inc and dec signals are true, or neither are true, the reset counter (rstcnt) is
cleared and the BCD counter is left unchanged.
Sravankumar pagadala, Department of
26
ECE, JNTU Hyderabad
 Scoreboard and Controller
 Controller:

State Graph for Scoreboard

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ECE, JNTU Hyderabad
 Scoreboard and Controller
 VHDL Model :
library IEEE;
use IEEE.numeric_bit.all; //any package with overloaded add and subtract

entity Scoreboard is
port(clk, rst, inc, dec: in bit;
S eg7disp1, seg7disp0: out unsigned(6 downto 0));
end Scoreboard;

architecture Behavioral of Scoreboard is

signal State: integer range 0 to 1;
signal BCD1, BCD0: unsigned(3 downto 0) := "0000"; -- unsigned bit vector
signal rstcnt: integer range 0 to 4 := 0;
type sevsegarray is array (0 to 9) of unsigned(6 downto 0);
constant seg7Rom: sevsegarray := ("0111111", "0000110", "1011011", "1001111", "1100110", "1101101", "1111100",
"0000111", "1111111", "1100111"); // active high with "gfedcba" order
begin
process(clk)
begin
if clk'event and clk = '1' then
case State is
when 0 => -- initial state
BCD1 <= "0000"; BCD0 <= "0000"; //clear counter
rstcnt <= 0; -- reset RESETCOUNT
State <= 1;
when 1 => //state in which the scoreboard waits for inc and dec
if rst = '1' then
if rstcnt = 4 then //checking whether 5th reset cycle
State <= 0;
else rstcnt <= rstcnt + 1;
end if;
elsif inc = '1' and dec = '0' then
rstcnt <= 0;
if BCD0 < "1001" then
BCD0 <= BCD0 + 1; //library with overloaded "+" required
elsif BCD1 < "1001" then
BCD1 <= BCD1 + 1;
BCD0 <= "0000"; Sravankumar pagadala, Department of
end if;
ECE, JNTU Hyderabad 28
 Scoreboard and Controller
 VHDL Model :
elsif dec = '1' and inc = '0' then
rstcnt <= 0;
if BCD0 > "0000" then
BCD0 <= BCD0 - 1; //library with overloaded "-" required
elsif BCD1 > "0000" then
BCD1 <= BCD1 - 1;
BCD0 <= "1001";
end if;
elsif (inc = '1' and dec = '1') or (inc = '0' and dec = '0') then
rstcnt <= 0;
end if;
end case;
end if;
end process;
seg7disp0 <= seg7rom(to_integer(BCD0)); -- type conversion function from
seg7disp1 <= seg7rom(to_integer(BCD1)); -- IEEE numeric_bit package used
end Behavioral;
BCD0 <= "0000";
end if;
Sravankumar pagadala, Department of
ECE, JNTU Hyderabad 29
 A shift and add multiplier
 we form the product A B, A is called the multiplicand, B is called the multiplier.
 Binary multiplication requires only shifting and adding.

 The multiplicand (1101) shifted over by the appropriate number of places or zero.
 Instead of forming all the partial products first and then adding.
 This eliminates the need for adding more than two binary numbers at a time.
 Multiplication of two 4-bit numbers requires
1. a 4-bit multiplicand register.
2. a 4-bit multiplier register.
3. a 4-bit full adder, and
4. an 8-bit register for the product.

Sravankumar pagadala, Department of

ECE, JNTU Hyderabad 30
 A shift and add multiplier

Diagram for Binary Multiplier

 The product register serves as an accumulator to accumulate the sum of the partial
products.
 If the multiplicand were shifted left each time before it was added to the
accumulator.
 So it is better to shift the contents of the product register to the right each time.
 This type of multiplier is sometimes referred to as a serial-parallel multiplier
Sravankumar pagadala, Department of
ECE, JNTU Hyderabad 31
 A shift and add multiplier
 The multiplier bits are processed serially, but the addition takes place in parallel.
 4 bits from the accumulator (ACC) and 4 bits from the multiplicand register are
connected to the adder inputs.
 The 4 sum bits and the carry output from the adder are connected back to the
accumulator.
 When Add signal (Ad) occurs, the adder outputs are transferred to the accumulator
by the next clock pulse, thus causing the multiplicand to be added to the
accumulator .
 An extra bit at the left end of the product register temporarily stores any carry that
is generated when the multiplicand is added to the accumulator.
 Since the lower 4 bits of the product register are initially unused, we will store the
multiplier in this location instead of in a separate register.
 each multiplier bit is used, it is shifted out the right end of the register to make
room for additional product bits.
 A signal Sh causes the contents of the product register (including the multiplier) to
be shifted right one place when the next clock pulse occurs.
 The control circuit puts out the proper sequence of add and shift signals after a start
signal (St 1) has been received.

Sravankumar pagadala, Department of

ECE, JNTU Hyderabad 32
 A shift and add multiplier
 If the current multiplier bit (M) is 1, the multiplicand is added to the accumulator
followed by a right shift. Otherwise addition is skipped and only the right shift
occurs.

State Graph for Binary Multiplier Control

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ECE, JNTU Hyderabad 33
A shift and add multiplier

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ECE, JNTU Hyderabad 34
A shift and add multiplier

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ECE, JNTU Hyderabad 35
A shift and add multiplier

Multiplier Control with Counter

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ECE, JNTU Hyderabad 36
A shift and add multiplier

Operation of Multiplier Using a Counter

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ECE, JNTU Hyderabad 37
 Array Multiplier
 It is a parallel multiplier that generates the partial products in a parallel fashion.
 Two 4-bit unsigned numbers, X3X2X1X0 and Y3Y2Y1Y0, are multiplied to generate
a product that is possibly 8 bits.

Four-bit Multiplier Partial Products

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ECE, JNTU Hyderabad 38
 Array Multiplier

Block Diagram of 4X4 Array Multiplier

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ECE, JNTU Hyderabad 39
VHDL Code for 4X4 Array Multiplier
Array Multiplier Block Diagram of 4X4 Array Multiplier

entity Array_Mult is
port(X, Y: in bit_vector(3 downto 0);
P: out bit_vector(7 downto 0));
end Array_Mult;
architecture Behavioral of Array_Mult is
signal C1, C2, C3: bit_vector(3 downto 0);
signal S1, S2, S3: bit_vector(3 downto 0);
signal XY0, XY1, XY2, XY3: bit_vector(3 downto 0);
component FullAdder port(X, Y, Cin: in bit; Cout, Sum: out bit);
end component;
component HalfAdder
port(X, Y: in bit; Cout, Sum: out bit)
end component;
Begin
XY0(0) <= X(0) and Y(0); XY1(0) <= X(0) and Y(1); XY0(1) <= X(1) and Y(0); XY1(1) <= X(1) and Y(1); XY0(2) <= X(2) and Y(0); XY1(2) <=
X(2) and Y(1); XY0(3) <= X(3) and Y(0); XY1(3) <= X(3) and Y(1);
XY2(0) <= X(0) and Y(2); XY3(0) <= X(0) and Y(3); XY2(1) <= X(1) and Y(2); XY3(1) <= X(1) and Y(3); XY2(2) <= X(2) and Y(2); XY3(2) <=
X(2) and Y(3); XY2(3) <= X(3) and Y(2); XY3(3) <= X(3) and Y(3);
FA1: FullAdder port map (XY0(2), XY1(1), C1(0), C1(1), S1(1)); FA2:
FullAdder port map (XY0(3), XY1(2), C1(1), C1(2), S1(2));
FA3: FullAdder port map (S1(2), XY2(1), C2(0), C2(1), S2(1));
FA4: FullAdder port map (S1(3), XY2(2), C2(1), C2(2), S2(2));
FA5: FullAdder port map (C1(3), XY2(3), C2(2), C2(3), S2(3));
FA6: FullAdder port map (S2(2), XY3(1), C3(0), C3(1), S3(1));
FA7: FullAdder port map (S2(3), XY3(2), C3(1), C3(2), S3(2));
FA8: FullAdder port map (C2(3), XY3(3), C3(2), C3(3), S3(3));
HA1: HalfAdder port map (XY0(1), XY1(0), C1(0), S1(0));
HA2: HalfAdder port map (XY1(3), C1(2), C1(3), S1(3));
HA3: HalfAdder port map (S1(1), XY2(0), C2(0), S2(0));
HA4: HalfAdder port map (S2(1), XY3(0), C3(0), S3(0));
P(0) <= XY0(0); P(1) <= S1(0); P(2) <= S2(0);
P(3) <= S3(0); P(4) <= S3(1);
P(5) <= S3(2); P(6) <= S3(3);
P(7) <= C3(3);
end Behavioral; //Full Adder and half adder entity and architecture descriptions –– should be in the project

Sravankumar pagadala, Department of

ECE, JNTU Hyderabad 40
 Array Multiplier
VHDL Code for Full Adder and half adder of 4X4 Array Multiplier

entity FullAdder is
port(X, Y, Cin: in bit; Cout, Sum: out bit);
end FullAdder;
architecture equations of FullAdder is
begin
Sum <= X xor Y xor Cin;
Cout <= (X and Y) or (X and Cin) or (Y and Cin);
end equations;
entity HalfAdder is
port(X, Y: in bit; Cout,Sum: out bit);
end HalfAdder;
architecture equations of HalfAdder is
Begin
Sum <= X xor Y; Cout <= X and Y;
end equations;

Sravankumar pagadala, Department of

ECE, JNTU Hyderabad 41
 Keypad Scanner
 The keypad is wired in matrix form with a switch at the intersection of each row
and column.
 The purpose of the scanner is to determine which key has been pressed.
 Produces a binary number N=N3N2N1N0, corresponds to the key number.
 example: pressing key 5 must output 0101.
pressing the * key must output 1010, and
pressing the # key must output 1011.

Keypad with Three

Columns and Four Rows

Block Diagram for Keypad Scanner

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ECE, JNTU Hyderabad 42
 Keypad Scanner
 The design will divide into several modules.
1. Scanner
2. Debounce
3. Decoder
 Scanner
 apply logic 1’s to columns C0,C1,and C2 and wait, 1 will appear on R0,R1,R2, or R3
when any key is pressed.
 apply a 1 to column C0 If any of the Ri’s is 1,a valid key is detected.
 If R1, R2, or R3 is received, switch 4,7,or * was pressed.
 apply 1’s to C0, C1, and C2 and wait until no key is pressed.

Scanner Modules

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ECE, JNTU Hyderabad 43
 Keypad Scanner
 Debouncer
 generates a signal K when a key has been pressed and a signal Kd after it has been debounced.
 we need to debounce the keys to avoid malfunctions due to switch bounce.

Debouncing and Synchronizing Circuit

 Decoder
 determines the key number from the row and column numbers.

Truth Table for Decoder

Sravankumar pagadala, Department of

ECE, JNTU Hyderabad 44
 Keypad Scanner
 Controller
 Machine State will be S1 with outputs C0= C1= C2= 1 until a key is pressed.
 In S2, C0=1, if the key that was pressed is in column 0,K=1, If R1, R2, or R3 is received,
switch 4,7,or * was pressed.

State Graph for Keypad Scanner

Sravankumar pagadala, Department of

ECE, JNTU Hyderabad 45
 Keypad Scanner
 Controller
 The state diagram works for many cases, it does have some timing problems.
 Is K true whenever a button is pressed?
 No K is true only if any one of row signals (R1,R2,R3,or R4) is true.
 If the column scan signals are not active, none of R1–R4 can be.

 Can Kd be false when a button is continuing to be pressed?

 Yes, K can go to 0 during the scan process even when the button is being pressed

 Can you go from S5 to S1 when a button is still pressed?

 the S4-to-S5 transition could happen when Kd is false.
 Kd might have become false while scanning C0 and C1.
 scanning process in S2 and S3, K is 0; Kd=K after two cycles later.
 the system can reach S5 when Kd is still 0 and a malfunction can happen.
 What if a key is pressed for only one or two clock cycles?
 This may not be a serious problem because usually the digital system clock is much
faster than any mechanical switch.

Scanner Modules

Sravankumar pagadala, Department of

ECE, JNTU Hyderabad 46
 Keypad Scanner
 Controller
 These problems can be fixed by assuring that we can reach S5 only if Kd is true.
 This circuit waits in state S2,S3,and S4 until Kd also becomes 1.Before transitioning to
state S5.

Modified State Graph for Keypad Scanner

Sravankumar pagadala, Department of

ECE, JNTU Hyderabad 47
 Binary Dividers
 Controller
 Binary division can be carried out by a series of subtract and shift operations

Block Diagram for Parallel Binary Divider

Sravankumar pagadala, Department of

ECE, JNTU Hyderabad 48
 Binary Dividers
 Controller
 Binary division can be carried out by a series of subtract and shift operations

State Diagram for Divider Control Circuit

State Table for Divider Control Circuit

Sravankumar pagadala, Department of

ECE, JNTU Hyderabad 49
Sravankumar pagadala, Department of
50
ECE, JNTU Hyderabad