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II Unit PDF
II Unit PDF
Digital Design
Digital designs can also be realized using PLAs (programmable logic arrays) and
flip-flops in a manner similar to using ROMs and flip-flops.
State assignment is important, because good state assignment can reduce no. of
product terms required.
delays are Tg ,a 1-bit adder delay is 2Tg. a 32-bit ripple-carry adder will take
approximately 64 gate delays. If Tg = 1ns maximum operating frequency for 32-bit
ripple-carry adder is 16 MHz (approximately).
component CLALogic is
port(G, P: in bit_vector(3 downto 0);
Ci: in bit; // Inputs
C: out bit_vector(3 downto 1);
Co, PG, GG: out bit); // Outputs end component;
signal G, P: bit_vector(3 downto 0); // carry internal signals
signal C: bit_vector(3 downto 1);
begin // instantiate four copies of the GPFullAdder
CarryLogic: CLALogic port map (G, P, Ci, C, Co, PG, GG);
FA0: GPFullAdder port map (A(0), B(0), Ci, G(0), P(0), S(0));
FA1: GPFullAdder port map (A(1), B(1), C(1), G(1), P(1), S(1));
FA2: GPFullAdder port map (A(2), B(2), C(2), G(2), P(2), S(2));
FA3: GPFullAdder port map (A(3), B(3), C(3), G(3), P(3), S(3));
end Structure;
entity CLALogic is
port(G, P: in bit_vector(3 downto 0);
Ci: in bit; // Inputs
C: out bit_vector(3 downto 1);
Co, PG, GG: out bit); // Outputs
end CLALogic;
architecture Equations of CLALogic is
signal GG_int, PG_int: bit;
Begin // concurrent assignment statements
C(1) <= G(0) or (P(0) and Ci);
C(2) <= G(1) or (P(1) and G(0)) or (P(1) and P(0) and Ci);
C(3) <= G(2) or (P(2) and G(1)) or (P(2) and P(1) and G(0)) or (P(2) and P(1) and P(0) and Ci);
PG_int <= P(3) and P(2) and P(1) and P(0);
GG_int <= G(3) or (P(3) and G(2)) or (P(3) and P(2) and G(1)) or (P(3) and P(2) and P(1) and G(0));
Co <= GG_int or (PG_int and Ci);
PG <= PG_int;
GG <= GG_int;
end Equations;
entity GPFullAdder is
port(X, Y, Cin: in bit; // Inputs
G, P, Sum: out bit); // Outputs
end GPFullAdder;
architecture Equations of GPFullAdder is
signal P_int: bit;
begin // concurrent assignment statements
G <= X and Y;
P <= P_int;
P_int <= X xor Y;
Sum <= P_int xor Cin;
end Equations;
The preceding partial state graph represents the following state table
entity Scoreboard is
port(clk, rst, inc, dec: in bit;
S eg7disp1, seg7disp0: out unsigned(6 downto 0));
end Scoreboard;
The multiplicand (1101) shifted over by the appropriate number of places or zero.
Instead of forming all the partial products first and then adding.
This eliminates the need for adding more than two binary numbers at a time.
Multiplication of two 4-bit numbers requires
1. a 4-bit multiplicand register.
2. a 4-bit multiplier register.
3. a 4-bit full adder, and
4. an 8-bit register for the product.
entity Array_Mult is
port(X, Y: in bit_vector(3 downto 0);
P: out bit_vector(7 downto 0));
end Array_Mult;
architecture Behavioral of Array_Mult is
signal C1, C2, C3: bit_vector(3 downto 0);
signal S1, S2, S3: bit_vector(3 downto 0);
signal XY0, XY1, XY2, XY3: bit_vector(3 downto 0);
component FullAdder port(X, Y, Cin: in bit; Cout, Sum: out bit);
end component;
component HalfAdder
port(X, Y: in bit; Cout, Sum: out bit)
end component;
Begin
XY0(0) <= X(0) and Y(0); XY1(0) <= X(0) and Y(1); XY0(1) <= X(1) and Y(0); XY1(1) <= X(1) and Y(1); XY0(2) <= X(2) and Y(0); XY1(2) <=
X(2) and Y(1); XY0(3) <= X(3) and Y(0); XY1(3) <= X(3) and Y(1);
XY2(0) <= X(0) and Y(2); XY3(0) <= X(0) and Y(3); XY2(1) <= X(1) and Y(2); XY3(1) <= X(1) and Y(3); XY2(2) <= X(2) and Y(2); XY3(2) <=
X(2) and Y(3); XY2(3) <= X(3) and Y(2); XY3(3) <= X(3) and Y(3);
FA1: FullAdder port map (XY0(2), XY1(1), C1(0), C1(1), S1(1)); FA2:
FullAdder port map (XY0(3), XY1(2), C1(1), C1(2), S1(2));
FA3: FullAdder port map (S1(2), XY2(1), C2(0), C2(1), S2(1));
FA4: FullAdder port map (S1(3), XY2(2), C2(1), C2(2), S2(2));
FA5: FullAdder port map (C1(3), XY2(3), C2(2), C2(3), S2(3));
FA6: FullAdder port map (S2(2), XY3(1), C3(0), C3(1), S3(1));
FA7: FullAdder port map (S2(3), XY3(2), C3(1), C3(2), S3(2));
FA8: FullAdder port map (C2(3), XY3(3), C3(2), C3(3), S3(3));
HA1: HalfAdder port map (XY0(1), XY1(0), C1(0), S1(0));
HA2: HalfAdder port map (XY1(3), C1(2), C1(3), S1(3));
HA3: HalfAdder port map (S1(1), XY2(0), C2(0), S2(0));
HA4: HalfAdder port map (S2(1), XY3(0), C3(0), S3(0));
P(0) <= XY0(0); P(1) <= S1(0); P(2) <= S2(0);
P(3) <= S3(0); P(4) <= S3(1);
P(5) <= S3(2); P(6) <= S3(3);
P(7) <= C3(3);
end Behavioral; //Full Adder and half adder entity and architecture descriptions –– should be in the project
entity FullAdder is
port(X, Y, Cin: in bit; Cout, Sum: out bit);
end FullAdder;
architecture equations of FullAdder is
begin
Sum <= X xor Y xor Cin;
Cout <= (X and Y) or (X and Cin) or (Y and Cin);
end equations;
entity HalfAdder is
port(X, Y: in bit; Cout,Sum: out bit);
end HalfAdder;
architecture equations of HalfAdder is
Begin
Sum <= X xor Y; Cout <= X and Y;
end equations;
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