Practical Buck Design Revised 2018

See discussions, stats, and author profiles for this publication at: https://www.researchgate.
net/publication/321903540
Practical Design of Buck Converter By Tauﬁk
Presentation · December 2017
CITATIONS READS
0 1,370
1 author:
Taufik Taufik
California Polytechnic State University, San Luis Obispo
161 PUBLICATIONS 514 CITATIONS
SEE PROFILE
Some of the authors of this publication are also working on these related projects:
The DC House Project View project
Comparison of the Utilization of 110 °C and 120 °C Heat Sources in a Geothermal Energy System Using Organic Rankine Cycle (ORC) with R245fa, R123, and Mixed-Ratio
Fluids as Working Fluids View project
All content following this page was uploaded by Taufik Taufik on 20 December 2017.
The user has requested enhancement of the downloaded file.

Practical Design of Buck Converter
Dr. TAUFIK
Professor of Electrical Engineering

Director of Electric Power Institute
California Polytechnic State University, San Luis Obispo, USA
taufik@calpoly.edu
http://www.ee.calpoly.edu/faculty/taufik
Outline
• DC-DC Converter Basics
• Design Equations
• Loss Considerations
• Layout Considerations
• Efficiency Improvements
• Controller
Practical Design of Buck Converter Taufik | Page 2

DC-DC Converter Basics
• A circuit employing switching network that
converts a DC voltage at one level to
another DC voltage
• Two basic topologies:
– Non-Isolated
• Buck, Boost, Buck-Boost, Cuk, SEPIC, Zeta
– Isolated
• Push-pull, Forward, Flyback, Half-Bridge,
Full-Bridge

VS
• When ON: The output voltage is the same as the input

voltage and the voltage across the switch is 0 V.
• When OFF: The output voltage is zero and there is no current
through the switch.
• Ideally, the Power Loss is zero since output power = input
power
• Periodic opening and closing of the switch results in pulse
output
VS
• Duty Cycle range: 0 < D < 1

• Two ways to vary the average output voltage:
– Pulse Width Modulation (PWM), where ton is varied while the
overall switching period T is kept constant
– Pulse Frequency Modulation (PFM), where ton is kept constant
while the switching period T is varied
VS

VS

Review: DC-DC Converter Basics
Source Side Load/User Side
DC-DC
VS Converter
Wants: Wants:
to switch
DC Voltage and DC controller
DC Voltage and DC
Current Current
Wants:
No AC Component
No Harmonics

Source Side Load/User Side

+ DC-DC
VS _ Converter
Gets: Gets:
Current with some Voltage with some

ripple ripple
Needs Filtering

What is Buck Converter?
• A dc-dc converter circuit that steps down a dc voltage at
its input
• Non-isolated, hence ideal for board-level circuitry where
local conversion is needed
– Cell-phones, PDAs, fax machines, copiers, scanners,
computers, anywhere when there is the need to convert
DC from one level (battery) to other levels
• Widely used in low voltage low power applications
(though it may be used for KW applications as well)

Basic Topology
VS
• Recall the basic switching circuit above produces

square-wave output
• The square-wave output voltage contains significant
ripple at switching frequency
• Switching frequency is typically high (10’s to 100’s of
kHz), so why not add a low pass LC filter
Basic Topology
Low Pass Filter
VS
• Above circuit has a serious problem!

– Switch is on, current flows through inductor
– Switch is off, inductor current refuses to stop creating a high
voltage across the switch, destroying the switch
• Add a freewheeling diode to provide the continuity of inductor
current when the switch is off

Basic Topology
• After adding the diode, the circuit is the power stage of a

BUCK converter!
• What is still missing is a mechanism to regulate the
output voltage
– The need to have a feedback control to close the loop

The Basic Topology
Controller
• Two types of Conduction Modes
– Continuous Conduction Mode (CCM)
where Inductor current remains positive
throughout the switching period
– Discontinuous Conduction Mode (DCM)
where Inductor current remains zero for
some time in the switching period
– Boundary Conduction Mode (BCM)
The Basic Topology
CCM
DCM

Steady State Analysis of CCM Buck: Transfer Function
• Inductor is the main storage element

• Transfer function may be derived from Volt Second
Balance (VSB):
– Average Voltage across Inductor is Zero in steady state
– Inductor looks like a short to a DC

CCM Buck: Transfer Function
• When the switch is closed or ON

– Diode is reverse biased since
• Cathode (at Positive of Input) is more positive than
Anode (at 0 V)
– Voltage across inductor:
– Recall that: D = ton/T
– Then, duration of on time, ton:
• When the switch is OPEN or OFF

– Source is disconnected while load still demands energy
– Forces inductor discharges causing its voltage to reverse polarity
– In turn, makes the diode to be forward biased and conduct current
since
• Anode (0 V) is more positive than the Cathode (at some
negative voltage)
– Voltage across inductor:
– Recall that:
vLon ton  vLoff toff  0
VS  VO  DT   VO 1  D  T  0

VS D  VO D  VO  VO D  0
VO  DVS
• Average output voltage is LESS than Input Voltage

since 0 < D < 1

CCM Buck: Sizing Components
For MOSFETs: Vds and Id L and Ipk
Vrrm, and If C, V and Irms

C, V and Irms
A MUST HAVE!!!

CCM Buck: Inductor Current
• When switch is ON, Inductor is charging:
di L diL VS  VO
v L  V S  VO  L  
dt dt L
VS  VO
iLon  ton
L
V V
iLon  S O DT
L

• When switch is OFF, Inductor is
discharging:
diL diL VO
vL  VO  L   
dt dt L
V
iLoff  O toff
L
VO
iLoff  1  D  T
L

Average Inductor
Current = Average
Output Current = Vo/R
since average
capacitor current = 0 A
iL
 We can then determine ILmin and ILmax

iL V0 1 V0   1 (1  D) 
I L min IL    (1  D)T   V0   
2 R 2 L   R 2 Lf 
iL V0 1  V0   1 (1  D ) 
I L max IL    (1  D )T   V0   
2 R 2L   R 2 Lf 
Sizing Inductor: Critical Inductance
Minimum Load
(output current)
 ILmin is used to determine the Critical Inductance (Minimum

Inductance value at which the inductor current reaches Boundary
Conduction Mode)
 Any inductance lower than critical inductance will cause the buck to
operate in Discontinuous Conduction Mode
 Requirement is set either by means of maximum ∆iL or by
specifying the minimum percentage load where converter still
maintains CCM
 Set ILmin = 0, then solve for L = LC, then choose L > LC
iL  1 (1  D)  (1  Dmax ) Rmax

I L min  0  I L   V0    LC 
2 R
 max 2 LC f  2f
(1  Dmax ) Rmax
LC 
2f
Calculated at Minimum  Calculated at Minimum Output

Input Voltage Current = Rmax = Vo/Iomin
 Iomin is either given as
percentage of load to maintain
CCM, e.g. 10% load with CCM
 Switching frequency typically
chosen by the designer  Or, Iomin is calculated as
specified by maximum ∆iL,
 The higher the switching
such that Iomin = ∆iL/2
frequency, the smaller the required
critical inductance, i.e. beneficial
for reducing size of Buck

• A more practical approach is to size the critical
inductance by using percent peak to peak inductor
current ripple ΔiL based on the maximum load current
(calculated at maximum output power)
• ΔiL is typically chosen between 30% to 40% of Iomax
(considering physical size, cost, losses, stability)
Practical Design of Buck Converter | Page 26

• The equation may be calculated from ON time or OFF
time of the switch
• Using the ON time:
• Using the OFF time:
• Thus:

Sizing Inductor: Peak Current
Maximum Load
(output current)
 ILmax is used to determine peak current rating of Inductor

 Worst case maximum inductor current occurs at maximum
load  Maximum output power rating per specified required
output voltage
Calculated from
iL  1 (1  Dmin ) 
I L max IL  V0    Highest Input
2 R
 min 2 Lf  Voltage
Chosen inductance value as

discussed previously
Sizing Switch: Voltage Rating
 With ideal diode and ideal buck, the Vswitch-max = Vinmax

 For non-ideal diode, Vswitch-max = Vinmax + VF where VF is the
maximum forward drop across the diode (calculated at
maximum load current)
 Use safety factor of at least 20%
 For synchronous MOSFET, the rating would be VDSmax
Sizing Switch: Current Rating
 Switch current rating is calculated based on average

value
 Draw switch current waveform and then compute the
average value
 By KCL, Inductor Current = Switch Current + Diode Current
 During tON, Inductor current equals switch current
 During tOFF, Inductor current equals diode current
Switch Current Waveform
iL
ON OFF ON OFF ON OFF

t
T 2T 3T
iSwitch
iDiode

Switch Current Waveform for Current Rating
iLmax
iSwitch
iLmin
Average Value
ON ON ON
t
0 T 2T
Average Switch Current is calculated from the area of the trapezoid

MOSFET Rating Example

Sizing Diode (Schottky): Voltage Rating
 Known as VRRM is the maximum reverse voltage across the

diode
 With ideal switch, the VRRM = Vinmax
 For non-ideal diode, VRRM = Vinmax + VSW where VSW is the
maximum forward drop across the switch (calculated at
maximum load current)
 Allow at least > 20% safety factor

Sizing Diode (Schottky): Current Rating
 Same approach as that for the switch current
iDiode Average Value
OFF OFF OFF

t
T 2T 3T
 iL min  iL max   toff

IF 
2 T
IF 
iL max  iL   iL max   1  D  T 
 2iL max  iL   1  D 
2 T 2
I F  I L  1  D   I o  1  D 
I F  I o max  1  Dmin 
Schottky Diode Rating Example
Courtesy of Infineon

Sizing Output Capacitor: Voltage Rating
• Capacitor Voltage should withstand the maximum output

voltage
– Ideally: Vcmax = Vo + ∆Vo/2
– More realistic: Capacitor has ESR (Equivalent Series
Resistance) which worsens ∆Vo
– Output voltage ripple contributed by ESR is (ESR * ∆IL)
– Suppressing ripple contribution from ESR
• Reduce ESR (Paralleling Caps, Low ESR Caps)
• Reduce ∆IL by increasing L or increasing switching frequency
Sizing Output Capacitor: Minimum Capacitance
• The AC component (ripple) of inductor current flows

through the capacitor, leaving the average flowing
through the load
• Capacitor current waveform will look like:
iC
0 t
T 2T 3T

Sizing Output Capacitor: Minimum Capacitance
+Q
iC
-Q t
T/2
VO
1  T   iL  iL 1  D  T 1  D VO
q  Area         L 
2  2  2  8 f 8f 8Lf 2
q  C  Vo  C 
q

1  D  VO

1 D
Vo 8 Lf Vo 8 Lf 2  Vo VO 
2
C
1  Dmin 
8Lf 2  Vo VO  Percent Vopp
Sizing Output Capacitor: RMS Current Rating
iLmax – Io = ∆iL/2
iC
t
T 2T 3T

Sizing Input Capacitor: Voltage Rating
• Capacitor Voltage should withstand the max input voltage

– Ideally: Vcmax = Vinmax
– More realistic: Capacitor has ESR (Equivalent Series
Resistance) contributes to capacitor loss
– Use of Electrolytic for energy storage in parallel with
ceramic for high frequency transient energy requirement
– Minimizing loss contribution from ESR
• Reduce ESR (Paralleling Caps, Low ESR Caps)
Sizing Input Capacitor: Minimum Capacitance
iC iLmax – D*IO
0 t
– D*IO
T 2T 3T
q  Area   toff  D  I O  1  D  T  D  I O 
1  D   D  IO
f
1  D   D  IO
q  C  Vin  C 
q

f

1  D   D  IO
Vin Vin f Vin
C
1  D   D  I O max
f Vin
Sizing Input Capacitor: RMS Current Rating
iC iLmax – D*IO
0 t
– D*IO
T 2T 3T
Recall
 I Switchrms    I switch avg 

2 2
I Crms 
2
   iL   
     D  I o 
 2
I Crms  I o D 1  
   2  Io   
 
To Summarize
 1 (1  Dmin ) 
I L max  V0   
I Switch  max  I o max  Dmax R
 min 2 Lf 
Vswitch-max = Vinmax (1  Dmax ) Rmax
LC 
2f
C
1  Dmin 
   i   
2
8 Lf 2  Vo VO 
  I o D  1   L      D  I o 
I F  I o max  1  Dmin 
2
I Crms

   2  I o    Vcmax = Vo + ∆Vo/2
C
1  D   D  I O max VRRM = Vinmax
iCrms 
1  Dmin VO
f Vin 2 3L
Simple Buck Design: 12V to 2.5V 1A
Given: Vs  12V Vo  2.5V Iomax  1A
Ioccm  0.1A %Vo  1% f  50kHz
Solution:
Vo
D  D  0.208
Vs
Inductor:
( 1  D) Vo 4
Lcrit   Lcrit  1.979  10 H
2 f Ioccm
6
Choose: L  200 10 H
( 1  D) Vo
ILmax  Iomax  ILmax  1.099 A
2 Lf
( 1  D) Vo
IL  IL  0.198 A
Lf
MOSFET:
Vds  Vs Vds  12 V
Id  DIomax Id  0.208 A
Diode:
Vrrm  Vs Vrrm  12 V
If  ( 1  D) Iomax If  0.792 A
Capacitor:
%VoVo
Vcmax  Vo  Vcmax  2.513 V
2
( 1  D) 1 5
C   C  1.979  10 F
2 %Vo
8 Lf
6
Choose Co  50 10 F
( 1  D)
%Vo  %Vo  0.396 %
2
8 Lf Co
Simple Buck Design: 12V to 2.5V 1A L1
1 2
200u
S1
-
++
-
V1 Sbreak D1 R1
12 Dbreak C1
2.5
50u
V1 = 0 V2
V2 = 1
TD = 0
TR = 10n
TF = 10n
PW = {(3.185/12)*(1/50k)}
PER = {1/50k}

1.25A Inductor Current
1.00A
SEL>>
0.59A
I(L1)
2.0A
Input Current
1.0A
0A
3.6800ms 3.7000ms 3.7200ms 3.7400ms 3.7600ms 3.7800ms 3.8000ms 3.8182ms
-I(V1)
Time

Closing the Loop
• As a minimum requirement, a practical buck converter must
employ a voltage feedback by sensing its output voltage to
maintain a constant output voltage
– This method is called the Voltage Mode Control
– The more popular method is the Current Mode Control
where another feedback mechanism is provided
(explained later)
• With Voltage Mode, the output voltage is sensed by a voltage
divider whose mid-output voltage is compared with a
reference voltage provided inside a controller  Error Signal
• The controller then processes the error signal to generate a
pulse signal outputted into the switch (gate of the MOSFET
used in the Buck as an example)

Closing the Loop
Analog Devices
www.analog.com
• Circuit diagram of Voltage Mode Control is shown above (courtesy of

Analog Devices, Application Note 140-9)
• In practice, resistors R1 and R2 must be large enough to prevent loading
• Often, potentiometer is used for R1 for fine adjustment of output voltage
• R2 is part of feedback path and sometimes a series RC network is connected in
parallel with R2 for compensation purpose
Closing the Loop
Analog Devices
www.analog.com
• Circuit diagram of Current Mode Control is shown above (courtesy of

Analog Devices, Application Note 140-9)
• In practice, the additional sensor is for current through the TOP MOSFET
since it carries the same peak current information as the inductor current,
plus it is for the more efficient sensing method
Closing the Loop
Analog Devices
www.analog.com
1.24 Voltage
Reference
• Output of voltage divider must be set to equal to the reference

voltage (1.24V in above example) per desired output voltage

Closing the Loop
• Referring to previous two figures, if say a 5V output is desired then R1 and
R2 are set following voltage divider equation
• Note that Vreference and Vout are known, R1 and R2 are not
• Select R2 then solve for R1 (since R1 may use potentiometer)
• If say R2 is chosen to be 100 k, then for a 5V output with 1.24V reference
the R1 value will be

Buck with Feedback Example

Using OrCAD Pspice Schematics
PARAMETERS:
Vref = 2.5
Vo = 12
ratio = {Vref/Vo}
Rtop = 10k
Vg mult = 0.992
percentload = 10
S1
+
-
0
I
L1 Vout
+
-
Sbreak 1 2
V1 50u
V
R1a Vfb
48 C1 {Rtop}
D1 R1
Dbreak 50u
R1b
{mult*((ratio*Rtop)/(1-ratio))}
0 {(100/percentload)*(Vo/10)}
4
COMPARATOR Vg
{Vref} 100 IN+ OUT+
0 IN- OUT-
Vfb EVALUE
LIMIT(1MEG*V(%IN+, %IN-),5,0)
V1 = 5 Vtri
V2 = 0
TD = 0
TR = {5u-10n} 0
TF = {5u-10n}
PW = 20n 0
PER = {1/100k}

20V
Output Voltage at Maximum Load
(12.008 V)
10V
SEL>>
0V
V(Vout)
30A
Inductor Current at Maximum Load
20A
(10.000 Amps)
10A
0A
0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms
I(L1)
Time
Output Voltage Ripple at Maximum Load

12.0200V
(12.023 V)
12.0000V
11.9800V
(11.977 V)
SEL>>
11.9695V
V(Vout)
11A
Inductor Current Ripple at Maximum Load
(9.1136 Amps)
10A
(10.883 Amps)
9A
4.68517ms 4.69000ms 4.69500ms 4.70000ms 4.70500ms 4.71000ms 4.71500ms
I(L1)
Time

Non-ideal Buck: Loss Considerations
• When efficiency estimation is required in the
design, losses in Buck circuit should be
considered
• Several major losses to consider:
– Static loss of MOSFET
– Switching loss of MOSFET
– MOSFET Gate Drive Losses
– Static loss of diode
– Switching loss of diode
– Inductor’s copper loss
– Capacitor’s ESR loss
Static Loss of MOSFET
• With MOSFET, its on resistance RDSon directly impacts
the conduction (static) loss
• RDSon depends on applied gate voltage and MOSFET’s
junction temperature

Static Loss of MOSFET
• Recall, switch current:
iLmax
iSwitch
iLmin
Average Value
ON ON ON
t
0 T 2T
• Static loss for MOSFET with RDSon:
Pstatic  I switch
2
 rms  RDSon
2
   iL   
Pstatic   I o D 1       RDSon
   2  Io   
 
Switching Loss of MOSFET
• The switching loss depends on how the voltage and current
overlaps
• May be approximated with a scenario where voltage and
current start moving simultaneously and reach their
endpoints
• The overlap causes power loss (V x I)
• Will assume to occur both at turn-on and turn-off transitions
turn on Io Io turn off

VIN VIN
ton toff
Switching Loss of MOSFET
turn on Io Io turn off
VIN VIN
0
ton toff
I oVinton I oVintoff
P(ton )  P (toff ) 
6T 6T
I oVin ton I oVin toff

Pswitching  P(ton )  P(toff )  
6T 6T
I oVin
Pswitching 
6T
 ton  toff 
Switching Loss of MOSFET & Gate Drive Loss
• When MOSFET is off, its output capacitance Coss is
being charged  translates to loss
• Gate drive loss comes from the total gate charge Qgate
and the gate drive voltage Vgate used

Static Loss of Diode: Forward Loss
• Losses that occur during diode’s fully on (forward
loss) and fully off (reverse loss) conditions
• Forward loss come from the product of diode’s
forward voltage (VF) and forward current (IF), in
addition to the rms loss due to diode dynamic
resistance, rd
Average RMS
Values Value

Static Loss of Diode: Forward Loss
From datasheet
I f  1  D   I o I f 
1  D   I 2
 max min  I max  I min 
 2
I
3

Static Loss of Diode: Reverse Loss
• Loss occurs when the diode is in the fully off or non-
conducting condition
Preverse  Vr  I r  1  D 

Switching Loss of Diode: Turn On Loss
• The switching behavior at turn-on is characterized by a
low value of peak forward voltage (VFP) and forward
recovery time (tfr)
PON  0.4  VFP  V f  t fr  I f  f

Switching Loss of Diode: Turn On Loss
• Both VFP and tfr are normally plotted against dId(t)/dt in the
datasheet, whereas dId(t)/dt itself is also available in the datasheet
for a given set of conditions

Switching Loss of Diode: Turn Off Loss
• Turn-off loss constitutes appreciable switching losses
due to the overlapping of diode voltage and current at
turn-off with its associated reverse-recovery time
Id0
t rra  I rrm
dI d
dt t1( rr )

t rrb  1.11  t rr  t rra 
t 2rr , t 3rr   k rr  t rrb
 0.033Vd 0 I rrm t rra  Vd 0 I rrm 0.467  0.433k rr  0.15k rr2 t rrb

Id0
Poff  0.5Vds I d 0

dI d
dt t1( rr ) 
Inductor’s Copper Loss
• Inductor’s winding is made of copper and hence
inherently it will have resistive loss
Average
Inductor
Current, I
• With inductor’s dc resistance of RL and inductor’s rms

current, the copper loss of inductor is:
2

PL  I L RL
2
I L  I 1  1  iL 
 
3  2I 
Inductor’s Core Loss
• Factors affecting core loss: switching frequency F,
temperature, flux swing B
• General form:
Core Loss = (Core Loss/Unit Volume) x Volume

Where,
Core Loss/Unit Volume = k1 x Bk2 x Fk3
• Constants k1, k2, and k3 are normally provided by the

core manufacturers

Capacitor’s ESR Loss
• Real world capacitors possess ESR (Equivalent Series
Resistance)
• ESR can measured with, for example, Capacitor Wizard
iC
t
T 2T 3T
• Loss due to Capacitor’s ESR is:

Buck Design With Losses
Buck Design with Losses Taufik
Maximum Output Power: 6

Pomax  120W   1 10
Nominal Output Voltage: 3
Vonom  12V m  1 10
Nominal Input Voltage: Vinom  24V
Switching Frequency: Fs  250kHz
Minimum Percent CCM: Iccm  10%
Maximum Ripple Percentage: Vopp  2%
Design Calculations and Sizing Components:
Vonom
Nominal Duty Cycle: D   0.5
Vinom
 Vonom2 
( 1  D)   
Critical Inductance: Lc 
 Iccm Pomax   12.000H 
2 Fs
Choose L > Lc Lo  200H with assumed DC resistance of: RLo  100m
ILopk  Vonom 
1 ( 1  D) 
Peak Inductor Current:   10.06A
 2 2 Lo Fs 
Vonom
 
 Pomax 
Switch Voltage: Vswmax Vinom  24V
Pomax
Switch Current: Id  D  5A
Vonom

Choose MOSFET IRF7471 40V 10A Rdson 13mO
Diode Vrrm: Vrrm Vinom  24V
Pomax
Diode Forward Current: If  ( 1  D)   5A
Vonom
Choose MBR3040
Capacitor Voltage Rating: Vcap  Vonom   Vopp Vonom   12.12V

 
 2 
( 1  D) 3
Capacitance: Co   250  10 F 
2
8 Lo Fs  Vopp
( 1  D)  Vonom
RMS Current Rating: Icaprms   0.035A
2 3 Lo Fs
Choose a 25V 50uF capacitor
Power Loss Calculations
MOSFET Loss Calculations: Rdson  13m  n  0  11

Load 
n
0.01
5
10
 Loadn  20
  Pomax 
100 30
Output Current Array: Io   
n
 Vonom  40
50
Static Loss: 60
70
Idrms  Io  D 1  Iccm 80
n n
90
n  n 2
Pmos1  Io  D 1  Iccm Rdson 100

Switching Loss: ton1  12ns toff1  15ns Coss  700pF Qg  21nC
Io  Vinom ( ton1  toff1)  Fs Vg  12V

n
Pmos2 
n 6
1 2 1
Pcoss   Coss  Vinom  Fs  0.05W Pgate   Qg Vg Fs  0.032W
2 2
Pmostot  Pmos1  Pmos2  Pcoss  Pgate

n n n
Diode Loss Calculations

Vf 
Ifavg  Io  ( 1  D) From Diode Datasheet: n
n n
0.02V
0.62V  0.4V
Dynamic Resistance: Rd   0.063 0.46V
4A  0.5A 0.5V
Vonom ( 1  D) 0.58V
Peak to peak IL   0.12A
Lo Fs 0.61V
Inductor Current
0.64V
0.66V
( 1  D)  IL 
2
 IL 
2
 Io  IL    Io  IL 
Ifrms    Io    n
 Io    n
   0.68V
n 3  n 2   2   2  n 2  0.7V
0.71V
Pd1  Vf  Ifavg  Ifrms
n n n  n 2Rd 0.73V
From Datasheet: Vr  Vinom  Vonom Ir  0.00015A

Pd2  Vr Ir ( 1  D)  0.001W

Assume: tfr  500ns Vfp  10V
n  n 
Pd3  0.4 Vfp  Vf  tfr Ifavg  Fs
n
Pdtot  Pd1  Pd2  Pd3

n n n
Inductor Loss Calculation 0.95

Efficiency of 12V 120W
0.905
2
  IL
 
1 2 0.86
ILrms  Io  1  PLo  ILrms  RLo
n n 3 2 Io  n n 0.815
 n 0.77
Efficiency
 n 0.725
Capacitor Loss Calculation Assume: ESR  150m  0.68
0.635
IL 2
Icrms   0.035A Pc  Icrms  ESR 0.59
2 3 0.545
0.5
0 10 20 30 40 50 60 70 80 90 100
Total Loss Calculation Loadn

Percent Load
Ptotal  Pmostot  Pdtot  PLo  Pc Po  Vonom Io

n n n n n n
Po
n
Efficiency ==>  
n Po  Ptotal
n n

Efficiency Improvements
• Ways to improve converter’s efficiency:
– MOSFET
• Low Rdson for High Duty Cycle
• Low Gate Charge for Low Duty Cycle
• Paralleling for High Current
– Schottky Diode
• Low forward drop
• Short recovery time
– Inductor
• Multiple parallel windings such as Bifiliar (two
parallel windings), Trifiliar (three parallel windings)

Efficiency Improvement
– Capacitors
• Low ESR
• Paralleling caps (increasing capacitance while
reducing ESRs)
– Lower inductor current ripple
• Reduce rms loss (inductor and output capacitor)
• Increase switching frequency or inductance
– Switching loss and real-estate trade off
– Lower gate drive voltage
– Use of Synchronous MOSFET in place of
diode, especially for low voltage and high
current output
Synchronous Rectification
• Replaces freewheeling schottky with MOSFET
• Especially beneficial on low duty cycle and high current applications
• Due to required dead time and slow MOSFET’s body diode, a
Schottky is connected across the Synchronous MOSFET
• MOSFET + Schottky = FETKY combo such as IRF7326D2

Soft-Switching
• Prevents hard-switching or the overlapping of switch’s voltage and
current during turn-on and turn-off transitions
– switching losses which is proportional to switching frequency
• Use of resonant circuit to shape switch voltage and/or current
waveforms to inherently go to zero at which switching transition is
initiated  zero switching loss
pswitching(t)
Ion Ion
Voff Voff
turn on turn off

Soft-Switching
• Quasi-resonant buck topologies such as Zero-Voltage
and Zero Current Resonant Switch Buck converter
• Needs constant-on or constant-off controllers such as
UC1865 - UC1868, UC1861 – UC1864, MC34067 and
MC33067, TDA4605-3, TDA4605-2
Voff Ion Ion

Voff
0
turn on turn off

Soft-Switching
• Zero-Current Resonant Switch Buck
– Turns switch OFF at zero current
• Zero-Voltage Resonant Switch Buck

– Turns switch ON at zero voltage

PWM Controller
• Recall two basic methods: Voltage Mode and Current
Mode
• Current Mode is widely used due to its many benefits
over Voltage Mode
• Advantages of Current Mode Controller
– Easy Compensation
• With voltage-mode requires a type III compensator to
stabilize the system due to the sharp phase drop after the
filter resonant frequency
• Current-mode control looks like a single-pole system, since
the inductor has been controlled by the current loop
• Improves the phase margin, making the converter easier to
control
• A type 2 compensator is adequate, simplifying the design
process

PWM Controller
– CCM and DCM Operation
• Compensator design not possible with voltage-mode that can
provide good performance in both CCM and DCM
• With current-mode, crossing the boundary between the two
types of operation is not a problem
– allowing the power stage to operate much more efficiently
– Line Rejection
• Closing the current loop gives a lot of attenuation of input
noise, even with only a moderate gain in the voltage
feedback loop
• With voltage-mode control, far more gain (or feed forward) is
needed in the main feedback loop to achieve the same
performance

PWM Controller
• For the sake of example, we’ll use UC184x or MIC38HC4x family

PWM Controller
Texas Instruments

PWM Controller
• Selecting Timing Resistor and Timing Capacitor
– Maximum Duty Cycle and Switching Frequency have to be determined
first
– Percent Dead time would then be computed from Dmax
– Using % Dead time along with Switching Frequency, we can then use
plots provided in the data sheet to determine the required timing capacitor
and timing resistor
• Example: Let’s say that Dmax was calculated to be 70% or 0.7. Add safety
factor to Dmax. Say 10% such that Dmax’ = 0.8
• The dead time is therefore = 100% - 80% = 20%

• If switching frequency used is 80 kHz, then the value for % dead time along
with switching frequency can be used to determine the required Timing
Capacitor
• This is done by using the plot provided in the data sheet.
PWM Controller
• From plot, 80 kHz intersects the 20% dead time at
approximately Timing Capacitor value of 10 nF.
• Next, the timing resistor is found from the plot which is
also provided in the data sheet

PWM Controller
• Plot shows that 80kHz intersects the timing capacitor plot for 10 nF
at timing resistance approximately equals to 2k
• So, in order to provide the 20% dead time at 80 kHz switching
frequency, the timing components are: CT = 10 nF and RT = 2 k
= 2k
= 10nF

PWM Controller
• Feedback Compensation
– As a start, typically a small capacitor is placed on ZF (such
as 2200 pF) for feedback compensation
– Once a prototype is built, the feedback compensation will
be investigated to give the desired gain and phase margin
and stability (over wide range of load)
– Involves the decision of whether to use type II or III
compensator

PWM Controller

PWM Controller
• Steps for selecting components in Type 2
– Choose cross-over frequency Fcross to be around 1/3 of
switching frequency Fswitch
– The required pole frequency Fp0 that yields the desired Fcross
crossover frequency of the open loop gain (where H0 is dc gain Fp 0 
of the plant) Ho
1
– Calculate capacitor C1 where R1 should have been selected when C1 
setting the voltage divider 2 R1 Fp 0
1
– Calculate R2 using the previously calculated C1 and the output R2 
pole of the plant Fp 2 C1 Fp
– Calculate capacitor C3 where Fesr is the location of the ESR zero 1
C3 
2 ESR  Fesr

PWM Controller
• Current Sensing Resistor
– Need to calculate power rating of the sensing resistor. This
involves calculating worst case Irms through the sensing resistor,
and then compute P = (Irms)2*Rsense
– A low pass RC filter circuit is also needed to eliminate leading
spike on the pulse voltage resulted from current being sensed
– Ensure that voltage out of the filter is less than 1V (for this
controller). If not, then reduce the value of Rsense

Layout Considerations
• Separate power path from signal path

• Use rounded edges instead of sharp edges on traces
• Ensure the trace is wide enough to carry current
• Keep trace inductance low (preferably by reducing
length, not increasing width) for the critical path (switch
and diode paths)
– Noise spikes may appear in input and output, and to
the controller chip
– Avoid using a current probe (a loop of wire) for diode
and switch due to additional inductance it will produce

Layout Considerations
• Provision of good Input decoupling since input capacitor

is in the critical path
– Besides the usual bulk capacitor, also put a small
ceramic capacitor at the supply end to ground, and
another one close to the switch to ground
• Provision of good decoupling with a small ceramic
capacitor between input and ground pins
• Try using shielded inductor, and position the inductor
away from the controller and feedback trace
• In multi-layer boards, dedicate one layer for ground

Power Electronics Lab at Cal Poly State University
• 6 Instructional Lab Benches, 2 Project/Thesis Benches
• For further information, contact Power Electronics Lab Coordinator, Dr. Taufik at taufik@calpoly.edu

View publication stats
Taufik was born in Jakarta, Indonesia. He received his BS in Electrical Engineering with minor
in Computer Science from Northern Arizona University (Cum Laude) in 1993, MS in Electrical
Engineering from University of Illinois Chicago in 1995, and Doctor of Engineering from
Cleveland State University in 1999. He joined the Electrical Engineering department at Cal
Poly State University in 1999 where he is currently a tenured Full Professor. He received
numerous teaching awards, most notably the 2012 Outstanding Teaching Award from the
American Society of Engineering Education - Pacific Southwest Section. He is a Senior
Member of IEEE and has industry experience with several companies including Capstone
Microturbine, Rockwell Automation, Picker International, San Diego Gas & Electric, APD
Semiconductor, Diodes Inc., Partoe Inc., Enerpro, Renewable Power Conversion and
Sempra Energy. His research areas include power electronics, power systems, rural
electrification, energy harvesting, renewable energy and smart grid. He has published over
200 papers in technical journals and conference papers. He holds one US Patent, and he has
served on the editorial review boards of several engineering journals. He is also an Adjunct
Faculty in the College of Engineering at Universitas Pertamina.

Practical Buck Design Revised 2018

Uploaded by

Copyright:

Available Formats

You might also like

Practical Buck Design Revised 2018

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Practical Buck Design Revised 2018

Uploaded by

Copyright:

Available Formats

See discussions, stats, and author profiles for this publication at: https://www.researchgate.

Practical Design of Buck Converter By Tauﬁk

Presentation · December 2017

The DC House Project View project

The user has requested enhancement of the downloaded file.

Professor of Electrical Engineering

Practical Design of Buck Converter Taufik | Page 2

Practical Design of Buck Converter Taufik | Page 3

• When ON: The output voltage is the same as the input

• Duty Cycle range: 0 < D < 1

Practical Design of Buck Converter Taufik | Page 6

Practical Design of Buck Converter Taufik | Page 7

Practical Design of Buck Converter Taufik | Page 8

Source Side Load/User Side

Current with some Voltage with some

Practical Design of Buck Converter Taufik | Page 9

Practical Design of Buck Converter Taufik | Page 10

• Recall the basic switching circuit above produces

• Above circuit has a serious problem!

Practical Design of Buck Converter Taufik | Page 12

• After adding the diode, the circuit is the power stage of a

Practical Design of Buck Converter Taufik | Page 13

Practical Design of Buck Converter Taufik | Page 15

• Inductor is the main storage element

Practical Design of Buck Converter Taufik | Page 16

• When the switch is closed or ON

• When the switch is OPEN or OFF

VS  VO  DT   VO 1  D  T  0

• Average output voltage is LESS than Input Voltage

Practical Design of Buck Converter Taufik | Page 19

For MOSFETs: Vds and Id L and Ipk

Vrrm, and If C, V and Irms

Practical Design of Buck Converter Taufik | Page 20

Practical Design of Buck Converter Taufik | Page 21

Practical Design of Buck Converter Taufik | Page 22

 We can then determine ILmin and ILmax

 ILmin is used to determine the Critical Inductance (Minimum

iL  1 (1  D)  (1  Dmax ) Rmax

Calculated at Minimum  Calculated at Minimum Output

Practical Design of Buck Converter Taufik | Page 25

Practical Design of Buck Converter | Page 26

• Using the OFF time:

Practical Design of Buck Converter | Page 27

 ILmax is used to determine peak current rating of Inductor

Chosen inductance value as

 With ideal diode and ideal buck, the Vswitch-max = Vinmax

 Switch current rating is calculated based on average

ON OFF ON OFF ON OFF

Practical Design of Buck Converter Taufik | Page 31

Average Switch Current is calculated from the area of the trapezoid

Practical Design of Buck Converter Taufik | Page 32

Practical Design of Buck Converter Taufik | Page 33

 Known as VRRM is the maximum reverse voltage across the

Practical Design of Buck Converter Taufik | Page 34

iDiode Average Value

OFF OFF OFF

 iL min  iL max   toff